From nobody Wed Oct 8 02:01:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEAD92E3AEC; Thu, 3 Jul 2025 11:32:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751542327; cv=none; b=jBS6qvM5ICUO98Lci792+OLHDNr91ec5N0ieXhTsJFKEI56/TF9xzRlCdGzN2A/9g5V5kDGVtcmsxK3M7Pnjq2HGRJ0QQNHMfjA4aaZ4lOl0s+ST2KUKeKmpNsSVdpnHePPjUD5lMpclSNZsD0/7v6CBu7hgPJ/+/b4+9Pc5veU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751542327; c=relaxed/simple; bh=CLjocfQhTv2btnL4nKTEDOp+4oS1ggJW5Qc2uMHm88I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tefayslFrUsK88QYJaXxHYFvMjDmd8valcXffekqCGXvNDxSpTlhWBQ9yh/oEwhB8iy2/0a84h+wjE+vyhNSOtFJ+Nv4yXoPbzhA1Y+ZEuHfS7j+9ebyN5JBUa2uF2xGfVjFJU/xO8yyMj6JPQIW+EicMj3kdwh0WgQqSOOUYRo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hHpz3G+g; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hHpz3G+g" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5B405C4CEF2; Thu, 3 Jul 2025 11:32:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751542327; bh=CLjocfQhTv2btnL4nKTEDOp+4oS1ggJW5Qc2uMHm88I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hHpz3G+geN/CcM5y5quORUTyr8cpVd9/ZlzxzgscG7w/OoGj1+a8PHhqWzyE5HELV 3yzM9JD1iezuM2ClUAvcSc3KOhBSW1UVURqLnxbD8NFiAW65snJiFv8UTdMqZ3truv 7Vm4gSLASMzp1nWNPoobPWBIefrD33iAw08J+18LTF4s9qWRUIGgdY55VKFMqhZ9v9 texn77h3huF0ifMhzfJTOY5HiY6PZb3ERyCEcUU+0bK7FpZJMvKfXNMSMzSJq0d7UM OSNE2GnFHBQLALOi3BNVw24Zb1zVlPGN3J3DmWSffmXSik3lfgD0AvSGMSYwgvxWWS s/TboRqeuNMOg== From: Michael Walle To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Greg Kroah-Hartman , Linus Walleij , Liam Girdwood , Mark Brown , Julien Panis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Michael Walle , Conor Dooley Subject: [PATCH v3 1/8] dt-bindings: mfd: ti,tps6594: Add TI TPS652G1 PMIC Date: Thu, 3 Jul 2025 13:31:46 +0200 Message-Id: <20250703113153.2447110-2-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250703113153.2447110-1-mwalle@kernel.org> References: <20250703113153.2447110-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TPS652G1 is a stripped down version of the TPS65224. From a software point of view, it lacks any voltage monitoring, the watchdog, the ESM and the ADC. Signed-off-by: Michael Walle Acked-by: Conor Dooley --- Documentation/devicetree/bindings/mfd/ti,tps6594.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml b/Docume= ntation/devicetree/bindings/mfd/ti,tps6594.yaml index 6341b6070366..a48cb00afe43 100644 --- a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml @@ -22,6 +22,7 @@ properties: - ti,tps6593-q1 - ti,tps6594-q1 - ti,tps65224-q1 + - ti,tps652g1 =20 reg: description: I2C slave address or SPI chip select number. --=20 2.39.5 From nobody Wed Oct 8 02:01:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C29072620E4; Thu, 3 Jul 2025 11:32:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751542331; cv=none; b=So2mzTYBGh04aRfSC9dQp2u9JnO8PB79iXKUecspsipziO59AiBrfxxJriYkWfXPa53PKv1hVy9Bn/9sIInn41VMgLtWhV5RZPtyiu2p+iZSNRoE0/nmoaTG27qU3dyzXDeS/QsRoConExh+4fn0Aq33SElVtshOcWHyCXRImHQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751542331; c=relaxed/simple; bh=1g8W1abvL7Vcuqx0UYFfKEzwpdKegawahvzBf/6GJ5s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fmxmJ00SeGRlp+gshvF9XIlUuIvxir98REUBt2xRqoJoi82TrCvrSlZGc5T/cLQEe72IJ/x5tMZ4u2DqKp5ywKH08NvxtyJk9zbJ8BVlkyXqiLFn06FNl+5U0FruCpB8iz7tGBKwJqlBKpKDYv5KQrTJRq26KJWEhZJSXkcOpBc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ciMW+WHm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ciMW+WHm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9F07AC4CEE3; Thu, 3 Jul 2025 11:32:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751542330; bh=1g8W1abvL7Vcuqx0UYFfKEzwpdKegawahvzBf/6GJ5s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ciMW+WHmP7wm0WgqjYMel6mZbxsh2mWcbTyR0CZ0lfqSO1990ev0K2YaDJT7WwOGz P9Kxs1gyBvAJbcmQjd8D2VsAkg+vNJfB7HCMYU0XGlATmYnyimRNjXcN9y3QFs/cKE faHtvDdjze1uTY01uaOngNnIqdYk3/f7vPQYlnAaAlRmFBF5po579nf2HniBdmMbA8 tpS4wBjXkVdwnrTG6NJi8syU/HIJxMSn2OWZufsPh3qrPmHP0KQKwIx+He84gSkz6l R6sDRe7PAAdXYLUaJPKUPwWG4XLaSngYClGHoIYepasetEnUQuJdn/M/UE1V5srcq9 CInQm2HjY2FJQ== From: Michael Walle To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Greg Kroah-Hartman , Linus Walleij , Liam Girdwood , Mark Brown , Julien Panis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Michael Walle Subject: [PATCH v3 2/8] mfd: tps6594: Add TI TPS652G1 support Date: Thu, 3 Jul 2025 13:31:47 +0200 Message-Id: <20250703113153.2447110-3-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250703113153.2447110-1-mwalle@kernel.org> References: <20250703113153.2447110-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TPS652G1 is a stripped down version of the TPS65224. From a software point of view, it lacks any voltage monitoring, the watchdog, the ESM and the ADC. Signed-off-by: Michael Walle --- drivers/mfd/tps6594-core.c | 88 ++++++++++++++++++++++++++++++++++--- drivers/mfd/tps6594-i2c.c | 10 ++++- drivers/mfd/tps6594-spi.c | 10 ++++- include/linux/mfd/tps6594.h | 1 + 4 files changed, 99 insertions(+), 10 deletions(-) diff --git a/drivers/mfd/tps6594-core.c b/drivers/mfd/tps6594-core.c index a7223e873cd1..c16c37e36617 100644 --- a/drivers/mfd/tps6594-core.c +++ b/drivers/mfd/tps6594-core.c @@ -1,6 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Core functions for TI TPS65224/TPS6594/TPS6593/LP8764 PMICs + * Core functions for following TI PMICs: + * - LP8764 + * - TPS65224 + * - TPS652G1 + * - TPS6593 + * - TPS6594 * * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/ */ @@ -414,6 +419,61 @@ static const unsigned int tps65224_irq_reg[] =3D { TPS6594_REG_INT_FSM_ERR, }; =20 +/* TPS652G1 Resources */ + +static const struct mfd_cell tps652g1_common_cells[] =3D { + MFD_CELL_RES("tps6594-pfsm", tps65224_pfsm_resources), + MFD_CELL_RES("tps6594-pinctrl", tps65224_pinctrl_resources), + MFD_CELL_NAME("tps6594-regulator"), +}; + +static const struct regmap_irq tps652g1_irqs[] =3D { + /* INT_GPIO register */ + REGMAP_IRQ_REG(TPS65224_IRQ_GPIO1, 2, TPS65224_BIT_GPIO1_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_GPIO2, 2, TPS65224_BIT_GPIO2_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_GPIO3, 2, TPS65224_BIT_GPIO3_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_GPIO4, 2, TPS65224_BIT_GPIO4_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_GPIO5, 2, TPS65224_BIT_GPIO5_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_GPIO6, 2, TPS65224_BIT_GPIO6_INT), + + /* INT_STARTUP register */ + REGMAP_IRQ_REG(TPS65224_IRQ_VSENSE, 3, TPS65224_BIT_VSENSE_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_ENABLE, 3, TPS6594_BIT_ENABLE_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_PB_SHORT, 3, TPS65224_BIT_PB_SHORT_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_FSD, 3, TPS6594_BIT_FSD_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_SOFT_REBOOT, 3, TPS6594_BIT_SOFT_REBOOT_INT), + + /* INT_MISC register */ + REGMAP_IRQ_REG(TPS65224_IRQ_BIST_PASS, 4, TPS6594_BIT_BIST_PASS_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_EXT_CLK, 4, TPS6594_BIT_EXT_CLK_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_REG_UNLOCK, 4, TPS65224_BIT_REG_UNLOCK_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_TWARN, 4, TPS6594_BIT_TWARN_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_PB_LONG, 4, TPS65224_BIT_PB_LONG_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_PB_FALL, 4, TPS65224_BIT_PB_FALL_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_PB_RISE, 4, TPS65224_BIT_PB_RISE_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_ADC_CONV_READY, 4, TPS65224_BIT_ADC_CONV_READ= Y_INT), + + /* INT_MODERATE_ERR register */ + REGMAP_IRQ_REG(TPS65224_IRQ_TSD_ORD, 5, TPS6594_BIT_TSD_ORD_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_BIST_FAIL, 5, TPS6594_BIT_BIST_FAIL_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_REG_CRC_ERR, 5, TPS6594_BIT_REG_CRC_ERR_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_RECOV_CNT, 5, TPS6594_BIT_RECOV_CNT_INT), + + /* INT_SEVERE_ERR register */ + REGMAP_IRQ_REG(TPS65224_IRQ_TSD_IMM, 6, TPS6594_BIT_TSD_IMM_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_VCCA_OVP, 6, TPS6594_BIT_VCCA_OVP_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_PFSM_ERR, 6, TPS6594_BIT_PFSM_ERR_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_BG_XMON, 6, TPS65224_BIT_BG_XMON_INT), + + /* INT_FSM_ERR register */ + REGMAP_IRQ_REG(TPS65224_IRQ_IMM_SHUTDOWN, 7, TPS6594_BIT_IMM_SHUTDOWN_INT= ), + REGMAP_IRQ_REG(TPS65224_IRQ_ORD_SHUTDOWN, 7, TPS6594_BIT_ORD_SHUTDOWN_INT= ), + REGMAP_IRQ_REG(TPS65224_IRQ_MCU_PWR_ERR, 7, TPS6594_BIT_MCU_PWR_ERR_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_SOC_PWR_ERR, 7, TPS6594_BIT_SOC_PWR_ERR_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_COMM_ERR, 7, TPS6594_BIT_COMM_ERR_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_I2C2_ERR, 7, TPS65224_BIT_I2C2_ERR_INT), +}; + static inline unsigned int tps6594_get_irq_reg(struct regmap_irq_chip_data= *data, unsigned int base, int index) { @@ -443,7 +503,7 @@ static int tps6594_handle_post_irq(void *irq_drv_data) * a new interrupt. */ if (tps->use_crc) { - if (tps->chip_id =3D=3D TPS65224) { + if (tps->chip_id =3D=3D TPS65224 || tps->chip_id =3D=3D TPS652G1) { regmap_reg =3D TPS6594_REG_INT_FSM_ERR; mask_val =3D TPS6594_BIT_COMM_ERR_INT; } else { @@ -481,6 +541,18 @@ static struct regmap_irq_chip tps65224_irq_chip =3D { .handle_post_irq =3D tps6594_handle_post_irq, }; =20 +static struct regmap_irq_chip tps652g1_irq_chip =3D { + .ack_base =3D TPS6594_REG_INT_BUCK, + .ack_invert =3D 1, + .clear_ack =3D 1, + .init_ack_masked =3D 1, + .num_regs =3D ARRAY_SIZE(tps65224_irq_reg), + .irqs =3D tps652g1_irqs, + .num_irqs =3D ARRAY_SIZE(tps652g1_irqs), + .get_irq_reg =3D tps65224_get_irq_reg, + .handle_post_irq =3D tps6594_handle_post_irq, +}; + static const struct regmap_range tps6594_volatile_ranges[] =3D { regmap_reg_range(TPS6594_REG_INT_TOP, TPS6594_REG_STAT_READBACK_ERR), regmap_reg_range(TPS6594_REG_RTC_STATUS, TPS6594_REG_RTC_STATUS), @@ -507,7 +579,7 @@ static int tps6594_check_crc_mode(struct tps6594 *tps, = bool primary_pmic) int ret; unsigned int regmap_reg, mask_val; =20 - if (tps->chip_id =3D=3D TPS65224) { + if (tps->chip_id =3D=3D TPS65224 || tps->chip_id =3D=3D TPS652G1) { regmap_reg =3D TPS6594_REG_CONFIG_2; mask_val =3D TPS65224_BIT_I2C1_SPI_CRC_EN; } else { @@ -537,7 +609,7 @@ static int tps6594_set_crc_feature(struct tps6594 *tps) int ret; unsigned int regmap_reg, mask_val; =20 - if (tps->chip_id =3D=3D TPS65224) { + if (tps->chip_id =3D=3D TPS65224 || tps->chip_id =3D=3D TPS652G1) { regmap_reg =3D TPS6594_REG_CONFIG_2; mask_val =3D TPS65224_BIT_I2C1_SPI_CRC_EN; } else { @@ -628,6 +700,10 @@ int tps6594_device_init(struct tps6594 *tps, bool enab= le_crc) irq_chip =3D &tps65224_irq_chip; n_cells =3D ARRAY_SIZE(tps65224_common_cells); cells =3D tps65224_common_cells; + } else if (tps->chip_id =3D=3D TPS652G1) { + irq_chip =3D &tps652g1_irq_chip; + n_cells =3D ARRAY_SIZE(tps652g1_common_cells); + cells =3D tps652g1_common_cells; } else { irq_chip =3D &tps6594_irq_chip; n_cells =3D ARRAY_SIZE(tps6594_common_cells); @@ -651,8 +727,8 @@ int tps6594_device_init(struct tps6594 *tps, bool enabl= e_crc) if (ret) return dev_err_probe(dev, ret, "Failed to add common child devices\n"); =20 - /* No RTC for LP8764 and TPS65224 */ - if (tps->chip_id !=3D LP8764 && tps->chip_id !=3D TPS65224) { + /* No RTC for LP8764, TPS65224 and TPS652G1 */ + if (tps->chip_id !=3D LP8764 && tps->chip_id !=3D TPS65224 && tps->chip_i= d !=3D TPS652G1) { ret =3D devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, tps6594_rtc_cells, ARRAY_SIZE(tps6594_rtc_cells), NULL, 0, regmap_irq_get_domain(tps->irq_data)); diff --git a/drivers/mfd/tps6594-i2c.c b/drivers/mfd/tps6594-i2c.c index 4ab91c34d9fb..7ff7516286fd 100644 --- a/drivers/mfd/tps6594-i2c.c +++ b/drivers/mfd/tps6594-i2c.c @@ -1,6 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * I2C access driver for TI TPS65224/TPS6594/TPS6593/LP8764 PMICs + * I2C access driver for the following TI PMICs: + * - LP8764 + * - TPS65224 + * - TPS652G1 + * - TPS6593 + * - TPS6594 * * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/ */ @@ -197,6 +202,7 @@ static const struct of_device_id tps6594_i2c_of_match_t= able[] =3D { { .compatible =3D "ti,tps6593-q1", .data =3D (void *)TPS6593, }, { .compatible =3D "ti,lp8764-q1", .data =3D (void *)LP8764, }, { .compatible =3D "ti,tps65224-q1", .data =3D (void *)TPS65224, }, + { .compatible =3D "ti,tps652g1", .data =3D (void *)TPS652G1, }, {} }; MODULE_DEVICE_TABLE(of, tps6594_i2c_of_match_table); @@ -222,7 +228,7 @@ static int tps6594_i2c_probe(struct i2c_client *client) return dev_err_probe(dev, -EINVAL, "Failed to find matching chip ID\n"); tps->chip_id =3D (unsigned long)match->data; =20 - if (tps->chip_id =3D=3D TPS65224) + if (tps->chip_id =3D=3D TPS65224 || tps->chip_id =3D=3D TPS652G1) tps6594_i2c_regmap_config.volatile_table =3D &tps65224_volatile_table; =20 tps->regmap =3D devm_regmap_init(dev, NULL, client, &tps6594_i2c_regmap_c= onfig); diff --git a/drivers/mfd/tps6594-spi.c b/drivers/mfd/tps6594-spi.c index 6ebccb79f0cc..944b7313a1d9 100644 --- a/drivers/mfd/tps6594-spi.c +++ b/drivers/mfd/tps6594-spi.c @@ -1,6 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * SPI access driver for TI TPS65224/TPS6594/TPS6593/LP8764 PMICs + * SPI access driver for the following TI PMICs: + * - LP8764 + * - TPS65224 + * - TPS652G1 + * - TPS6593 + * - TPS6594 * * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/ */ @@ -82,6 +87,7 @@ static const struct of_device_id tps6594_spi_of_match_tab= le[] =3D { { .compatible =3D "ti,tps6593-q1", .data =3D (void *)TPS6593, }, { .compatible =3D "ti,lp8764-q1", .data =3D (void *)LP8764, }, { .compatible =3D "ti,tps65224-q1", .data =3D (void *)TPS65224, }, + { .compatible =3D "ti,tps652g1", .data =3D (void *)TPS652G1, }, {} }; MODULE_DEVICE_TABLE(of, tps6594_spi_of_match_table); @@ -107,7 +113,7 @@ static int tps6594_spi_probe(struct spi_device *spi) return dev_err_probe(dev, -EINVAL, "Failed to find matching chip ID\n"); tps->chip_id =3D (unsigned long)match->data; =20 - if (tps->chip_id =3D=3D TPS65224) + if (tps->chip_id =3D=3D TPS65224 || tps->chip_id =3D=3D TPS652G1) tps6594_spi_regmap_config.volatile_table =3D &tps65224_volatile_table; =20 tps->regmap =3D devm_regmap_init(dev, NULL, spi, &tps6594_spi_regmap_conf= ig); diff --git a/include/linux/mfd/tps6594.h b/include/linux/mfd/tps6594.h index 16543fd4d83e..021db8875963 100644 --- a/include/linux/mfd/tps6594.h +++ b/include/linux/mfd/tps6594.h @@ -19,6 +19,7 @@ enum pmic_id { TPS6593, LP8764, TPS65224, + TPS652G1, }; =20 /* Macro to get page index from register address */ --=20 2.39.5 From nobody Wed Oct 8 02:01:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D577624BBF0; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="os3G3U11" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B4ACBC4CEF1; Thu, 3 Jul 2025 11:32:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751542333; bh=KSR7zOmaHbVzQefF4HKm7LHKbPaAfBRxeWV3mJ8gRmA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=os3G3U11JVdT0zK9NXnD79ytmG+FLG0nC8eumfKz1DpdRJIqlGx4sJ477cYuowONO jBNID5g3lLIZhKefQ7e/cm4MsSJoSKM5wpiBwmqnQ9nLofZnrpyta05gRqNM9k1+Rh pd9ZsQFdqg4UYtLyd+tDz4bMgu/1ktMmwFKtPvUYcBVZqXOke4Bv5ww5nERf/bsuze ApOh6tBH9cclXL8zBzQpJreY7xURVRQLdIhWV3jZaLRIV6SUYpVlvbBWJHv2f+ScGq YCx52OM8kcavCNsYN1hFC83v5PeSVVAJa3drIdP8cJXeTFroboe8dbjr+7XVvhlnL5 3Iv4/aTHVWJ1Q== From: Michael Walle To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Greg Kroah-Hartman , Linus Walleij , Liam Girdwood , Mark Brown , Julien Panis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Michael Walle Subject: [PATCH v3 3/8] misc: tps6594-pfsm: Add TI TPS652G1 PMIC PFSM Date: Thu, 3 Jul 2025 13:31:48 +0200 Message-Id: <20250703113153.2447110-4-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250703113153.2447110-1-mwalle@kernel.org> References: <20250703113153.2447110-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TPS652G1 is a stripped down TPS65224, but the PFSM is the same. Thus, handle it the same way as the TPS65224 in the driver. Signed-off-by: Michael Walle Acked-by: Arnd Bergmann # drivers/misc/ --- drivers/misc/tps6594-pfsm.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/misc/tps6594-pfsm.c b/drivers/misc/tps6594-pfsm.c index 6db1c9d48f8f..44fa81d6cec2 100644 --- a/drivers/misc/tps6594-pfsm.c +++ b/drivers/misc/tps6594-pfsm.c @@ -1,6 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * PFSM (Pre-configurable Finite State Machine) driver for TI TPS65224/TPS= 6594/TPS6593/LP8764 PMICs + * PFSM (Pre-configurable Finite State Machine) driver for the following + * PMICs: + * - LP8764 + * - TPS65224 + * - TPS652G1 + * - TPS6594 + * - TPS6593 * * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/ */ @@ -141,7 +147,7 @@ static long tps6594_pfsm_ioctl(struct file *f, unsigned= int cmd, unsigned long a switch (cmd) { case PMIC_GOTO_STANDBY: /* Disable LP mode on TPS6594 Family PMIC */ - if (pfsm->chip_id !=3D TPS65224) { + if (pfsm->chip_id !=3D TPS65224 && pfsm->chip_id !=3D TPS652G1) { ret =3D regmap_clear_bits(pfsm->regmap, TPS6594_REG_RTC_CTRL_2, TPS6594_BIT_LP_STANDBY_SEL); =20 @@ -154,8 +160,8 @@ static long tps6594_pfsm_ioctl(struct file *f, unsigned= int cmd, unsigned long a TPS6594_BIT_TRIGGER_I2C(0), TPS6594_BIT_TRIGGER_I2C(0)); break; case PMIC_GOTO_LP_STANDBY: - /* TPS65224 does not support LP STANDBY */ - if (pfsm->chip_id =3D=3D TPS65224) + /* TPS65224/TPS652G1 does not support LP STANDBY */ + if (pfsm->chip_id =3D=3D TPS65224 || pfsm->chip_id =3D=3D TPS652G1) return ret; =20 /* Enable LP mode */ @@ -179,8 +185,8 @@ static long tps6594_pfsm_ioctl(struct file *f, unsigned= int cmd, unsigned long a TPS6594_BIT_NSLEEP1B | TPS6594_BIT_NSLEEP2B); break; case PMIC_SET_MCU_ONLY_STATE: - /* TPS65224 does not support MCU_ONLY_STATE */ - if (pfsm->chip_id =3D=3D TPS65224) + /* TPS65224/TPS652G1 does not support MCU_ONLY_STATE */ + if (pfsm->chip_id =3D=3D TPS65224 || pfsm->chip_id =3D=3D TPS652G1) return ret; =20 if (copy_from_user(&state_opt, argp, sizeof(state_opt))) @@ -206,7 +212,7 @@ static long tps6594_pfsm_ioctl(struct file *f, unsigned= int cmd, unsigned long a return -EFAULT; =20 /* Configure wake-up destination */ - if (pfsm->chip_id =3D=3D TPS65224) { + if (pfsm->chip_id =3D=3D TPS65224 || pfsm->chip_id =3D=3D TPS652G1) { regmap_reg =3D TPS65224_REG_STARTUP_CTRL; mask =3D TPS65224_MASK_STARTUP_DEST; } else { @@ -230,9 +236,14 @@ static long tps6594_pfsm_ioctl(struct file *f, unsigne= d int cmd, unsigned long a return ret; =20 /* Modify NSLEEP1-2 bits */ - ret =3D regmap_clear_bits(pfsm->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS, - pfsm->chip_id =3D=3D TPS65224 ? - TPS6594_BIT_NSLEEP1B : TPS6594_BIT_NSLEEP2B); + if (pfsm->chip_id =3D=3D TPS65224 || pfsm->chip_id =3D=3D TPS652G1) + ret =3D regmap_clear_bits(pfsm->regmap, + TPS6594_REG_FSM_NSLEEP_TRIGGERS, + TPS6594_BIT_NSLEEP1B); + else + ret =3D regmap_clear_bits(pfsm->regmap, + TPS6594_REG_FSM_NSLEEP_TRIGGERS, + TPS6594_BIT_NSLEEP2B); break; } =20 --=20 2.39.5 From nobody Wed Oct 8 02:01:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EBD52E613D; Thu, 3 Jul 2025 11:32:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751542336; cv=none; b=hqJKpc/jpTL3IZ7hDqw8rTyqqtzVwADLvZAMjE2wX7lAP9eZi9TYAguandkUT6Nr6yxQg9EUCiXWNLxr9tov7LBwlTccNiF6gMLvax1y7eVoNJVy20xIcagrJPSOj5VhFEj4rMbo0S9hqC7CtscGGOJaZoKJn6s/z7BwxUHlhCU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751542336; c=relaxed/simple; bh=ocZ2re+U8WMMPhbIQruoOerVGVWD9zswfN8MaVgrtsc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QJiFJn52gk5anA+x411uWLFXlXAGTZP2gp3aX9Eh1IaKW2li1LZ5zUT3O16KMVrw/K/jX9ISLCzMCjmNZzZ8kCNOk4Snr9EDiD4TYQIABVzj7T1TeO71SsWPosHSVFXcAp37XFgHoPWHqMZLkpNxYzMyPCbmJSoC9dpwfHBWVlg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cfrcAsuA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cfrcAsuA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C83B3C4CEEB; Thu, 3 Jul 2025 11:32:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751542336; bh=ocZ2re+U8WMMPhbIQruoOerVGVWD9zswfN8MaVgrtsc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cfrcAsuAm1T3UitJSL59FM/jrpWNoGNlX4VcvaZbWpDezqD711D8b9kxQhQ/PZsQl JizuUdnhoMMeb+wr4g9ew9wQD7MM3rMxI6DZpF7VK6F1aREXTkIyywJe536MXEjCVv AJeLbToY+AJHUQh4ImAwQiboa71ZrYKNS4043qIcCj3mgKpCYXJL6ZDr1KnQe+9Zng qtHuNTnWIhv9Q+q5XrVEfPcpzXh5q2B1O5fIcIhxFjBuOAV3DHAX4MrAAhBj5yVOJe rQ5RFQYs7InbL6TyPTzGfK0MTkSa1f685MkhqvsUr2ermql7Qy3b2lIKVe4CA/n7k0 LpYhdPagTyOIw== From: Michael Walle To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Greg Kroah-Hartman , Linus Walleij , Liam Girdwood , Mark Brown , Julien Panis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Michael Walle Subject: [PATCH v3 4/8] pinctrl: pinctrl-tps6594: Add TPS652G1 PMIC pinctrl and GPIO Date: Thu, 3 Jul 2025 13:31:49 +0200 Message-Id: <20250703113153.2447110-5-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250703113153.2447110-1-mwalle@kernel.org> References: <20250703113153.2447110-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TPS652G1 is a stripped down version of the TPS65224. Compared to the TPS65224 it lacks some pin mux functions, like the ADC, voltage monitoring and the second I2C bus. Signed-off-by: Michael Walle Reviewed-by: Linus Walleij --- drivers/pinctrl/pinctrl-tps6594.c | 35 +++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/pinctrl/pinctrl-tps6594.c b/drivers/pinctrl/pinctrl-tp= s6594.c index 54cc810f79d6..6726853110d1 100644 --- a/drivers/pinctrl/pinctrl-tps6594.c +++ b/drivers/pinctrl/pinctrl-tps6594.c @@ -226,6 +226,10 @@ static const char *const tps65224_nerr_mcu_func_group_= names[] =3D { "GPIO5", }; =20 +static const char *const tps652g1_cs_spi_func_group_names[] =3D { + "GPIO1", +}; + struct tps6594_pinctrl_function { struct pinfunction pinfunction; u8 muxval; @@ -287,6 +291,18 @@ static const struct tps6594_pinctrl_function tps65224_= pinctrl_functions[] =3D { FUNCTION(tps65224, nerr_mcu, TPS65224_PINCTRL_NERR_MCU_FUNCTION), }; =20 +static const struct tps6594_pinctrl_function tps652g1_pinctrl_functions[] = =3D { + FUNCTION(tps65224, gpio, TPS6594_PINCTRL_GPIO_FUNCTION), + FUNCTION(tps65224, sda_i2c2_sdo_spi, TPS65224_PINCTRL_SDA_I2C2_SDO_SPI_FU= NCTION), + FUNCTION(tps65224, nsleep2, TPS65224_PINCTRL_NSLEEP2_FUNCTION), + FUNCTION(tps65224, nint, TPS65224_PINCTRL_NINT_FUNCTION), + FUNCTION(tps652g1, cs_spi, TPS65224_PINCTRL_SCL_I2C2_CS_SPI_FUNCTION), + FUNCTION(tps65224, nsleep1, TPS65224_PINCTRL_NSLEEP1_FUNCTION), + FUNCTION(tps65224, pb, TPS65224_PINCTRL_PB_FUNCTION), + FUNCTION(tps65224, wkup, TPS65224_PINCTRL_WKUP_FUNCTION), + FUNCTION(tps65224, syncclkin, TPS65224_PINCTRL_SYNCCLKIN_FUNCTION), +}; + struct tps6594_pinctrl { struct tps6594 *tps; struct gpio_regmap *gpio_regmap; @@ -300,6 +316,16 @@ struct tps6594_pinctrl { struct muxval_remap *remap; }; =20 +static struct tps6594_pinctrl tps652g1_template_pinctrl =3D { + .funcs =3D tps652g1_pinctrl_functions, + .func_cnt =3D ARRAY_SIZE(tps652g1_pinctrl_functions), + .pins =3D tps65224_pins, + .num_pins =3D ARRAY_SIZE(tps65224_pins), + .mux_sel_mask =3D TPS65224_MASK_GPIO_SEL, + .remap =3D tps65224_muxval_remap, + .remap_cnt =3D ARRAY_SIZE(tps65224_muxval_remap), +}; + static struct tps6594_pinctrl tps65224_template_pinctrl =3D { .funcs =3D tps65224_pinctrl_functions, .func_cnt =3D ARRAY_SIZE(tps65224_pinctrl_functions), @@ -475,6 +501,15 @@ static int tps6594_pinctrl_probe(struct platform_devic= e *pdev) return -ENOMEM; =20 switch (tps->chip_id) { + case TPS652G1: + pctrl_desc->pins =3D tps65224_pins; + pctrl_desc->npins =3D ARRAY_SIZE(tps65224_pins); + + *pinctrl =3D tps652g1_template_pinctrl; + + config.ngpio =3D ARRAY_SIZE(tps65224_gpio_func_group_names); + config.ngpio_per_reg =3D TPS65224_NGPIO_PER_REG; + break; case TPS65224: pctrl_desc->pins =3D tps65224_pins; pctrl_desc->npins =3D ARRAY_SIZE(tps65224_pins); --=20 2.39.5 From nobody Wed Oct 8 02:01:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 027B92E6D1C; Thu, 3 Jul 2025 11:32:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751542340; cv=none; b=Q6oPImXPS6Fq5HUTXREQk2o0jWs9+6SXLaBfs7DH7izQxGTR12R+sGoPTlmCCpi0YTW73t48fuG38Qas5FvfY1YHq39qXcQXcEXAasiXNtPt+wxCkYsSxQ2naAl2tqSCU38CWLxDnmReBMiVUE2QxoamR5BAaO5hsqCi5MfEYcI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751542340; c=relaxed/simple; bh=nTrlgvIw4zBK4D3q9sYSa9w4/R3QYV0kl1AgSzTtEJ0=; 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charset="utf-8" In .probe() interrupt_count and nr_types is essentially the same. It contains the number of different interrupt per LDO or buck converter. Drop one. This is a preparation patch to further simplify the handling of different variants of this PMIC. This patch is only compile-time tested. Signed-off-by: Michael Walle Acked-by: Mark Brown --- drivers/regulator/tps6594-regulator.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/regulator/tps6594-regulator.c b/drivers/regulator/tps6= 594-regulator.c index 51264c869aa0..26669f3f1033 100644 --- a/drivers/regulator/tps6594-regulator.c +++ b/drivers/regulator/tps6594-regulator.c @@ -577,18 +577,15 @@ static int tps6594_regulator_probe(struct platform_de= vice *pdev) const struct regulator_desc *multi_regs; const struct tps6594_regulator_irq_type **ldos_irq_types; const struct regulator_desc *ldo_regs; - size_t interrupt_count; =20 if (tps->chip_id =3D=3D TPS65224) { bucks_irq_types =3D tps65224_bucks_irq_types; - interrupt_count =3D ARRAY_SIZE(tps65224_buck1_irq_types); multi_regs =3D tps65224_multi_regs; ldos_irq_types =3D tps65224_ldos_irq_types; ldo_regs =3D tps65224_ldo_regs; multi_phase_cnt =3D ARRAY_SIZE(tps65224_multi_regs); } else { bucks_irq_types =3D tps6594_bucks_irq_types; - interrupt_count =3D ARRAY_SIZE(tps6594_buck1_irq_types); multi_regs =3D tps6594_multi_regs; ldos_irq_types =3D tps6594_ldos_irq_types; ldo_regs =3D tps6594_ldo_regs; @@ -686,29 +683,27 @@ static int tps6594_regulator_probe(struct platform_de= vice *pdev) =20 error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, bucks_irq_types[buck_idx], - interrupt_count, &irq_idx); + nr_types, &irq_idx); if (error) return error; =20 error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, bucks_irq_types[buck_idx + 1], - interrupt_count, &irq_idx); + nr_types, &irq_idx); if (error) return error; =20 if (i =3D=3D MULTI_BUCK123 || i =3D=3D MULTI_BUCK1234) { error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, tps6594_bucks_irq_types[buck_idx + 2], - interrupt_count, - &irq_idx); + nr_types, &irq_idx); if (error) return error; } if (i =3D=3D MULTI_BUCK1234) { error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, tps6594_bucks_irq_types[buck_idx + 3], - interrupt_count, - &irq_idx); + nr_types, &irq_idx); if (error) return error; } @@ -727,7 +722,7 @@ static int tps6594_regulator_probe(struct platform_devi= ce *pdev) "failed to register %s regulator\n", pdev->name); =20 error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, - bucks_irq_types[i], interrupt_count, &irq_idx); + bucks_irq_types[i], nr_types, &irq_idx); if (error) return error; } @@ -742,7 +737,7 @@ static int tps6594_regulator_probe(struct platform_devi= ce *pdev) pdev->name); =20 error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, - ldos_irq_types[i], interrupt_count, + ldos_irq_types[i], nr_types, &irq_idx); if (error) return error; --=20 2.39.5 From nobody Wed Oct 8 02:01:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB3492E6D0F; Thu, 3 Jul 2025 11:32:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 3 Jul 2025 11:32:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751542342; bh=Pb8T1fs8hc/HXciFLS9ppoBRsmEt8rdNEhTeKhcNkgU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SG+uUU5gMLd5rvYA9SEzCtXfKk+cW/eOPd+QXUcS5iT5wNsXCxVRAzKtU999JFjkf yjPOLbgxsqDI2AV8Qc5o2SN07/qJtHNAKLN4ml+OiwFXX++era8oQoEhtXFYoPThHL /972gE6FjCQDhGgvtUGh2cOE9MI4LBfcmNFzKEh5f4Ga7okHs0QKS7q29d4rkQRWp8 0YnEd65ICIKWCdR1pUtq8VJcGqq3E8klLxWsJNqgtn/HULV4RYOwZWkk8FHEWJKhk1 8FPohdc6OmhpfVDNzmth5+yBG6S50ezbpV29tV9GvXDtjirNh2E8OMCSJbIoB81Y7/ dySrZhM34JuDw== From: Michael Walle To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Greg Kroah-Hartman , Linus Walleij , Liam Girdwood , Mark Brown , Julien Panis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Michael Walle Subject: [PATCH v3 6/8] regulator: tps6594-regulator: remove hardcoded buck config Date: Thu, 3 Jul 2025 13:31:51 +0200 Message-Id: <20250703113153.2447110-7-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250703113153.2447110-1-mwalle@kernel.org> References: <20250703113153.2447110-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 00c826525fba ("regulator: tps6594-regulator: Add TI TPS65224 PMIC regulators") added support for the TPS65224 and made the description of the multi-phase buck converter variable depending on the variant of the PMIC. But this was just done for MUTLI_BUCK12 and MULTI_BUCK12_34 configs probably because this variant only supports a multi-phase configuration on buck 1 and 2. Remove the hardcoded value for the remaining two configs, too as future PMIC variants might also support these. This is a preparation patch to refactor the regulator description and is compile-time only tested. Signed-off-by: Michael Walle Acked-by: Mark Brown --- drivers/regulator/tps6594-regulator.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/regulator/tps6594-regulator.c b/drivers/regulator/tps6= 594-regulator.c index 26669f3f1033..2c7c4df80695 100644 --- a/drivers/regulator/tps6594-regulator.c +++ b/drivers/regulator/tps6594-regulator.c @@ -695,14 +695,14 @@ static int tps6594_regulator_probe(struct platform_de= vice *pdev) =20 if (i =3D=3D MULTI_BUCK123 || i =3D=3D MULTI_BUCK1234) { error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, - tps6594_bucks_irq_types[buck_idx + 2], + bucks_irq_types[buck_idx + 2], nr_types, &irq_idx); if (error) return error; } if (i =3D=3D MULTI_BUCK1234) { error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, - tps6594_bucks_irq_types[buck_idx + 3], + bucks_irq_types[buck_idx + 3], nr_types, &irq_idx); if (error) return error; --=20 2.39.5 From nobody Wed Oct 8 02:01:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AF9E2E7BDC; Thu, 3 Jul 2025 11:32:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751542346; cv=none; b=TkC3MqI0hqMiw2ZlSNn5FIFZXVgWNBtnfwrivR8ys+Jz/Ac+aJoGIKkGOkHhI+jQHbBhktekj/mkH5reH3z/EarTGta+vg2aUXsDJEPvHYb0rHN95EzWC88Z8Z7HNcddTZSv4mG0rWIHoVi/ujbI6sIIg5R/OgJLvwuDRTeqNXk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751542346; c=relaxed/simple; bh=0+BrFq8UJUgrXrzTNW/WoFpuZ6X2firnB27vkFu+wfs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eLWCieaHL3YiN+LqK3OT5aBn5AQ+iEcPUIe7bOUfb9BB3HnVHBsf9xLKut+G3o/x41UMY+TVtiOHRjfCx68JxMIfRQBn8T7nwbM7PScFCA7M7cjukfnLA/W+DD7wzWpElvnP2/tvcQjJTvY8Z3N7xqL0DQA0vc4t6nLyJ1eofqg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fO0oKpLI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fO0oKpLI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 14038C4CEEB; Thu, 3 Jul 2025 11:32:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751542345; bh=0+BrFq8UJUgrXrzTNW/WoFpuZ6X2firnB27vkFu+wfs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fO0oKpLIXupdZpDCPZDwAB7a9R6vua594b/SVSQtty2o5fqA4iFj7ekiBMF2JdhEE QvuEC5HDkwg3cBozvkQFTq6FkcVgyvVnrakAGjS/Mct9KIsgqj1+EiXjx54NMwo4Fs ql+71WayUQPU/PKISIFU1nuFZgPNH7KzP4pUqgGuUTg0ot15TYjIwCtBDkZVZ1o0fR adC3BDGW1HYt3vgTahc5Xzdl8jqWiS+VhFcWAVQqHK5szwsLCrp3HH1idZwx0QAuBn 3WbyiQy1KzlP6ew0myu952lfhelN/XrI1gYx9rszrPOqvGwG5qcvsTQ3wUAa29JZ4W sdBTzB4RY4LjA== From: Michael Walle To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Greg Kroah-Hartman , Linus Walleij , Liam Girdwood , Mark Brown , Julien Panis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Michael Walle Subject: [PATCH v3 7/8] regulator: tps6594-regulator: refactor variant descriptions Date: Thu, 3 Jul 2025 13:31:52 +0200 Message-Id: <20250703113153.2447110-8-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250703113153.2447110-1-mwalle@kernel.org> References: <20250703113153.2447110-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Instead of using conditionals or tri state operators throughout the .probe() provide a description per variant. This will make it much easier to add new variants later. While at it, make the variable naming more consistent. This patch is only compile-time tested. Signed-off-by: Michael Walle Acked-by: Mark Brown --- drivers/regulator/tps6594-regulator.c | 199 +++++++++++++++----------- 1 file changed, 112 insertions(+), 87 deletions(-) diff --git a/drivers/regulator/tps6594-regulator.c b/drivers/regulator/tps6= 594-regulator.c index 2c7c4df80695..39adb2db6de8 100644 --- a/drivers/regulator/tps6594-regulator.c +++ b/drivers/regulator/tps6594-regulator.c @@ -21,10 +21,6 @@ #define BUCK_NB 5 #define LDO_NB 4 #define MULTI_PHASE_NB 4 -/* TPS6593 and LP8764 supports OV, UV, SC, ILIM */ -#define REGS_INT_NB 4 -/* TPS65224 supports OV or UV */ -#define TPS65224_REGS_INT_NB 1 =20 enum tps6594_regulator_id { /* DCDC's */ @@ -192,7 +188,7 @@ static const struct regulator_ops tps6594_ldos_4_ops = =3D { .map_voltage =3D regulator_map_voltage_linear_range, }; =20 -static const struct regulator_desc buck_regs[] =3D { +static const struct regulator_desc tps6594_buck_regs[] =3D { TPS6594_REGULATOR("BUCK1", "buck1", TPS6594_BUCK_1, REGULATOR_VOLTAGE, tps6594_bucks_ops, TPS6594_MASK_BUCKS_VSET, TPS6594_REG_BUCKX_VOUT_1(0), @@ -549,6 +545,63 @@ static int tps6594_request_reg_irqs(struct platform_de= vice *pdev, return 0; } =20 +struct tps6594_regulator_desc { + const struct regulator_desc *multi_phase_regs; + unsigned int num_multi_phase_regs; + + const struct regulator_desc *buck_regs; + int num_buck_regs; + + const struct regulator_desc *ldo_regs; + int num_ldo_regs; + + const struct tps6594_regulator_irq_type **bucks_irq_types; + const struct tps6594_regulator_irq_type **ldos_irq_types; + int num_irq_types; + + const struct tps6594_regulator_irq_type *ext_irq_types; + int num_ext_irqs; +}; + +static const struct tps6594_regulator_desc tps65224_reg_desc =3D { + .multi_phase_regs =3D tps65224_multi_regs, + .num_multi_phase_regs =3D ARRAY_SIZE(tps65224_multi_regs), + .buck_regs =3D tps65224_buck_regs, + .num_buck_regs =3D ARRAY_SIZE(tps65224_buck_regs), + .ldo_regs =3D tps65224_ldo_regs, + .num_ldo_regs =3D ARRAY_SIZE(tps65224_ldo_regs), + .bucks_irq_types =3D tps65224_bucks_irq_types, + .ldos_irq_types =3D tps65224_ldos_irq_types, + .num_irq_types =3D 1, /* OV or UV */ + .ext_irq_types =3D tps65224_ext_regulator_irq_types, + .num_ext_irqs =3D ARRAY_SIZE(tps65224_ext_regulator_irq_types), +}; + +static const struct tps6594_regulator_desc tps6594_reg_desc =3D { + .multi_phase_regs =3D tps6594_multi_regs, + .num_multi_phase_regs =3D ARRAY_SIZE(tps6594_multi_regs), + .buck_regs =3D tps6594_buck_regs, + .num_buck_regs =3D ARRAY_SIZE(tps6594_buck_regs), + .ldo_regs =3D tps6594_ldo_regs, + .num_ldo_regs =3D ARRAY_SIZE(tps6594_ldo_regs), + .bucks_irq_types =3D tps6594_bucks_irq_types, + .ldos_irq_types =3D tps6594_ldos_irq_types, + .num_irq_types =3D 4, /* OV, UV, SC and ILIM */ + .ext_irq_types =3D tps6594_ext_regulator_irq_types, + .num_ext_irqs =3D 2, /* only VCCA OV and UV */ +}; + +static const struct tps6594_regulator_desc lp8764_reg_desc =3D { + .multi_phase_regs =3D tps6594_multi_regs, + .num_multi_phase_regs =3D ARRAY_SIZE(tps6594_multi_regs), + .buck_regs =3D tps6594_buck_regs, + .num_buck_regs =3D ARRAY_SIZE(tps6594_buck_regs), + .bucks_irq_types =3D tps6594_bucks_irq_types, + .num_irq_types =3D 4, /* OV, UV, SC and ILIM */ + .ext_irq_types =3D tps6594_ext_regulator_irq_types, + .num_ext_irqs =3D ARRAY_SIZE(tps6594_ext_regulator_irq_types), +}; + static int tps6594_regulator_probe(struct platform_device *pdev) { struct tps6594 *tps =3D dev_get_drvdata(pdev->dev.parent); @@ -559,38 +612,32 @@ static int tps6594_regulator_probe(struct platform_de= vice *pdev) struct tps6594_regulator_irq_data *irq_data; struct tps6594_ext_regulator_irq_data *irq_ext_reg_data; const struct tps6594_regulator_irq_type *irq_type; - const struct tps6594_regulator_irq_type *irq_types; bool buck_configured[BUCK_NB] =3D { false }; bool buck_multi[MULTI_PHASE_NB] =3D { false }; + const struct tps6594_regulator_desc *desc; + const struct regulator_desc *multi_regs; =20 const char *npname; int error, i, irq, multi; int irq_idx =3D 0; int buck_idx =3D 0; - int nr_ldo; - int nr_buck; - int nr_types; - unsigned int irq_count; - unsigned int multi_phase_cnt; size_t reg_irq_nb; - const struct tps6594_regulator_irq_type **bucks_irq_types; - const struct regulator_desc *multi_regs; - const struct tps6594_regulator_irq_type **ldos_irq_types; - const struct regulator_desc *ldo_regs; =20 - if (tps->chip_id =3D=3D TPS65224) { - bucks_irq_types =3D tps65224_bucks_irq_types; - multi_regs =3D tps65224_multi_regs; - ldos_irq_types =3D tps65224_ldos_irq_types; - ldo_regs =3D tps65224_ldo_regs; - multi_phase_cnt =3D ARRAY_SIZE(tps65224_multi_regs); - } else { - bucks_irq_types =3D tps6594_bucks_irq_types; - multi_regs =3D tps6594_multi_regs; - ldos_irq_types =3D tps6594_ldos_irq_types; - ldo_regs =3D tps6594_ldo_regs; - multi_phase_cnt =3D ARRAY_SIZE(tps6594_multi_regs); - } + switch (tps->chip_id) { + case TPS65224: + desc =3D &tps65224_reg_desc; + break; + case TPS6594: + case TPS6593: + desc =3D &tps6594_reg_desc; + break; + case LP8764: + desc =3D &lp8764_reg_desc; + break; + default: + dev_err(tps->dev, "unknown chip_id %lu\n", tps->chip_id); + return -EINVAL; + }; =20 enum { MULTI_BUCK12, @@ -611,13 +658,14 @@ static int tps6594_regulator_probe(struct platform_de= vice *pdev) * In case of Multiphase configuration, value should be defined for * buck_configured to avoid creating bucks for every buck in multiphase */ - for (multi =3D 0; multi < multi_phase_cnt; multi++) { - np =3D of_find_node_by_name(tps->dev->of_node, multi_regs[multi].supply_= name); + for (multi =3D 0; multi < desc->num_multi_phase_regs; multi++) { + multi_regs =3D &desc->multi_phase_regs[multi]; + np =3D of_find_node_by_name(tps->dev->of_node, multi_regs->supply_name); npname =3D of_node_full_name(np); np_pmic_parent =3D of_get_parent(of_get_parent(np)); if (of_node_cmp(of_node_full_name(np_pmic_parent), tps->dev->of_node->fu= ll_name)) continue; - if (strcmp(npname, multi_regs[multi].supply_name) =3D=3D 0) { + if (strcmp(npname, multi_regs->supply_name) =3D=3D 0) { switch (multi) { case MULTI_BUCK12: buck_multi[0] =3D true; @@ -650,28 +698,19 @@ static int tps6594_regulator_probe(struct platform_de= vice *pdev) } } =20 - if (tps->chip_id =3D=3D TPS65224) { - nr_buck =3D ARRAY_SIZE(tps65224_buck_regs); - nr_ldo =3D ARRAY_SIZE(tps65224_ldo_regs); - nr_types =3D TPS65224_REGS_INT_NB; - } else { - nr_buck =3D ARRAY_SIZE(buck_regs); - nr_ldo =3D (tps->chip_id =3D=3D LP8764) ? 0 : ARRAY_SIZE(tps6594_ldo_reg= s); - nr_types =3D REGS_INT_NB; - } - - reg_irq_nb =3D nr_types * (nr_buck + nr_ldo); + reg_irq_nb =3D desc->num_irq_types * (desc->num_buck_regs + desc->num_ldo= _regs); =20 irq_data =3D devm_kmalloc_array(tps->dev, reg_irq_nb, sizeof(struct tps6594_regulator_irq_data), GFP_KERNEL); if (!irq_data) return -ENOMEM; =20 - for (i =3D 0; i < multi_phase_cnt; i++) { + for (i =3D 0; i < desc->num_multi_phase_regs; i++) { if (!buck_multi[i]) continue; =20 - rdev =3D devm_regulator_register(&pdev->dev, &multi_regs[i], &config); + rdev =3D devm_regulator_register(&pdev->dev, &desc->multi_phase_regs[i], + &config); if (IS_ERR(rdev)) return dev_err_probe(tps->dev, PTR_ERR(rdev), "failed to register %s regulator\n", @@ -682,89 +721,74 @@ static int tps6594_regulator_probe(struct platform_de= vice *pdev) buck_idx =3D 2; =20 error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, - bucks_irq_types[buck_idx], - nr_types, &irq_idx); + desc->bucks_irq_types[buck_idx], + desc->num_irq_types, &irq_idx); if (error) return error; =20 error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, - bucks_irq_types[buck_idx + 1], - nr_types, &irq_idx); + desc->bucks_irq_types[buck_idx + 1], + desc->num_irq_types, &irq_idx); if (error) return error; =20 if (i =3D=3D MULTI_BUCK123 || i =3D=3D MULTI_BUCK1234) { error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, - bucks_irq_types[buck_idx + 2], - nr_types, &irq_idx); + desc->bucks_irq_types[buck_idx + 2], + desc->num_irq_types, + &irq_idx); if (error) return error; } if (i =3D=3D MULTI_BUCK1234) { error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, - bucks_irq_types[buck_idx + 3], - nr_types, &irq_idx); + desc->bucks_irq_types[buck_idx + 3], + desc->num_irq_types, + &irq_idx); if (error) return error; } } =20 - for (i =3D 0; i < nr_buck; i++) { + for (i =3D 0; i < desc->num_buck_regs; i++) { if (buck_configured[i]) continue; =20 - const struct regulator_desc *buck_cfg =3D (tps->chip_id =3D=3D TPS65224)= ? - tps65224_buck_regs : buck_regs; - - rdev =3D devm_regulator_register(&pdev->dev, &buck_cfg[i], &config); + rdev =3D devm_regulator_register(&pdev->dev, &desc->buck_regs[i], &confi= g); if (IS_ERR(rdev)) return dev_err_probe(tps->dev, PTR_ERR(rdev), "failed to register %s regulator\n", pdev->name); =20 error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, - bucks_irq_types[i], nr_types, &irq_idx); + desc->bucks_irq_types[i], + desc->num_irq_types, &irq_idx); if (error) return error; } =20 - /* LP8764 doesn't have LDO */ - if (tps->chip_id !=3D LP8764) { - for (i =3D 0; i < nr_ldo; i++) { - rdev =3D devm_regulator_register(&pdev->dev, &ldo_regs[i], &config); - if (IS_ERR(rdev)) - return dev_err_probe(tps->dev, PTR_ERR(rdev), - "failed to register %s regulator\n", - pdev->name); - - error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, - ldos_irq_types[i], nr_types, - &irq_idx); - if (error) - return error; - } - } + for (i =3D 0; i < desc->num_ldo_regs; i++) { + rdev =3D devm_regulator_register(&pdev->dev, &desc->ldo_regs[i], &config= ); + if (IS_ERR(rdev)) + return dev_err_probe(tps->dev, PTR_ERR(rdev), + "failed to register %s regulator\n", + pdev->name); =20 - if (tps->chip_id =3D=3D TPS65224) { - irq_types =3D tps65224_ext_regulator_irq_types; - irq_count =3D ARRAY_SIZE(tps65224_ext_regulator_irq_types); - } else { - irq_types =3D tps6594_ext_regulator_irq_types; - if (tps->chip_id =3D=3D LP8764) - irq_count =3D ARRAY_SIZE(tps6594_ext_regulator_irq_types); - else - /* TPS6593 supports only VCCA OV and UV */ - irq_count =3D 2; + error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, + desc->ldos_irq_types[i], + desc->num_irq_types, &irq_idx); + if (error) + return error; } =20 irq_ext_reg_data =3D devm_kmalloc_array(tps->dev, - irq_count, + desc->num_ext_irqs, sizeof(struct tps6594_ext_regulator_irq_data), GFP_KERNEL); if (!irq_ext_reg_data) return -ENOMEM; =20 - for (i =3D 0; i < irq_count; ++i) { - irq_type =3D &irq_types[i]; + for (i =3D 0; i < desc->num_ext_irqs; ++i) { + irq_type =3D &desc->ext_irq_types[i]; irq =3D platform_get_irq_byname(pdev, irq_type->irq_name); if (irq < 0) return -EINVAL; @@ -782,6 +806,7 @@ static int tps6594_regulator_probe(struct platform_devi= ce *pdev) "failed to request %s IRQ %d\n", irq_type->irq_name, irq); } + return 0; } =20 --=20 2.39.5 From nobody Wed Oct 8 02:01:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3C492E4242; Thu, 3 Jul 2025 11:32:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751542349; cv=none; b=DrA53yEfHN7cxHQvR0F81NeKEhcEKm0pYVDEjMnfv42CEf1Ai62nHKBBqQ6An1/PCuNWP4pPc2CqgkCK9aGqVEKQTTb/XPJQQzam+ZcJK6MrWN0Kq56EtSt9/kW/qG9YyVWTNHpzn133OfaJ5XbuONIr9yNJ+S9aO7oAxwvJ4wc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751542349; c=relaxed/simple; bh=3KImKcixsymPQbWmcMwg6wTAMzEv4bSW9MSSSpiBfvU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TWJahP6h25L9u1sSchNIUv7IST9WbmHYKvFp/79RZwmxpeIThhtsOQLe1wTPjYA4+wrDNp9mI4PpUcROsAajBcRvy/2EcprsJ9UVJaPQr7WLMaJjJvqBABqo/ETwOPE9+gD+ot8vGfuB3Th0g8YvVx5q6IqmRpK80Psv+pJ353U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iZ2J6VF1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iZ2J6VF1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 27914C4CEED; Thu, 3 Jul 2025 11:32:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751542348; bh=3KImKcixsymPQbWmcMwg6wTAMzEv4bSW9MSSSpiBfvU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iZ2J6VF1Fhuzs0vcSA/IkbtEitA0bPewCNAriCsgNzSYiQk+1Rr/81nsNukXLPADv Hs323Yc1ZLu7W8yUIYbRBiXCBGCztzvFmkqbh8D0AaGwxEZpy1ofNh/kNPK2k2M1Aw yabRp7oqoGBYi5dGS2/mZhJ91vfDzMaY+tO2nQWgxHi41ND7Hn6lfVv/iyHuXHgWv/ T9/MHCX6qvfZqvUS8T6hnTEWeItLMaV5/rr5iljxk7yzcVekoy5aUT4eX+xHr+UmHs VQGOGEOiqz6za2jB36Rbyva8pAn7fYNMEH5aUblexZgMKZqTr8F2PjNqXtNHcMy4Zf gyQDSunOLnrvg== From: Michael Walle To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Greg Kroah-Hartman , Linus Walleij , Liam Girdwood , Mark Brown , Julien Panis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Michael Walle Subject: [PATCH v3 8/8] regulator: tps6594-regulator: Add TI TPS652G1 PMIC regulators Date: Thu, 3 Jul 2025 13:31:53 +0200 Message-Id: <20250703113153.2447110-9-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250703113153.2447110-1-mwalle@kernel.org> References: <20250703113153.2447110-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TI TPS652G1 is a stripped down version of the TPS65224 PMIC. It doesn't feature the multiphase buck converter nor any voltage monitoring. Due to the latter there are no interrupts serviced. In case of the TPS652G1 any interrupt related setup is just skipped. Signed-off-by: Michael Walle Acked-by: Mark Brown --- drivers/regulator/tps6594-regulator.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/regulator/tps6594-regulator.c b/drivers/regulator/tps6= 594-regulator.c index 39adb2db6de8..ab882daec7c5 100644 --- a/drivers/regulator/tps6594-regulator.c +++ b/drivers/regulator/tps6594-regulator.c @@ -577,6 +577,13 @@ static const struct tps6594_regulator_desc tps65224_re= g_desc =3D { .num_ext_irqs =3D ARRAY_SIZE(tps65224_ext_regulator_irq_types), }; =20 +static const struct tps6594_regulator_desc tps652g1_reg_desc =3D { + .ldo_regs =3D tps65224_ldo_regs, + .num_ldo_regs =3D ARRAY_SIZE(tps65224_ldo_regs), + .buck_regs =3D tps65224_buck_regs, + .num_buck_regs =3D ARRAY_SIZE(tps65224_buck_regs), +}; + static const struct tps6594_regulator_desc tps6594_reg_desc =3D { .multi_phase_regs =3D tps6594_multi_regs, .num_multi_phase_regs =3D ARRAY_SIZE(tps6594_multi_regs), @@ -627,6 +634,9 @@ static int tps6594_regulator_probe(struct platform_devi= ce *pdev) case TPS65224: desc =3D &tps65224_reg_desc; break; + case TPS652G1: + desc =3D &tps652g1_reg_desc; + break; case TPS6594: case TPS6593: desc =3D &tps6594_reg_desc; @@ -716,6 +726,9 @@ static int tps6594_regulator_probe(struct platform_devi= ce *pdev) "failed to register %s regulator\n", pdev->name); =20 + if (!desc->num_irq_types) + continue; + /* config multiphase buck12+buck34 */ if (i =3D=3D MULTI_BUCK12_34) buck_idx =3D 2; @@ -759,6 +772,9 @@ static int tps6594_regulator_probe(struct platform_devi= ce *pdev) return dev_err_probe(tps->dev, PTR_ERR(rdev), "failed to register %s regulator\n", pdev->name); =20 + if (!desc->num_irq_types) + continue; + error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, desc->bucks_irq_types[i], desc->num_irq_types, &irq_idx); @@ -773,6 +789,9 @@ static int tps6594_regulator_probe(struct platform_devi= ce *pdev) "failed to register %s regulator\n", pdev->name); =20 + if (!desc->num_irq_types) + continue; + error =3D tps6594_request_reg_irqs(pdev, rdev, irq_data, desc->ldos_irq_types[i], desc->num_irq_types, &irq_idx); --=20 2.39.5