From nobody Wed Oct 8 04:09:23 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B78F2E6D04; Thu, 3 Jul 2025 11:02:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751540581; cv=none; b=Pf56NtFIn1Fp+CuuqKjD3jXgim8znsYXGXrufFeVxCjq5LiokZBIhoOBBvLeJLHyG+7cKWnmjtGXvDcbP9RHqsR5j2oQVw4xYo5+vXk3LQ/I2PSmxQlpJDehVBwaj4gAyM8hkjzYR0yTIwe98Ajv3mkJXO3pvFyWezeUW4IgX8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751540581; c=relaxed/simple; bh=qZTsC6PG17SyDIrpz6CO07nqG1IcC1CJAMLmRzacT/E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DYBbPFbpCfYiu4Gq9ajXedZcDb58RBhJxZMtbAscrzXWzbuvsBUUm5n+Pd5m2rDwLJtpIXw1W7R8xpQQlpUkPoNlM3enHrezBz2fEPgjBrfpMkbDAFEsVoRX1cWA05HSScjHJrUqxe8h/3y2umDRghBP/rg482iYSioR4FQ8vLM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=kBIutfYp; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="kBIutfYp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1751540577; bh=qZTsC6PG17SyDIrpz6CO07nqG1IcC1CJAMLmRzacT/E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kBIutfYppfL5oGnPUgnwOrFYXdct1z3pW9aDEn9430kaK/ezReIjTcmc1+yuG60lD mTKfbWzPwKxR4+oNNY3tXno1XYEG2kO5BzilsDu1ZhjRHcC3hIvW8bLXLfEPeeuCha +hBc5KX2DpL4KzKO14P+8cJjiU/foeP0mGV/yvuOWKeO2si2LBRhhwMrEV3bn85hqE c3ed0VsTwk90D/5PqFmEIWJ4dJL0RkwJ6rLvbtaWlaaPpHeOafL93R2ShVgmpakQ3p xLnGv5pmN/KsRgZlk3/tlkGEGcmBwRZn/r5iOxzdSJoo+ZI6pRnHuEOXgUT0dzb0NP PmbKq+B5fLsTA== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7D75317E0F3C; Thu, 3 Jul 2025 13:02:56 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ulf.hansson@linaro.org, y.oudjana@protonmail.com, fshao@chromium.org, wenst@chromium.org, lihongbo22@huawei.com, mandyjh.liu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com Subject: [PATCH 06/10] pmdomain: mediatek: Move ctl sequences out of power_on/off functions Date: Thu, 3 Jul 2025 13:02:43 +0200 Message-ID: <20250703110247.99927-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250703110247.99927-1-angelogioacchino.delregno@collabora.com> References: <20250703110247.99927-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation to support power domains of new SoCs and the modem power domains for both new and already supported chips, move the generic control power sequences out of the scpsys_power_on() and scpsys_power_off() and put them in new scpsys_ctl_pwrseq_on(), scpsys_ctl_pewseq_off() functions. Signed-off-by: AngeloGioacchino Del Regno --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 57 ++++++++++++++-------- 1 file changed, 38 insertions(+), 19 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/= mediatek/mtk-pm-domains.c index dd7f5f377271..92a3b523002b 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -244,11 +244,45 @@ static int scpsys_regulator_disable(struct regulator = *supply) return supply ? regulator_disable(supply) : 0; } =20 +static int scpsys_ctl_pwrseq_on(struct scpsys_domain *pd) +{ + struct scpsys *scpsys =3D pd->scpsys; + bool tmp; + int ret; + + /* subsys power on */ + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); + + /* wait until PWR_ACK =3D 1 */ + ret =3D readx_poll_timeout(scpsys_domain_is_on, pd, tmp, tmp, MTK_POLL_DE= LAY_US, + MTK_POLL_TIMEOUT); + if (ret < 0) + return ret; + + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); + + return 0; +} + +static void scpsys_ctl_pwrseq_off(struct scpsys_domain *pd) +{ + struct scpsys *scpsys =3D pd->scpsys; + + /* subsys power off */ + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); +} + static int scpsys_power_on(struct generic_pm_domain *genpd) { struct scpsys_domain *pd =3D container_of(genpd, struct scpsys_domain, ge= npd); struct scpsys *scpsys =3D pd->scpsys; - bool tmp; int ret; =20 ret =3D scpsys_regulator_enable(pd->supply); @@ -263,20 +297,10 @@ static int scpsys_power_on(struct generic_pm_domain *= genpd) regmap_clear_bits(scpsys->base, pd->data->ext_buck_iso_offs, pd->data->ext_buck_iso_mask); =20 - /* subsys power on */ - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); - - /* wait until PWR_ACK =3D 1 */ - ret =3D readx_poll_timeout(scpsys_domain_is_on, pd, tmp, tmp, MTK_POLL_DE= LAY_US, - MTK_POLL_TIMEOUT); - if (ret < 0) + ret =3D scpsys_ctl_pwrseq_on(pd); + if (ret) goto err_pwr_ack; =20 - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); - /* * In few Mediatek platforms(e.g. MT6779), the bus protect policy is * stricter, which leads to bus protect release must be prior to bus @@ -342,12 +366,7 @@ static int scpsys_power_off(struct generic_pm_domain *= genpd) =20 clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); =20 - /* subsys power off */ - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); + scpsys_ctl_pwrseq_off(pd); =20 /* wait until PWR_ACK =3D 0 */ ret =3D readx_poll_timeout(scpsys_domain_is_on, pd, tmp, !tmp, MTK_POLL_D= ELAY_US, --=20 2.49.0