From nobody Wed Oct 8 00:25:01 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 708542F85FB; Thu, 3 Jul 2025 19:31:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751571067; cv=pass; b=nG4J9EWFfYnLVmOVnscsLamPYDb91DroyKrwtmm56IQ3+iEHZNpEGxW8OtBpq+izO/v+j/eZnHkVrBfqSINe3YEM3YiC2zedK/MysDl8s67HlSdXym93DgK2CliARsQrIU4CK651gWwHhloPsa6RjdRecvu2NQqsFLB0sIzQy5k= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751571067; c=relaxed/simple; bh=aEMkXvUthUB8l3Ze03TQRSrmmhr7dlle2OHZ3th5mnM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XEsYDrGkWYzIeELVw/wPQJpKaMuYfw0mYdb3Lno66bwPDd1Ly1+HG1QwmqC/ffv/rn5v9fIzNcjd4Ku+VigsUCuG5IPnBM/E7bSwbdGIEIxEmASGc8KuYBwnsg+6/+Z70CHpoQgPd18s4xgL862R7t7rOCMKxk0tSp2Ryxkofko= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=daniel.almeida@collabora.com header.b=DsLACnb1; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=daniel.almeida@collabora.com header.b="DsLACnb1" ARC-Seal: i=1; a=rsa-sha256; t=1751571046; cv=none; d=zohomail.com; s=zohoarc; b=QxNiabCTIjq66TjKplNEJZRT3eW7MFGF51oR+dFu8wldiBwXtrSdfSMQWGISpIOLP1aPyQwXV027stt8nY2S8GJt40xqpu7KzjB7A37pD1joPsOmzjdloRyejmqJTzKUSGAACx0m9R0aAUW7rXBLvmuNofNXmTdoPMIyGaflV+g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751571046; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=gfN2hhL3lfXYyJIhQf1mFRJtLEy5tuC2aFyzf06oeU0=; b=PYWT19QVCYTG1XNkrQFvcejv0axFlW4AzkhTT8Ti2O4CxXRQj0iwiKzw+miyIf+gEN98qKryVWEcC6q7AdUPcXF84jg6fRDFSmQWxqY2OAflcq5fnuyPoMNv08Fb+DIRWtkp3clJXeS7P1D5DQLKtOWo2LpB+5/153r5z4caJkg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=daniel.almeida@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1751571046; s=zohomail; d=collabora.com; i=daniel.almeida@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=gfN2hhL3lfXYyJIhQf1mFRJtLEy5tuC2aFyzf06oeU0=; b=DsLACnb1nvR/BR50ZlHNL2D2aJjnuySqT103Yvp6oP7CGHPzt8MufVRrsL3iCUV4 d/GuJgJx9u0ASYw2FlEgjfk6AbHJwXOfSu6jwA4E32SxO7we2i1dsU2Reem0CYhnWaJ AQSXnddmmw9IHWJny0c2VMvQsWc0seGsyVRL+hLw= Received: by mx.zohomail.com with SMTPS id 1751571043331493.12856796447954; Thu, 3 Jul 2025 12:30:43 -0700 (PDT) From: Daniel Almeida Date: Thu, 03 Jul 2025 16:29:59 -0300 Subject: [PATCH v6 1/6] rust: irq: add irq module Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250703-topics-tyr-request_irq-v6-1-74103bdc7c52@collabora.com> References: <20250703-topics-tyr-request_irq-v6-0-74103bdc7c52@collabora.com> In-Reply-To: <20250703-topics-tyr-request_irq-v6-0-74103bdc7c52@collabora.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Greg Kroah-Hartman , "Rafael J. Wysocki" , Thomas Gleixner , Benno Lossin , Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Benno Lossin Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org, Daniel Almeida X-Mailer: b4 0.14.2 X-ZohoMailClient: External Add the IRQ module. Future patches will then introduce support for IRQ registrations and handlers. Signed-off-by: Daniel Almeida Reviewed-by: Alice Ryhl --- rust/kernel/irq.rs | 11 +++++++++++ rust/kernel/lib.rs | 1 + 2 files changed, 12 insertions(+) diff --git a/rust/kernel/irq.rs b/rust/kernel/irq.rs new file mode 100644 index 0000000000000000000000000000000000000000..fae7b15effc80c936d6bffbd5b4= 150000d6c2898 --- /dev/null +++ b/rust/kernel/irq.rs @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! IRQ abstractions. +//! +//! An IRQ is an interrupt request from a device. It is used to get the CP= U's +//! attention so it can service a hardware event in a timely manner. +//! +//! The current abstractions handle IRQ requests and handlers, i.e.: it al= lows +//! drivers to register a handler for a given IRQ line. +//! +//! C header: [`include/linux/device.h`](srctree/include/linux/interrupt.h) diff --git a/rust/kernel/lib.rs b/rust/kernel/lib.rs index 6b4774b2b1c37f4da1866e993be6230bc6715841..28dd0ef077fa47211fc0eae899a= e4ac82fb6be24 100644 --- a/rust/kernel/lib.rs +++ b/rust/kernel/lib.rs @@ -81,6 +81,7 @@ pub mod init; pub mod io; pub mod ioctl; +pub mod irq; pub mod jump_label; #[cfg(CONFIG_KUNIT)] pub mod kunit; --=20 2.50.0 From nobody Wed Oct 8 00:25:01 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACF3C2F2736; Thu, 3 Jul 2025 19:31:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751571076; cv=pass; b=BQ2yyBl3KTi9g0eonV9gwBXoZp7BtMypWVKwYBrbzHB5/6iEdY+/i8Oy5OTdyC39mmtWyZx2otbfnyVtpBVjCwKXIC/uQpIX/tK36fruSBgH9jZJv5rWG79KnzbdKW1xM/+wKNcKgWU4mot4WIesaasfL5sm+xKK+sYT1Ycvtzs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751571076; c=relaxed/simple; bh=FN+vUZHISonksf0avqO410vexj0U6dH3mX8aymZfaNY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ufGFoF2dmDH33An3T+03/4QkY78p5y57MYkbsnIYNatt/SjJSLOhCW+tt3sCwxvvAQhTL56AXHXe+l7qmBOJJ796iQaH5Aha96s3V8GEKxA6wNH2u52eMgwy6Clak33wn86H390HpQ0EGKRzCQZiXyNteliKbMrc2402b+TetWA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=daniel.almeida@collabora.com header.b=VBp/1wBm; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=daniel.almeida@collabora.com header.b="VBp/1wBm" ARC-Seal: i=1; a=rsa-sha256; t=1751571050; cv=none; d=zohomail.com; s=zohoarc; b=C1e613ap+8bZOSYDqaWav5Uni3LvVQvymVpCvYDY6KjSqm5MBoKS+vnJEv9Mazn8rOQgdBDKGQr2M+I+B1XsEXDlM7Iwmn5h+/HDbE0ve3leK5t5QJL9G5nbwuyhiOm53USRAxJEwvp84IESpG+YxA/6VIZrQ2P76EHusN+CBMw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751571050; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=alrRo8Nvsmb0Eo4JXfNn9cIOlYnb8zdQKewhwjmgfsI=; b=i+JAsoUrss7z73ptLOLaB4cPOd9PIRUZ5wLzyxHuLwSmHbWOwgEOLMKB+Jn2pMnVoO56Hu5PnP7BDMUJvX8/w6TZpM4/ZYmwZ+pXXeStq8t5OnLShwi/6mW2MKxuir/kOE+qE0znYXv9rcWxOX1NEiC/JpQbh2j6tFvbqfIctXM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=daniel.almeida@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1751571050; s=zohomail; d=collabora.com; i=daniel.almeida@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=alrRo8Nvsmb0Eo4JXfNn9cIOlYnb8zdQKewhwjmgfsI=; b=VBp/1wBmaYsblUSk7ICEeteA8s/DppKgO+J2GegWtroOiZ54G4Isc7io5KlGYL1d +8jO+18JotJrH/oEXYx6t1mNE1LA8y2wulegGmTdsUeDyt3T6Z+IvTZ29UAa2nYpJzx 4igAq3nrcDEZjuXHv/8oS3G4mjtOJ4XuSfAVJ824= Received: by mx.zohomail.com with SMTPS id 1751571047607576.0930779126198; Thu, 3 Jul 2025 12:30:47 -0700 (PDT) From: Daniel Almeida Date: Thu, 03 Jul 2025 16:30:00 -0300 Subject: [PATCH v6 2/6] rust: irq: add flags module Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250703-topics-tyr-request_irq-v6-2-74103bdc7c52@collabora.com> References: <20250703-topics-tyr-request_irq-v6-0-74103bdc7c52@collabora.com> In-Reply-To: <20250703-topics-tyr-request_irq-v6-0-74103bdc7c52@collabora.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Greg Kroah-Hartman , "Rafael J. Wysocki" , Thomas Gleixner , Benno Lossin , Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Benno Lossin Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org, Daniel Almeida X-Mailer: b4 0.14.2 X-ZohoMailClient: External Manipulating IRQ flags (i.e.: IRQF_*) will soon be necessary, specially to register IRQ handlers through bindings::request_irq(). Add a kernel::irq::Flags for that purpose. Signed-off-by: Daniel Almeida Reviewed-by: Alice Ryhl --- rust/kernel/irq.rs | 3 ++ rust/kernel/irq/flags.rs | 102 +++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 105 insertions(+) diff --git a/rust/kernel/irq.rs b/rust/kernel/irq.rs index fae7b15effc80c936d6bffbd5b4150000d6c2898..9abd9a6dc36f3e3ecc1f92ad7b0= 040176b56a079 100644 --- a/rust/kernel/irq.rs +++ b/rust/kernel/irq.rs @@ -9,3 +9,6 @@ //! drivers to register a handler for a given IRQ line. //! //! C header: [`include/linux/device.h`](srctree/include/linux/interrupt.h) + +/// Flags to be used when registering IRQ handlers. +pub mod flags; diff --git a/rust/kernel/irq/flags.rs b/rust/kernel/irq/flags.rs new file mode 100644 index 0000000000000000000000000000000000000000..3cfaef65ae14f6c02f55ebcf4d5= 2450c0052df30 --- /dev/null +++ b/rust/kernel/irq/flags.rs @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright 2025 Collabora ltd. + +use crate::bindings; + +/// Flags to be used when registering IRQ handlers. +/// +/// They can be combined with the operators `|`, `&`, and `!`. +#[derive(Clone, Copy, PartialEq, Eq)] +pub struct Flags(u64); + +impl Flags { + pub(crate) fn into_inner(self) -> u64 { + self.0 + } +} + +impl core::ops::BitOr for Flags { + type Output =3D Self; + fn bitor(self, rhs: Self) -> Self::Output { + Self(self.0 | rhs.0) + } +} + +impl core::ops::BitAnd for Flags { + type Output =3D Self; + fn bitand(self, rhs: Self) -> Self::Output { + Self(self.0 & rhs.0) + } +} + +impl core::ops::Not for Flags { + type Output =3D Self; + fn not(self) -> Self::Output { + Self(!self.0) + } +} + +/// Use the interrupt line as already configured. +pub const TRIGGER_NONE: Flags =3D Flags(bindings::IRQF_TRIGGER_NONE as u64= ); + +/// The interrupt is triggered when the signal goes from low to high. +pub const TRIGGER_RISING: Flags =3D Flags(bindings::IRQF_TRIGGER_RISING as= u64); + +/// The interrupt is triggered when the signal goes from high to low. +pub const TRIGGER_FALLING: Flags =3D Flags(bindings::IRQF_TRIGGER_FALLING = as u64); + +/// The interrupt is triggered while the signal is held high. +pub const TRIGGER_HIGH: Flags =3D Flags(bindings::IRQF_TRIGGER_HIGH as u64= ); + +/// The interrupt is triggered while the signal is held low. +pub const TRIGGER_LOW: Flags =3D Flags(bindings::IRQF_TRIGGER_LOW as u64); + +/// Allow sharing the irq among several devices. +pub const SHARED: Flags =3D Flags(bindings::IRQF_SHARED as u64); + +/// Set by callers when they expect sharing mismatches to occur. +pub const PROBE_SHARED: Flags =3D Flags(bindings::IRQF_PROBE_SHARED as u64= ); + +/// Flag to mark this interrupt as timer interrupt. +pub const TIMER: Flags =3D Flags(bindings::IRQF_TIMER as u64); + +/// Interrupt is per cpu. +pub const PERCPU: Flags =3D Flags(bindings::IRQF_PERCPU as u64); + +/// Flag to exclude this interrupt from irq balancing. +pub const NOBALANCING: Flags =3D Flags(bindings::IRQF_NOBALANCING as u64); + +/// Interrupt is used for polling (only the interrupt that is registered +/// first in a shared interrupt is considered for performance reasons). +pub const IRQPOLL: Flags =3D Flags(bindings::IRQF_IRQPOLL as u64); + +/// Interrupt is not reenabled after the hardirq handler finished. Used by +/// threaded interrupts which need to keep the irq line disabled until the +/// threaded handler has been run. +pub const ONESHOT: Flags =3D Flags(bindings::IRQF_ONESHOT as u64); + +/// Do not disable this IRQ during suspend. Does not guarantee that this +/// interrupt will wake the system from a suspended state. +pub const NO_SUSPEND: Flags =3D Flags(bindings::IRQF_NO_SUSPEND as u64); + +/// Force enable it on resume even if [`NO_SUSPEND`] is set. +pub const FORCE_RESUME: Flags =3D Flags(bindings::IRQF_FORCE_RESUME as u64= ); + +/// Interrupt cannot be threaded. +pub const NO_THREAD: Flags =3D Flags(bindings::IRQF_NO_THREAD as u64); + +/// Resume IRQ early during syscore instead of at device resume time. +pub const EARLY_RESUME: Flags =3D Flags(bindings::IRQF_EARLY_RESUME as u64= ); + +/// If the IRQ is shared with a [`NO_SUSPEND`] user, execute this interrupt +/// handler after suspending interrupts. For system wakeup devices users +/// need to implement wakeup detection in their interrupt handlers. +pub const COND_SUSPEND: Flags =3D Flags(bindings::IRQF_COND_SUSPEND as u64= ); + +/// Don't enable IRQ or NMI automatically when users request it. Users will +/// enable it explicitly by `enable_irq` or `enable_nmi` later. +pub const NO_AUTOEN: Flags =3D Flags(bindings::IRQF_NO_AUTOEN as u64); + +/// Exclude from runnaway detection for IPI and similar handlers, depends = on +/// `PERCPU`. +pub const NO_DEBUG: Flags =3D Flags(bindings::IRQF_NO_DEBUG as u64); --=20 2.50.0 From nobody Wed Oct 8 00:25:01 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5569E2FEE34; Thu, 3 Jul 2025 19:31:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751571084; cv=pass; b=AzkkFmqZJR6WPGV0OIIhLYpNFGjTdqNrRYwmY6sfkIY2ejZy2smtkUIyMcjo8XOVTliia+0GV8A1EQTYsOxXESObl52U+WWEr+Ocv2D3g4yPPx/YEt34M5HakcXm4WNc9JCEBnXwjtV+VXD4QLT8gQ1UxBd8zwO9krVAJq95/wg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751571084; c=relaxed/simple; bh=R141UbZ2MJ+Lmd8p/5NuzNewQfpmG80jwub4dwATn98=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fjb/o7VTC2YVoDF0ZmqxVp1emzUG4eN02uub/OWNT366DMw9WSCPS/dJrF58U4DDIt/+/9uFgV2oVdYTXihxteIPDFAKCInhO2mC87GoDafBUuNhWWPcMWSh/wTvryvH6Z7wa5QnOKlDNsxwBSnn9pXZxyleU8G7jXMyjSjZUw8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=daniel.almeida@collabora.com header.b=QYWQlwd3; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=daniel.almeida@collabora.com header.b="QYWQlwd3" ARC-Seal: i=1; a=rsa-sha256; t=1751571054; cv=none; d=zohomail.com; s=zohoarc; b=V9g3C6c2BG7NoM1zqAQBgI43XlPCDTsXEch5jwn2/F5ue99WSBer+npmmEFKDEvp9+5ivG9xREO2J0r0ExNU3Rcy1z/l/Z5AKLVIiG9jAIH4ndEz52/08AYStuzcvc1UA3dbk82JWYrjNnGaWzN889fi+UDGaHsuUXMgqbtpPTs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751571054; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=7tzGk2bWskELc3lBl6isyxFZIxOYyDuIcmJBxgT3gsA=; b=mJzvDbVhT8NAf0uOdNPEisfKUbgFqvWU9jx3d/EWYbrGQ4nzUQtU3bYc0/gY0Eqs7I6ZzZ08MBS/TpCmgJiVEW0w0agVxVJHLdLDVnP/IN+IngYXMhtBMGMFPZBubbc/4+ZRqQSjMFta8raSkrgpVKIRQQ3xpLkX0ubxxxqsF9M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=daniel.almeida@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1751571054; s=zohomail; d=collabora.com; i=daniel.almeida@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=7tzGk2bWskELc3lBl6isyxFZIxOYyDuIcmJBxgT3gsA=; b=QYWQlwd3qHW730BCZQ8kv224QN8W8Yj5axCCS7CSCqSZmQuEn6ZcD0vPfFfePIDL 76nyEj83m+bgB1cq/ctewk9qerarfsFy3ET8nB4d2l9Ud4tLdy2ZKnfxSixEreruA+s 25M2nhWTZsZOJDoOjWcMH0puFX5qhVq4erv/k7Eg= Received: by mx.zohomail.com with SMTPS id 17515710517921006.8159695544626; Thu, 3 Jul 2025 12:30:51 -0700 (PDT) From: Daniel Almeida Date: Thu, 03 Jul 2025 16:30:01 -0300 Subject: [PATCH v6 3/6] rust: irq: add support for non-threaded IRQs and handlers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250703-topics-tyr-request_irq-v6-3-74103bdc7c52@collabora.com> References: <20250703-topics-tyr-request_irq-v6-0-74103bdc7c52@collabora.com> In-Reply-To: <20250703-topics-tyr-request_irq-v6-0-74103bdc7c52@collabora.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Greg Kroah-Hartman , "Rafael J. Wysocki" , Thomas Gleixner , Benno Lossin , Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Benno Lossin Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org, Daniel Almeida X-Mailer: b4 0.14.2 X-ZohoMailClient: External This patch adds support for non-threaded IRQs and handlers through irq::Registration and the irq::Handler trait. Registering an irq is dependent upon having a IrqRequest that was previously allocated by a given device. This will be introduced in subsequent patches. Signed-off-by: Daniel Almeida --- rust/bindings/bindings_helper.h | 1 + rust/helpers/helpers.c | 1 + rust/helpers/irq.c | 9 ++ rust/kernel/irq.rs | 5 + rust/kernel/irq/request.rs | 273 ++++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 289 insertions(+) diff --git a/rust/bindings/bindings_helper.h b/rust/bindings/bindings_helpe= r.h index 8cbb660e2ec218021d16e6e0144acf6f4d7cca13..da0bd23fad59a2373bd873d12ad= 69c55208aaa38 100644 --- a/rust/bindings/bindings_helper.h +++ b/rust/bindings/bindings_helper.h @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include diff --git a/rust/helpers/helpers.c b/rust/helpers/helpers.c index 393ad201befb80a9ae39866a725744ab88620fbb..e3579fc7e1cfc30c913207a4a78= b790259d7ae7a 100644 --- a/rust/helpers/helpers.c +++ b/rust/helpers/helpers.c @@ -22,6 +22,7 @@ #include "dma.c" #include "drm.c" #include "err.c" +#include "irq.c" #include "fs.c" #include "io.c" #include "jump_label.c" diff --git a/rust/helpers/irq.c b/rust/helpers/irq.c new file mode 100644 index 0000000000000000000000000000000000000000..1faca428e2c047a656dec317185= 5c1508d67e60b --- /dev/null +++ b/rust/helpers/irq.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +int rust_helper_request_irq(unsigned int irq, irq_handler_t handler, + unsigned long flags, const char *name, void *dev) +{ + return request_irq(irq, handler, flags, name, dev); +} diff --git a/rust/kernel/irq.rs b/rust/kernel/irq.rs index 9abd9a6dc36f3e3ecc1f92ad7b0040176b56a079..01bd08884b72c2a3a9460897bce= 751c732a19794 100644 --- a/rust/kernel/irq.rs +++ b/rust/kernel/irq.rs @@ -12,3 +12,8 @@ =20 /// Flags to be used when registering IRQ handlers. pub mod flags; + +/// IRQ allocation and handling. +pub mod request; + +pub use request::{Handler, IrqRequest, IrqReturn, Registration}; diff --git a/rust/kernel/irq/request.rs b/rust/kernel/irq/request.rs new file mode 100644 index 0000000000000000000000000000000000000000..4f4beaa3c7887660440b9ddc524= 14020a0d165ac --- /dev/null +++ b/rust/kernel/irq/request.rs @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright 2025 Collabora ltd. + +//! This module provides types like [`Registration`] which allow users to +//! register handlers for a given IRQ line. + +use core::marker::PhantomPinned; + +use crate::alloc::Allocator; +use crate::device::Bound; +use crate::device::Device; +use crate::devres::Devres; +use crate::error::to_result; +use crate::irq::flags::Flags; +use crate::prelude::*; +use crate::str::CStr; +use crate::sync::Arc; + +/// The value that can be returned from an IrqHandler or a ThreadedIrqHand= ler. +pub enum IrqReturn { + /// The interrupt was not from this device or was not handled. + None, + + /// The interrupt was handled by this device. + Handled, +} + +impl IrqReturn { + fn into_inner(self) -> u32 { + match self { + IrqReturn::None =3D> bindings::irqreturn_IRQ_NONE, + IrqReturn::Handled =3D> bindings::irqreturn_IRQ_HANDLED, + } + } +} + +/// Callbacks for an IRQ handler. +pub trait Handler: Sync { + /// The hard IRQ handler. + /// + /// This is executed in interrupt context, hence all corresponding + /// limitations do apply. + /// + /// All work that does not necessarily need to be executed from + /// interrupt context, should be deferred to a threaded handler. + /// See also [`ThreadedRegistration`]. + fn handle(&self) -> IrqReturn; +} + +impl Handler for Arc { + fn handle(&self) -> IrqReturn { + T::handle(self) + } +} + +impl Handler for Box { + fn handle(&self) -> IrqReturn { + T::handle(self) + } +} + +/// # Invariants +/// +/// - `self.irq` is the same as the one passed to `request_{threaded}_irq`. +/// - `cookie` was passed to `request_{threaded}_irq` as the cookie. It +/// is guaranteed to be unique by the type system, since each call to +/// `new` will return a different instance of `Registration`. +#[pin_data(PinnedDrop)] +struct RegistrationInner { + irq: u32, + cookie: *mut kernel::ffi::c_void, +} + +impl RegistrationInner { + fn synchronize(&self) { + // SAFETY: safe as per the invariants of `RegistrationInner` + unsafe { bindings::synchronize_irq(self.irq) }; + } +} + +#[pinned_drop] +impl PinnedDrop for RegistrationInner { + fn drop(self: Pin<&mut Self>) { + // SAFETY: + // + // Safe as per the invariants of `RegistrationInner` and: + // + // - The containing struct is `!Unpin` and was initialized using + // pin-init, so it occupied the same memory location for the entir= ety of + // its lifetime. + // + // Notice that this will block until all handlers finish executing, + // i.e.: at no point will &self be invalid while the handler is ru= nning. + unsafe { bindings::free_irq(self.irq, self.cookie) }; + } +} + +// SAFETY: We only use `inner` on drop, which called at most once with no +// concurrent access. +unsafe impl Sync for RegistrationInner {} + +// SAFETY: It is safe to send `RegistrationInner` across threads. +unsafe impl Send for RegistrationInner {} + +/// A request for an IRQ line for a given device. +/// +/// # Invariants +/// +/// - `=C3=ACrq` is the number of an interrupt source of `dev`. +/// - `irq` has not been registered yet. +pub struct IrqRequest<'a> { + dev: &'a Device, + irq: u32, +} + +impl<'a> IrqRequest<'a> { + /// Creates a new IRQ request for the given device and IRQ number. + /// + /// # Safety + /// + /// - `irq` should be a valid IRQ number for `dev`. + pub(crate) unsafe fn new(dev: &'a Device, irq: u32) -> Self { + IrqRequest { dev, irq } + } +} + +/// A registration of an IRQ handler for a given IRQ line. +/// +/// # Examples +/// +/// The following is an example of using `Registration`. It uses a +/// [`AtomicU32`](core::sync::AtomicU32) to provide the interior mutabilit= y. +/// +/// ``` +/// use core::sync::atomic::AtomicU32; +/// use core::sync::atomic::Ordering; +/// +/// use kernel::prelude::*; +/// use kernel::device::Bound; +/// use kernel::irq::flags; +/// use kernel::irq::Registration; +/// use kernel::irq::IrqRequest; +/// use kernel::irq::IrqReturn; +/// use kernel::sync::Arc; +/// use kernel::c_str; +/// use kernel::alloc::flags::GFP_KERNEL; +/// +/// // Declare a struct that will be passed in when the interrupt fires. T= he u32 +/// // merely serves as an example of some internal data. +/// struct Data(AtomicU32); +/// +/// // [`kernel::irq::request::Handler::handle`] takes `&self`. This examp= le +/// // illustrates how interior mutability can be used when sharing the da= ta +/// // between process context and IRQ context. +/// +/// type Handler =3D Data; +/// +/// impl kernel::irq::request::Handler for Handler { +/// // This is executing in IRQ context in some CPU. Other CPUs can st= ill +/// // try to access to data. +/// fn handle(&self) -> IrqReturn { +/// self.0.fetch_add(1, Ordering::Relaxed); +/// +/// IrqReturn::Handled +/// } +/// } +/// +/// // Registers an IRQ handler for the given IrqRequest. +/// // +/// // This is executing in process context and assumes that `request` was +/// // previously acquired from a device. +/// fn register_irq(handler: Handler, request: IrqRequest<'_>) -> Result>> { +/// let registration =3D Registration::new(request, flags::SHARED, c_s= tr!("my_device"), handler); +/// +/// let registration =3D Arc::pin_init(registration, GFP_KERNEL)?; +/// +/// // The data can be accessed from process context too. +/// registration.handler().0.fetch_add(1, Ordering::Relaxed); +/// +/// Ok(registration) +/// } +/// # Ok::<(), Error>(()) +/// ``` +/// +/// # Invariants +/// +/// * We own an irq handler using `&self.handler` as its private data. +/// +#[pin_data] +pub struct Registration { + #[pin] + inner: Devres, + + #[pin] + handler: T, + + /// Pinned because we need address stability so that we can pass a poi= nter + /// to the callback. + #[pin] + _pin: PhantomPinned, +} + +impl Registration { + /// Registers the IRQ handler with the system for the given IRQ number. + pub fn new<'a>( + request: IrqRequest<'a>, + flags: Flags, + name: &'static CStr, + handler: T, + ) -> impl PinInit + 'a { + try_pin_init!(&this in Self { + handler, + inner <- Devres::new( + request.dev, + try_pin_init!(RegistrationInner { + // SAFETY: `this` is a valid pointer to the `Registrat= ion` instance + cookie: unsafe { &raw mut (*this.as_ptr()).handler }.c= ast(), + irq: { + // SAFETY: + // - The callbacks are valid for use with request_= irq. + // - If this succeeds, the slot is guaranteed to b= e valid until the + // destructor of Self runs, which will deregister = the callbacks + // before the memory location becomes invalid. + to_result(unsafe { + bindings::request_irq( + request.irq, + Some(handle_irq_callback::), + flags.into_inner() as usize, + name.as_char_ptr(), + (&raw mut (*this.as_ptr()).handler).cast(), + ) + })?; + request.irq + } + }) + ), + _pin: PhantomPinned, + }) + } + + /// Returns a reference to the handler that was registered with the sy= stem. + pub fn handler(&self) -> &T { + &self.handler + } + + /// Wait for pending IRQ handlers on other CPUs. + /// + /// This will attempt to access the inner [`Devres`] container. + pub fn try_synchronize(&self) -> Result { + let inner =3D self.inner.try_access().ok_or(ENODEV)?; + inner.synchronize(); + Ok(()) + } + + /// Wait for pending IRQ handlers on other CPUs. + pub fn synchronize(&self, dev: &Device) -> Result { + let inner =3D self.inner.access(dev)?; + inner.synchronize(); + Ok(()) + } +} + +/// # Safety +/// +/// This function should be only used as the callback in `request_irq`. +unsafe extern "C" fn handle_irq_callback( + _irq: i32, + ptr: *mut core::ffi::c_void, +) -> core::ffi::c_uint { + // SAFETY: `ptr` is a pointer to T set in `Registration::new` + let handler =3D unsafe { &*(ptr as *const T) }; + T::handle(handler).into_inner() +} --=20 2.50.0 From nobody Wed Oct 8 00:25:01 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB63A2E6D1A; Thu, 3 Jul 2025 19:31:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751571079; cv=pass; b=TBxfDWMZSFBU8u10+PJrKnyiIq6stvHgn2y/lkmKi8Z3CMPFZLZ0fq7YjbCxQugycatue19PSHvwE5bQr3qvqePYgTwVYuAcczqrun7jZF6dMXb1d7ktoHTI7AezyXU+BqBxcQosjh5LaJE3ugvPPcVbpuRCE4fHOOUIC0Lf4qg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751571079; c=relaxed/simple; bh=eOG5pQABl4JYkNqWR/rxul6Cu7pK4+O9VAC3fnHhKUQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WB92Rr0AILBD4JgMMt1jOaSXuq5L/GCmB34F3w30kGzBZBVzquHX7i9Th6cK0cy0RATHBV/qNxM37vcvuzcpqQMcKzMAq3qOlGai01TUn1JO4ugy1hc+lW/yQLUO9cEKJ+9hk5j4kJQ9ucbyK0CtcAQsJhJO1/pFM1LLvC1fU9Q= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=daniel.almeida@collabora.com header.b=HPEmjJyY; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=daniel.almeida@collabora.com header.b="HPEmjJyY" ARC-Seal: i=1; a=rsa-sha256; t=1751571058; cv=none; d=zohomail.com; s=zohoarc; b=hrnC1gji5Fpk8HCSv9DKuJt0Nc1nnDGCx1EwCjW0Erwdh6e+FyburzGQJYKMMeipCcLkIQc/NOqrt2cObyeN4rPOi2tlsfo3k91bkYxBSLWA9FXvdItecBTLriUyNhMdOYv/ESfldfNnwjGHxjtHypsBbnKd6/KGaAJ0h1RktyA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751571058; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=osUfrQWHNPE7M9En9unBFOgkYLz7UPzVl5xTOtphdyI=; b=nLgQStmC0oF3pthS5u2r5AFk6MOjnxmaOI8osVISkkC/EKRI98BOG/wPgHXB9NYgGZo2WGYCoI1uDKXv+X6VawPqWbtO3IxU8GRl6Xsg2wW69w0/QqseB0jJm6+txJrddmM/DqOvfjE2slH55ocpUTN23+f6z3PI+ZyHj7TcxHo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=daniel.almeida@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1751571058; s=zohomail; d=collabora.com; i=daniel.almeida@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=osUfrQWHNPE7M9En9unBFOgkYLz7UPzVl5xTOtphdyI=; b=HPEmjJyYm2hteCtqdMp+VdLoQTEd5Whwjpr33yBA+KCZAwYyt/KS3V9Sh8mWEsKT QJqe1ABb8y6nsoGg6AiTxH5fhK8//Ym3TtwNhzgm2JN/bnr6CvUhekH3yGhqU14amAF ovEvcvMJJLOrIgWcd57CPuMDzTKBf3N9tEJodVIo= Received: by mx.zohomail.com with SMTPS id 1751571056420222.88377847435845; Thu, 3 Jul 2025 12:30:56 -0700 (PDT) From: Daniel Almeida Date: Thu, 03 Jul 2025 16:30:02 -0300 Subject: [PATCH v6 4/6] rust: irq: add support for threaded IRQs and handlers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250703-topics-tyr-request_irq-v6-4-74103bdc7c52@collabora.com> References: <20250703-topics-tyr-request_irq-v6-0-74103bdc7c52@collabora.com> In-Reply-To: <20250703-topics-tyr-request_irq-v6-0-74103bdc7c52@collabora.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Greg Kroah-Hartman , "Rafael J. Wysocki" , Thomas Gleixner , Benno Lossin , Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Benno Lossin Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org, Daniel Almeida X-Mailer: b4 0.14.2 X-ZohoMailClient: External This patch adds support for threaded IRQs and handlers through irq::ThreadedRegistration and the irq::ThreadedHandler trait. Threaded interrupts are more permissive in the sense that further processing is possible in a kthread. This means that said execution takes place outside of interrupt context, which is rather restrictive in many ways. Registering a threaded irq is dependent upon having an IrqRequest that was previously allocated by a given device. This will be introduced in subsequent patches. Signed-off-by: Daniel Almeida --- rust/kernel/irq.rs | 5 +- rust/kernel/irq/request.rs | 239 +++++++++++++++++++++++++++++++++++++++++= +++- 2 files changed, 241 insertions(+), 3 deletions(-) diff --git a/rust/kernel/irq.rs b/rust/kernel/irq.rs index 01bd08884b72c2a3a9460897bce751c732a19794..aaa40001bafca617c588c799bb4= 1144921595cae 100644 --- a/rust/kernel/irq.rs +++ b/rust/kernel/irq.rs @@ -16,4 +16,7 @@ /// IRQ allocation and handling. pub mod request; =20 -pub use request::{Handler, IrqRequest, IrqReturn, Registration}; +pub use request::{ + Handler, IrqRequest, IrqReturn, Registration, ThreadedHandler, Threade= dIrqReturn, + ThreadedRegistration, +}; diff --git a/rust/kernel/irq/request.rs b/rust/kernel/irq/request.rs index 4f4beaa3c7887660440b9ddc52414020a0d165ac..bd489b8d23868a3b315a4f212f9= 4a31870c9f02e 100644 --- a/rust/kernel/irq/request.rs +++ b/rust/kernel/irq/request.rs @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 // SPDX-FileCopyrightText: Copyright 2025 Collabora ltd. =20 -//! This module provides types like [`Registration`] which allow users to -//! register handlers for a given IRQ line. +//! This module provides types like [`Registration`] and +//! [`ThreadedRegistration`], which allow users to register handlers for a= given +//! IRQ line. =20 use core::marker::PhantomPinned; =20 @@ -271,3 +272,237 @@ pub fn synchronize(&self, dev: &Device) -> Res= ult { let handler =3D unsafe { &*(ptr as *const T) }; T::handle(handler).into_inner() } + +/// The value that can be returned from `ThreadedHandler::handle_irq`. +pub enum ThreadedIrqReturn { + /// The interrupt was not from this device or was not handled. + None, + + /// The interrupt was handled by this device. + Handled, + + /// The handler wants the handler thread to wake up. + WakeThread, +} + +impl ThreadedIrqReturn { + fn into_inner(self) -> u32 { + match self { + ThreadedIrqReturn::None =3D> bindings::irqreturn_IRQ_NONE, + ThreadedIrqReturn::Handled =3D> bindings::irqreturn_IRQ_HANDLE= D, + ThreadedIrqReturn::WakeThread =3D> bindings::irqreturn_IRQ_WAK= E_THREAD, + } + } +} + +/// Callbacks for a threaded IRQ handler. +pub trait ThreadedHandler: Sync { + /// The hard IRQ handler. + /// + /// This is executed in interrupt context, hence all corresponding + /// limitations do apply. All work that does not necessarily need to be + /// executed from interrupt context, should be deferred to the threaded + /// handler, i.e. [`ThreadedHandler::handle_threaded`]. + fn handle(&self) -> ThreadedIrqReturn; + + /// The threaded IRQ handler. + /// + /// This is executed in process context. The kernel creates a dedicated + /// kthread for this purpose. + fn handle_threaded(&self) -> IrqReturn; +} + +impl ThreadedHandler for Arc { + fn handle(&self) -> ThreadedIrqReturn { + T::handle(self) + } + + fn handle_threaded(&self) -> IrqReturn { + T::handle_threaded(self) + } +} + +impl ThreadedHandler for Box { + fn handle(&self) -> ThreadedIrqReturn { + T::handle(self) + } + + fn handle_threaded(&self) -> IrqReturn { + T::handle_threaded(self) + } +} + +/// A registration of a threaded IRQ handler for a given IRQ line. +/// +/// Two callbacks are required: one to handle the IRQ, and one to handle a= ny +/// other work in a separate thread. +/// +/// The thread handler is only called if the IRQ handler returns `WakeThre= ad`. +/// +/// # Examples +/// +/// The following is an example of using `ThreadedRegistration`. It uses a +/// [`AtomicU32`](core::sync::AtomicU32) to provide the interior mutabilit= y. +/// +/// ``` +/// use core::sync::atomic::AtomicU32; +/// use core::sync::atomic::Ordering; +/// +/// use kernel::prelude::*; +/// use kernel::device::Bound; +/// use kernel::irq::flags; +/// use kernel::irq::ThreadedIrqReturn; +/// use kernel::irq::ThreadedRegistration; +/// use kernel::irq::IrqRequest; +/// use kernel::irq::IrqReturn; +/// use kernel::sync::Arc; +/// use kernel::c_str; +/// use kernel::alloc::flags::GFP_KERNEL; +/// +/// // Declare a struct that will be passed in when the interrupt fires. T= he u32 +/// // merely serves as an example of some internal data. +/// struct Data(AtomicU32); +/// +/// // [`kernel::irq::request::ThreadedHandler::handle`] takes `&self`. Th= is example +/// // illustrates how interior mutability can be used when sharing the da= ta +/// // between process context and IRQ context. +/// type Handler =3D Data; +/// +/// impl kernel::irq::request::ThreadedHandler for Handler { +/// // This is executing in IRQ context in some CPU. Other CPUs can st= ill +/// // try to access the data. +/// fn handle(&self) -> ThreadedIrqReturn { +/// self.0.fetch_add(1, Ordering::Relaxed); +/// // By returning `WakeThread`, we indicate to the system that t= he +/// // thread function should be called. Otherwise, return +/// // ThreadedIrqReturn::Handled. +/// ThreadedIrqReturn::WakeThread +/// } +/// +/// // This will run (in a separate kthread) if and only if `handle` +/// // returns `WakeThread`. +/// fn handle_threaded(&self) -> IrqReturn { +/// self.0.fetch_add(1, Ordering::Relaxed); +/// IrqReturn::Handled +/// } +/// } +/// +/// // Registers a threaded IRQ handler for the given IrqRequest. +/// // +/// // This is executing in process context and assumes that `request` was +/// // previously acquired from a device. +/// fn register_threaded_irq(handler: Handler, request: IrqRequest<'_>) ->= Result>> { +/// let registration =3D ThreadedRegistration::new(request, flags::SHA= RED, c_str!("my_device"), handler); +/// +/// let registration =3D Arc::pin_init(registration, GFP_KERNEL)?; +/// +/// // The data can be accessed from process context too. +/// registration.handler().0.fetch_add(1, Ordering::Relaxed); +/// +/// Ok(registration) +/// } +/// # Ok::<(), Error>(()) +/// ``` +/// +/// # Invariants +/// +/// * We own an irq handler using `&T` as its private data. +/// +#[pin_data] +pub struct ThreadedRegistration { + #[pin] + inner: Devres, + + #[pin] + handler: T, + + /// Pinned because we need address stability so that we can pass a poi= nter + /// to the callback. + #[pin] + _pin: PhantomPinned, +} + +impl ThreadedRegistration { + /// Registers the IRQ handler with the system for the given IRQ number. + pub fn new<'a>( + request: IrqRequest<'a>, + flags: Flags, + name: &'static CStr, + handler: T, + ) -> impl PinInit + 'a { + try_pin_init!(&this in Self { + handler, + inner <- Devres::new( + request.dev, + try_pin_init!(RegistrationInner { + // SAFETY: `this` is a valid pointer to the `ThreadedR= egistration` instance. + cookie: unsafe { &raw mut (*this.as_ptr()).handler }.c= ast(), + irq: { + // SAFETY: + // - The callbacks are valid for use with request_= threaded_irq. + // - If this succeeds, the slot is guaranteed to b= e valid until the + // destructor of Self runs, which will deregister = the callbacks + // before the memory location becomes invalid. + to_result(unsafe { + bindings::request_threaded_irq( + request.irq, + Some(handle_threaded_irq_callback::), + Some(thread_fn_callback::), + flags.into_inner() as usize, + name.as_char_ptr(), + (&raw mut (*this.as_ptr()).handler).cast(), + ) + })?; + request.irq + } + }) + ), + _pin: PhantomPinned, + }) + } + + /// Returns a reference to the handler that was registered with the sy= stem. + pub fn handler(&self) -> &T { + &self.handler + } + + /// Wait for pending IRQ handlers on other CPUs. + /// + /// This will attempt to access the inner [`Devres`] container. + pub fn try_synchronize(&self) -> Result { + let inner =3D self.inner.try_access().ok_or(ENODEV)?; + inner.synchronize(); + Ok(()) + } + + /// Wait for pending IRQ handlers on other CPUs. + pub fn synchronize(&self, dev: &Device) -> Result { + let inner =3D self.inner.access(dev)?; + inner.synchronize(); + Ok(()) + } +} + +/// # Safety +/// +/// This function should be only used as the callback in `request_threaded= _irq`. +unsafe extern "C" fn handle_threaded_irq_callback( + _irq: i32, + ptr: *mut core::ffi::c_void, +) -> core::ffi::c_uint { + // SAFETY: `ptr` is a pointer to T set in `ThreadedRegistration::new` + let handler =3D unsafe { &*(ptr as *const T) }; + T::handle(handler).into_inner() +} + +/// # Safety +/// +/// This function should be only used as the callback in `request_threaded= _irq`. +unsafe extern "C" fn thread_fn_callback( + _irq: i32, + ptr: *mut core::ffi::c_void, +) -> core::ffi::c_uint { + // SAFETY: `ptr` is a pointer to T set in `ThreadedRegistration::new` + let handler =3D unsafe { &*(ptr as *const T) }; + T::handle_threaded(handler).into_inner() +} --=20 2.50.0 From nobody Wed Oct 8 00:25:01 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 261ED2FD893; Thu, 3 Jul 2025 19:31:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751571080; cv=pass; b=sg55hIBBPIPvYRFLna5kSOMpsnXLhE15QULTG0wlGkJ6Td+U891+cJXSbDj4vynA1z9kNI+dcPGMMfh8bxFCycUWv3SdQ6HKJwdh4EMNMlceiWL6HFEvp10TJPG6qNjfBWUhG3CKLYPXCJNrO2eyi+elX6p16YHPCkPko0nP8iA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751571080; c=relaxed/simple; bh=ZLDLUqsL9OVHvTzOI6upwErEbN1KGeykv+eKN7VI/Dc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kjvuaG9Kh2O6OqU71gS4DRHxL+yO74p8R6c7t5tSojkypvVUnSqgBvFQpuk4FGcosx6icHEkF3rX9UeFDaZ9rVtydT8G4NaGslfomB+mh8edEcbGw/6pUVJaDKS6I7F+HhrKPj+Mv22q5/Yackr3iSPm+FC0vf40UrR4nijwbbc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=daniel.almeida@collabora.com header.b=IuVdeHPY; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=daniel.almeida@collabora.com header.b="IuVdeHPY" ARC-Seal: i=1; a=rsa-sha256; t=1751571062; cv=none; d=zohomail.com; s=zohoarc; b=e+AZRwDOHIFeaOCKT6aPMwFCpTUF2yvll6ii+KdcvwAKKdvsmM725JBbm4qwPkW5uyzk2OZHIUayKhXrubKloYw+XZU7KmGFehb3tDBFsGYyLE1WA/AzX05q8qDL1mS0kgOIfddXVN/ZzQIRcCkKaus4fOM4glzIqjgkdiv18eM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751571062; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=sVrpre0c7L2TaP9WKeCKO5pMHXH39R9mkb4dxL3v/Eg=; b=KNMX8CUrrzDgGwBOYhDWTOLKm4rmPWO+3JDkgP0GRB1GYMGIyqyyRwrLOOJDl8uhyZhxAy/g4m6JbbCqeMBHbNMcqPZleI3y/FQ0wTyp5omLnWvOdO3LgpbX2eJ0cnCV1vDwoOmkq4zje+5x0g1arWMYh0UUNtM0DhjzxCjQnI8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=daniel.almeida@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1751571062; s=zohomail; d=collabora.com; i=daniel.almeida@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=sVrpre0c7L2TaP9WKeCKO5pMHXH39R9mkb4dxL3v/Eg=; b=IuVdeHPYvvuVWlyfjLVqsdP2GONVOUv1RxQOIa8rcPdBmGwABCdKl0T1hAKXi4sr /5OwmfLDzrr1fv/p9IIkTOmQjSl/x66ZxwjSww6/m3tKG2DbARtQUySn1VT5SfouKj/ hBTekPh61Y71hvLxkz4kEtijGdZv9yVf3j5MqElE= Received: by mx.zohomail.com with SMTPS id 17515710610641017.9677972502745; Thu, 3 Jul 2025 12:31:01 -0700 (PDT) From: Daniel Almeida Date: Thu, 03 Jul 2025 16:30:03 -0300 Subject: [PATCH v6 5/6] rust: platform: add irq accessors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250703-topics-tyr-request_irq-v6-5-74103bdc7c52@collabora.com> References: <20250703-topics-tyr-request_irq-v6-0-74103bdc7c52@collabora.com> In-Reply-To: <20250703-topics-tyr-request_irq-v6-0-74103bdc7c52@collabora.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Greg Kroah-Hartman , "Rafael J. Wysocki" , Thomas Gleixner , Benno Lossin , Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Benno Lossin Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org, Daniel Almeida X-Mailer: b4 0.14.2 X-ZohoMailClient: External These accessors can be used to retrieve a irq::Registration and irq::ThreadedRegistration from a platform device by index or name. Alternatively, drivers can retrieve an IrqRequest from a bound platform device for later use. These accessors ensure that only valid IRQ lines can ever be registered. Signed-off-by: Daniel Almeida Reviewed-by: Alice Ryhl --- rust/kernel/platform.rs | 143 ++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 142 insertions(+), 1 deletion(-) diff --git a/rust/kernel/platform.rs b/rust/kernel/platform.rs index 5b21fa517e55348582622ec10471918919502959..bfcb4962dda7ec420dc86dfa043= 11be0462ad9f2 100644 --- a/rust/kernel/platform.rs +++ b/rust/kernel/platform.rs @@ -5,8 +5,11 @@ //! C header: [`include/linux/platform_device.h`](srctree/include/linux/pl= atform_device.h) =20 use crate::{ - bindings, container_of, device, driver, + bindings, container_of, + device::{self, Bound}, + driver, error::{to_result, Result}, + irq::{self, request::IrqRequest}, of, prelude::*, str::CStr, @@ -190,6 +193,144 @@ fn as_raw(&self) -> *mut bindings::platform_device { } } =20 +macro_rules! define_irq_accessor_by_index { + ($(#[$meta:meta])* $fn_name:ident, $request_fn:ident, $reg_type:ident,= $handler_trait:ident) =3D> { + $(#[$meta])* + pub fn $fn_name( + &self, + flags: irq::flags::Flags, + index: u32, + name: &'static CStr, + handler: T, + ) -> Result, Error> + '_> { + let request =3D self.$request_fn(index)?; + + Ok(irq::$reg_type::::new( + request, + flags, + name, + handler, + )) + } + }; +} + +macro_rules! define_irq_accessor_by_name { + ($(#[$meta:meta])* $fn_name:ident, $request_fn:ident, $reg_type:ident,= $handler_trait:ident) =3D> { + $(#[$meta])* + pub fn $fn_name( + &self, + flags: irq::flags::Flags, + irq_name: &'static CStr, + name: &'static CStr, + handler: T, + ) -> Result, Error> + '_> { + let request =3D self.$request_fn(irq_name)?; + + Ok(irq::$reg_type::::new( + request, + flags, + name, + handler, + )) + } + }; +} + +impl Device { + /// Returns an [`IrqRequest`] for the IRQ at the given index, if any. + pub fn request_irq_by_index(&self, index: u32) -> Result> { + // SAFETY: `self.as_raw` returns a valid pointer to a `struct plat= form_device`. + let irq =3D unsafe { bindings::platform_get_irq(self.as_raw(), ind= ex) }; + + if irq < 0 { + return Err(Error::from_errno(irq)); + } + + // SAFETY: `irq` is guaranteed to be a valid IRQ number for `&self= `. + Ok(unsafe { IrqRequest::new(self.as_ref(), irq as u32) }) + } + + /// Returns an [`IrqRequest`] for the IRQ at the given index, but does= not print an error if the IRQ cannot be obtained. + pub fn request_optional_irq_by_index(&self, index: u32) -> Result> { + // SAFETY: `self.as_raw` returns a valid pointer to a `struct plat= form_device`. + let irq =3D unsafe { bindings::platform_get_irq_optional(self.as_r= aw(), index) }; + + if irq < 0 { + return Err(Error::from_errno(irq)); + } + + // SAFETY: `irq` is guaranteed to be a valid IRQ number for `&self= `. + Ok(unsafe { IrqRequest::new(self.as_ref(), irq as u32) }) + } + + /// Returns an [`IrqRequest`] for the IRQ with the given name, if any. + pub fn request_irq_by_name(&self, name: &'static CStr) -> Result> { + // SAFETY: `self.as_raw` returns a valid pointer to a `struct plat= form_device`. + let irq =3D unsafe { bindings::platform_get_irq_byname(self.as_raw= (), name.as_char_ptr()) }; + + if irq < 0 { + return Err(Error::from_errno(irq)); + } + + // SAFETY: `irq` is guaranteed to be a valid IRQ number for `&self= `. + Ok(unsafe { IrqRequest::new(self.as_ref(), irq as u32) }) + } + + /// Returns an [`IrqRequest`] for the IRQ with the given name, but doe= s not print an error if the IRQ cannot be obtained. + pub fn request_optional_irq_by_name(&self, name: &'static CStr) -> Res= ult> { + // SAFETY: `self.as_raw` returns a valid pointer to a `struct plat= form_device`. + let irq =3D unsafe { + bindings::platform_get_irq_byname_optional(self.as_raw(), name= .as_char_ptr()) + }; + + if irq < 0 { + return Err(Error::from_errno(irq)); + } + + // SAFETY: `irq` is guaranteed to be a valid IRQ number for `&self= `. + Ok(unsafe { IrqRequest::new(self.as_ref(), irq as u32) }) + } + + define_irq_accessor_by_index!( + /// Returns a [`irq::Registration`] for the IRQ at the given index. + irq_by_index, request_irq_by_index, Registration, Handler + ); + define_irq_accessor_by_name!( + /// Returns a [`irq::Registration`] for the IRQ with the given nam= e. + irq_by_name, request_irq_by_name, Registration, Handler + ); + define_irq_accessor_by_index!( + /// Does the same as [`Self::irq_by_index`], except that it does n= ot + /// print an error message if the IRQ cannot be obtained. + optional_irq_by_index, request_optional_irq_by_index, Registration= , Handler + ); + define_irq_accessor_by_name!( + /// Does the same as [`Self::irq_by_name`], except that it does not + /// print an error message if the IRQ cannot be obtained. + optional_irq_by_name, request_optional_irq_by_name, Registration, = Handler + ); + + define_irq_accessor_by_index!( + /// Returns a [`irq::ThreadedRegistration`] for the IRQ at the giv= en index. + threaded_irq_by_index, request_irq_by_index, ThreadedRegistration,= ThreadedHandler + ); + define_irq_accessor_by_name!( + /// Returns a [`irq::ThreadedRegistration`] for the IRQ with the g= iven name. + threaded_irq_by_name, request_irq_by_name, ThreadedRegistration, T= hreadedHandler + ); + define_irq_accessor_by_index!( + /// Does the same as [`Self::threaded_irq_by_index`], except that = it + /// does not print an error message if the IRQ cannot be obtained. + optional_threaded_irq_by_index, request_optional_irq_by_index, Thr= eadedRegistration, ThreadedHandler + ); + define_irq_accessor_by_name!( + /// Does the same as [`Self::threaded_irq_by_name`], except that it + /// does not print an error message if the IRQ cannot be obtained. + optional_threaded_irq_by_name, request_optional_irq_by_name, Threa= dedRegistration, ThreadedHandler + ); +} + // SAFETY: `Device` is a transparent wrapper of a type that doesn't depend= on `Device`'s generic // argument. kernel::impl_device_context_deref!(unsafe { Device }); --=20 2.50.0 From nobody Wed Oct 8 00:25:01 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 686DA301140; Thu, 3 Jul 2025 19:31:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751571089; cv=pass; b=HdfgZgD3BDFLlDex4Lqug76ppGn5SKW/Dj/8zPDmZRoLJ34PMFxScODvNRo+Lyx0mbCMfBS0xtKat/Z/IGLSJqlTjRHFeHRG7/0fcsNOMkiY+5IhI6uQA/gZhTdaKAjgbn8WTU15fUX0bB5e6+Ku/BAjEGA3IAsP3Jlz1ZBehO8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751571089; c=relaxed/simple; bh=9QVLNmpFlJxco9Io8+xRWl3/tkfvBnkJ5v4p1lVDt5M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bxcU+rjlijixfOd3bgVYPwWmUy+SZF9uCf8TCe907cDPb/4oKc7rLbS0LY4XKd71MVb8Sj6/IX0zSXalVGOfVZ2RW/QFS/zu9MLFG2S2WW9I+NnZLcTrU0kuzPTQ7N1ZhSR5aV8aHHa/6JHVZpDPt9lHfKJPpraQF8qDciS3CNw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=daniel.almeida@collabora.com header.b=d8wnR/LI; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=daniel.almeida@collabora.com header.b="d8wnR/LI" ARC-Seal: i=1; a=rsa-sha256; t=1751571066; cv=none; d=zohomail.com; s=zohoarc; b=nEcR6+v1uOVjI1O9P9cY7K3lU3fMAldzjK5ivz7yQPMS2lC7JhDtTZtroOgcPmgj4eyKTg3deBjMi07jwiywg1EHpwmkgtR3BKtQu7DX/DNkM1Ne+MrHjvRjyNZ8Xu2SPmnlCGI591kLUOSUGOtfkestEA4ZME2ER2ZtDIGj8kw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751571066; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=8KUHteAG14bnq4zqajKJEsvYdoQ2vrt6l/2WIKsu2Dc=; b=Z4cVVJTpSwvlkWcUm1cKlewpoHB0Ya6M2GmOQaVdtvoZwbp+tUiatOC9/MCqeeN4QI76L5ZnGs037m0iEUnbPjYvNWLaAlLbwHqaGYS+CzwFpl05ny1Fpwe+cxEkZ+47mq1TpSHNlVNfmeV3Ts7fvytIXb8TkHhTciJK8BHK0LU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=daniel.almeida@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1751571066; s=zohomail; d=collabora.com; i=daniel.almeida@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=8KUHteAG14bnq4zqajKJEsvYdoQ2vrt6l/2WIKsu2Dc=; b=d8wnR/LIwgYjb5ppI5fnfixPwvvhY/liVDH7V6JBUbHCCcc5T7Bm8G740fZKpNuG 5GIDazcQ083fq9lIygTP6l1xHju59zd6wjDeTm8iPTDeEMibQFzoepOfKX1lcKz+BWl NDhKs2qx/zlBRiLHc9BVbe7y9Eut4+P5HSUWRjqE= Received: by mx.zohomail.com with SMTPS id 1751571065262167.70532316283425; Thu, 3 Jul 2025 12:31:05 -0700 (PDT) From: Daniel Almeida Date: Thu, 03 Jul 2025 16:30:04 -0300 Subject: [PATCH v6 6/6] rust: pci: add irq accessors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250703-topics-tyr-request_irq-v6-6-74103bdc7c52@collabora.com> References: <20250703-topics-tyr-request_irq-v6-0-74103bdc7c52@collabora.com> In-Reply-To: <20250703-topics-tyr-request_irq-v6-0-74103bdc7c52@collabora.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Greg Kroah-Hartman , "Rafael J. Wysocki" , Thomas Gleixner , Benno Lossin , Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Benno Lossin Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org, Daniel Almeida X-Mailer: b4 0.14.2 X-ZohoMailClient: External These accessors can be used to retrieve a irq::Registration or a irq::ThreadedRegistration from a pci device. Alternatively, drivers can retrieve an IrqRequest from a bound PCI device for later use. These accessors ensure that only valid IRQ lines can ever be registered. Signed-off-by: Daniel Almeida Reviewed-by: Alice Ryhl --- rust/helpers/pci.c | 8 ++++++++ rust/kernel/pci.rs | 45 +++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 51 insertions(+), 2 deletions(-) diff --git a/rust/helpers/pci.c b/rust/helpers/pci.c index cd0e6bf2cc4d9b37db3a717e7a8422b054f348ec..f372a32e8fd19730563ab51500e= 8c8764854ae47 100644 --- a/rust/helpers/pci.c +++ b/rust/helpers/pci.c @@ -21,3 +21,11 @@ bool rust_helper_dev_is_pci(const struct device *dev) { return dev_is_pci(dev); } + +#ifndef CONFIG_PCI_MSI +int rust_helper_pci_irq_vector(struct pci_dev *pdev, unsigned int nvec) +{ + return pci_irq_vector(pdev, nvec); +} + +#endif diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index db0eb7eaf9b10c5316366ef16fe722a03044a517..60d37d6459518c79136535ce03c= 73a5a3097eda8 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -10,8 +10,8 @@ devres::Devres, driver, error::{to_result, Result}, - io::Io, - io::IoRaw, + io::{Io, IoRaw}, + irq::{self, request::IrqRequest}, str::CStr, types::{ARef, ForeignOwnable, Opaque}, ThisModule, @@ -413,6 +413,47 @@ pub fn iomap_region<'a>( ) -> impl PinInit, Error> + 'a { self.iomap_region_sized::<0>(bar, name) } + + /// Returns an [`IrqRequest`] for the IRQ vector at the given index, i= f any. + pub fn request_irq_by_index(&self, index: u32) -> Result> { + // SAFETY: `self.as_raw` returns a valid pointer to a `struct pci_= dev`. + let irq =3D unsafe { crate::bindings::pci_irq_vector(self.as_raw()= , index) }; + if irq < 0 { + return Err(crate::error::Error::from_errno(irq)); + } + // SAFETY: `irq` is guaranteed to be a valid IRQ number for `&self= `. + Ok(unsafe { IrqRequest::new(self.as_ref(), irq as u32) }) + } + + /// Returns a [`kernel::irq::Registration`] for the IRQ vector at the = given + /// index. + pub fn irq_by_index( + &self, + index: u32, + flags: irq::flags::Flags, + name: &'static CStr, + handler: T, + ) -> Result, Error> + '_> { + let request =3D self.request_irq_by_index(index)?; + + Ok(irq::Registration::::new(request, flags, name, handler)) + } + + /// Returns a [`kernel::irq::ThreadedRegistration`] for the IRQ vector= at + /// the given index. + pub fn threaded_irq_by_index( + &self, + index: u32, + flags: irq::flags::Flags, + name: &'static CStr, + handler: T, + ) -> Result, Error> + '_> { + let request =3D self.request_irq_by_index(index)?; + + Ok(irq::ThreadedRegistration::::new( + request, flags, name, handler, + )) + } } =20 impl Device { --=20 2.50.0