From nobody Wed Oct 8 04:04:49 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A7622E7BA8; Thu, 3 Jul 2025 10:26:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751538407; cv=none; b=FSBbEAlkHFlUCeKqH+iWkrYw2of+65+GzTM5w1zIjjg8bmuOKAxh/IPusgJF8a1HE0NbAu1DWg1hQMvnUGq20MSkSzuarwcaM3q0eEOdIHjJPIi1wmq43CD1h6wovI/vGBOavuHXFSOJCiBi5oBXoNcBd82x/SzXVm2voAIP5rk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751538407; c=relaxed/simple; bh=Z8Ojm3tu2K7fLVQhABMYAuAVcs0eLame5+RGMEmHY/A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DBswa485JuiA9+YyVbhvjJViRHH1+8LKFmtbs9Wq56KuyDCBDbJ6e38XxsjepETNfJOSyMEGCJsMCINAQqyQAYYboQyrtNdwe6kgLDoVjXHtv3m2enstqRk380/ebA9DYS64YPnwIKZImNhLMHItQXGaa+af/8C/BfKXT0zkdGI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MfnkMMKr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MfnkMMKr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28B09C4CEEB; Thu, 3 Jul 2025 10:26:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751538407; bh=Z8Ojm3tu2K7fLVQhABMYAuAVcs0eLame5+RGMEmHY/A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MfnkMMKrenQurkIeFvn7yhMz17v3mJo2uhcTlhb48vr0QZ4vDkfH/WYcPYat2b5d7 1DD4OgEd9WIQf9NiVCuh6G2UROdmiJOwDj9SKk87THYksxXlssInNkAIlRQy9feIc9 zFfhvYc3poEtHswA+LscW2L3y/SEn0sZtkEOoyu+7KwDNIP635/mSYe+lgGtbjMino LcDU0OO4FIPDX2GA4nVYuLwRimWEwXPsocJaTZqYBqsXTQIJ2am5GjcNCYnlIZPeKv J9IzZvMVau27h6lOQYvyTpIWwO5vsc16U13/w/twAFxSWw5fqPqXQN827fbLKvByV5 47yl8SPH99P+Q== From: Lorenzo Pieralisi Date: Thu, 03 Jul 2025 12:25:07 +0200 Subject: [PATCH v7 17/31] arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250703-gicv5-host-v7-17-12e71f1b3528@kernel.org> References: <20250703-gicv5-host-v7-0-12e71f1b3528@kernel.org> In-Reply-To: <20250703-gicv5-host-v7-0-12e71f1b3528@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Jonathan Cameron , Timothy Hayes , Bjorn Helgaas , "Liam R. Howlett" , Peter Maydell , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15-dev-6f78e Implement the GCIE capability as a strict boot cpu capability to detect whether architectural GICv5 support is available in HW. Plug it in with a naming consistent with the existing GICv3 CPU interface capability. Signed-off-by: Lorenzo Pieralisi Reviewed-by: Marc Zyngier Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier Acked-by: Catalin Marinas --- arch/arm64/kernel/cpufeature.c | 7 +++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 8 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 42ba76b6c8cd..2fa26129762c 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -3061,6 +3061,13 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .matches =3D has_pmuv3, }, #endif + { + .desc =3D "GICv5 CPU interface", + .type =3D ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, + .capability =3D ARM64_HAS_GICV5_CPUIF, + .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) + }, {}, }; =20 diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index a7a4d9e6e12e..8665e4cfbeab 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -36,6 +36,7 @@ HAS_GENERIC_AUTH_ARCH_QARMA3 HAS_GENERIC_AUTH_ARCH_QARMA5 HAS_GENERIC_AUTH_IMP_DEF HAS_GICV3_CPUIF +HAS_GICV5_CPUIF HAS_GIC_PRIO_MASKING HAS_GIC_PRIO_RELAXED_SYNC HAS_HCR_NV1 --=20 2.48.0