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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2025 15:56:48.5016 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b788693-fe46-4492-9ded-08ddb9810d8a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000017.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4300 Content-Type: text/plain; charset="utf-8" Creates tile memory information structure to store size and offsets for core data and program memory and memory tile memory for AIEML. Signed-off-by: Gregory Williams --- drivers/accel/amd-ai-engine/ai-engine-aie.c | 39 +++++++++ drivers/accel/amd-ai-engine/ai-engine-aieml.c | 47 ++++++++++ .../accel/amd-ai-engine/ai-engine-internal.h | 85 +++++++++++++------ drivers/accel/amd-ai-engine/ai-engine-part.c | 45 ++++++++++ 4 files changed, 192 insertions(+), 24 deletions(-) diff --git a/drivers/accel/amd-ai-engine/ai-engine-aie.c b/drivers/accel/am= d-ai-engine/ai-engine-aie.c index 5e3cb44a16c8..056db0b7be0e 100644 --- a/drivers/accel/amd-ai-engine/ai-engine-aie.c +++ b/drivers/accel/amd-ai-engine/ai-engine-aie.c @@ -16,6 +16,8 @@ #define AIE_COL_SHIFT 23U #define AIE_ROW_SHIFT 18U =20 +#define NUM_TYPES_OF_MEM 2U + /* * Register offsets */ @@ -41,6 +43,42 @@ static u32 aie_get_tile_type(struct aie_device *adev, st= ruct aie_location *loc) return AIE_TILE_TYPE_SHIMNOC; } =20 +static unsigned int aie_get_mem_info(struct aie_device *adev, + struct aie_range *range, + struct aie_part_mem *pmem) +{ + u8 start_row, num_rows; + unsigned int i; + + if (range->start.row + range->size.row <=3D 1) { + /* SHIM row only, no memories in this range */ + return 0; + } + if (!pmem) + return NUM_TYPES_OF_MEM; + + for (i =3D 0; i < NUM_TYPES_OF_MEM; i++) { + struct aie_mem *mem =3D &pmem[i].mem; + + memcpy(&mem->range, range, sizeof(*range)); + } + + start_row =3D adev->ttype_attr[AIE_TILE_TYPE_TILE].start_row; + num_rows =3D adev->ttype_attr[AIE_TILE_TYPE_TILE].num_rows; + /* Setup tile data memory information */ + pmem[0].mem.offset =3D 0; + pmem[0].mem.size =3D KBYTES(32); + pmem[0].mem.range.start.row =3D start_row; + pmem[0].mem.range.size.row =3D num_rows; + /* Setup program memory information */ + pmem[1].mem.offset =3D 0x20000; + pmem[1].mem.size =3D KBYTES(16); + pmem[1].mem.range.start.row =3D start_row; + pmem[1].mem.range.size.row =3D num_rows; + + return NUM_TYPES_OF_MEM; +} + /* aie_scan_part_clocks() - scan clocks of a partition * @apart: AI engine partition * @@ -258,6 +296,7 @@ static int aie_set_part_clocks(struct aie_partition *ap= art) } static const struct aie_tile_operations aie_ops =3D { .get_tile_type =3D aie_get_tile_type, + .get_mem_info =3D aie_get_mem_info, .scan_part_clocks =3D aie_scan_part_clocks, .set_part_clocks =3D aie_set_part_clocks, }; diff --git a/drivers/accel/amd-ai-engine/ai-engine-aieml.c b/drivers/accel/= amd-ai-engine/ai-engine-aieml.c index 328688942a6a..7730609ff7c0 100644 --- a/drivers/accel/amd-ai-engine/ai-engine-aieml.c +++ b/drivers/accel/amd-ai-engine/ai-engine-aieml.c @@ -50,6 +50,52 @@ static u32 aieml_get_tile_type(struct aie_device *adev, return AIE_TILE_TYPE_SHIMNOC; } =20 +static unsigned int aieml_get_mem_info(struct aie_device *adev, + struct aie_range *range, + struct aie_part_mem *pmem) +{ + u8 start_row, num_rows; + unsigned int i; + + if (range->start.row + range->size.row <=3D 1) { + /* SHIM row only, no memories in this range */ + return 0; + } + + if (!pmem) + return NUM_TYPES_OF_MEM; + + for (i =3D 0; i < NUM_TYPES_OF_MEM; i++) { + struct aie_mem *mem =3D &pmem[i].mem; + + memcpy(&mem->range, range, sizeof(*range)); + } + + start_row =3D adev->ttype_attr[AIE_TILE_TYPE_TILE].start_row; + num_rows =3D adev->ttype_attr[AIE_TILE_TYPE_TILE].num_rows; + /* Setup tile data memory information */ + pmem[0].mem.offset =3D 0; + pmem[0].mem.size =3D KBYTES(64); + pmem[0].mem.range.start.row =3D start_row; + pmem[0].mem.range.size.row =3D num_rows; + + /* Setup program memory information */ + pmem[1].mem.offset =3D 0x20000; + pmem[1].mem.size =3D KBYTES(16); + pmem[1].mem.range.start.row =3D start_row; + pmem[1].mem.range.size.row =3D num_rows; + + start_row =3D adev->ttype_attr[AIE_TILE_TYPE_MEMORY].start_row; + num_rows =3D adev->ttype_attr[AIE_TILE_TYPE_MEMORY].num_rows; + /* Setup memory tile memory information */ + pmem[2].mem.offset =3D 0; + pmem[2].mem.size =3D KBYTES(512); + pmem[2].mem.range.start.row =3D start_row; + pmem[2].mem.range.size.row =3D num_rows; + + return NUM_TYPES_OF_MEM; +} + /* aieml_scan_part_clocks() - scan clocks of a partition * @apart: AI engine partition * @@ -188,6 +234,7 @@ static int aieml_set_part_clocks(struct aie_partition *= apart) =20 static const struct aie_tile_operations aieml_ops =3D { .get_tile_type =3D aieml_get_tile_type, + .get_mem_info =3D aieml_get_mem_info, .scan_part_clocks =3D aieml_scan_part_clocks, .set_part_clocks =3D aieml_set_part_clocks, }; diff --git a/drivers/accel/amd-ai-engine/ai-engine-internal.h b/drivers/acc= el/amd-ai-engine/ai-engine-internal.h index 31a45575cc43..13a39c4e3331 100644 --- a/drivers/accel/amd-ai-engine/ai-engine-internal.h +++ b/drivers/accel/amd-ai-engine/ai-engine-internal.h @@ -68,30 +68,6 @@ struct aie_device; struct aie_partition; struct aie_aperture; =20 -/** - * struct aie_tile_operations - AI engine device operations - * @get_tile_type: get type of tile based on tile operation - * @scan_part_clocks: scan partition modules to check whether the modules = are - * clock gated or not, and update the soft clock states - * structure. It is required to be called when the partition - * is requested so that the driver knows which modules are - * clock gated when the partition is requested. This function - * expects the caller to apply partition lock before calling - * this function. - * @set_part_clocks: set partition modules clocks gate registers based on = the - * partition clock states bitmap. This function expects the - * caller to apply partition lock before calling this - * function. The caller function will need to set the bitmap - * on which tiles are required to be clocked on. - * Different AI engine device version has its own device - * operation. - */ -struct aie_tile_operations { - u32 (*get_tile_type)(struct aie_device *adev, struct aie_location *loc); - int (*scan_part_clocks)(struct aie_partition *apart); - int (*set_part_clocks)(struct aie_partition *apart); -}; - /** * struct aie_resource - AI engine resource structure * @bitmap: resource bitmap @@ -112,6 +88,37 @@ struct aie_range { struct aie_location size; }; =20 +/** + * struct aie_mem - AIE memory information + * @range: range of tiles of the memory + * @offset: register offset within a tile of the memory + * @size: of a the memory in one tile + */ +struct aie_mem { + struct aie_range range; + __kernel_size_t offset; + __kernel_size_t size; +}; + +/** + * struct aie_part_mem - AI engine partition memory information structure + * @apart: AI engine partition + * @mem: memory information of a type of memory + * @size: size of the total memories in the partition + * + * This structure is to keep the information of a type of memory in a + * partition. The memory information will be stored in @mem property. + * The following information will be kept: + * * memory start address offset within a tile + * * memory size + * * what tiles contain this type of memory + */ +struct aie_part_mem { + struct aie_partition *apart; + struct aie_mem mem; + size_t size; +}; + /** * struct aie_tile_attr - AI engine device tile type attributes * @start_row: start row @@ -126,6 +133,34 @@ struct aie_tile_attr { const enum aie_module_type *mods; }; =20 +/** + * struct aie_tile_operations - AI engine device operations + * @get_tile_type: get type of tile based on tile operation + * @get_mem_info: get different types of memories information + * @scan_part_clocks: scan partition modules to check whether the modules = are + * clock gated or not, and update the soft clock states + * structure. It is required to be called when the partition + * is requested so that the driver knows which modules are + * clock gated when the partition is requested. This function + * expects the caller to apply partition lock before calling + * this function. + * @set_part_clocks: set partition modules clocks gate registers based on = the + * partition clock states bitmap. This function expects the + * caller to apply partition lock before calling this + * function. The caller function will need to set the bitmap + * on which tiles are required to be clocked on. + * Different AI engine device version has its own device + * operation. + */ +struct aie_tile_operations { + u32 (*get_tile_type)(struct aie_device *adev, struct aie_location *loc); + unsigned int (*get_mem_info)(struct aie_device *adev, + struct aie_range *range, + struct aie_part_mem *pmem); + int (*scan_part_clocks)(struct aie_partition *apart); + int (*set_part_clocks)(struct aie_partition *apart); +}; + /** * struct aie_device - AI engine device structure * @apertures: list of apertures @@ -188,6 +223,7 @@ struct aie_aperture { * @range: range of partition * @cores_clk_state: bitmap to indicate the power state of core and mem ti= les * @tiles_inuse: bitmap to indicate if a tile is in use + * @pmems: pointer to partition memories types * @mlock: protection for AI engine partition operations * @freq_req: required frequency */ @@ -198,6 +234,7 @@ struct aie_partition { struct aie_range range; struct aie_resource cores_clk_state; struct aie_resource tiles_inuse; + struct aie_part_mem *pmems; struct mutex mlock; /* protection for AI engine partition operations */ u64 freq_req; }; diff --git a/drivers/accel/amd-ai-engine/ai-engine-part.c b/drivers/accel/a= md-ai-engine/ai-engine-part.c index 83099cb60161..878597eff202 100644 --- a/drivers/accel/amd-ai-engine/ai-engine-part.c +++ b/drivers/accel/amd-ai-engine/ai-engine-part.c @@ -12,6 +12,44 @@ =20 #include "ai-engine-internal.h" =20 +/** + * aie_part_create_mems_info() - creates array to store the AI engine part= ition + * different memories types information + * @apart: AI engine partition + * + * Return: 0 for success, negative value for failure + * + * This function will create array to store the information of different + * memories types in the partition. This array is stored in @apart->pmems. + */ +static int aie_part_create_mems_info(struct aie_partition *apart) +{ + unsigned int i, num_mems; + + num_mems =3D apart->adev->ops->get_mem_info(apart->adev, &apart->range, + NULL); + if (!num_mems) + return 0; + + apart->pmems =3D devm_kcalloc(apart->aperture->dev, num_mems, + sizeof(struct aie_part_mem), + GFP_KERNEL); + if (!apart->pmems) + return -ENOMEM; + + apart->adev->ops->get_mem_info(apart->adev, &apart->range, + apart->pmems); + for (i =3D 0; i < num_mems; i++) { + struct aie_mem *mem =3D &apart->pmems[i].mem; + + apart->pmems[i].apart =3D apart; + apart->pmems[i].size =3D mem->size * + mem->range.size.col * + mem->range.size.row; + } + return 0; +} + /** * aie_part_release() - release an AI engine partition instance * @apart: AI engine partition device @@ -29,6 +67,7 @@ void aie_part_release(struct aie_partition *apart) aie_resource_uninitialize(&apart->cores_clk_state); aie_resource_uninitialize(&apart->tiles_inuse); list_del(&apart->node); + devm_kfree(aperture->dev, apart->pmems); devm_kfree(aperture->dev, apart); mutex_unlock(&aperture->mlock); } @@ -64,6 +103,12 @@ struct aie_partition *aie_part_create(struct aie_apertu= re *aperture, apart->range.start.row =3D aperture->range.start.row; apart->range.size.row =3D aperture->range.size.row; =20 + ret =3D aie_part_create_mems_info(apart); + if (ret) { + dev_err(aperture->dev, "failed to create tile memory information."); + return ERR_PTR(ret); + } + /* SHIM row always enabled so it is not needed in the bitmap */ num_tiles =3D apart->range.size.col * (apart->range.size.row - 1); ret =3D aie_resource_initialize(&apart->cores_clk_state, num_tiles); --=20 2.34.1