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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2025 15:56:47.5535 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee813fe6-c30e-43a9-b66f-08ddb9810cf9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000017.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8955 Content-Type: text/plain; charset="utf-8" Adds driver support for AIEML generation devices. The following modules are enabled: - Get tile type from location (support for new memory tile type) - Clock state tracking and request and release of tiles Signed-off-by: Gregory Williams --- drivers/accel/amd-ai-engine/Makefile | 1 + drivers/accel/amd-ai-engine/ai-engine-aieml.c | 210 ++++++++++++++++++ drivers/accel/amd-ai-engine/ai-engine-dev.c | 2 + .../accel/amd-ai-engine/ai-engine-internal.h | 2 + 4 files changed, 215 insertions(+) create mode 100644 drivers/accel/amd-ai-engine/ai-engine-aieml.c diff --git a/drivers/accel/amd-ai-engine/Makefile b/drivers/accel/amd-ai-en= gine/Makefile index 9a830f7432d2..66cbce4705ea 100644 --- a/drivers/accel/amd-ai-engine/Makefile +++ b/drivers/accel/amd-ai-engine/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_ACCEL_AMDAIE) +=3D amd-aie.o =20 amd-aie-$(CONFIG_DRM_ACCEL_AMDAIE) :=3D \ ai-engine-aie.o \ + ai-engine-aieml.o \ ai-engine-aperture.o \ ai-engine-clock.o \ ai-engine-dev.o \ diff --git a/drivers/accel/amd-ai-engine/ai-engine-aieml.c b/drivers/accel/= amd-ai-engine/ai-engine-aieml.c new file mode 100644 index 000000000000..328688942a6a --- /dev/null +++ b/drivers/accel/amd-ai-engine/ai-engine-aieml.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD AI Engine driver AIEML device specific implementation + * + * Copyright(C) 2025 Advanced Micro Devices, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "ai-engine-internal.h" + +#define AIEML_ARRAY_SHIFT 32U +#define AIEML_COL_SHIFT 25U +#define AIEML_ROW_SHIFT 20U + +#define NUM_TYPES_OF_MEM 3U + +#define NUM_MODS_CORE_TILE 2U +#define NUM_MODS_MEM_TILE 1U +#define NUM_MODS_SHIMPL_TILE 1U + +/* + * Register offsets + */ +#define AIEML_SHIMPL_COLCLOCK_CTRL_REGOFF 0x000fff20U + +/* + * Register masks + */ +#define AIEML_SHIMPL_COLRESET_CTRL_MASK GENMASK(1, 0) +#define AIEML_SHIMPL_COLCLOCK_CTRL_MASK GENMASK(1, 0) + +static u32 aieml_get_tile_type(struct aie_device *adev, + struct aie_location *loc) +{ + u8 num_mem_rows =3D adev->ttype_attr[AIE_TILE_TYPE_MEMORY].num_rows; + + if (loc->row > num_mem_rows) + return AIE_TILE_TYPE_TILE; + if (loc->row && loc->row <=3D num_mem_rows) + return AIE_TILE_TYPE_MEMORY; + if (loc->row =3D=3D 0) + if ((loc->col % 4) < 2) + return AIE_TILE_TYPE_SHIMPL; + + return AIE_TILE_TYPE_SHIMNOC; +} + +/* aieml_scan_part_clocks() - scan clocks of a partition + * @apart: AI engine partition + * + * Return: 0 for success, negative value for errors. + */ +static int aieml_scan_part_clocks(struct aie_partition *apart) +{ + struct aie_aperture *aperture =3D apart->aperture; + struct aie_range *range =3D &apart->range; + struct aie_device *adev =3D apart->adev; + struct aie_location loc; + int ret; + + /* Clear the bitmap of cores and memories clock state */ + aie_resource_put_region(&apart->cores_clk_state, 0, + apart->cores_clk_state.total); + + /* + * In aieml if clock buffer on shim tile is enabled, the clock for all + * tiles in the same column is enabled. + */ + for (loc.col =3D range->start.col; + loc.col < range->start.col + range->size.col; + loc.col++) { + void __iomem *va; + u32 val, nbitpos; + + nbitpos =3D (loc.col - range->start.col) * (range->size.row - 1); + + va =3D aperture->base + + aie_cal_regoff(adev, loc, + AIEML_SHIMPL_COLCLOCK_CTRL_REGOFF); + val =3D readl(va); + + if (!(val & AIEML_SHIMPL_COLCLOCK_CTRL_MASK)) + continue; + + ret =3D aie_resource_set(&apart->cores_clk_state, nbitpos, + range->size.row - 1); + if (ret) { + dev_err(aperture->dev, + "failed to set clock state bitmaps for column %u", + loc.col); + return ret; + } + } + /* + * Set the tiles in use bitmap. + * In case of scanning, tiles which are powered on are considered as + * tiles in use. + */ + bitmap_copy(apart->tiles_inuse.bitmap, apart->cores_clk_state.bitmap, + apart->tiles_inuse.total); + + return 0; +} + +/* aieml_set_part_clocks() - set clocks of a partition + * @apart: AI engine partition + * + * Return: 0 for success, negative value for errors. + */ +static int aieml_set_part_clocks(struct aie_partition *apart) +{ + struct aie_aperture *aperture =3D apart->aperture; + struct aie_range *range =3D &apart->range; + u32 node_id =3D apart->adev->pm_node_id; + struct aie_location loc; + int ret; + + for (loc.col =3D range->start.col; + loc.col < range->start.col + range->size.col; + loc.col++) { + u32 startbit, col_inuse =3D 0; + + startbit =3D (loc.col - range->start.col) * (range->size.row - 1); + + for (loc.row =3D range->start.row + 1; + loc.row < range->start.row + range->size.row; + loc.row++) { + u32 nbitpos =3D startbit + loc.row - 1; + + if (aie_resource_testbit(&apart->tiles_inuse, nbitpos)) { + col_inuse =3D 1; + break; + } + } + + if (col_inuse) { + ret =3D zynqmp_pm_aie_operation(node_id, loc.col, + 1, + XILINX_AIE_OPS_ENB_COL_CLK_BUFF); + if (ret < 0) { + dev_err(aperture->dev, + "failed to enable clock for column: %d", + loc.col); + return ret; + } + + ret =3D aie_resource_set(&apart->tiles_inuse, + startbit, apart->range.size.row - 1) | + aie_resource_set(&apart->cores_clk_state, + startbit, apart->range.size.row - 1); + if (ret) { + dev_err(aperture->dev, + "failed to set bitmaps for column: %d", + loc.col); + return ret; + } + } else { + ret =3D zynqmp_pm_aie_operation(node_id, loc.col, + 1, + XILINX_AIE_OPS_DIS_COL_CLK_BUFF); + if (ret < 0) { + dev_err(aperture->dev, + "failed to disable clock for column: %d", + loc.col); + return ret; + } + + ret =3D aie_resource_clear(&apart->tiles_inuse, + startbit, apart->range.size.row - 1) | + aie_resource_clear(&apart->cores_clk_state, + startbit, apart->range.size.row - 1); + if (ret) { + dev_err(aperture->dev, + "failed to clear bitmaps for column: %d", + loc.col); + return ret; + } + } + } + + return 0; +} + +static const struct aie_tile_operations aieml_ops =3D { + .get_tile_type =3D aieml_get_tile_type, + .scan_part_clocks =3D aieml_scan_part_clocks, + .set_part_clocks =3D aieml_set_part_clocks, +}; + +/** + * aieml_device_init() - Initialize AI engine device struct AIEML specific + * @adev: AI engine device + * + * This function initialize the AI engine device structure device version + * specific elements such as register addressing related array shift, + * column shift, and row shift; AIEML device specific device operations, d= evice + * columns resource. + */ +void aieml_device_init(struct aie_device *adev) +{ + adev->array_shift =3D AIEML_ARRAY_SHIFT; + adev->col_shift =3D AIEML_COL_SHIFT; + adev->row_shift =3D AIEML_ROW_SHIFT; + adev->ops =3D &aieml_ops; +} diff --git a/drivers/accel/amd-ai-engine/ai-engine-dev.c b/drivers/accel/am= d-ai-engine/ai-engine-dev.c index ba28257cbd04..f713d38ff8c3 100644 --- a/drivers/accel/amd-ai-engine/ai-engine-dev.c +++ b/drivers/accel/amd-ai-engine/ai-engine-dev.c @@ -154,6 +154,8 @@ static int amd_ai_engine_probe(struct platform_device *= pdev) adev->dev_gen =3D aie_gen; if (aie_gen =3D=3D AIE_DEVICE_GEN_AIE) { aie_device_init(adev); + } else if (aie_gen =3D=3D AIE_DEVICE_GEN_AIEML) { + aieml_device_init(adev); } else { dev_err(&pdev->dev, "Invalid device generation"); return -EINVAL; diff --git a/drivers/accel/amd-ai-engine/ai-engine-internal.h b/drivers/acc= el/amd-ai-engine/ai-engine-internal.h index 495d56d5f993..31a45575cc43 100644 --- a/drivers/accel/amd-ai-engine/ai-engine-internal.h +++ b/drivers/accel/amd-ai-engine/ai-engine-internal.h @@ -19,6 +19,7 @@ #include =20 #define AIE_DEVICE_GEN_AIE 1U +#define AIE_DEVICE_GEN_AIEML 2U =20 #define KBYTES(n) ((n) * SZ_1K) =20 @@ -246,6 +247,7 @@ static inline u32 aie_cal_regoff(struct aie_device *ade= v, } =20 void aie_device_init(struct aie_device *adev); +void aieml_device_init(struct aie_device *adev); struct aie_partition * aie_aperture_request_part(struct aie_aperture *aperture, struct aie_partition_req *req); --=20 2.34.1