From nobody Wed Oct 8 04:06:42 2025 Received: from mail-m19731115.qiye.163.com (mail-m19731115.qiye.163.com [220.197.31.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9C9C19AD89; Wed, 2 Jul 2025 10:01:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.115 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751450512; cv=none; b=XNMWXI05kMmmLFv3hsIcpp15PuI5ETS2XoLTP3EOHQUxsok2lUib99Et/KfYAc9W9DrztWMM4tb8t7zu7ol8PDQLSuZHDk7+K/S9Lvq43tblIuRGKoItmygWIDwgGaYHtRH5ZqNXIB2M5Z3x+WFxXmdKs0Z93kiSdQbd3lUQzeY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751450512; c=relaxed/simple; bh=eNKdiGfqO/VuWb4nuKPgERe+wyH9DEVM80fafn4TfEc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=N0oLk+x72s9ApHeMZ5dgir3fytaJe6TCNQKsUhXFlKjV/3/I8tW3Ag1sYP/lvKY2HGpBAkZBGqoAV4LPybkPhdP8hlUZVzbiMU0Z+uSOzTBdFKJJl5tcxzyGQqWAgBv6C8p/YnKkd68E/6S5tnHO4LqE9iev2Bki7rCgVl5Nh+g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com; spf=pass smtp.mailfrom=thundersoft.com; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b=bRQvynVU; arc=none smtp.client-ip=220.197.31.115 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="bRQvynVU" Received: from localhost.localdomain (unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1aaa9ed2b; Wed, 2 Jul 2025 17:46:28 +0800 (GMT+08:00) From: Albert Yang To: robh@kernel.org, krzk+dt@kernel.org, krzk@kernel.org, conor+dt@kernel.org, gordon.ge@bst.ai, catalin.marinas@arm.com, geert.uytterhoeven@gmail.com, will@kernel.org, ulf.hansson@linaro.org, adrian.hunter@intel.com, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, bst-upstream@bstai.top, neil.armstrong@linaro.org, jonathan.cameron@huawei.com, bigfoot@classfun.cn, kever.yang@rock-chips.com, mani@kernel.org, geert+renesas@glider.be, andersson@kernel.org, nm@ti.com, nfraprado@collabora.com, quic_tdas@quicinc.com, ebiggers@google.com, victor.shih@genesyslogic.com.tw, shanchun1218@gmail.com, ben.chuang@genesyslogic.com.tw, Albert Yang Subject: [PATCH v2 1/8] dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd. Date: Wed, 2 Jul 2025 17:44:37 +0800 Message-Id: <20250702094444.3523973-2-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250702094444.3523973-1-yangzh0906@thundersoft.com> References: <20250528085403.481055-1-yangzh0906@thundersoft.com> <20250702094444.3523973-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDSkgaVk4ZGkNNTBofQ09OGFYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE5VSk tLVUpCS0tZBg++ X-HM-Tid: 0a97ca87d4b509cckunmee1cabff3eba7e X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MVE6Pzo4LjE4NE8PHSE6HQE6 VjIKC0tVSlVKTE5KT09CTkJKS0hKVTMWGhIXVQIaFRwBE0tCS007DxMOFR8eCQgUHQ9VGBQWRVlX WRILWUFZSkpMVUpDT1VKSUJVSkhPWVdZCAFZQUlPS0k3Bg++ DKIM-Signature: a=rsa-sha256; b=bRQvynVUXniiVJyyH/q9DnWCaWegCDyqvNxnpqcOsl2JGrj4Lp17augQtBgTZqfrea5swTq0A7M/4pQt89ZzyIlff4KcZcrt4pvdvzrIrSyWMezcOqVZY1eHYXD7auzMGNh7585V6XitzXFdlqGw0EGjlU2k3TaBYmrQv3o4sUA=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=XEabmgEszbyuyR1aOE7h10DY4QzFMJFpCj2YxqFGf80=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Black Sesame Technologies Co., Ltd.s a leading automotive-grade computing SoC and SoC-based intelligent vehicle solution provider. Link: https://bst.ai/. Acked-by: Rob Herring (Arm) Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 5d2a7a8d3ac6..3c2031417232 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -222,6 +222,8 @@ patternProperties: description: Shenzhen BigTree Tech Co., LTD "^bitmain,.*": description: Bitmain Technologies + "^bst,.*": + description: Black Sesame Technologies Co., Ltd. "^blaize,.*": description: Blaize, Inc. "^blutek,.*": --=20 2.25.1 From nobody Wed Oct 8 04:06:42 2025 Received: from mail-m49207.qiye.163.com (mail-m49207.qiye.163.com [45.254.49.207]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5352E24DD1F; Wed, 2 Jul 2025 09:46:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.207 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751449604; cv=none; b=g5ktyZGYmjID7R5uzgpuYfF3nS6c/CcGAXWsxGfoMQCPIBR8uKRx7klPtu0gKs/YFldCuzqzePBVUVzvzORnpXw1j5G+Xq23qVb6DLhnKsmD2Y/b6BUnJQA7Z0UyymUEIB7Gbve2vT8B2owG3vOxhMXD6k5naP04to0IptS6wCg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751449604; c=relaxed/simple; bh=R0CWMLD/EEHYNbcG8KgTMPj2hzXibcGsXODlklTI5q4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=GEWLFRnLQJV3C0p2BbmcTABZf2xjC5Hk1LYE+FYlfcwYtTDkLXAkM6QBaDHcvo3bWU7feaiX4jIbXvxITNPikbwq42EuV8/cH+yJVTkiITVZqtx047CbTJAPQOVnVYWcdccSVytovd581AT/mtSHyrAyhSSbEx3yYtv/4ayvtYk= ARC-Authentication-Results: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUhXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDGR1JVk4YGENDTEpJHh5OQ1YVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSklVT1 VKT1kG X-HM-Tid: 0a97ca87dd3009cckunmee1cabff3ebaba X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Pxg6KTo6TzE*T089KxksHQw9 CD4aCQ5VSlVKTE5KT09CTkJIS0NKVTMWGhIXVQIaFRwBE0tCS007DxMOFR8eCQgUHQ9VGBQWRVlX WRILWUFZSkpMVUpDT1VKSUJVSkhPWVdZCAFZQUhKSEw3Bg++ DKIM-Signature: a=rsa-sha256; b=km48lblwqhJ9eMNaOOixs21bDUWw710nq+WF3nGAJkUGzohpfAFY+A5CVIoRyltnZs22ksywNjzOgET76hamxpDBF9R2HS4wUCyQgTxvo7xVqyRedMN6Tw+WsJO1RgD0TEFox7TMi1Djhh6zAs54h+QEhBwVrqNNP5Gokbgz6uA=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=7HId0QjN1Uxd1UcS1PVWLgSUuLheSa0vzbbArIAI4e0=; h=date:mime-version:subject:message-id:from; Add device tree bindings for Black Sesame Technologies Arm SoC, it consists several SoC models like C1200, etc. --- Changes for v2: - Removed unnecessary pipe (`|`) in description - Dropped invalid=C2=A0`compatible`=C2=A0entry for standalone SoC - Removed root node (`$nodename: '/'`) definition Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- .../devicetree/bindings/arm/bst.yaml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/bst.yaml diff --git a/Documentation/devicetree/bindings/arm/bst.yaml b/Documentation= /devicetree/bindings/arm/bst.yaml new file mode 100644 index 000000000000..e6f48f569768 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bst.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BST platforms + +description: + Black Sesame Technologies (BST) is a semiconductor company that produces + automotive-grade system-on-chips (SoCs) for intelligent driving, focusing + on computer vision and AI capabilities. The BST C1200 family includes So= Cs + for ADAS (Advanced Driver Assistance Systems) and autonomous driving app= lications. + +maintainers: + - Ge Gordon + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BST C1200 CDCU1.0 ADAS 4C2G board + items: + - const: bst,c1200-cdcu1.0-adas-4c2g + - const: bst,c1200 + +additionalProperties: true + +... --=20 2.25.1 From nobody Wed Oct 8 04:06:42 2025 Received: from mail-m49202.qiye.163.com (mail-m49202.qiye.163.com [45.254.49.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 773CB24DCF6; Wed, 2 Jul 2025 10:01:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751450516; cv=none; b=YY5dIUv5Tg25+bfoTe3VKi/whOdNgrKaCb2hWVdb7eZtU5fB4igHEV05FgAcevC90oVz70ZM0p4RRm7gi9zkJ2RxhxmiyNFZPobkNGUHK7R8oRSyuzk234mY2b599sZ58GxhrHwtODsk6cwsrA3EKNwv9PAXALHPE052n7qVDeY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751450516; c=relaxed/simple; bh=i9OB2XoW87G6P7CVuqhw+Zp1R6CIsj11Qr8nH7WUQ4k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jjCYxiKYagHhc/FiPV4ih6xyeLrdYs4qSeCkk8J3J8xFGu+EnQh56sa5hv9fw8LQXcQGlBdSjhiYksmCC+NUO2sSuCPdhsVJMRk4Q6B0vUh9g0zZK1t2gPq0XgCLtCgLbfSAF+gpxnNiMxgFdIlNUo8Dg6rQLcqyxcILNHqh1AQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com; spf=pass smtp.mailfrom=thundersoft.com; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b=CCVhNbF0; arc=none smtp.client-ip=45.254.49.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="CCVhNbF0" Received: from localhost.localdomain (unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1aaa9ed42; Wed, 2 Jul 2025 17:46:33 +0800 (GMT+08:00) From: Albert Yang To: robh@kernel.org, krzk+dt@kernel.org, krzk@kernel.org, conor+dt@kernel.org, gordon.ge@bst.ai, catalin.marinas@arm.com, geert.uytterhoeven@gmail.com, will@kernel.org, ulf.hansson@linaro.org, adrian.hunter@intel.com, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, bst-upstream@bstai.top, neil.armstrong@linaro.org, jonathan.cameron@huawei.com, bigfoot@classfun.cn, kever.yang@rock-chips.com, mani@kernel.org, geert+renesas@glider.be, andersson@kernel.org, nm@ti.com, nfraprado@collabora.com, quic_tdas@quicinc.com, ebiggers@google.com, victor.shih@genesyslogic.com.tw, shanchun1218@gmail.com, ben.chuang@genesyslogic.com.tw, Albert Yang Subject: [PATCH v2 3/8] arm64: Kconfig: add ARCH_BST for bst silicons Date: Wed, 2 Jul 2025 17:44:39 +0800 Message-Id: <20250702094444.3523973-4-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250702094444.3523973-1-yangzh0906@thundersoft.com> References: <20250528085403.481055-1-yangzh0906@thundersoft.com> <20250702094444.3523973-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCHkNOVk9LQktMGRpOSBgYH1YVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCS0NVSk tLVUpCWQY+ X-HM-Tid: 0a97ca87e53409cckunmee1cabff3ebb07 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Nxg6DAw5HjE5LE9RQiIzHUkP TC8aCi5VSlVKTE5KT09CTkJPQkxPVTMWGhIXVQIaFRwBE0tCS007DxMOFR8eCQgUHQ9VGBQWRVlX WRILWUFZSkpMVUpDT1VKSUJVSkhPWVdZCAFZQUlMSU43Bg++ DKIM-Signature: a=rsa-sha256; b=CCVhNbF0z/nZNzKXzKPmTCziV/mfP8r7/JXYSuX3+o352hI3g6Kd+ZBKmVA2IicGO6JRd2Fv501c/80xty3Xoc6C9D1Fk8SXqWl+jay/xIqLslItLvj1HV/8BynCZlGPmq7wpK9nT9EFSJP0rrE9PrdQfzgP4wfgYZcHo+W1q0c=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=+mZ281H0S02t7176D+bqxjl4chkVEj1RFfKyhGtpJ7c=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add ARCH_BST for bst SoC series support. Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- Changes for v2: - Placed the configuration entry in correct alphabetical order - Used generic family name (ARCH_BST) instead of SoC-specific naming - Followed upstream kernel naming and description conventions --- arch/arm64/Kconfig.platforms | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a541bb029aa4..4412d54b224d 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -106,6 +106,14 @@ config ARCH_BLAIZE help This enables support for the Blaize SoC family =20 +config ARCH_BST + bool "Black Sesame Technologies SoC Family" + help + This enables support for Black Sesame Technologies (BST) SoC family. + BST produces automotive-grade system-on-chips for intelligent driving, + focusing on computer vision and AI capabilities. The BST C1200 family + includes SoCs for ADAS and autonomous driving applications. + config ARCH_EXYNOS bool "Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG @@ -402,4 +410,6 @@ config ARCH_ZYNQMP help This enables support for Xilinx ZynqMP Family =20 + + endmenu # "Platform selection" --=20 2.25.1 From nobody Wed Oct 8 04:06:42 2025 Received: from mail-m19731103.qiye.163.com (mail-m19731103.qiye.163.com [220.197.31.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAC2B2309B0; Wed, 2 Jul 2025 09:51:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.103 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751449915; cv=none; b=fg7W/ZJmvDsYZIxoUtBMj+Hd1OLY9gu/xLTJoRps+6WOuboEuG5+R9yX4UY2s7CoTYYPFLbeqny4RYHFRN1ILBP5pMu2c6VvmEPqfsiTk2uG/gt0J1LW3vp38mviiq/UXK9IlNrOnajg1lpkB5t4XHzrWXFVpPm6ORCxQHArvZ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751449915; c=relaxed/simple; bh=1EDFj4goj5CsQ5wj3psPIN+ghrdp1Uo32Zl1NGBk7fg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MFiDgNVf0FbkzNu+2RdILHDvchKa+GKYuZyPAawKckNpDqudE1tDdQlnScokDpU7Y4JVfbFeMksh29MIaU75Dwm5GqUq+j0RFx2kYGEk1L6E2URwu8Q5+74fLlh3/gW7uZEXK/u8hlnHpIHdYWG90mL4YO5T4AvR8Z806r34I+8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com; spf=pass smtp.mailfrom=thundersoft.com; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b=joicoOyL; arc=none smtp.client-ip=220.197.31.103 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="joicoOyL" Received: from localhost.localdomain (unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1aaa9ed49; Wed, 2 Jul 2025 17:46:35 +0800 (GMT+08:00) From: Albert Yang To: robh@kernel.org, krzk+dt@kernel.org, krzk@kernel.org, conor+dt@kernel.org, gordon.ge@bst.ai, catalin.marinas@arm.com, geert.uytterhoeven@gmail.com, will@kernel.org, ulf.hansson@linaro.org, adrian.hunter@intel.com, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, bst-upstream@bstai.top, neil.armstrong@linaro.org, jonathan.cameron@huawei.com, bigfoot@classfun.cn, kever.yang@rock-chips.com, mani@kernel.org, geert+renesas@glider.be, andersson@kernel.org, nm@ti.com, nfraprado@collabora.com, quic_tdas@quicinc.com, ebiggers@google.com, victor.shih@genesyslogic.com.tw, shanchun1218@gmail.com, ben.chuang@genesyslogic.com.tw, Albert Yang Subject: [PATCH v2 4/8] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller Date: Wed, 2 Jul 2025 17:44:40 +0800 Message-Id: <20250702094444.3523973-5-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250702094444.3523973-1-yangzh0906@thundersoft.com> References: <20250528085403.481055-1-yangzh0906@thundersoft.com> <20250702094444.3523973-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDGhhKVkgdS08YGExNTk5IQlYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE5VSk tLVUpCS0tZBg++ X-HM-Tid: 0a97ca87ec9609cckunmee1cabff3ebb45 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MDo6Ejo6LDE3Ck8iHSE0HQIC NQwKCzNVSlVKTE5KT09CTkJMSk5CVTMWGhIXVQIaFRwBE0tCS007DxMOFR8eCQgUHQ9VGBQWRVlX WRILWUFZSkpMVUpDT1VKSUJVSkhPWVdZCAFZQU9ITkw3Bg++ DKIM-Signature: a=rsa-sha256; b=joicoOyLfPcI5Htb1jQL3vfoaIeY1lc6q9SmjGU0vYGNsKgX5FlzEe//fUMFt+F2Dt5msY0bIJHRnbNv2d+Ki7OV8xn3wNKMXXvBaG4Q66kys7HQLCJrgjS6tDstwINmLA7RWk/T5myjQBO8memOyK9cx2gDTqhwHD5Wld7+YVM=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=TfcFw4Er+lRQGjZg8dmF9mso3a6O4zW0NF5yIyCmuEU=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add device tree binding documentation for the Black Sesame Technologies (BST) DWCMSHC SDHCI controller. This binding describes the required and optional properties for the bst,dwcmshc-sdhci compatible controller, including register layout, interrupts, bus width, clock configuration, and other controller-specific features. --- Changes for v2: - Simplified description, removed redundant paragraphs - Updated $schema to reference mmc-specific scheme - Corrected compatible to add soc name (bst,c1200-dwcmshc-sdhci) - Removed all redundant property descriptions - Dropped invalid mmc_crm_base/size properties, use reg for all address ranges - Cleaned up required properties to only essential entries - Standardized example DTS format, fixed reg syntax and property ordering - Removed additionalProperties: true Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- .../bindings/mmc/bst,dwcmshc-sdhci.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci= .yaml diff --git a/Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml b= /Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml new file mode 100644 index 000000000000..699dc404caac --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/bst,dwcmshc-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Black Sesame Technologies DWCMSHC SDHCI Controller + +maintainers: + - Ge Gordon + +allOf: + - $ref: mmc-controller.yaml# + +properties: + compatible: + const: bst,c1200-dwcmshc-sdhci + + reg: + maxItems: 2 + description: | + Register base addresses and sizes for the SDHCI controller. + First entry is the core SDHCI registers, second entry is the + CRM registers. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + memory-region: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + mmc@22200000 { + compatible =3D "bst,c1200-dwcmshc-sdhci"; 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Wed, 2 Jul 2025 17:46:37 +0800 (GMT+08:00) From: Albert Yang To: robh@kernel.org, krzk+dt@kernel.org, krzk@kernel.org, conor+dt@kernel.org, gordon.ge@bst.ai, catalin.marinas@arm.com, geert.uytterhoeven@gmail.com, will@kernel.org, ulf.hansson@linaro.org, adrian.hunter@intel.com, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, bst-upstream@bstai.top, neil.armstrong@linaro.org, jonathan.cameron@huawei.com, bigfoot@classfun.cn, kever.yang@rock-chips.com, mani@kernel.org, geert+renesas@glider.be, andersson@kernel.org, nm@ti.com, nfraprado@collabora.com, quic_tdas@quicinc.com, ebiggers@google.com, victor.shih@genesyslogic.com.tw, shanchun1218@gmail.com, ben.chuang@genesyslogic.com.tw, Albert Yang Subject: [PATCH v2 5/8] mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver Date: Wed, 2 Jul 2025 17:44:41 +0800 Message-Id: <20250702094444.3523973-6-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250702094444.3523973-1-yangzh0906@thundersoft.com> References: <20250528085403.481055-1-yangzh0906@thundersoft.com> <20250702094444.3523973-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDT00aVkMfHUpPT0sdSB1OSlYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCS0NVSk tLVUpCWQY+ X-HM-Tid: 0a97ca87f57c09cckunmee1cabff3ebb6b X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Mjo6HRw6FTEwDk9MHSIdHUIe HjoKCQpVSlVKTE5KT09CTkJCSEpLVTMWGhIXVQIaFRwBE0tCS007DxMOFR8eCQgUHQ9VGBQWRVlX WRILWUFZSkpMVUpDT1VKSUJVSkhPWVdZCAFZQUlKSEpMNwY+ DKIM-Signature: a=rsa-sha256; b=YZ+gg0I13tP/zaaF1VsRnGYMrsM7x8Xr1kPKy3uzt36Y3l+1w+tj/YR9ZIEhkNzn3fRaEz7VlniDkCu5MDUpvBp8O8CqUF/EZSKWnX1M3jEXdHXsiPdhmFlfOgiUq+xTK2VOaH0vZGQYVP7yRF+9A34UM9VGxtCnVpMJ+AE8oI4=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=zviMpMe/GKMuDeXucGk8dIUIyAzyPbzHcM5/aawzXlY=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add a driver for the DesignWare Mobile Storage Host Controller (DWCMSHC) SDHCI controller found in Black Sesame Technologies C1200 SoCs. The driver provides specialized clock configuration, tuning, voltage switching, and power management for the BST DWCMSHC controller. It also includes support for eMMC boot and memory-mapped I/O for CRM registers. --- Changes for v2: 1. Dependency Simplification : - Removed COMMON_CLK dependency from Kconfig (MMC_SDHCI_BST) - Add ARCH_BST || COMPILE_TEST dependency from Kconfig (MMC_SDHCI_BST) 2. Resource Management Improvements : - Replaced temporary ioremap with persistent mapping * Mapped CRM registers once during probe instead of per-access * Added proper cleanup in remove callback - Refactored bounce buffer allocation: * Simplified error handling and memory management * Removed unnecessary DMA configuration layers 3. Code Cleanup & Optimization : - Pruned unused headers and legacy vendor debug code - Removed deprecated sdhci_bst_print_vendor() export - Converted internal functions to static scope - Standardized naming conventions: * Renamed DRIVER_NAME to match kernel standards * Changed default_max_freq to DEFAULT_MAX_FREQ - Optimized clock configuration routines 4. Hardware Integration Fixes : - Fixed register access macros for EMMC_CTRL * Added proper offset calculation via SDHCI_VENDOR_PTR_R - Corrected device tree compatibility string to: "bst,c1200-dwcmshc-sdhci" 5. Error Handling Enhancements : - Added robust ioremap error checking - Improved bounce buffer allocation failure handling - Streamlined probe/remove flow 6. Maintainability : - Updated MODULE_DESCRIPTION and AUTHOR fields - Added explanatory comments for hardware limitations - Removed redundant multi-host setup infrastructure 7. fix build warnings from lkp | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202505290615.GZzN5rNL-lkp@intel.com/ Signed-off-by: Albert Yang Signed-off-by: Ge Gordon --- drivers/mmc/host/Kconfig | 11 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-of-bst-c1200.c | 557 ++++++++++++++++++++++++++ 3 files changed, 569 insertions(+) create mode 100644 drivers/mmc/host/sdhci-of-bst-c1200.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index c3f0f41a426d..a93ea150dcbf 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -1126,3 +1126,14 @@ config MMC_LITEX module will be called litex_mmc. =20 If unsure, say N. + +config MMC_SDHCI_BST + tristate "SDHCI OF support for the BST DWC MSHC" + depends on ARCH_BST || COMPILE_TEST + depends on MMC_SDHCI_PLTFM + depends on OF + help + This selects Synopsys DesignWare Cores Mobile Storage Controller + support. + If you have a controller with this interface, say Y or M here. + If unsure, say N. diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 75bafc7b162b..bb5df05c3174 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_MMC_MXS) +=3D mxs-mmc.o obj-$(CONFIG_MMC_SDHCI) +=3D sdhci.o obj-$(CONFIG_MMC_SDHCI_UHS2) +=3D sdhci-uhs2.o obj-$(CONFIG_MMC_SDHCI_PCI) +=3D sdhci-pci.o +obj-$(CONFIG_MMC_SDHCI_BST) +=3D sdhci-of-bst-c1200.o sdhci-pci-y +=3D sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o= \ sdhci-pci-dwc-mshc.o sdhci-pci-gli.o obj-$(CONFIG_MMC_SDHCI_ACPI) +=3D sdhci-acpi.o diff --git a/drivers/mmc/host/sdhci-of-bst-c1200.c b/drivers/mmc/host/sdhci= -of-bst-c1200.c new file mode 100644 index 000000000000..233ad959e6e5 --- /dev/null +++ b/drivers/mmc/host/sdhci-of-bst-c1200.c @@ -0,0 +1,557 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Black Sesame Technologies SDHCI driver + * + * Copyright (C) 2024 Black Sesame Technologies. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "sdhci.h" +#include "sdhci-pltfm.h" + +struct dwcmshc_priv { + void __iomem *crm_reg_base; + u32 phy_crm_reg_base; + u32 phy_crm_reg_size; +}; + +#define SDHCI_CLOCK_PLL_EN 0x0008 +#define SDHCI_TUNING_COUNT 0x20 +#define SDHCI_VENDOR_PTR_R 0xE8 +#define MBIU_CTRL 0x510 +#define BURST_INCR16_EN BIT(3) +#define BURST_INCR8_EN BIT(2) +#define BURST_INCR4_EN BIT(1) +#define BURST_EN (BURST_INCR16_EN | BURST_INCR8_EN | BURST_INCR4_EN) + +/* Synopsys vendor specific registers */ +#define SDHC_EMMC_CTRL_R_OFFSET 0x2C + +#define SDEMMC_CRM_BCLK_DIV_CTRL 0x08 +#define SDEMMC_CRM_RX_CLK_CTRL 0x14 +#define SDEMMC_CRM_TIMER_DIV_CTRL 0x0C +#define SDEMMC_CRM_VOL_CTRL 0x1C +#define REG_WR_PROTECT 0x88 +#define REG_WR_PROTECT_KEY 0x1234abcd +#define DELAY_CHAIN_SEL 0x94 +#define BST_VOL_STABLE_ON BIT(7) +#define DEFAULT_MAX_FREQ 200000UL + +static u32 bst_read_phys_bst(void __iomem *addr) +{ + return ioread32(addr); +} + +static void bst_write_phys_bst(void __iomem *addr, u32 value) +{ + iowrite32(value, addr); +} + +static unsigned int bst_get_max_clock(struct sdhci_host *host) +{ + return host->mmc->f_max; +} + +static unsigned int bst_get_min_clock(struct sdhci_host *host) +{ + return host->mmc->f_min; +} + +struct rx_ctrl { + struct { + u32 rx_revert:1; + u32 rx_clk_sel_sec:1; + u32 rx_clk_div:4; + u32 rx_clk_phase_inner:2; + u32 rx_clk_sel_first:1; + u32 rx_clk_phase_out:2; + u32 rx_clk_en:1; + u32 res0:20; + } bit; + u32 reg; +}; + +struct sdmmc_iocfg { + struct { + u32 res0:16; + u32 SC_SDMMC0_PVDD18POCSD0:2; + u32 SC_SDMMC0_PVDD18POCSD1:2; + u32 SC_SDMMC0_PVDD18POCSD2:2; + u32 SC_SDMMC1_PVDD18POCSD0:2; + u32 SC_SDMMC1_PVDD18POCSD1:2; + u32 SC_SDMMC1_PVDD18POCSD2:2; + u32 res1:4; + } bit; + u32 reg; +}; + +static void sdhci_enable_bst_clk(struct sdhci_host *host, unsigned int clk) +{ + struct sdhci_pltfm_host *pltfm_host; + struct dwcmshc_priv *priv; + unsigned int div; + u32 val; + struct rx_ctrl rx_reg; + + pltfm_host =3D sdhci_priv(host); + priv =3D sdhci_pltfm_priv(pltfm_host); + if (clk =3D=3D 0) { + div =3D clk; + } else if (clk > DEFAULT_MAX_FREQ) { + div =3D clk / 1000; + div =3D DEFAULT_MAX_FREQ / div; + } else if (clk < 1500) { + div =3D clk; + } else { + div =3D DEFAULT_MAX_FREQ * 100; + div =3D div / clk; + div /=3D 100; + } + + clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk &=3D ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + clk &=3D ~SDHCI_CLOCK_PLL_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + val =3D bst_read_phys_bst(priv->crm_reg_base + SDEMMC_CRM_TIMER_DIV_CTRL); + val &=3D ~BIT(8); + bst_write_phys_bst(priv->crm_reg_base + SDEMMC_CRM_TIMER_DIV_CTRL, val); + + val =3D bst_read_phys_bst(priv->crm_reg_base + SDEMMC_CRM_TIMER_DIV_CTRL); + val &=3D ~0xff; + val |=3D 0x20; + bst_write_phys_bst(priv->crm_reg_base + SDEMMC_CRM_TIMER_DIV_CTRL, val); + + val =3D bst_read_phys_bst(priv->crm_reg_base + SDEMMC_CRM_TIMER_DIV_CTRL); + val |=3D BIT(8); + bst_write_phys_bst(priv->crm_reg_base + SDEMMC_CRM_TIMER_DIV_CTRL, val); + + val =3D bst_read_phys_bst(priv->crm_reg_base + SDEMMC_CRM_RX_CLK_CTRL); + val &=3D ~BIT(11); + bst_write_phys_bst(priv->crm_reg_base + SDEMMC_CRM_RX_CLK_CTRL, val); + + rx_reg.reg =3D bst_read_phys_bst(priv->crm_reg_base + SDEMMC_CRM_RX_CLK_C= TRL); + + rx_reg.bit.rx_revert =3D 0; + rx_reg.bit.rx_clk_sel_sec =3D 1; + rx_reg.bit.rx_clk_div =3D 4; + rx_reg.bit.rx_clk_phase_inner =3D 2; + rx_reg.bit.rx_clk_sel_first =3D 0; + rx_reg.bit.rx_clk_phase_out =3D 2; + + bst_write_phys_bst(priv->crm_reg_base + SDEMMC_CRM_RX_CLK_CTRL, rx_reg.re= g); + + val =3D bst_read_phys_bst(priv->crm_reg_base + SDEMMC_CRM_RX_CLK_CTRL); + val |=3D BIT(11); + bst_write_phys_bst(priv->crm_reg_base + SDEMMC_CRM_RX_CLK_CTRL, val); + + /* Disable clock first */ + val =3D bst_read_phys_bst(priv->crm_reg_base + SDEMMC_CRM_BCLK_DIV_CTRL); + val &=3D ~BIT(10); + bst_write_phys_bst(priv->crm_reg_base + SDEMMC_CRM_BCLK_DIV_CTRL, val); + + /* Setup clock divider */ + val =3D bst_read_phys_bst(priv->crm_reg_base + SDEMMC_CRM_BCLK_DIV_CTRL); + val &=3D ~GENMASK(9, 0); + val |=3D div; + bst_write_phys_bst(priv->crm_reg_base + SDEMMC_CRM_BCLK_DIV_CTRL, val); + + /* Enable clock */ + val =3D bst_read_phys_bst(priv->crm_reg_base + SDEMMC_CRM_BCLK_DIV_CTRL); + val |=3D BIT(10); + bst_write_phys_bst(priv->crm_reg_base + SDEMMC_CRM_BCLK_DIV_CTRL, val); + + sdhci_writew(host, (div & 0xff) << 8, SDHCI_CLOCK_CONTROL); + + sdhci_writew(host, (div & 0xff) << 8, SDHCI_CLOCK_CONTROL); + clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk |=3D SDHCI_CLOCK_PLL_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + clk |=3D SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + clk |=3D SDHCI_CLOCK_INT_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); +} + +static void sdhci_set_bst_clock(struct sdhci_host *host, unsigned int cloc= k) +{ + if (clock =3D=3D 0) + return; + sdhci_enable_bst_clk(host, clock); +} + +/** + * sdhci_bst_reset - Reset the SDHCI host controller + * @host: SDHCI host controller + * @mask: Reset mask + * + * Performs a reset of the SDHCI host controller with special handling for= eMMC. + */ +static void sdhci_bst_reset(struct sdhci_host *host, u8 mask) +{ + u16 vendor_ptr, emmc_ctrl_reg; + + if (host->mmc->caps2 & MMC_CAP2_NO_SD) { + vendor_ptr =3D sdhci_readw(host, SDHCI_VENDOR_PTR_R); + emmc_ctrl_reg =3D vendor_ptr + SDHC_EMMC_CTRL_R_OFFSET; + + sdhci_writew(host, + sdhci_readw(host, emmc_ctrl_reg) & (~BIT(2)), + emmc_ctrl_reg); + sdhci_reset(host, mask); + usleep_range(10, 20); + sdhci_writew(host, + sdhci_readw(host, emmc_ctrl_reg) | BIT(2), + emmc_ctrl_reg); + } else { + sdhci_reset(host, mask); + } +} + +/** + * sdhci_bst_timeout - Set timeout value for commands + * @host: SDHCI host controller + * @cmd: MMC command + * + * Sets the timeout control register to maximum value (0xE). + */ +static void sdhci_bst_timeout(struct sdhci_host *host, struct mmc_command = *cmd) +{ + sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL); +} + +/** + * sdhci_bst_set_power - Set power mode and voltage + * @host: SDHCI host controller + * @mode: Power mode to set + * @vdd: Voltage to set + * + * Sets power mode and voltage, also configures MBIU control register. + */ +static void sdhci_bst_set_power(struct sdhci_host *host, unsigned char mod= e, + unsigned short vdd) +{ + sdhci_set_power(host, mode, vdd); + sdhci_writeb(host, 0xF, SDHCI_POWER_CONTROL); + sdhci_writew(host, + (sdhci_readw(host, MBIU_CTRL) & (~0xf)) | BURST_EN, + MBIU_CTRL); +} + +/** + * bst_sdhci_execute_tuning - Execute tuning procedure + * @host: SDHCI host controller + * @opcode: Opcode to use for tuning + * + * Performs tuning procedure by trying different values and selecting the = best one. + * + * Return: 0 on success, negative errno on failure + */ +static int bst_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + struct sdhci_pltfm_host *pltfm_host; + struct dwcmshc_priv *priv; + unsigned int clk =3D 0, timeout; + int ret =3D 0, error; + int start0 =3D -1, end0 =3D -1, best =3D 0; + int start1 =3D -1, end1 =3D -1, flag =3D 0; + int i; + + pltfm_host =3D sdhci_priv(host); + priv =3D sdhci_pltfm_priv(pltfm_host); + + for (i =3D 0; i < SDHCI_TUNING_COUNT; i++) { + /* Protected write */ + bst_write_phys_bst(priv->crm_reg_base + REG_WR_PROTECT, REG_WR_PROTECT_K= EY); + /* Write tuning value */ + bst_write_phys_bst(priv->crm_reg_base + DELAY_CHAIN_SEL, + (1ul << i) - 1); + + timeout =3D 20; + while (!((clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL)) & + SDHCI_CLOCK_INT_STABLE)) { + if (timeout =3D=3D 0) { + dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n"); + return -EBUSY; + } + timeout--; + usleep_range(1000, 1100); + } + + ret =3D mmc_send_tuning(host->mmc, opcode, &error); + if (ret !=3D 0) { + flag =3D 1; + } else { + if (flag =3D=3D 0) { + if (start0 =3D=3D -1) + start0 =3D i; + end0 =3D i; + } else { + if (start1 =3D=3D -1) + start1 =3D i; + end1 =3D i; + } + } + } + + /* Calculate best tuning value */ + if (end0 - start0 >=3D end1 - start1) + best =3D ((end0 - start0) >> 1) + start0; + else + best =3D ((end1 - start1) >> 1) + start1; + + if (best < 0) + best =3D 0; + + bst_write_phys_bst(priv->crm_reg_base + DELAY_CHAIN_SEL, (1ul << best) - = 1); + timeout =3D 20; + + while (!((clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL)) & + SDHCI_CLOCK_INT_STABLE)) { + if (timeout =3D=3D 0) { + dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n"); + return -EBUSY; + } + timeout--; + usleep_range(1000, 1100); + } + + return 0; +} + +/** + * sdhci_bst_voltage_switch - Perform voltage switch + * @host: SDHCI host controller + * + * Enables voltage stable power. + */ +static void sdhci_bst_voltage_switch(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + + /* vol stable power on */ + bst_write_phys_bst(priv->crm_reg_base + SDEMMC_CRM_VOL_CTRL, + BST_VOL_STABLE_ON); +} + +static const struct sdhci_ops sdhci_dwcmshc_ops =3D { + .set_clock =3D sdhci_set_bst_clock, + .set_bus_width =3D sdhci_set_bus_width, + .set_uhs_signaling =3D sdhci_set_uhs_signaling, + .get_min_clock =3D bst_get_min_clock, + .get_max_clock =3D bst_get_max_clock, + .reset =3D sdhci_bst_reset, + .set_power =3D sdhci_bst_set_power, + .set_timeout =3D sdhci_bst_timeout, + .platform_execute_tuning =3D bst_sdhci_execute_tuning, + .voltage_switch =3D sdhci_bst_voltage_switch, +}; + +static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata =3D { + .ops =3D &sdhci_dwcmshc_ops, + .quirks =3D SDHCI_QUIRK_DELAY_AFTER_POWER | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | + SDHCI_QUIRK_INVERTED_WRITE_PROTECT, + .quirks2 =3D SDHCI_QUIRK2_BROKEN_DDR50 | + SDHCI_QUIRK2_TUNING_WORK_AROUND | + SDHCI_QUIRK2_ACMD23_BROKEN, +}; + +static int bst_sdhci_reallocate_bounce_buffer(struct sdhci_host *host) +{ + struct mmc_host *mmc =3D host->mmc; + unsigned int max_blocks; + unsigned int bounce_size; + int ret; + + /* + * Cap the bounce buffer at 64KB. Using a bigger bounce buffer + * has diminishing returns, this is probably because SD/MMC + * cards are usually optimized to handle this size of requests. + */ + bounce_size =3D SZ_32K; + /* + * Adjust downwards to maximum request size if this is less + * than our segment size, else hammer down the maximum + * request size to the maximum buffer size. + */ + if (mmc->max_req_size < bounce_size) + bounce_size =3D mmc->max_req_size; + max_blocks =3D bounce_size / 512; + + ret =3D of_reserved_mem_device_init_by_idx(mmc_dev(mmc), mmc_dev(mmc)->of= _node, 0); + if (ret) { + dev_err(mmc_dev(mmc), "Failed to initialize reserved memory\n"); + return ret; + } + + host->bounce_buffer =3D dma_alloc_coherent(mmc_dev(mmc), bounce_size, + &host->bounce_addr, GFP_KERNEL); + if (!host->bounce_buffer) + return -ENOMEM; + + host->bounce_buffer_size =3D bounce_size; + + /* Lie about this since we're bouncing */ + mmc->max_segs =3D max_blocks; + mmc->max_seg_size =3D bounce_size; + mmc->max_req_size =3D bounce_size; + + dev_info(mmc_dev(mmc), "BST reallocate %s bounce up to %u segments into o= ne, max segment size %u bytes\n", + mmc_hostname(mmc), max_blocks, bounce_size); + + return 0; +} + +/** + * dwcmshc_probe - Platform driver probe + * @pdev: Platform device + * + * Initializes the SDHCI host controller and registers it. + * + * Return: 0 on success, negative errno on failure + */ +static int dwcmshc_probe(struct platform_device *pdev) +{ + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_host *host; + struct dwcmshc_priv *priv; + struct resource *crm_res; + int err; + + host =3D sdhci_pltfm_init(pdev, &sdhci_dwcmshc_pdata, + sizeof(struct dwcmshc_priv)); + if (IS_ERR(host)) + return PTR_ERR(host); + + pltfm_host =3D sdhci_priv(host); + priv =3D sdhci_pltfm_priv(pltfm_host); + + err =3D mmc_of_parse(host->mmc); + if (err) + goto err; + + sdhci_get_of_property(pdev); + + /* Get CRM registers from the second reg entry */ + crm_res =3D platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!crm_res) { + dev_err(&pdev->dev, "Failed to get CRM register resource\n"); + err =3D -ENODEV; + goto err; + } + + priv->phy_crm_reg_base =3D crm_res->start; + priv->phy_crm_reg_size =3D resource_size(crm_res); + + priv->crm_reg_base =3D ioremap(priv->phy_crm_reg_base, priv->phy_crm_reg_= size); + if (!priv->crm_reg_base) { + dev_err(&pdev->dev, "Failed to ioremap CRM registers\n"); + err =3D -ENOMEM; + goto err; + } + + err =3D sdhci_add_host(host); + if (err) + goto err_iounmap; + + /* + * Hardware limitation workaround: + * + * Our platform supports 64-bit physical addressing, but the eMMC + * controller's SRAM-based DMA engine is constrained to a 32-bit + * address space. When using the standard SDHCI interface, which + * allocates DDR-based DMA buffers with 64-bit addresses, the + * dma_map_single() operation fails because the DMA engine cannot + * handle addresses beyond 32 bits. + * + * To resolve this hardware limitation, we implement a bounce buffer + * allocated via dma_alloc_coherent() to satisfy DMA addressing + * constraints. + */ + err =3D bst_sdhci_reallocate_bounce_buffer(host); + if (err) { + dev_err(&pdev->dev, "Failed to allocate bounce buffer: %d\n", err); + goto err_remove_host; + } + + return 0; + +err_remove_host: + sdhci_remove_host(host, 1); +err_iounmap: + if (priv->crm_reg_base) + iounmap(priv->crm_reg_base); +err: + sdhci_pltfm_free(pdev); + return err; +} + +/** + * dwcmshc_remove - Platform driver remove + * @pdev: Platform device + * + * Removes the SDHCI host controller. + * + * Return: 0 on success + */ +static void dwcmshc_remove(struct platform_device *pdev) +{ + struct sdhci_host *host =3D platform_get_drvdata(pdev); + struct sdhci_pltfm_host *pltfm_host; + struct dwcmshc_priv *priv; + + pltfm_host =3D sdhci_priv(host); + priv =3D sdhci_pltfm_priv(pltfm_host); + + /* Free bounce buffer if allocated */ + if (host->bounce_buffer) { + dma_free_coherent(mmc_dev(host->mmc), host->bounce_buffer_size, + host->bounce_buffer, host->bounce_addr); + host->bounce_buffer =3D NULL; + } + + /* Release reserved memory */ + of_reserved_mem_device_release(mmc_dev(host->mmc)); + + iounmap(priv->crm_reg_base); + + sdhci_remove_host(host, 0); + sdhci_pltfm_free(pdev); +} + +static const struct of_device_id sdhci_dwcmshc_dt_ids[] =3D { + { .compatible =3D "bst,c1200-dwcmshc-sdhci" }, + {} +}; +MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); + +static struct platform_driver sdhci_dwcmshc_driver =3D { + .driver =3D { + .name =3D "sdhci-dwcmshc", + .of_match_table =3D sdhci_dwcmshc_dt_ids, + }, + .probe =3D dwcmshc_probe, + .remove =3D dwcmshc_remove, +}; +module_platform_driver(sdhci_dwcmshc_driver); + +MODULE_DESCRIPTION("Black Sesame Technologies DWCMSHC SDHCI driver"); +MODULE_AUTHOR("Black Sesame Technologies Co., Ltd."); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Wed Oct 8 04:06:42 2025 Received: from mail-m32100.qiye.163.com (mail-m32100.qiye.163.com [220.197.32.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC042221F37; Wed, 2 Jul 2025 11:02:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.100 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751454138; cv=none; b=uoVFCsf5AwTp0HWtQ86fuFnErh1VYd/h5601xhZfYPtkw5Bh3ffXGIjkMTQNSBirpixyzHxZUdBBDh0P6kg6C3PiHknn7qoUWgCj9PXCsw+jTIWzjZWzipVAFuGPm96sF4aBRqfydSV+v6UgH8gReiM6RTSVUvboFZ+SL+3Z4og= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751454138; c=relaxed/simple; bh=kgU0nR5T2dnMIfBxf0LYdE0M+4042kRTIUsHe+PjCFY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RX7zeibFjxe+9+Ip4g4tVWzkriTa6aI81CijAwE5dhWwd1Bq1G+C8zFbRRBYJqcKA+TBB6uk2/K/cqYYXyhitrbW0aDgGLn4AuIUXx+v8NV0oFw/CvdJhr+aEwu6hIxz59vrUN4xzBtdSA5SmP8iqOq2GyTzcnmOi3ebAaGL7Do= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com; spf=pass smtp.mailfrom=thundersoft.com; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b=LcD177pC; arc=none smtp.client-ip=220.197.32.100 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="LcD177pC" Received: from localhost.localdomain (unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1aaa9ed5f; Wed, 2 Jul 2025 17:46:39 +0800 (GMT+08:00) From: Albert Yang To: robh@kernel.org, krzk+dt@kernel.org, krzk@kernel.org, conor+dt@kernel.org, gordon.ge@bst.ai, catalin.marinas@arm.com, geert.uytterhoeven@gmail.com, will@kernel.org, ulf.hansson@linaro.org, adrian.hunter@intel.com, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, bst-upstream@bstai.top, neil.armstrong@linaro.org, jonathan.cameron@huawei.com, bigfoot@classfun.cn, kever.yang@rock-chips.com, mani@kernel.org, geert+renesas@glider.be, andersson@kernel.org, nm@ti.com, nfraprado@collabora.com, quic_tdas@quicinc.com, ebiggers@google.com, victor.shih@genesyslogic.com.tw, shanchun1218@gmail.com, ben.chuang@genesyslogic.com.tw, Albert Yang Subject: [PATCH v2 6/8] arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board and defconfig Date: Wed, 2 Jul 2025 17:44:42 +0800 Message-Id: <20250702094444.3523973-7-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250702094444.3523973-1-yangzh0906@thundersoft.com> References: <20250528085403.481055-1-yangzh0906@thundersoft.com> <20250702094444.3523973-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkZGh1KVhkZSh5IShofGEIZQlYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCS0NVSk tLVUpCWQY+ X-HM-Tid: 0a97ca87fe7709cckunmee1cabff3ebbc1 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NxQ6FRw6ATE9S082Kxo#HU4K SktPChJVSlVKTE5KT09CTUtKTkhLVTMWGhIXVQIaFRwBE0tCS007DxMOFR8eCQgUHQ9VGBQWRVlX WRILWUFZSkpMVUpDT1VKSUJVSkhPWVdZCAFZQUNOSEg3Bg++ DKIM-Signature: a=rsa-sha256; b=LcD177pCHl9iMO/5tUAt9Aup0ONwc3+JngKUJx11307DXxj7xrMMLTfrkru6dy9fG5OqClUhFsen0OXjZr3TQkj6TkPZbRato/YtS6S3q4HxRwn3mjk/5qP8dqv6YM2UrPx63HayhL6GMD7TkHzCDa5meJI89+FfSMnivNyI5SM=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=7zX9xAz2D0jYqJzruhcDB4kWgwhYwe/xmi9zdJYXp4s=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add device tree support for the Black Sesame Technologies (BST) C1200 CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC family. The changes include: - Adding a new BST device tree directory - Adding Makefile entries to build the BST platform device trees - Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board This board features a quad-core Cortex-A78 CPU, and various peripherals including UART, MMC, watchdog timer, and interrupt controller. --- Changes for v2: 1. Reorganized memory map into discrete regions 2. Updated MMC controller definition: - Split into core/CRM register regions - Removed deprecated properties - Updated compatible string 3. Standardized interrupt definitions and numeric formats 4. Removed reserved-memory node (superseded by bounce buffers) 5. Added root compatible string for platform identification 6. Add soc defconfig Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/bst/Makefile | 2 + .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 60 +++++++++ arch/arm64/boot/dts/bst/bstc1200.dtsi | 117 ++++++++++++++++++ arch/arm64/configs/defconfig | 1 + 5 files changed, 181 insertions(+) create mode 100644 arch/arm64/boot/dts/bst/Makefile create mode 100644 arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts create mode 100644 arch/arm64/boot/dts/bst/bstc1200.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 79b73a21ddc2..a39b6cafb644 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -12,6 +12,7 @@ subdir-y +=3D arm subdir-y +=3D bitmain subdir-y +=3D blaize subdir-y +=3D broadcom +subdir-y +=3D bst subdir-y +=3D cavium subdir-y +=3D exynos subdir-y +=3D freescale diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Mak= efile new file mode 100644 index 000000000000..4c1b8b4cdad8 --- /dev/null +++ b/arch/arm64/boot/dts/bst/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BST) +=3D bstc1200-cdcu1.0-adas_4c2g.dtb diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/= arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts new file mode 100644 index 000000000000..4036e0ac2e1d --- /dev/null +++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "bstc1200.dtsi" + +/ { + model =3D "BST C1200-96 CDCU1.0 4C2G"; + compatible =3D "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@810000000 { + device_type =3D "memory"; + reg =3D <0x8 0x10000000 0x0 0x30000000>; + }; + + memory@8c0000000 { + device_type =3D "memory"; + reg =3D <0x8 0xc0000000 0x1 0x0>; + }; + + memory@c00000000 { + device_type =3D "memory"; + reg =3D <0xc 0x0 0x0 0x40000000>; + }; + + memory@800254000 { + device_type =3D "memory"; + reg =3D <0x8 0x254000 0x0 0x1000>; + }; + + memory@800151000 { + device_type =3D "memory"; + reg =3D <0x8 0x151000 0x0 0x1000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + mmc0_reserved: mmc0@5160000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x5160000 0x0 0x10000>; + no-map; + }; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&mmc0 { + status =3D "okay"; + memory-region =3D <&mmc0_reserved>; +}; + diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bs= t/bstc1200.dtsi new file mode 100644 index 000000000000..ddff2cb82cb0 --- /dev/null +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +/ { + compatible =3D "bst,c1200"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,cortex-a78"; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + reg =3D <0>; + }; + + cpu@1 { + compatible =3D "arm,cortex-a78"; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + reg =3D <0x100>; + }; + + cpu@2 { + compatible =3D "arm,cortex-a78"; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + reg =3D <0x200>; + }; + + cpu@3 { + compatible =3D "arm,cortex-a78"; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + reg =3D <0x300>; + }; + + l2_cache: l2-cache-1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + clk_mmc: clock-4000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <4000000>; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + always-on; + interrupts =3D , + , + , + ; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x0 0xffffffff 0xffffffff>; + interrupt-parent =3D <&gic>; + + mmc0: mmc@22200000 { + compatible =3D "bst,c1200-dwcmshc-sdhci"; + reg =3D <0x0 0x22200000 0x0 0x1000>, + <0x0 0x23006000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_mmc>; + clock-names =3D "core"; + max-frequency =3D <200000000>; + bus-width =3D <8>; + non-removable; + dma-coherent; + status =3D "disabled"; + }; + + uart0: serial@20008000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x20008000 0x0 0x1000>; + interrupts =3D ; + clock-frequency =3D <25000000>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + gic: interrupt-controller@32800000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <3>; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-controller; + ranges; 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spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="R9lyRD54" Received: from localhost.localdomain (unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1aaa9ed6b; Wed, 2 Jul 2025 17:46:41 +0800 (GMT+08:00) From: Albert Yang To: robh@kernel.org, krzk+dt@kernel.org, krzk@kernel.org, conor+dt@kernel.org, gordon.ge@bst.ai, catalin.marinas@arm.com, geert.uytterhoeven@gmail.com, will@kernel.org, ulf.hansson@linaro.org, adrian.hunter@intel.com, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, bst-upstream@bstai.top, neil.armstrong@linaro.org, jonathan.cameron@huawei.com, bigfoot@classfun.cn, kever.yang@rock-chips.com, mani@kernel.org, geert+renesas@glider.be, andersson@kernel.org, nm@ti.com, nfraprado@collabora.com, quic_tdas@quicinc.com, ebiggers@google.com, victor.shih@genesyslogic.com.tw, shanchun1218@gmail.com, ben.chuang@genesyslogic.com.tw, Albert Yang Subject: [PATCH v2 7/8] arm64: defconfig: enable BST C1200 DWCMSHC SDHCI controller Date: Wed, 2 Jul 2025 17:44:43 +0800 Message-Id: <20250702094444.3523973-8-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250702094444.3523973-1-yangzh0906@thundersoft.com> References: <20250528085403.481055-1-yangzh0906@thundersoft.com> <20250702094444.3523973-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDSUJCVhgaHR1OT0xMSx1MHVYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCS0NVSk tLVUpCWQY+ X-HM-Tid: 0a97ca88063009cckunmee1cabff3ebc08 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Ny46Fgw4FzErGk80QhkOHUwd IjoKFDdVSlVKTE5KT09CTUtIT05IVTMWGhIXVQIaFRwBE0tCS007DxMOFR8eCQgUHQ9VGBQWRVlX WRILWUFZSkpMVUpDT1VKSUJVSkhPWVdZCAFZQUlISUk3Bg++ DKIM-Signature: a=rsa-sha256; b=R9lyRD54Sd2OSBXZOeyjBa35mm+g96MMrnIt2kvkDlTYu3kRcoCuzYY0U2D7Gzudg67W3pnoe5K6jnrW1+/uXPFQaNXNawf7h4diraXb5uDEllw/WY9jjbGY1wVICrUII2PnhUu9iQfOiWyzVySSlUZAolI9SkPZ88dbqxSS3Y0=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=sSxvWs1jHzibMyZ86YFGGKkxcE98EspXtSKi7G7lkyg=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Enable the BST C1200 DWCMSHC SDHCI controller driver (CONFIG_MMC_SDHCI_BST) in the ARM64 defconfig to support eMMC/SD card access on Black Sesame Technologies C1200 series SoCs. This driver provides hardware-specific implementation for the Synopsys DesignWare Mobile Storage Host Controller integrated in BST SoCs. Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0a1cfaa19688..8daf8cf3dc97 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1188,6 +1188,7 @@ CONFIG_MMC_SDHCI_CADENCE=3Dy CONFIG_MMC_SDHCI_ESDHC_IMX=3Dy CONFIG_MMC_SDHCI_TEGRA=3Dy CONFIG_MMC_SDHCI_F_SDH30=3Dy +CONFIG_MMC_SDHCI_BST=3Dy CONFIG_MMC_MESON_GX=3Dy CONFIG_MMC_SDHCI_MSM=3Dy CONFIG_MMC_SPI=3Dy --=20 2.25.1 From nobody Wed Oct 8 04:06:42 2025 Received: from mail-m32114.qiye.163.com (mail-m32114.qiye.163.com [220.197.32.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B95E2309B0; Wed, 2 Jul 2025 09:52:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.114 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751449923; cv=none; b=Vimzj/OgyOu8Ik56xERE0YsTbwg2VR+8aEidjJYoscwgn/loUVg9nYtXBbDXWI6U0T9ogDcxZcZynHB2DEiGqRyQxqbK918jSI0oNPScnZTN45yhxayXj0ZzEx8OYf/PM5f7BHhiCjaAekV9mZuDl9lrDIjbLgOHUs83LlwgHxM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751449923; c=relaxed/simple; bh=lPb9dIxD5+q4ZIVxyYI/lgNb35z0XDJuRZgexaTKPl0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PZ41P3/W7nvf6pIpA2W1UESc/G06p//9RNP/+/REgqRWH122j4dRzjNaeVtSh7lTpZ6yxZSysV9cNN8ZSJfM5H+12lUMsndSaWikcec1V86gZL6ZVYKBUAuyQye2C1DrmBXQtkRyIcwpV2hvSNnSBEK/VXGb7Q0dnKo7/S9bHbs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com; spf=pass smtp.mailfrom=thundersoft.com; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b=k/yCuMJx; arc=none smtp.client-ip=220.197.32.114 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="k/yCuMJx" Received: from localhost.localdomain (unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1aaa9ed79; Wed, 2 Jul 2025 17:46:43 +0800 (GMT+08:00) From: Albert Yang To: robh@kernel.org, krzk+dt@kernel.org, krzk@kernel.org, conor+dt@kernel.org, gordon.ge@bst.ai, catalin.marinas@arm.com, geert.uytterhoeven@gmail.com, will@kernel.org, ulf.hansson@linaro.org, adrian.hunter@intel.com, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, bst-upstream@bstai.top, neil.armstrong@linaro.org, jonathan.cameron@huawei.com, bigfoot@classfun.cn, kever.yang@rock-chips.com, mani@kernel.org, geert+renesas@glider.be, andersson@kernel.org, nm@ti.com, nfraprado@collabora.com, quic_tdas@quicinc.com, ebiggers@google.com, victor.shih@genesyslogic.com.tw, shanchun1218@gmail.com, ben.chuang@genesyslogic.com.tw, Albert Yang Subject: [PATCH v2 8/8] MAINTAINERS: add and consolidate Black Sesame Technologies (BST) ARM SoC support Date: Wed, 2 Jul 2025 17:44:44 +0800 Message-Id: <20250702094444.3523973-9-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250702094444.3523973-1-yangzh0906@thundersoft.com> References: <20250528085403.481055-1-yangzh0906@thundersoft.com> <20250702094444.3523973-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDSB0YVk9CGE8ZGUxOHh8fTlYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCS0NVSk tLVUpCWQY+ X-HM-Tid: 0a97ca880db309cckunmee1cabff3ebc57 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Ojo6TCo6OTE0KE8xQiEqHUoj DRxPFDJVSlVKTE5KT09CTUtOT01MVTMWGhIXVQIaFRwBE0tCS007DxMOFR8eCQgUHQ9VGBQWRVlX WRILWUFZSkpMVUpDT1VKSUJVSkhPWVdZCAFZQUlNSko3Bg++ DKIM-Signature: a=rsa-sha256; b=k/yCuMJxVeOXaX4UC8xJi8N4oYoHJBUgI1LfpKFjPnB0IpJl5J+ZvP1CeNHd5xPvj8sBdGPHEl5OeI/GNiObheVCq98z6l4Hw7F/B6KMhgVIlpNsRy5+0mWzl6SfnEY1pagXQRbRF+bJDcH1Q70fM5B+IBaK9MIBcLl45KFJN0A=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=p49bABjbEnShhniwT4G/iwpGc59+QIBwBwIG2CyY6WA=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add and consolidate the MAINTAINERS entry for Black Sesame Technologies ARM SoC support. This entry covers device tree bindings, drivers, and board files for BST SoCs, including MMC, and platform support. Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index efb51ee92683..e3236384c28a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2441,6 +2441,16 @@ S: Maintained F: Documentation/devicetree/bindings/arm/blaize.yaml F: arch/arm64/boot/dts/blaize/ =20 +ARM/BST SOC SUPPORT +M: Ge Gordon +R: BST Linux Kernel Upstream Group +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/arm/bst.yaml +F: Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml +F: arch/arm64/boot/dts/bst/ +F: drivers/mmc/host/sdhci-of-bst-c1200.c + ARM/CALXEDA HIGHBANK ARCHITECTURE M: Andre Przywara L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.25.1