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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2025 09:38:41.9942 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18f2bde5-29ff-46cb-eb9a-08ddb94c3b53 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV5PR12MB9754 Content-Type: text/plain; charset="utf-8" Rearrange initial setup of AMD IOMMU debugfs to segregate per IOMMU setup and setup which is common for all IOMMUs. This ensures that common debugfs paths (introduced in subsequent patches) are created only once instead of being created for each IOMMU. With the change, there is no need to use lock as amd_iommu_debugfs_setup() will be called only once during AMD IOMMU initialization. So remove lock acquisition in amd_iommu_debugfs_setup(). Signed-off-by: Dheeraj Kumar Srivastava Reviewed-by: Suravee Suthikulpanit Reviewed-by: Vasant Hegde --- drivers/iommu/amd/amd_iommu.h | 4 ++-- drivers/iommu/amd/debugfs.c | 16 +++++++--------- drivers/iommu/amd/init.c | 5 ++--- 3 files changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 220c598b7e14..70873bb78b3c 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -28,9 +28,9 @@ void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, size_t size); =20 #ifdef CONFIG_AMD_IOMMU_DEBUGFS -void amd_iommu_debugfs_setup(struct amd_iommu *iommu); +void amd_iommu_debugfs_setup(void); #else -static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {} +static inline void amd_iommu_debugfs_setup(void) {} #endif =20 /* Needed for interrupt remapping */ diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index 545372fcc72f..ff9520e002be 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -13,20 +13,18 @@ #include "amd_iommu.h" =20 static struct dentry *amd_iommu_debugfs; -static DEFINE_MUTEX(amd_iommu_debugfs_lock); =20 #define MAX_NAME_LEN 20 =20 -void amd_iommu_debugfs_setup(struct amd_iommu *iommu) +void amd_iommu_debugfs_setup(void) { + struct amd_iommu *iommu; char name[MAX_NAME_LEN + 1]; =20 - mutex_lock(&amd_iommu_debugfs_lock); - if (!amd_iommu_debugfs) - amd_iommu_debugfs =3D debugfs_create_dir("amd", - iommu_debugfs_dir); - mutex_unlock(&amd_iommu_debugfs_lock); + amd_iommu_debugfs =3D debugfs_create_dir("amd", iommu_debugfs_dir); =20 - snprintf(name, MAX_NAME_LEN, "iommu%02d", iommu->index); - iommu->debugfs =3D debugfs_create_dir(name, amd_iommu_debugfs); + for_each_iommu(iommu) { + snprintf(name, MAX_NAME_LEN, "iommu%02d", iommu->index); + iommu->debugfs =3D debugfs_create_dir(name, amd_iommu_debugfs); + } } diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 14aa0d77df26..ecc6c246f87e 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -3387,7 +3387,6 @@ int amd_iommu_enable_faulting(unsigned int cpu) */ static int __init amd_iommu_init(void) { - struct amd_iommu *iommu; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2025 09:38:58.7797 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13857265-7862-42df-672f-08ddb94c4555 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9182 Content-Type: text/plain; charset="utf-8" Analyzing IOMMU MMIO registers gives a view of what IOMMU is configured with on the system and is helpful to debug issues with IOMMU. eg. -> To get mmio registers value at offset 0x18 for iommu (say, iommu00) # echo "0x18" > /sys/kernel/debug/iommu/amd/iommu00/mmio # cat /sys/kernel/debug/iommu/amd/iommu00/mmio Signed-off-by: Dheeraj Kumar Srivastava Reviewed-by: Vasant Hegde --- drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/debugfs.c | 47 +++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 5089b58e528a..5aec9cc7441f 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -796,6 +796,7 @@ struct amd_iommu { #ifdef CONFIG_AMD_IOMMU_DEBUGFS /* DebugFS Info */ struct dentry *debugfs; + int dbg_mmio_offset; #endif =20 /* IOPF support */ diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index ff9520e002be..c025b4d2398d 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -15,6 +15,48 @@ static struct dentry *amd_iommu_debugfs; =20 #define MAX_NAME_LEN 20 +#define OFS_IN_SZ 8 + +static ssize_t iommu_mmio_write(struct file *filp, const char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + struct seq_file *m =3D filp->private_data; + struct amd_iommu *iommu =3D m->private; + int ret; + + iommu->dbg_mmio_offset =3D -1; + + if (cnt > OFS_IN_SZ) + return -EINVAL; + + ret =3D kstrtou32_from_user(ubuf, cnt, 0, &iommu->dbg_mmio_offset); + if (ret) + return ret; + + if (iommu->dbg_mmio_offset > iommu->mmio_phys_end - 4) { + iommu->dbg_mmio_offset =3D -1; + return -EINVAL; + } + + return cnt; +} + +static int iommu_mmio_show(struct seq_file *m, void *unused) +{ + struct amd_iommu *iommu =3D m->private; + u64 value; + + if (iommu->dbg_mmio_offset < 0) { + seq_puts(m, "Please provide mmio register's offset\n"); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2025 09:39:17.7419 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63bd00a4-dddf-42c4-a2cc-08ddb94c50a2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD83.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8833 Content-Type: text/plain; charset="utf-8" IOMMU Capability registers defines capabilities of IOMMU and information needed for initialising MMIO registers and device table. This is useful to dump these registers for debugging IOMMU related issues. e.g. -> To get capability registers value at offset 0x10 for iommu (say, iommu00) # echo "0x10" > /sys/kernel/debug/iommu/amd/iommu00/capability # cat /sys/kernel/debug/iommu/amd/iommu00/capability Signed-off-by: Dheeraj Kumar Srivastava Reviewed-by: Vasant Hegde --- drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/debugfs.c | 52 +++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 5aec9cc7441f..01edab37c25c 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -797,6 +797,7 @@ struct amd_iommu { /* DebugFS Info */ struct dentry *debugfs; int dbg_mmio_offset; + int dbg_cap_offset; #endif =20 /* IOPF support */ diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index c025b4d2398d..f843e184a62b 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -58,6 +58,55 @@ static int iommu_mmio_show(struct seq_file *m, void *unu= sed) } DEFINE_SHOW_STORE_ATTRIBUTE(iommu_mmio); =20 +static ssize_t iommu_capability_write(struct file *filp, const char __user= *ubuf, + size_t cnt, loff_t *ppos) +{ + struct seq_file *m =3D filp->private_data; + struct amd_iommu *iommu =3D m->private; + int ret; + + iommu->dbg_cap_offset =3D -1; + + if (cnt > OFS_IN_SZ) + return -EINVAL; + + ret =3D kstrtou32_from_user(ubuf, cnt, 0, &iommu->dbg_cap_offset); + if (ret) + return ret; + + /* Capability register at offset 0x14 is the last IOMMU capability regist= er. */ + if (iommu->dbg_cap_offset > 0x14) { + iommu->dbg_cap_offset =3D -1; + return -EINVAL; + } + + return cnt; +} + +static int iommu_capability_show(struct seq_file *m, void *unused) +{ + struct amd_iommu *iommu =3D m->private; + u32 value; + int err; + + if (iommu->dbg_cap_offset < 0) { + seq_puts(m, "Please provide capability register's offset in the range [0= x00 - 0x14]\n"); + return 0; + } + + err =3D pci_read_config_dword(iommu->dev, iommu->cap_ptr + iommu->dbg_cap= _offset, &value); + if (err) { + seq_printf(m, "Not able to read capability register at 0x%x\n", + iommu->dbg_cap_offset); + return 0; + } + + seq_printf(m, "Offset:0x%x Value:0x%08x\n", iommu->dbg_cap_offset, value); + + return 0; +} +DEFINE_SHOW_STORE_ATTRIBUTE(iommu_capability); + void amd_iommu_debugfs_setup(void) { struct amd_iommu *iommu; @@ -67,11 +116,14 @@ void amd_iommu_debugfs_setup(void) =20 for_each_iommu(iommu) { iommu->dbg_mmio_offset =3D -1; + iommu->dbg_cap_offset =3D -1; =20 snprintf(name, MAX_NAME_LEN, "iommu%02d", iommu->index); iommu->debugfs =3D debugfs_create_dir(name, amd_iommu_debugfs); =20 debugfs_create_file("mmio", 0644, iommu->debugfs, iommu, &iommu_mmio_fops); + debugfs_create_file("capability", 0644, iommu->debugfs, iommu, + &iommu_capability_fops); } } --=20 2.25.1 From nobody Wed Oct 8 04:06:42 2025 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2079.outbound.protection.outlook.com [40.107.94.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D40D0228CBE for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2025 09:39:32.6024 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43c3e046-061e-41ee-9cd1-08ddb94c597d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD83.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9540 Content-Type: text/plain; charset="utf-8" IOMMU driver sends command to IOMMU hardware via command buffer. In cases where IOMMU hardware fails to process commands in command buffer, dumping it is a valuable input to debug the issue. IOMMU hardware processes command buffer entry at offset equals to the head pointer. Dumping just the entry at the head pointer may not always be useful. The current head may not be pointing to the entry of the command buffer which is causing the issue. IOMMU Hardware may have processed the entry and updated the head pointer. So dumping the entire command buffer gives a broad understanding of what hardware was/is doing. The command buffer dump will have all entries from start to end of the command buffer. Along with that, it will have a head and tail command buffer pointer register dump to facilitate where the IOMMU driver and hardware are in the command buffer for injecting and processing the entries respectively. Command buffer is a per IOMMU data structure. So dumping on per IOMMU basis. eg. -> To get command buffer dump for iommu (say, iommu00) #cat /sys/kernel/debug/iommu/amd/iommu00/cmdbuf Signed-off-by: Dheeraj Kumar Srivastava Reviewed-by: Vasant Hegde --- drivers/iommu/amd/amd_iommu_types.h | 7 +++++++ drivers/iommu/amd/debugfs.c | 26 ++++++++++++++++++++++++++ drivers/iommu/amd/iommu.c | 7 ------- 3 files changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 01edab37c25c..38bd765acaf9 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -898,6 +898,13 @@ struct dev_table_entry { }; }; =20 +/* + * Structure defining one entry in the command buffer + */ +struct iommu_cmd { + u32 data[4]; +}; + /* * Structure to sture persistent DTE flags from IVHD */ diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index f843e184a62b..e78f6b217a7b 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -107,6 +107,30 @@ static int iommu_capability_show(struct seq_file *m, v= oid *unused) } DEFINE_SHOW_STORE_ATTRIBUTE(iommu_capability); =20 +static int iommu_cmdbuf_show(struct seq_file *m, void *unused) +{ + struct amd_iommu *iommu =3D m->private; + struct iommu_cmd *cmd; + unsigned long flag; + u32 head, tail; + int i; + + raw_spin_lock_irqsave(&iommu->lock, flag); + head =3D readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); + tail =3D readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); + seq_printf(m, "CMD Buffer Head Offset:%d Tail Offset:%d\n", + (head >> 4) & 0x7fff, (tail >> 4) & 0x7fff); + for (i =3D 0; i < CMD_BUFFER_ENTRIES; i++) { + cmd =3D (struct iommu_cmd *)(iommu->cmd_buf + i * sizeof(*cmd)); + seq_printf(m, "%3d: %08x %08x %08x %08x\n", i, cmd->data[0], + cmd->data[1], cmd->data[2], cmd->data[3]); + } + raw_spin_unlock_irqrestore(&iommu->lock, flag); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(iommu_cmdbuf); + void amd_iommu_debugfs_setup(void) { struct amd_iommu *iommu; @@ -125,5 +149,7 @@ void amd_iommu_debugfs_setup(void) &iommu_mmio_fops); debugfs_create_file("capability", 0644, iommu->debugfs, iommu, &iommu_capability_fops); + debugfs_create_file("cmdbuf", 0444, iommu->debugfs, iommu, + &iommu_cmdbuf_fops); } } diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index f34209b08b4c..522251f60e8e 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -62,13 +62,6 @@ static const struct iommu_dirty_ops amd_dirty_ops; =20 int amd_iommu_max_glx_val =3D -1; =20 -/* - * general struct to manage commands send to an IOMMU - */ -struct iommu_cmd { - u32 data[4]; -}; - /* * AMD IOMMU allows up to 2^16 different protection domains. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2025 09:39:49.7084 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4783f976-0abf-4c1f-53c3-08ddb94c63b0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFF1E6547B5 Content-Type: text/plain; charset="utf-8" Dumping IOMMU data structures like device table, IRT, etc., for all devices on the system will be a lot of data dumped in a file. Also, user may want to dump and analyze these data structures just for one or few devices. So dumping IOMMU data structures like device table, IRT etc for all devices is not a good approach. Add "device id" user input to be used for dumping IOMMU data structures like device table, IRT etc in AMD IOMMU debugfs. eg. 1. # echo 0000:01:00.0 > /sys/kernel/debug/iommu/amd/devid # cat /sys/kernel/debug/iommu/amd/devid Output : 0000:01:00.0 2. # echo 01:00.0 > /sys/kernel/debug/iommu/amd/devid # cat /sys/kernel/debug/iommu/amd/devid Output : 0000:01:00.0 Signed-off-by: Dheeraj Kumar Srivastava Reviewed-by: Vasant Hegde --- drivers/iommu/amd/debugfs.c | 80 +++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index e78f6b217a7b..065b150bba15 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -16,6 +16,9 @@ static struct dentry *amd_iommu_debugfs; =20 #define MAX_NAME_LEN 20 #define OFS_IN_SZ 8 +#define DEVID_IN_SZ 16 + +static int sbdf =3D -1; =20 static ssize_t iommu_mmio_write(struct file *filp, const char __user *ubuf, size_t cnt, loff_t *ppos) @@ -131,6 +134,80 @@ static int iommu_cmdbuf_show(struct seq_file *m, void = *unused) } DEFINE_SHOW_ATTRIBUTE(iommu_cmdbuf); =20 +static ssize_t devid_write(struct file *filp, const char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + struct amd_iommu_pci_seg *pci_seg; + int seg, bus, slot, func; + struct amd_iommu *iommu; + char *srcid_ptr; + u16 devid; + int i; + + sbdf =3D -1; + + if (cnt >=3D DEVID_IN_SZ) + return -EINVAL; + + srcid_ptr =3D memdup_user_nul(ubuf, cnt); + if (IS_ERR(srcid_ptr)) + return PTR_ERR(srcid_ptr); + + i =3D sscanf(srcid_ptr, "%x:%x:%x.%x", &seg, &bus, &slot, &func); + if (i !=3D 4) { + i =3D sscanf(srcid_ptr, "%x:%x.%x", &bus, &slot, &func); + if (i !=3D 3) { + kfree(srcid_ptr); + return -EINVAL; + } + seg =3D 0; + } + + devid =3D PCI_DEVID(bus, PCI_DEVFN(slot, func)); + + /* Check if user device id input is a valid input */ + for_each_pci_segment(pci_seg) { + if (pci_seg->id !=3D seg) + continue; + if (devid > pci_seg->last_bdf) { + kfree(srcid_ptr); + return -EINVAL; + } + iommu =3D pci_seg->rlookup_table[devid]; + if (!iommu) { + kfree(srcid_ptr); + return -ENODEV; + } + break; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2025 09:40:06.4964 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3435acf8-2d1f-465c-1fb3-08ddb94c6db2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD82.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7770 Content-Type: text/plain; charset="utf-8" IOMMU uses device table data structure to get per-device information for DMA remapping, interrupt remapping, and other functionalities. It's a valuable data structure to visualize for debugging issues related to IOMMU. eg. -> To dump device table entry for a particular device #echo 0000:c4:00.0 > /sys/kernel/debug/iommu/amd/devid #cat /sys/kernel/debug/iommu/amd/devtbl or #echo c4:00.0 > /sys/kernel/debug/iommu/amd/devid #cat /sys/kernel/debug/iommu/amd/devtbl Signed-off-by: Dheeraj Kumar Srivastava Reviewed-by: Vasant Hegde --- drivers/iommu/amd/debugfs.c | 49 +++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index 065b150bba15..b01eea2fbe03 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -208,6 +208,53 @@ static int devid_show(struct seq_file *m, void *unused) } DEFINE_SHOW_STORE_ATTRIBUTE(devid); =20 +static void dump_dte(struct seq_file *m, struct amd_iommu_pci_seg *pci_seg= , u16 devid) +{ + struct dev_table_entry *dev_table; + struct amd_iommu *iommu; + + iommu =3D pci_seg->rlookup_table[devid]; + if (!iommu) + return; + + dev_table =3D get_dev_table(iommu); + if (!dev_table) { + seq_puts(m, "Device table not found"); + return; + } + + seq_printf(m, "%-12s %16s %16s %16s %16s iommu\n", "DeviceId", + "QWORD[3]", "QWORD[2]", "QWORD[1]", "QWORD[0]"); + seq_printf(m, "%04x:%02x:%02x.%x ", pci_seg->id, PCI_BUS_NUM(devid), + PCI_SLOT(devid), PCI_FUNC(devid)); + for (int i =3D 3; i >=3D 0; --i) + seq_printf(m, "%016llx ", dev_table[devid].data[i]); + seq_printf(m, "iommu%d\n", iommu->index); +} + +static int iommu_devtbl_show(struct seq_file *m, void *unused) +{ + struct amd_iommu_pci_seg *pci_seg; + u16 seg, devid; + + if (sbdf < 0) { + seq_puts(m, "Enter a valid device ID to 'devid' file\n"); + return 0; + } + seg =3D PCI_SBDF_TO_SEGID(sbdf); + devid =3D PCI_SBDF_TO_DEVID(sbdf); + + for_each_pci_segment(pci_seg) { + if (pci_seg->id !=3D seg) + continue; + dump_dte(m, pci_seg, devid); + break; + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(iommu_devtbl); + void amd_iommu_debugfs_setup(void) { struct amd_iommu *iommu; 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Wed, 2 Jul 2025 09:40:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD83.mail.protection.outlook.com (10.167.244.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8901.15 via Frontend Transport; Wed, 2 Jul 2025 09:40:23 +0000 Received: from BLRDHSRIVAS.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 2 Jul 2025 04:40:19 -0500 From: Dheeraj Kumar Srivastava To: , , , , , , CC: Subject: [PATCH v7 7/8] iommu/amd: Add debugfs support to dump IRT Table Date: Wed, 2 Jul 2025 15:08:03 +0530 Message-ID: <20250702093804.849-8-dheerajkumar.srivastava@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250702093804.849-1-dheerajkumar.srivastava@amd.com> References: <20250702093804.849-1-dheerajkumar.srivastava@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD83:EE_|DM6PR12MB4155:EE_ X-MS-Office365-Filtering-Correlation-Id: 67dd3531-4704-4d20-6b9f-08ddb94c77a3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2025 09:40:23.1807 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 67dd3531-4704-4d20-6b9f-08ddb94c77a3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD83.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4155 Content-Type: text/plain; charset="utf-8" In cases where we have an issue in the device interrupt path with IOMMU interrupt remapping enabled, dumping valid IRT table entries for the device is very useful and good input for debugging the issue. eg. -> To dump irte entries for a particular device #echo "c4:00.0" > /sys/kernel/debug/iommu/amd/devid #cat /sys/kernel/debug/iommu/amd/irqtbl | less or #echo "0000:c4:00.0" > /sys/kernel/debug/iommu/amd/devid #cat /sys/kernel/debug/iommu/amd/irqtbl | less Signed-off-by: Dheeraj Kumar Srivastava Reviewed-by: Vasant Hegde --- drivers/iommu/amd/debugfs.c | 108 ++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index b01eea2fbe03..10fa217a7119 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -11,6 +11,7 @@ #include =20 #include "amd_iommu.h" +#include "../irq_remapping.h" =20 static struct dentry *amd_iommu_debugfs; =20 @@ -255,6 +256,111 @@ static int iommu_devtbl_show(struct seq_file *m, void= *unused) } DEFINE_SHOW_ATTRIBUTE(iommu_devtbl); =20 +static void dump_128_irte(struct seq_file *m, struct irq_remap_table *tabl= e, u16 int_tab_len) +{ + struct irte_ga *ptr, *irte; + int index; + + for (index =3D 0; index < int_tab_len; index++) { + ptr =3D (struct irte_ga *)table->table; + irte =3D &ptr[index]; + + if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && + !irte->lo.fields_vapic.valid) + continue; + else if (!irte->lo.fields_remap.valid) + continue; + seq_printf(m, "IRT[%04d] %016llx %016llx\n", index, irte->hi.val, irte->= lo.val); + } +} + +static void dump_32_irte(struct seq_file *m, struct irq_remap_table *table= , u16 int_tab_len) +{ + union irte *ptr, *irte; + int index; + + for (index =3D 0; index < int_tab_len; index++) { + ptr =3D (union irte *)table->table; + irte =3D &ptr[index]; + + if (!irte->fields.valid) + continue; + seq_printf(m, "IRT[%04d] %08x\n", index, irte->val); + } +} + +static void dump_irte(struct seq_file *m, u16 devid, struct amd_iommu_pci_= seg *pci_seg) +{ + struct dev_table_entry *dev_table; + struct irq_remap_table *table; + struct amd_iommu *iommu; + unsigned long flags; + u16 int_tab_len; + + table =3D pci_seg->irq_lookup_table[devid]; + if (!table) { + seq_printf(m, "IRQ lookup table not set for %04x:%02x:%02x:%x\n", + pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid)); + return; + } + + iommu =3D pci_seg->rlookup_table[devid]; + if (!iommu) + return; + + dev_table =3D get_dev_table(iommu); + if (!dev_table) { + seq_puts(m, "Device table not found"); + return; + } + + int_tab_len =3D dev_table[devid].data[2] & DTE_INTTABLEN_MASK; + if (int_tab_len !=3D DTE_INTTABLEN_512 && int_tab_len !=3D DTE_INTTABLEN_= 2K) { + seq_puts(m, "The device's DTE contains an invalid IRT length value."); + return; + } + + seq_printf(m, "DeviceId %04x:%02x:%02x.%x\n", pci_seg->id, PCI_BUS_NUM(de= vid), + PCI_SLOT(devid), PCI_FUNC(devid)); + + raw_spin_lock_irqsave(&table->lock, flags); + if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) + dump_128_irte(m, table, BIT(int_tab_len >> 1)); + else + dump_32_irte(m, table, BIT(int_tab_len >> 1)); + seq_puts(m, "\n"); + raw_spin_unlock_irqrestore(&table->lock, flags); +} + +static int iommu_irqtbl_show(struct seq_file *m, void *unused) +{ + struct amd_iommu_pci_seg *pci_seg; + u16 devid, seg; + + if (!irq_remapping_enabled) { + seq_puts(m, "Interrupt remapping is disabled\n"); + return 0; + } + + if (sbdf < 0) { + seq_puts(m, "Enter a valid device ID to 'devid' file\n"); + return 0; + } + + seg =3D PCI_SBDF_TO_SEGID(sbdf); + devid =3D PCI_SBDF_TO_DEVID(sbdf); + + for_each_pci_segment(pci_seg) { + if (pci_seg->id !=3D seg) + continue; + dump_irte(m, devid, pci_seg); + break; + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(iommu_irqtbl); + void amd_iommu_debugfs_setup(void) { struct amd_iommu *iommu; @@ -281,4 +387,6 @@ void amd_iommu_debugfs_setup(void) &devid_fops); debugfs_create_file("devtbl", 0444, amd_iommu_debugfs, NULL, &iommu_devtbl_fops); + debugfs_create_file("irqtbl", 0444, amd_iommu_debugfs, NULL, + &iommu_irqtbl_fops); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2025 09:40:40.9813 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2618f69-b7d9-44ce-340a-08ddb94c8240 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPF8002542C7 Content-Type: text/plain; charset="utf-8" Add documentation describing how to use AMD IOMMU debugfs support to dump IOMMU data structures - IRT table, Device table, Registers (MMIO and Capability) and command buffer. Signed-off-by: Dheeraj Kumar Srivastava Reviewed-by: Vasant Hegde --- Documentation/ABI/testing/debugfs-amd-iommu | 114 ++++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/ABI/testing/debugfs-amd-iommu diff --git a/Documentation/ABI/testing/debugfs-amd-iommu b/Documentation/AB= I/testing/debugfs-amd-iommu new file mode 100644 index 000000000000..c14b1620aec1 --- /dev/null +++ b/Documentation/ABI/testing/debugfs-amd-iommu @@ -0,0 +1,114 @@ +What: /sys/kernel/debug/iommu/amd/iommu/mmio +Date: January 2025 +Contact: Dheeraj Kumar Srivastava +Description: + This file provides read/write access for user input. Users specify the + MMIO register offset for iommu, and the file outputs the corresponding + MMIO register value of iommu + + Example: + $ echo "0x18" > /sys/kernel/debug/iommu/amd/iommu00/mmio + $ cat /sys/kernel/debug/iommu/amd/iommu00/mmio + + Output: + Offset:0x18 Value:0x000c22000003f48d + +What: /sys/kernel/debug/iommu/amd/iommu/capability +Date: January 2025 +Contact: Dheeraj Kumar Srivastava +Description: + This file provides read/write access for user input. Users specify the + capability register offset for iommu, and the file outputs the + corresponding capability register value of iommu. + + Example: + $ echo "0x10" > /sys/kernel/debug/iommu/amd/iommu00/capability + $ cat /sys/kernel/debug/iommu/amd/iommu00/capability + + Output: + Offset:0x10 Value:0x00203040 + +What: /sys/kernel/debug/iommu/amd/iommu/cmdbuf +Date: January 2025 +Contact: Dheeraj Kumar Srivastava +Description: + This file is a read-only output file containing iommu command + buffer entries. + + Examples: + $ cat /sys/kernel/debug/iommu/amd/iommu/cmdbuf + + Output: + CMD Buffer Head Offset:339 Tail Offset:339 + 0: 00835001 10000001 00003c00 00000000 + 1: 00000000 30000005 fffff003 7fffffff + 2: 00835001 10000001 00003c01 00000000 + 3: 00000000 30000005 fffff003 7fffffff + 4: 00835001 10000001 00003c02 00000000 + 5: 00000000 30000005 fffff003 7fffffff + 6: 00835001 10000001 00003c03 00000000 + 7: 00000000 30000005 fffff003 7fffffff + 8: 00835001 10000001 00003c04 00000000 + 9: 00000000 30000005 fffff003 7fffffff + 10: 00835001 10000001 00003c05 00000000 + 11: 00000000 30000005 fffff003 7fffffff + [...] + +What: /sys/kernel/debug/iommu/amd/devid +Date: January 2025 +Contact: Dheeraj Kumar Srivastava +Description: + This file provides read/write access for user input. Users specify the + device ID, which can be used to dump IOMMU data structures such as the + interrupt remapping table and device table. + + Example: + 1. + $ echo 0000:01:00.0 > /sys/kernel/debug/iommu/amd/devid + $ cat /sys/kernel/debug/iommu/amd/devid + + Output: + 0000:01:00.0 + + 2. + $ echo 01:00.0 > /sys/kernel/debug/iommu/amd/devid + $ cat /sys/kernel/debug/iommu/amd/devid + + Output: + 0000:01:00.0 + +What: /sys/kernel/debug/iommu/amd/devtbl +Date: January 2025 +Contact: Dheeraj Kumar Srivastava +Description: + This file is a read-only output file containing the device table entry + for the device ID provided in /sys/kernel/debug/iommu/amd/devid. + + Example: + $ cat /sys/kernel/debug/iommu/amd/devtbl + + Output: + DeviceId QWORD[3] QWORD[2] QWORD[1] = QWORD[0] iommu + 0000:01:00.0 0000000000000000 20000001373b8013 0000000000000038 60000001= 14d7b603 iommu3 + +What: /sys/kernel/debug/iommu/amd/irqtbl +Date: January 2025 +Contact: Dheeraj Kumar Srivastava +Description: + This file is a read-only output file containing valid IRT table entries + for the device ID provided in /sys/kernel/debug/iommu/amd/devid. + + Example: + $ cat /sys/kernel/debug/iommu/amd/irqtbl + + Output: + DeviceId 0000:01:00.0 + IRT[0000] 0000000000000020 0000000000000241 + IRT[0001] 0000000000000020 0000000000000841 + IRT[0002] 0000000000000020 0000000000002041 + IRT[0003] 0000000000000020 0000000000008041 + IRT[0004] 0000000000000020 0000000000020041 + IRT[0005] 0000000000000020 0000000000080041 + IRT[0006] 0000000000000020 0000000000200041 + IRT[0007] 0000000000000020 0000000000800041 + [...] --=20 2.25.1