From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A1541F3FF4 for ; Wed, 2 Jul 2025 05:14:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433256; cv=none; b=LsBW5woyk2k+KsjLUDOgJF8xiN1A2+RsSFfB9XcmJFYekOrU445F/bu3PfqynGj8MF8gNGSJ5pPs99q43vUMj7jeRjNoWPJCj1X1f33kvXorbSs/8tbPWQ5oQ0p/FHP6mp+Ys+Gxn47Wgrpiy+kCjlZpB83KwU0lxXDQ67yM/ws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433256; c=relaxed/simple; bh=B3l9G9xHfhvz8EaPHO3ldfTP94vcz4sc4fSmpOQNlnQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CwPrAhGRzbbj7na2n2Jlm8P/0atv+zYFluW9eUjrJe64CB6fUKz+UHmXHiz8TXN/AEhfmY+QN+ubox8pbenqPlyqbm6hXR9243RUUWpiQwA2VkXvSPNkbxLgUB9rz7hNdF/zCo5+q2rROpjBv4OV3s9pImfrWMgINR4kRIovDoM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=CUEbXs1w; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="CUEbXs1w" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-237311f5a54so36406915ad.2 for ; Tue, 01 Jul 2025 22:14:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433254; x=1752038054; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ziNNelNAtU8Lu0O2/2Qc6bW/trdK9/SPi3ZGrwyyiyE=; b=CUEbXs1wfPVpM5SlMDp6JSbwtfqmuKO5QY0gW/x9Q84ErxhUZ/j+nCSsTzoOJQ/7eC OKnxh7Xu4nVxy6C1CIr3farra+tXG7q5z9v3TuqH3pFAbv/ViQ6SuSbrCDkxTupcbbdX 67/sXNCd3rNMUnMmRuqPaPKmlbwQ2TLuzmTI/b2fULZQ8uKFsDPNuc1ZjT1KQjMVc/ea sOEIfbei5e7wu3hzo4DWWqDP+qhQthRagePdeO2lFQ6iJzfEZXTSmwgwsTVhKN67Kkmx 1g5FW+THzXQ9hDIS5t9P146cKmaivU5Mq5UYhgR6QU0/o6iS/RX3UvZGtZJhAGkuYZLL cOzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433254; x=1752038054; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ziNNelNAtU8Lu0O2/2Qc6bW/trdK9/SPi3ZGrwyyiyE=; b=Zfg9CUNtQoXjbeKa5XdFYAyq0HpFuci0rLPXKCn/lLb8EHQjQlcOaPuAL16iwPe314 FJDXmCiJ5rM1WL6xFm0pblwA2CuqipBTaiupJFiXpHvELmsAjv/iCiZkHvP2ZQ3iJs8d XOXrtFYp4L7o9gt2bCyf/q1jVwHrEu/UQ1mH0tm5xz5xMamYEyZ0xPl6X2X64h6FaWyq jWJuNQe7VQivSGRyY4mahc2YNwu/gsg41HlTKldb6AQypt9GJZ/vWD46JWt0B2WEfWAo 2DhYdIl/XfuebL1RPPEQXKdOTKYQW3zM2zL3rELijwxAEQB9L3539oPKHWKMRIXL8qYo GhPw== X-Forwarded-Encrypted: i=1; AJvYcCWpYFmLMyL8EVzCUO1Ne2Ws2jpD9yCqRcJixiXmB1/n1UYOOXU/cZCGsUg2opgxXlLZYBLVzSxlX7aIIiw=@vger.kernel.org X-Gm-Message-State: AOJu0YwTmttLDvx5Qjmwl0FoG44OY7dBZVXXlJ/A5HdrNMvETBle3adX aJPOHEJ2JkWUm8TEu7p4C31L+yxYFdhyfLJkjjls8xp+ADkOSSxj9M3c0qKN7VpxWiw= X-Gm-Gg: ASbGnctR+cbZfb5TIlROqupOhQXfo9Wd6eDl3CsUFiyUVLainEsNGsQpui+L6OTQKNI zcaaKeD1zHCdsRZc9XJLmPXWJ0Uptnhg0s+FqEgYCByAze6bvB+IZrezwILiRQ9FFek7eoMtURN +sbLmp7+iKsp8Es57VxgcPsfCYWjEIzib+BCvGynvsvlBaKWpYHA5u1AKEd0RZ2Q9F/imcrOEFd lVD1i8v3/QZkIO8H40KAAuGN6EHagnhcFdxWfj7q9X7M1h83oxDNARlgxswofcLvNX670IisKQq P7YX2CW1vJW+eYq8LLgsN6bqpEJVrMQRFaz/XvO3+iFK+v8ge5oVZuY+TY67yulOOPX3amMDKGd 58LIHZ75e/8ejBCde X-Google-Smtp-Source: AGHT+IH1zQLMeLZCjz953CYwcFQdb4n2Jpuxqc1/A4tWexX1v4V8AZfDafl9hgJbDhtKkT2fEqefSw== X-Received: by 2002:a17:903:1aee:b0:21f:4649:fd49 with SMTP id d9443c01a7336-23c6e5e0440mr23121485ad.49.1751433254208; Tue, 01 Jul 2025 22:14:14 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.14.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:14:13 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Conor Dooley Subject: [PATCH v7 01/24] dt-bindings: mailbox: Add bindings for RPMI shared memory transport Date: Wed, 2 Jul 2025 10:43:22 +0530 Message-ID: <20250702051345.1460497-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the common RISC-V Platform Management Interface (RPMI) shared memory transport as a mailbox controller. Reviewed-by: Conor Dooley Signed-off-by: Anup Patel --- .../mailbox/riscv,rpmi-shmem-mbox.yaml | 124 ++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/riscv,rpmi-sh= mem-mbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbo= x.yaml b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.ya= ml new file mode 100644 index 000000000000..3aabc52a0c03 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/riscv,rpmi-shmem-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Platform Management Interface (RPMI) shared memory mailbox + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a common sha= red + memory based RPMI transport. This RPMI shared memory transport integrate= s as + mailbox controller in the SBI implementation or supervisor software wher= eas + each RPMI service group is mailbox client in the SBI implementation and + supervisor software. + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + References + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) + https://github.com/riscv-non-isa/riscv-rpmi/releases + +properties: + compatible: + const: riscv,rpmi-shmem-mbox + + reg: + minItems: 2 + items: + - description: A2P request queue base address + - description: P2A acknowledgment queue base address + - description: P2A request queue base address + - description: A2P acknowledgment queue base address + - description: A2P doorbell address + + reg-names: + minItems: 2 + items: + - const: a2p-req + - const: p2a-ack + - enum: [ p2a-req, a2p-doorbell ] + - const: a2p-ack + - const: a2p-doorbell + + interrupts: + maxItems: 1 + description: + The RPMI shared memory transport supports P2A doorbell as a wired + interrupt and this property specifies the interrupt source. + + msi-parent: + description: + The RPMI shared memory transport supports P2A doorbell as a system M= SI + and this property specifies the target MSI controller. + + riscv,slot-size: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 64 + description: + Power-of-2 RPMI slot size of the RPMI shared memory transport. + + riscv,a2p-doorbell-value: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x1 + description: + Value written to the 32-bit A2P doorbell register. + + riscv,p2a-doorbell-sysmsi-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The RPMI shared memory transport supports P2A doorbell as a system M= SI + and this property specifies system MSI index to be used for configur= ing + the P2A doorbell MSI. + + "#mbox-cells": + const: 1 + description: + The first cell specifies RPMI service group ID. + +required: + - compatible + - reg + - reg-names + - riscv,slot-size + - "#mbox-cells" + +anyOf: + - required: + - interrupts + - required: + - msi-parent + +additionalProperties: false + +examples: + - | + // Example 1 (RPMI shared memory with only 2 queues): + mailbox@10080000 { + compatible =3D "riscv,rpmi-shmem-mbox"; + reg =3D <0x10080000 0x10000>, + <0x10090000 0x10000>; + reg-names =3D "a2p-req", "p2a-ack"; + msi-parent =3D <&imsic_mlevel>; + riscv,slot-size =3D <64>; + #mbox-cells =3D <1>; + }; + - | + // Example 2 (RPMI shared memory with only 4 queues): + mailbox@10001000 { + compatible =3D "riscv,rpmi-shmem-mbox"; + reg =3D <0x10001000 0x800>, + <0x10001800 0x800>, + <0x10002000 0x800>, + <0x10002800 0x800>, + <0x10003000 0x4>; + reg-names =3D "a2p-req", "p2a-ack", "p2a-req", "a2p-ack", "a2p-doo= rbell"; + msi-parent =3D <&imsic_mlevel>; + riscv,slot-size =3D <64>; + riscv,a2p-doorbell-value =3D <0x00008000>; + #mbox-cells =3D <1>; + }; --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DA651F4C8A for ; Wed, 2 Jul 2025 05:14:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433264; cv=none; b=tHn30fMHa/tL6BdBffnMJbgfezmdsy6X0XzyIUP3H5rR7UGrcST696+Jc7S3iOeXo4iI6FPlOoN0wRCEUqNHC33q2Km/suW8K6ZbZdOoTJMphUfkk2Pzcirq79gmzWij711Vo7LiwG7/yv03gyOUCdccDkGseP1SmeO9cOPhd5Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433264; c=relaxed/simple; bh=wpGteD02sLvwEnKA7TBa2+SX4iYwOSU082ERtl6/Vjc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TK0jDssltPFtXX3C7s0J75QDSeTWC/FxEZqjlX60E58JLStAZMJZSS7XxQyLft5yDaRimEVeUYfe4GoNXOV8Lu2ifRLYtzy3GB5q7E+kOeegxiF7XoDW4sZsgCmd8xlAF4j19gtSVlrgsA3cmeU61ye3EFALdBo3/MwUJtwYIFY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=dHQZ3EnM; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="dHQZ3EnM" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-235d6de331fso51539785ad.3 for ; Tue, 01 Jul 2025 22:14:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433262; x=1752038062; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EGFMyHcY75Un2ey32rj/OGQJrYLrfBUEB3tHZxTx41w=; b=dHQZ3EnMGfJHsTfcH8UnP1mMvdJmezlR7gQfYTJShx9qFPtZKDvUy/sxQPNyTWDkhp xpAKFbrgESKJ/Z6YtnlvKIrWLVn5Aw8hXX58mszoyIhmad1tpJAVPuiKL5vlgIMTbEMR 4FmxbXLmRRSDGHktMF7GT16OltAbyxdiOSJq9zVpRIn8Eo3iaTj9oF5K2wlcVfT2kQF3 yApim1ixps4ywvuMqpOp6Cz+xW1RxeAFAtdXc+B3we7kWxCv2DcT0Sx0XxFlr3xoYv+h zofLffD+SLP86Plj1zTWwnMxKa2OPRteXWtVXQpYSVlYBusJG+A76MaOT6WsFDvUbRuL lWOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433262; x=1752038062; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EGFMyHcY75Un2ey32rj/OGQJrYLrfBUEB3tHZxTx41w=; b=X6MIxcMcpaGY+99CIETHjNPkYdhojdWUXxRauFj19azGUhiDgYAiWMRC3rLWlXJTN6 bDVk2SEXonT4gqhKPm7VKyEbXMSYENnB29mMkjcD03mp8+JDiP0DfMLGW7xEhrdRuSy5 +5uC3HYPgQQqba4opsiEPYTS/kXm5v4Ff7LqRS03zJ25BzFtkNoedvvYEUyISzzC7+MK 1e3RlqbaEEmWgn0DMP5CYDCs3/m795/CyvXTVyhsoXdVHYMY03pVzqEYbh4BzAEAkuUG NhDtSl5Bs1z9SUUkzi2mqlNeNtKkBMp/tdMtVAqyJuC1naeUxhs8B1Jh0aM3VfX2R25I iVyw== X-Forwarded-Encrypted: i=1; AJvYcCU352MgJu4fnMQ1j3tsBwaSfNcdUj9V1cWYLrosduNWacdiEugD08E59M9OZVfNKctU2yXMVoJ60Fs8DNU=@vger.kernel.org X-Gm-Message-State: AOJu0YxLiAv/i2CeGZxbrq+tq30btv+0HD6sVvENgrbHyx/b9woFY+U8 MAPtGD30DpjPrk7y36MDEY4kXDVhmLihso460XVPkpGMMQ0uqP4dq9PJ3XeQkSJBDO4= X-Gm-Gg: ASbGncs5+LLXffIEErrPWLHi/mTCih8bTjSP2ulK6CEkKWsaKRC57pcoXuH4gYNVGNZ E/8197iDDKFIu8h5xZLpSLS2qqpX5ny+A2J6SSXccqEjOJnU0WjhvKbNFCDFvbp9aapvhmvSaxI uvqyhiSQ4Rozl4yLk52yAdAjPakdF/KfKCYJkvaUTIx2m+4s5/ElurIb74P0uU4dcTB5g4uehiP ExG8+et/TlU0B0lubWGeMrV/O2ozTvhkskwUCoWVeL13a58KWBFSUofc1CNYWToRapy5rDHob/8 Okmp86eslqXs7mtbjXTqlBmLgtKWm23uyaBBbZwTGCtA1vDEvKRJOOyKQ0ZkgSBBgdgGgeh0ePB etgJvXVL52dO/ezEf X-Google-Smtp-Source: AGHT+IFyaNYbGu3J51YigXq7SSnInqGclIg3bY+r/3Kl6d4xMMAbKmX0D6qCx0IXUy6MpajxqM48mw== X-Received: by 2002:a17:902:e852:b0:234:df51:d16c with SMTP id d9443c01a7336-23c6e5826camr22426015ad.45.1751433261848; Tue, 01 Jul 2025 22:14:21 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.14.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:14:21 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Conor Dooley Subject: [PATCH v7 02/24] dt-bindings: mailbox: Add bindings for RISC-V SBI MPXY extension Date: Wed, 2 Jul 2025 10:43:23 +0530 Message-ID: <20250702051345.1460497-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the RISC-V SBI Message Proxy (MPXY) extension as a mailbox controller. Reviewed-by: Conor Dooley Signed-off-by: Anup Patel --- .../bindings/mailbox/riscv,sbi-mpxy-mbox.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/riscv,sbi-mpx= y-mbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/riscv,sbi-mpxy-mbox.= yaml b/Documentation/devicetree/bindings/mailbox/riscv,sbi-mpxy-mbox.yaml new file mode 100644 index 000000000000..061437a0b45a --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/riscv,sbi-mpxy-mbox.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/riscv,sbi-mpxy-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V SBI Message Proxy (MPXY) extension based mailbox + +maintainers: + - Anup Patel + +description: | + The RISC-V SBI Message Proxy (MPXY) extension [1] allows supervisor + software to send messages through the SBI implementation (M-mode + firmware or HS-mode hypervisor). The underlying message protocol + and message format used by the supervisor software could be some + other standard protocol compatible with the SBI MPXY extension + (such as RISC-V Platform Management Interface (RPMI) [2]). + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + References + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + [1] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + + [2] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) + https://github.com/riscv-non-isa/riscv-rpmi/releases + +properties: + compatible: + const: riscv,sbi-mpxy-mbox + + "#mbox-cells": + const: 2 + description: + The first cell specifies channel_id of the SBI MPXY channel, + the second cell specifies MSG_PROT_ID of the SBI MPXY channel + +required: + - compatible + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + mailbox { + compatible =3D "riscv,sbi-mpxy-mbox"; + #mbox-cells =3D <2>; + }; --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 551CD1FC0E3 for ; Wed, 2 Jul 2025 05:14:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433271; cv=none; b=c8JZ6KbAnNZ2zr/gHt0BVmrF66lamPzVDCcmXy6elRHtZrYmkN9D4R6wQgF5JfcWE3pdSrNIAYhqFN+ieaMNzuqCJzdwU2/144XAE2dyP3LKdSuv7P0IPyJmuFVkEgF4TV4UYMdPi+wiTi9WhdFc6+0kQPub5pTcPSdn2cJu10A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433271; c=relaxed/simple; bh=WhFOZeO6QPZYot9X8PgUO7X8WeF9pMZndeU1I3waGkg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tFsu5J46XsXVjlvBMbm7HEU+hb6GzdoUd0yrGJJKmxaEnjdyAIq6TxD8js+YFAakGQfxThbwKVczYWOTZfz04XrdEJatHt6oRbGeMAeJo7BdSasm1GhO/9+/MJJYfQ/BXMeuoSF2BsC5h6tq3PMy6JDJ3tOtZQFxL4NInDExD+A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=dPKRXDaZ; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="dPKRXDaZ" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-236470b2dceso34023815ad.0 for ; Tue, 01 Jul 2025 22:14:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433270; x=1752038070; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/sxHWlmZntdYALz3N2e235Pk7qD/y6rLx7JLAfVbzfY=; b=dPKRXDaZhZgKu3RHThxsvzEhuNVWzqs1K4jFboGj1OOq8XV9/66cN/Er9hW4z/wZsH 06NGXZcY02ZIFLCj39EKHdljk7OrtCDdfM9KMEcoZnSMURtrz0x2jxNz6kktcmZNgK0t 5ce7PBNDXbxOs6SRZd+zcjN7XEmXmLhKFl2UvnZItjU/VlNYna2ekVHIGyw8LJSWBZ9K 5+VnA0UckOMl181jfKKAERqGpz6LIrWqsit0hOSrc+JL0WMVb9nQYVCcOCOEaKP8IWQp mkCEiZ7YKOTkfGlkM5QQexcjKJEgwONGQxOV/I7xZXZyHFATkVbOuMvYmY8KRBuhVdPq 0D/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433270; x=1752038070; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/sxHWlmZntdYALz3N2e235Pk7qD/y6rLx7JLAfVbzfY=; b=Y7deTNP8K/FhCFWBtJEFLuhoe/P9O9aslyVBw+gJ9iJXm+Dzn+WOCt/tLfoos0Ks3m ibeoe8wOQGZoNjtk6HjfYp4FTc/2QHrP5M8xcG7TNnBR6WYu4XTLaUV8ICWA4KldVHO0 2VkqfWX2c9Q1YxDAIUMzYL9AW8EgLunGH3Xch9c7EOKBv1NwZbkH4umWG7QjIUbyvdNX zkPqwokxDh9qXzU5JYTPDMC560PTtypyRAv3jPlGDzz3BXaOJeFBa2CHtT4AKh6E0ryh SlZcZuhpS6tkRRVa6u0x5itDQCs6Q8SaOVBkx6ZU770mMTpmIliV5tdaC/7cNUg10JRt DN1g== X-Forwarded-Encrypted: i=1; AJvYcCWrCO5unGW5hpHjBNu5ENydNEItKR7e3j9drWSxJ/XbxABSdBGvts/KpO79OHsJOihBy+VqTecUQL/o+YI=@vger.kernel.org X-Gm-Message-State: AOJu0YwHi+/2YXOeLtS7+Iqsy1PNC635gwfIBQVJMRJZlwuKbcfvRGVd hAjHuz91huDzEh8f2ioWnPigohEZEzABRZvCXKc+BYSMKRx40kRShueugiMFGzZbQPrBKuGmj7R dyRf3 X-Gm-Gg: ASbGnctAb9sMZ5X48kgc3Cf6Up9rHB9jSAsi4Q8jOeT0SPucxYDWYcG2x/kw3oh/McQ Z3JZYm/teKkeUgrKGXFneVXjNrSW0iOEdqX4lukoVLW1JtT3sZx3TSKToBVNoMqkp71gI6S2P55 UdtKoQjtT3VmNzcYlMDe9Rbjcu6JzVV2WDvM51wfTKfZfz2cL1QPhZKSBvfk3kWzP0Bs6W/0PWU ETHxo+ZOwlHvtsjXHfdssTjqAj9wnt6GYRZrLzAPDypRdAbOOirVW5QITH6bzPa3M5lrCZznG4T BaGJQIrOZVTsTpvMG7zleVcF2idHHIMdfm5UcIL1gjwlJsp0oNvsr/9T/rfIZqhVPvOCofGdy/V +EeQsryekCFz9KBwh X-Google-Smtp-Source: AGHT+IHMGd/9qBl/omjJ5870DXltKh0wARVvx5nQ5ubBQ6cP0FDKJQIwjqOoR2ghmUNQi63Y0l8eoA== X-Received: by 2002:a17:902:ced1:b0:231:c9bb:60fd with SMTP id d9443c01a7336-23c6e58accdmr22920115ad.33.1751433269504; Tue, 01 Jul 2025 22:14:29 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.14.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:14:29 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Atish Patra Subject: [PATCH v7 03/24] RISC-V: Add defines for the SBI message proxy extension Date: Wed, 2 Jul 2025 10:43:24 +0530 Message-ID: <20250702051345.1460497-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add defines for the new SBI message proxy extension which is part of the SBI v3.0 specification. Reviewed-by: Atish Patra Co-developed-by: Rahul Pathak Signed-off-by: Rahul Pathak Signed-off-by: Anup Patel Reviewed-by: Andy Shevchenko --- arch/riscv/include/asm/sbi.h | 63 ++++++++++++++++++++++++++++++++++++ include/linux/wordpart.h | 8 +++++ 2 files changed, 71 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 341e74238aa0..59a7285ff956 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -10,6 +10,7 @@ #include #include #include +#include =20 #ifdef CONFIG_RISCV_SBI enum sbi_ext_id { @@ -36,6 +37,7 @@ enum sbi_ext_id { SBI_EXT_STA =3D 0x535441, SBI_EXT_NACL =3D 0x4E41434C, SBI_EXT_FWFT =3D 0x46574654, + SBI_EXT_MPXY =3D 0x4D505859, =20 /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START =3D 0x08000000, @@ -430,6 +432,67 @@ enum sbi_fwft_feature_t { =20 #define SBI_FWFT_SET_FLAG_LOCK BIT(0) =20 +enum sbi_ext_mpxy_fid { + SBI_EXT_MPXY_GET_SHMEM_SIZE, + SBI_EXT_MPXY_SET_SHMEM, + SBI_EXT_MPXY_GET_CHANNEL_IDS, + SBI_EXT_MPXY_READ_ATTRS, + SBI_EXT_MPXY_WRITE_ATTRS, + SBI_EXT_MPXY_SEND_MSG_WITH_RESP, + SBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP, + SBI_EXT_MPXY_GET_NOTIFICATION_EVENTS +}; + +enum sbi_mpxy_attribute_id { + /* Standard channel attributes managed by MPXY framework */ + SBI_MPXY_ATTR_MSG_PROT_ID =3D 0x00000000, + SBI_MPXY_ATTR_MSG_PROT_VER =3D 0x00000001, + SBI_MPXY_ATTR_MSG_MAX_LEN =3D 0x00000002, + SBI_MPXY_ATTR_MSG_SEND_TIMEOUT =3D 0x00000003, + SBI_MPXY_ATTR_MSG_COMPLETION_TIMEOUT =3D 0x00000004, + SBI_MPXY_ATTR_CHANNEL_CAPABILITY =3D 0x00000005, + SBI_MPXY_ATTR_SSE_EVENT_ID =3D 0x00000006, + SBI_MPXY_ATTR_MSI_CONTROL =3D 0x00000007, + SBI_MPXY_ATTR_MSI_ADDR_LO =3D 0x00000008, + SBI_MPXY_ATTR_MSI_ADDR_HI =3D 0x00000009, + SBI_MPXY_ATTR_MSI_DATA =3D 0x0000000A, + SBI_MPXY_ATTR_EVENTS_STATE_CONTROL =3D 0x0000000B, + SBI_MPXY_ATTR_STD_ATTR_MAX_IDX, + /* + * Message protocol specific attributes, managed by + * the message protocol specification. + */ + SBI_MPXY_ATTR_MSGPROTO_ATTR_START =3D 0x80000000, + SBI_MPXY_ATTR_MSGPROTO_ATTR_END =3D 0xffffffff +}; + +/* Possible values of MSG_PROT_ID attribute */ +enum sbi_mpxy_msgproto_id { + SBI_MPXY_MSGPROTO_RPMI_ID =3D 0x0 +}; + +/* RPMI message protocol specific MPXY attributes */ +enum sbi_mpxy_rpmi_attribute_id { + SBI_MPXY_RPMI_ATTR_SERVICEGROUP_ID =3D SBI_MPXY_ATTR_MSGPROTO_ATTR_START, + SBI_MPXY_RPMI_ATTR_SERVICEGROUP_VERSION, + SBI_MPXY_RPMI_ATTR_IMPL_ID, + SBI_MPXY_RPMI_ATTR_IMPL_VERSION, + SBI_MPXY_RPMI_ATTR_MAX_ID +}; + +/* Encoding of MSG_PROT_VER attribute */ +#define SBI_MPXY_MSG_PROT_VER_MAJOR(__ver) upper_16_bits(__ver) +#define SBI_MPXY_MSG_PROT_VER_MINOR(__ver) lower_16_bits(__ver) +#define SBI_MPXY_MSG_PROT_MKVER(__maj, __min) make_u32_from_two_u16(__maj,= __min) + +/* Capabilities available through CHANNEL_CAPABILITY attribute */ +#define SBI_MPXY_CHAN_CAP_MSI BIT(0) +#define SBI_MPXY_CHAN_CAP_SSE BIT(1) +#define SBI_MPXY_CHAN_CAP_EVENTS_STATE BIT(2) +#define SBI_MPXY_CHAN_CAP_SEND_WITH_RESP BIT(3) +#define SBI_MPXY_CHAN_CAP_SEND_WITHOUT_RESP BIT(4) +#define SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS BIT(5) + /* SBI spec version fields */ #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 diff --git a/include/linux/wordpart.h b/include/linux/wordpart.h index 5a7b97bb7c95..ed8717730037 100644 --- a/include/linux/wordpart.h +++ b/include/linux/wordpart.h @@ -31,6 +31,14 @@ */ #define lower_16_bits(n) ((u16)((n) & 0xffff)) =20 +/** + * make_u32_from_two_u16 - return u32 number by combining + * two u16 numbers. + * @hi: upper 16 bit number + * @lo: lower 16 bit number + */ +#define make_u32_from_two_u16(hi, lo) (((u32)(hi) << 16) | (u32)(lo)) + /** * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long va= lue * @x: value to repeat --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E424C1F78F2 for ; Wed, 2 Jul 2025 05:14:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433279; cv=none; b=AkUO4EL/qoWvH9mvExJ2pSN7PQbnCc39CY8bGLs//oLcjA8afRMDMJwwSMi4Tp+qazTftxmtl17sk/J8l1Dp6A84xzyrrJF5GiYY91IuJRlJbVoTKLcv542GZAzIZ4GcDZCp2aOxGROVjgjKftlY/ucmVws/xGi5ZYd4RWQ9uoI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433279; c=relaxed/simple; bh=j2OFfQpWBaGYJhqPKT9rFOG4EIUH8lrP+UpGBH4mqxQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MYi5UHYXsKfHyXtS0jMM+Myo6mksjeWzxMUz8Ffal4C/eQIPzWV4xAL3a1BZtt7HjpkY0qw3rDB8ZYQPGXCeXny/8edni3KUZUH6ANGWj7ePGBN3JXjsvzW6LGT10E1Y1TmaPfhhBnonaRcCQ1wIiC1IQEpDMeGr5DWT3kqE4K0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=Wv0t/MUi; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="Wv0t/MUi" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-2350b1b9129so26377175ad.0 for ; Tue, 01 Jul 2025 22:14:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433277; x=1752038077; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d/5/u8lxcTpaYqZ0TVUq4VuL6zz3DLTGiHSQJRlenIE=; b=Wv0t/MUi0VPQAbpgM96MexQJbVeMQ3SLJwGrUBC6p/Pk2RYwtJYhSbGdCdEWDxAHcJ yUJlx5NBn+IwSinLEpVmwdVfnrnhrNQMiZKHKYmifMxeIafBq/SUI7Y+H8SOsBWKXGYZ gBjfe56XXgiEF1984ZUSq9Ah392S/1FpNFgAXB8zKCjIT5NurbOBLrDhpto3F790AY2x ZRprR8euhOpK2thIBN+QjjVrVwc7tI0MkcquaMyLiyK1CUTr8s4VRWYGwade9h8vzHNd YNyS/+YvVv1LwmWtOEUdzCNFKoRiARGUDvAHM6Sv2o8Eb8yO7dVW/KXWzce2r549G6hn QC4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433277; x=1752038077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d/5/u8lxcTpaYqZ0TVUq4VuL6zz3DLTGiHSQJRlenIE=; b=h0+SCOo+iDOIMLOvFhN8OXjUyiaLSLE63ILb59wfZ3gCOPJ7qQUHxgBhcxM7F8xm1I XhopBQ04jFBTIegge94UYMkUk+PDKRU1qK6278KrWFP64+IAqJLWZtxf1jhGeGgQAbGD i4n0cRJ5dUaBiy4oHor6b8l3ruwIgRV7ETlrQZcnZrgYZBVfIWTRUcxBe4ofvm+72OtO YjkENvFcRPlskJbrj5JY3Z2rZRwX/UcC2UAupsiKTi4UlOesoXn72uOueh/JXjhwKSnU C/mEXZbfCqf4KiHoZVgWVcML+kQQzGD4NQaWrBEK+/8QY/vUP/uFOOYFzyf0vz0iqlkw Zm9w== X-Forwarded-Encrypted: i=1; AJvYcCV+UOlOtEom1QFdQJkI6hUidiVX/JcOg0yLC3v+IM5Q1nVboUcZJLM5wwu1UV/mWtT7hOwK3xlJ22QFhLM=@vger.kernel.org X-Gm-Message-State: AOJu0YwYBMt7W25NUcYd46wyQaNQaLyUls4O1NWqdEsHr2fU0kqW/0BL tFRP0I4Ig80uAvK3aEGvHtPSrlHljywU1ZvTxJqzCT6WKasRsjNEx545oVivYOAKS3U= X-Gm-Gg: ASbGncvImlazBBAizjuKHbL+1NU/pTVyVsQ9ynmWIe3/2lKiSTUpzNBEkQnfqg87q3L cVEQ+bEC5BUtFCT9YfPxHkrPpkdCxjrrXkKPNjEx1uu4j3LhhcHRnucH3WBjkIot7OMTEjmjsk9 +G0PEATVL+UK6HfrJiDMPMAJ/FxdfOAYGigrjrSTvHC7luxMJoL+Gml/Wb7l/bec0pObUWHBYGW mnJ1nXX8UwqzLJtDN/ESGbLxx+76Zjgf6GYIymUvkmDYFmYxtz/1Y4O34fBFEN7yMTnLm6V8BaS 8wQQ2bfN2sumjLuNn6QMrkL9TLA0FTlg04YCCeEfxoLU1CU9E0dWsrlRKp1MDvKtXywHMipWN6P qU7DTrIZCshvdaNccWq8Lz3wRqVM= X-Google-Smtp-Source: AGHT+IES9LhEnWB4A9fxqUJqeryubwD4uQ/CtDShKyl6gs+Nv1L1brdg7eqin6hNQ7dmbZoM/4qL7w== X-Received: by 2002:a17:903:1a4e:b0:235:129e:f649 with SMTP id d9443c01a7336-23c6e4b0bedmr30949955ad.12.1751433276946; Tue, 01 Jul 2025 22:14:36 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:14:36 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 04/24] mailbox: Add common header for RPMI messages sent via mailbox Date: Wed, 2 Jul 2025 10:43:25 +0530 Message-ID: <20250702051345.1460497-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RPMI based mailbox controller drivers and mailbox clients need to share defines related to RPMI messages over mailbox interface so add a common header for this purpose. Co-developed-by: Rahul Pathak Signed-off-by: Rahul Pathak Signed-off-by: Anup Patel --- include/linux/mailbox/riscv-rpmi-message.h | 214 +++++++++++++++++++++ 1 file changed, 214 insertions(+) create mode 100644 include/linux/mailbox/riscv-rpmi-message.h diff --git a/include/linux/mailbox/riscv-rpmi-message.h b/include/linux/mai= lbox/riscv-rpmi-message.h new file mode 100644 index 000000000000..3f4c73529aa5 --- /dev/null +++ b/include/linux/mailbox/riscv-rpmi-message.h @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (C) 2025 Ventana Micro Systems Inc. */ + +#ifndef _LINUX_RISCV_RPMI_MESSAGE_H_ +#define _LINUX_RISCV_RPMI_MESSAGE_H_ + +#include +#include +#include +#include + +/* RPMI version encode/decode macros */ +#define RPMI_VER_MAJOR(__ver) upper_16_bits(__ver) +#define RPMI_VER_MINOR(__ver) lower_16_bits(__ver) +#define RPMI_MKVER(__maj, __min) make_u32_from_two_u16(__maj, __min) + +/* RPMI message header */ +struct rpmi_message_header { + __le16 servicegroup_id; + u8 service_id; + u8 flags; + __le16 datalen; + __le16 token; +}; + +/* RPMI message */ +struct rpmi_message { + struct rpmi_message_header header; + u8 data[]; +}; + +/* RPMI notification event */ +struct rpmi_notification_event { + __le16 event_datalen; + u8 event_id; + u8 reserved; + u8 event_data[]; +}; + +/* RPMI error codes */ +enum rpmi_error_codes { + RPMI_SUCCESS =3D 0, + RPMI_ERR_FAILED =3D -1, + RPMI_ERR_NOTSUPP =3D -2, + RPMI_ERR_INVALID_PARAM =3D -3, + RPMI_ERR_DENIED =3D -4, + RPMI_ERR_INVALID_ADDR =3D -5, + RPMI_ERR_ALREADY =3D -6, + RPMI_ERR_EXTENSION =3D -7, + RPMI_ERR_HW_FAULT =3D -8, + RPMI_ERR_BUSY =3D -9, + RPMI_ERR_INVALID_STATE =3D -10, + RPMI_ERR_BAD_RANGE =3D -11, + RPMI_ERR_TIMEOUT =3D -12, + RPMI_ERR_IO =3D -13, + RPMI_ERR_NO_DATA =3D -14, + RPMI_ERR_RESERVED_START =3D -15, + RPMI_ERR_RESERVED_END =3D -127, + RPMI_ERR_VENDOR_START =3D -128, +}; + +static inline int rpmi_to_linux_error(int rpmi_error) +{ + switch (rpmi_error) { + case RPMI_SUCCESS: + return 0; + case RPMI_ERR_INVALID_PARAM: + case RPMI_ERR_BAD_RANGE: + case RPMI_ERR_INVALID_STATE: + return -EINVAL; + case RPMI_ERR_DENIED: + return -EPERM; + case RPMI_ERR_INVALID_ADDR: + case RPMI_ERR_HW_FAULT: + return -EFAULT; + case RPMI_ERR_ALREADY: + return -EALREADY; + case RPMI_ERR_BUSY: + return -EBUSY; + case RPMI_ERR_TIMEOUT: + return -ETIMEDOUT; + case RPMI_ERR_IO: + return -ECOMM; + case RPMI_ERR_FAILED: + case RPMI_ERR_NOTSUPP: + case RPMI_ERR_NO_DATA: + case RPMI_ERR_EXTENSION: + default: + return -EOPNOTSUPP; + } +} + +/* RPMI Linux mailbox attribute IDs */ +enum rpmi_mbox_attribute_id { + RPMI_MBOX_ATTR_SPEC_VERSION, + RPMI_MBOX_ATTR_MAX_MSG_DATA_SIZE, + RPMI_MBOX_ATTR_SERVICEGROUP_ID, + RPMI_MBOX_ATTR_SERVICEGROUP_VERSION, + RPMI_MBOX_ATTR_IMPL_ID, + RPMI_MBOX_ATTR_IMPL_VERSION, + RPMI_MBOX_ATTR_MAX_ID +}; + +/* RPMI Linux mailbox message types */ +enum rpmi_mbox_message_type { + RPMI_MBOX_MSG_TYPE_GET_ATTRIBUTE, + RPMI_MBOX_MSG_TYPE_SET_ATTRIBUTE, + RPMI_MBOX_MSG_TYPE_SEND_WITH_RESPONSE, + RPMI_MBOX_MSG_TYPE_SEND_WITHOUT_RESPONSE, + RPMI_MBOX_MSG_TYPE_NOTIFICATION_EVENT, + RPMI_MBOX_MSG_MAX_TYPE +}; + +/* RPMI Linux mailbox message instance */ +struct rpmi_mbox_message { + enum rpmi_mbox_message_type type; + union { + struct { + enum rpmi_mbox_attribute_id id; + u32 value; + } attr; + + struct { + u32 service_id; + void *request; + unsigned long request_len; + void *response; + unsigned long max_response_len; + unsigned long out_response_len; + } data; + + struct { + u16 event_datalen; + u8 event_id; + u8 *event_data; + } notif; + }; + int error; +}; + +/* RPMI Linux mailbox message helper routines */ +static inline void rpmi_mbox_init_get_attribute(struct rpmi_mbox_message *= msg, + enum rpmi_mbox_attribute_id id) +{ + msg->type =3D RPMI_MBOX_MSG_TYPE_GET_ATTRIBUTE; + msg->attr.id =3D id; + msg->attr.value =3D 0; + msg->error =3D 0; +} + +static inline void rpmi_mbox_init_set_attribute(struct rpmi_mbox_message *= msg, + enum rpmi_mbox_attribute_id id, + u32 value) +{ + msg->type =3D RPMI_MBOX_MSG_TYPE_SET_ATTRIBUTE; + msg->attr.id =3D id; + msg->attr.value =3D value; + msg->error =3D 0; +} + +static inline void rpmi_mbox_init_send_with_response(struct rpmi_mbox_mess= age *msg, + u32 service_id, + void *request, + unsigned long request_len, + void *response, + unsigned long max_response_len) +{ + msg->type =3D RPMI_MBOX_MSG_TYPE_SEND_WITH_RESPONSE; + msg->data.service_id =3D service_id; + msg->data.request =3D request; + msg->data.request_len =3D request_len; + msg->data.response =3D response; + msg->data.max_response_len =3D max_response_len; + msg->data.out_response_len =3D 0; + msg->error =3D 0; +} + +static inline void rpmi_mbox_init_send_without_response(struct rpmi_mbox_m= essage *msg, + u32 service_id, + void *request, + unsigned long request_len) +{ + msg->type =3D RPMI_MBOX_MSG_TYPE_SEND_WITHOUT_RESPONSE; + msg->data.service_id =3D service_id; + msg->data.request =3D request; + msg->data.request_len =3D request_len; + msg->data.response =3D NULL; + msg->data.max_response_len =3D 0; + msg->data.out_response_len =3D 0; + msg->error =3D 0; +} + +static inline void *rpmi_mbox_get_msg_response(struct rpmi_mbox_message *m= sg) +{ + return msg ? msg->data.response : NULL; +} + +static inline int rpmi_mbox_send_message(struct mbox_chan *chan, + struct rpmi_mbox_message *msg) +{ + int ret; + + /* Send message for the underlying mailbox channel */ + ret =3D mbox_send_message(chan, msg); + if (ret < 0) + return ret; + + /* Explicitly signal txdone for mailbox channel */ + ret =3D msg->error; + mbox_client_txdone(chan, ret); + return ret; +} + +#endif /* _LINUX_RISCV_RPMI_MESSAGE_H_ */ --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 352A71F4621 for ; Wed, 2 Jul 2025 05:14:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433286; cv=none; b=uJ/KZsYoNx85oG/Cy0NPPHQPDWBdkxSrwMjLutmPPr2yNKV7jZbp9JxpWf8gBLBMbsFWLp+kB+r1g52v8JzXPWcbsHz/MK7406yydEA9LenE0LufPLL37qfVXX0MnAekVOvX/Vp005p4eQY3MC5cnzAm+BzZB0+RA0Mp627hwjM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433286; c=relaxed/simple; bh=eP0nLjelGbOd1owGOdUwIHJWAQpQfBfflyMTXkP8FKA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ky9VdJxyyI8Ju+LyJddI3xGG/PpMOGdg0bTyOj8g0yWYdjjBC+kBGuw9lDjWQppOeNKOWbkhAvI9bnhq9ooiSvnOcP26n+Z9LgO6DlvYGGuLbjKPSqB3RgjfX1MsQfW2S/zRSljcztvtOSqcP8c2fN2ahhvz6R1755RYbnRXRlA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=Dq0XblWg; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="Dq0XblWg" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-236470b2dceso34025075ad.0 for ; Tue, 01 Jul 2025 22:14:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433284; x=1752038084; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oP6ThGaZGs8MyIgO+nprUM8QR3vfVMjtp+0dcAYkEZA=; b=Dq0XblWgS/84zlSmjzNjs7zph1Am4Wd0xmREaSF4C7/keZPjL69r/SMTTPbk29Qrum i1qPoC6gT/Lf3t8X0grrZVdRh5S0oCPRPFghJA4fSm7NQqfSsZf3DgEd+nDzio11vuZ8 3PHydDHH6ab9m5rX0oPOAgZqnC0XBz3AWUiDcCdGh7p9AWnNg9Seu1wmxkUqv7M9iCwz q/Iok2gVgk7k2xW2eOR1flcGBVxS8hMLppyFx7Nak4BcDO0wG7jahuzxe9nIIBVS0nI5 /MhPLwxFBjsWi5OV4OoTZ7dE9PuFzK4J1i/Na85D2ppNdvSTLF0t1wR8dYwhuVXw9834 R6/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433284; x=1752038084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oP6ThGaZGs8MyIgO+nprUM8QR3vfVMjtp+0dcAYkEZA=; b=JuTugtaGDc1+kIZsS0j0O27nad9Y8ciDMX7vDPOK/4ix1GD/GfK1/lzrGw15LxfcLw x3ooajld/emthZ871hbm82XMCU2S/ZRQX5Pxmk2A4DyFVNU04bj0QJtxOqd9Z7hhzUPM uRptD8jhap7x57FJE5roePBR0us6VLryXALA3h6FN9xKPt1XVbEYE0fKEWI3ch5tbgWO T0LTH2F5HPU5D8nkkko3WgZ1wfvMry4Jazyr64PrOLT9udv+vgr/P3Fj5H5E1wh3wJgl 8HFwNHPsDDKfmAs5ryfgKmQu+HyManBmKmXTeWqgO4N2Sq/cZVSUBkcJiVVsKMlwesWI dfZw== X-Forwarded-Encrypted: i=1; AJvYcCVNn9ByCNG8brB8OxDE+djqiMGwmS5wAw5apJWe8IsUKJURK/ur2LwFS5kZS0XykhYgLuIYQBvaqOmBfiE=@vger.kernel.org X-Gm-Message-State: AOJu0Yw6iybRNdn+eCcWu/3GrXySc6sJWYJC1d3GtbfCeVNP4jkBxpOs BHsEoGvZx7EnmD3qagCjqVhm5j96E2ijUE0yH0IxxLTcZL4JK66Kuti/m4U6NJmHr3s= X-Gm-Gg: ASbGncvQ3p9VSJOuWVuGDmP0mOSo4/X9lEoLCzoiYxV6yX+pCkoA9vlF64z8FAyOiO+ p9BZ4kIs3l3XQrQUK7hTUvr7EsDh9Db7RhdgYvpCJue6vrgk2zE5wk306B0EMY6w5kW8ApT7lYh E86NtAoG/0LjQvdbQy39PvsbrSNwX4t0h4SzqbPzn+Re6Oa1pNpjdlFDe/PWqUc7XiH6AWInZHh tzndfRn2IE1UVfq1OqcfeNwkc2KPQjz0/3ho/1nLPEVGwYfcLjWS8fcm7LFHyiZoNdjYYQKDiHG SQzDrzmqTRYBTzrXcvSQYUPs7o2vfwFie8RPFmrar+YpBxHzqh2IiX4RkHf3BrexUz6cHlqH6o9 u7H/5OgkIJbsvorCJ X-Google-Smtp-Source: AGHT+IHW6+yjygzJaRYVJbk398vw/ZCnNjzG8uYmd5NcS+WaiG0hLE/XIX5nmwnliNsaVR742l1nrQ== X-Received: by 2002:a17:903:1a2e:b0:232:59b:58fe with SMTP id d9443c01a7336-23c6e4d6e93mr19975825ad.1.1751433284391; Tue, 01 Jul 2025 22:14:44 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:14:43 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 05/24] mailbox: Allow controller specific mapping using fwnode Date: Wed, 2 Jul 2025 10:43:26 +0530 Message-ID: <20250702051345.1460497-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce optional fw_node() callback which allows a mailbox controller driver to provide controller specific mapping using fwnode. The Linux OF framework already implements fwnode operations for the Linux DD framework so the fw_xlate() callback works fine with device tree as well. Signed-off-by: Anup Patel Reviewed-by: Andy Shevchenko --- drivers/mailbox/mailbox.c | 65 ++++++++++++++++++------------ include/linux/mailbox_controller.h | 3 ++ 2 files changed, 43 insertions(+), 25 deletions(-) diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index 5cd8ae222073..2acc6ec229a4 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 #include "mailbox.h" @@ -383,34 +384,56 @@ EXPORT_SYMBOL_GPL(mbox_bind_client); */ struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index) { - struct device *dev =3D cl->dev; + struct fwnode_reference_args fwspec; + struct fwnode_handle *fwnode; struct mbox_controller *mbox; struct of_phandle_args spec; struct mbox_chan *chan; + struct device *dev; + unsigned int i; int ret; =20 - if (!dev || !dev->of_node) { - pr_debug("%s: No owner device node\n", __func__); + dev =3D cl->dev; + if (!dev) { + pr_debug("No owner device\n"); return ERR_PTR(-ENODEV); } =20 - ret =3D of_parse_phandle_with_args(dev->of_node, "mboxes", "#mbox-cells", - index, &spec); + fwnode =3D dev_fwnode(dev); + if (!fwnode) { + dev_dbg(dev, "No owner fwnode\n"); + return ERR_PTR(-ENODEV); + } + + ret =3D fwnode_property_get_reference_args(fwnode, "mboxes", "#mbox-cells= ", + 0, index, &fwspec); if (ret) { - dev_err(dev, "%s: can't parse \"mboxes\" property\n", __func__); + dev_err(dev, "%s: can't parse \"%s\" property\n", __func__, "mboxes"); return ERR_PTR(ret); } =20 + spec.np =3D to_of_node(fwspec.fwnode); + spec.args_count =3D fwspec.nargs; + for (i =3D 0; i < spec.args_count; i++) + spec.args[i] =3D fwspec.args[i]; + scoped_guard(mutex, &con_mutex) { chan =3D ERR_PTR(-EPROBE_DEFER); - list_for_each_entry(mbox, &mbox_cons, node) - if (mbox->dev->of_node =3D=3D spec.np) { - chan =3D mbox->of_xlate(mbox, &spec); - if (!IS_ERR(chan)) - break; + list_for_each_entry(mbox, &mbox_cons, node) { + if (device_match_fwnode(mbox->dev, fwspec.fwnode)) { + if (mbox->fw_xlate) { + chan =3D mbox->fw_xlate(mbox, &fwspec); + if (!IS_ERR(chan)) + break; + } else if (mbox->of_xlate) { + chan =3D mbox->of_xlate(mbox, &spec); + if (!IS_ERR(chan)) + break; + } } + } =20 - of_node_put(spec.np); + fwnode_handle_put(fwspec.fwnode); =20 if (IS_ERR(chan)) return chan; @@ -427,15 +450,8 @@ EXPORT_SYMBOL_GPL(mbox_request_channel); struct mbox_chan *mbox_request_channel_byname(struct mbox_client *cl, const char *name) { - struct device_node *np =3D cl->dev->of_node; - int index; - - if (!np) { - dev_err(cl->dev, "%s() currently only supports DT\n", __func__); - return ERR_PTR(-EINVAL); - } + int index =3D device_property_match_string(cl->dev, "mbox-names", name); =20 - index =3D of_property_match_string(np, "mbox-names", name); if (index < 0) { dev_err(cl->dev, "%s() could not locate channel named \"%s\"\n", __func__, name); @@ -470,9 +486,8 @@ void mbox_free_channel(struct mbox_chan *chan) } EXPORT_SYMBOL_GPL(mbox_free_channel); =20 -static struct mbox_chan * -of_mbox_index_xlate(struct mbox_controller *mbox, - const struct of_phandle_args *sp) +static struct mbox_chan *fw_mbox_index_xlate(struct mbox_controller *mbox, + const struct fwnode_reference_args *sp) { int ind =3D sp->args[0]; =20 @@ -523,8 +538,8 @@ int mbox_controller_register(struct mbox_controller *mb= ox) spin_lock_init(&chan->lock); } =20 - if (!mbox->of_xlate) - mbox->of_xlate =3D of_mbox_index_xlate; + if (!mbox->fw_xlate && !mbox->of_xlate) + mbox->fw_xlate =3D fw_mbox_index_xlate; =20 scoped_guard(mutex, &con_mutex) list_add_tail(&mbox->node, &mbox_cons); diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_con= troller.h index ad01c4082358..80a427c7ca29 100644 --- a/include/linux/mailbox_controller.h +++ b/include/linux/mailbox_controller.h @@ -66,6 +66,7 @@ struct mbox_chan_ops { * no interrupt rises. Ignored if 'txdone_irq' is set. * @txpoll_period: If 'txdone_poll' is in effect, the API polls for * last TX's status after these many millisecs + * @fw_xlate: Controller driver specific mapping of channel via fwnode * @of_xlate: Controller driver specific mapping of channel via DT * @poll_hrt: API private. hrtimer used to poll for TXDONE on all * channels. @@ -79,6 +80,8 @@ struct mbox_controller { bool txdone_irq; bool txdone_poll; unsigned txpoll_period; + struct mbox_chan *(*fw_xlate)(struct mbox_controller *mbox, + const struct fwnode_reference_args *sp); struct mbox_chan *(*of_xlate)(struct mbox_controller *mbox, const struct of_phandle_args *sp); /* Internal to API */ --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D2751F419B for ; Wed, 2 Jul 2025 05:14:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433294; cv=none; b=uK39r+eKGufRfO0vqXkErMFZ4FWu9NwIRR831hynfOnpTvd1CoQ2Cbp8+Pmm2sKgzesM+xIg9l0ejTRWqA24DVy4BWjQVlPkN7RVDyQnK3mUnB/o3r0mOdxebhVdug5HzKcmGAcTCnKQlhwxDT0oWjhozCLFFsZareEHQr8pCZY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433294; c=relaxed/simple; bh=WFYchEV23h84fSWMGcTr9nuW4BY0/9Qrh/fSfYTERSA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=chZwd1OQoLKe9/9o6zoq5qw0Lv1nA+0l04JePzqkFbgBrqRv1J8IXsCZ70De4U8mzno9eh6y7zTw5SDwAksbbLfQi3HabOc26ZrXiUd9GGv/4U83tjhAE9iaR7cIDOsobeIzNg+WrFKkpu2v6mxyDoWH7rjPlo2i5VJwRd412cE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=KAUunC5P; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="KAUunC5P" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-23aeac7d77aso36085675ad.3 for ; Tue, 01 Jul 2025 22:14:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433292; x=1752038092; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nqC4VLtB/5V/tfhRhr6dfZ8k+2Am0+dgL1H83VW+Xe4=; b=KAUunC5POYHxczW+Um+J3pkwdxy2NrUT3EzfwPsMFC02pFOmdL+UiFfukbSUHwh3TX tqiNCOi5se3TaLiTznwrFQ4BsKZoafDz7ObQxUb7ptqew8A4Jd1UOqM2goOwyw1c/LAd XtZQwFygfRuWjfDflfkxZn5QGEJInm277VNR43ueEOOq2OSuKnNKBHMOi2+9ye2l4Yd9 ynumkKV1pT/2xTyqYoyxFLGzAD1ksnY+yW5RwTDaA8b58U8+LRQXcnwAivSGIoNdAZp+ I4Ug0CC1AWudjjHIxWxyfVad/Eq5JZAmzTGI9753lD4M17DZAmCpHIr7Yg57p7HOxsjv j4vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433292; x=1752038092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nqC4VLtB/5V/tfhRhr6dfZ8k+2Am0+dgL1H83VW+Xe4=; b=GwxF74h90KNBtNkHxg9VRB8U8JJoU0PX//TYEQPBqsrIiZExfUOWppGE1SI03LL2u3 ekL0YFMR0q1Cg8Msbom090YBpe8hqAtByE6lZ02kWgZLhFZ4oJ3QKIWwnxJgeY13YsCp SGG52NYRrDM0j57ekjf++JC/9VAw+OjCXOWTxKBrB0oQP58Ll7QFOBwPrqSR3CTW+Jrn WQgn35vmZtAhAw+hgoQ2vefg8Uz+YJy522zcJCvUsxsZD2YKDQZuLuoUnql9nWosksv4 0Zr7+Hob9QxnV5CKKUJCMHuK72YYB5iIMjkYUXEFRnYshZSRt1TejUwe/wU9Nc2oMnxf ZOkA== X-Forwarded-Encrypted: i=1; AJvYcCUySZc5YrM02o5jsuuAtuvUQbbr+eIh7ACiep70VWHnYgDu7ZcnyYnRFFJRrAxUD29w0uAmziLLmUpCW34=@vger.kernel.org X-Gm-Message-State: AOJu0YwCwJnUyH1A2fYqsMvLZY2HaWZnzOea1adCrn1z2cAOmTEpXpts wHXZhU10Ci2LUpeIQJGQmb8PdgJAcPZBx5BuyEmQ9KyZu25dGqInZaG8GEFD5Eb0RB8= X-Gm-Gg: ASbGnctUAiBcJpkLSIeA3kcRtF4D4Isqt/sNtsf3LIAOZkjCvJvUeH3v4MamwT/3zea OSI7rVVerc0K4Wexufseatki7//IWZVXHMy+YhPzBYenNoMSHqUruqVEIOoKAxPaEllnvqDJnwi FCeTU66wxClfFEuteJ5xe6PDRiKbNtZrR+EAs+8WIBnLuAB6zfUivIvSyMn98j0O4udmDuzqykC 5jxfME736MZg0oIgXhgXJh+V75ww+/zY5Qifr8RjnMfsVb54K0g4GN3bcqtVs7NKaylisAeNT+z JelF30EagQPA2DhN2t7fXB3WCgRKc6vMU3x5+7VB9xB45io59KuWY+xtJYadv2OHnQBBWO7y/jI +sdH8A6D0AaULuKrR X-Google-Smtp-Source: AGHT+IGlyNbAZQuDOeCGGhEH6QTSFXwRevz7KU5t+CywLuVwtZ+G8tX33M+R/3t7hDV3PPKWLn7voA== X-Received: by 2002:a17:902:d2c6:b0:234:8ef1:aa7b with SMTP id d9443c01a7336-23c6e48f8admr18399295ad.20.1751433291916; Tue, 01 Jul 2025 22:14:51 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.14.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:14:51 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 06/24] byteorder: Add memcpy_to_le32() and memcpy_from_le32() Date: Wed, 2 Jul 2025 10:43:27 +0530 Message-ID: <20250702051345.1460497-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add common memcpy APIs for copying u32 array to/from __le32 array. Suggested-by: Andy Shevchenko Signed-off-by: Anup Patel Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij --- include/linux/byteorder/generic.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/linux/byteorder/generic.h b/include/linux/byteorder/ge= neric.h index c9a4c96c9943..b3705e8bbe2b 100644 --- a/include/linux/byteorder/generic.h +++ b/include/linux/byteorder/generic.h @@ -173,6 +173,22 @@ static inline void cpu_to_le32_array(u32 *buf, unsigne= d int words) } } =20 +static inline void memcpy_from_le32(u32 *dst, const __le32 *src, size_t wo= rds) +{ + size_t i; + + for (i =3D 0; i < words; i++) + dst[i] =3D le32_to_cpu(src[i]); +} + +static inline void memcpy_to_le32(__le32 *dst, const u32 *src, size_t word= s) +{ + size_t i; + + for (i =3D 0; i < words; i++) + dst[i] =3D cpu_to_le32(src[i]); +} + static inline void be16_add_cpu(__be16 *var, u16 val) { *var =3D cpu_to_be16(be16_to_cpu(*var) + val); --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72F101F419B for ; Wed, 2 Jul 2025 05:15:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433303; cv=none; b=N2/Eb1NLr+72TF5jJ39pLgZC0lzZTEyYAhP/xdmFFpmt4eTPhy8RfduDOGFtbZC6YtEhkv0DHnF2sBGZgPK81NFn21llcGa7OrfmrZYdXMR9s6G+YeHZXB4PyANvvNRkTS26eI0+DTXST2oKOSov2QJHLlglr3L5sRjbsI3U4Bs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433303; c=relaxed/simple; bh=jf+OkoEcwc90TgVCwXQGb087vA12voL2LL/tsH+LTNQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R3E1BeWh1N1Ii/LtAny+LH/hrM17vQRzPzUT3Sc2Vqr/8F+e0n+PgWzIFY/LNfJytpifuz7nwk1bzLFm1D69P6Km/ZP5cjyNvLWZSfaYrpcIMmoQUTV+tDQfSbHrEcPaDZ/gmwAbaXRp4f/UA1gFxm/BCzJqjg8EIsaJ6uvRhus= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=CfWfpEND; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="CfWfpEND" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-234fcadde3eso52611705ad.0 for ; Tue, 01 Jul 2025 22:15:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433300; x=1752038100; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q3+EcTY75VjQYt3/VY9he8DzkIGme89Cv35uV43GtjI=; b=CfWfpENDvX/4iIU6+uVF2BudTEJq2k3ySBvJWrUgN5SpTwK88WbYbJwm4XIY/qmvtU 6H63UJW30Zmsd6S8xkqUI4nyFWC+XbgK5CdSG5C7LsQPoNGT/3w6bJ1yJoAczEYhGdYD nHMCCIvm9+hn8uzaYxKKTZzlYSWGY39Nbkf6zb3GRH+6ehCmZ/WT6rDfnFm43mtcnc6f BkmxAsC8bagZmzKGqN7jGeXwE9KFk1M+184/SO6A/bl5ZIJB6G64B4O4wqMIv9okf36e K44lArH+X/Ej+X41DW8Wb6FgyxhZJBYu8h3kU8eBxI6MLPCX8eCl07/a5fPwpEeIBjc6 p3ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433300; x=1752038100; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q3+EcTY75VjQYt3/VY9he8DzkIGme89Cv35uV43GtjI=; b=pnu1s7nuQU2QywiGf55iBCmDiQaaV5EzB7NB5U+OjpKYP37cMNsqmGkdie6Bd9z+gS INtIe87lEKBbUZX+VbkSPiKgej5Up4l6G/78RRL62bW4nX0w7ZHel/dWJCIMPXv+fl6b d0rkaSeh93bFIWbtyF+IEJ0ySrgy0vpZyRVD5GJbBF+byY5M3KejuB/imlscUcXnYSuJ KuE6/UhuA3iTW50FFXZwHb6wYo2w32RjjlLQtaaeq2raQCnlDv7uxLH0SQBja5CQHExL p1cZ/ZP315BJgdQoYywEXrTaJn5GkPjJmWTCyAB/90cqUx0Aro3qvNxze5+dAdb/K77H MS0Q== X-Forwarded-Encrypted: i=1; AJvYcCVSy3rXuVrlUY2UTAuqtS2bLhnK3D2dRK80lKeHGmD/eMknQDRlLcoMW2MO1Qvm5w29i0woLeNYk+PWsvM=@vger.kernel.org X-Gm-Message-State: AOJu0YyJ9dqxcqxHHBIM944IzFN5hANHxFYPhSzaJKGExWvFn13cJ851 LcOfFLUvLpsHu1AYFm0m7BpBtSsgl5MNWQhgvZzDWdN4rck40xTDpmOsscmNk/cgwcY= X-Gm-Gg: ASbGncu6mn/jghBgfo/48vVD+H3ejb0WNOuusqVbZIrpSDhK5dCuucEGPf30qlRDXCp EjDMPraH1WRZ2+ym7ONcm8PmFRdN3FdjFxuXePeG9fcaGqu0V7vCt6AFn2hmeed61qXXJrAM6CJ RzYn1sg/SzJHFFL6RqoAqsCvOBLjO1aZulfzwp68B7IIqy68jZN9SyE91dIjJb0KF4RDR2wl1oj cDrdBz5EFcVHyJvbSjSr6rcNthlK1qFUANbiDktoerzrVN2fRtprp2hpFe0vs698y7h7w6iMd7I 9cS4MsPbi/8PMgX5E7gvahJ3dpPuBmMGHXDL6iH1AKV4/Slz2NSdUXmrN9n8q1SCZJSEtaFtymI xNilbkfEQUjseSt4O X-Google-Smtp-Source: AGHT+IGW0k6oeOHrzm5x55iHWHIJK/2k07LFHt+lRoWk84qe0hC5nCoa3vxK+FCq2SLVQtXMmyDDqw== X-Received: by 2002:a17:902:f60c:b0:235:c781:c305 with SMTP id d9443c01a7336-23c6e58aa83mr25137845ad.24.1751433299574; Tue, 01 Jul 2025 22:14:59 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:14:59 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 07/24] mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver Date: Wed, 2 Jul 2025 10:43:28 +0530 Message-ID: <20250702051345.1460497-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a mailbox controller driver for the new SBI message proxy extension which is part of the SBI v3.0 specification. Co-developed-by: Rahul Pathak Signed-off-by: Rahul Pathak Signed-off-by: Anup Patel --- drivers/mailbox/Kconfig | 11 + drivers/mailbox/Makefile | 2 + drivers/mailbox/riscv-sbi-mpxy-mbox.c | 988 ++++++++++++++++++++++++++ 3 files changed, 1001 insertions(+) create mode 100644 drivers/mailbox/riscv-sbi-mpxy-mbox.c diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 68eeed660a4a..eb5e0384fec6 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -340,4 +340,15 @@ config THEAD_TH1520_MBOX kernel is running, and E902 core used for power management among other things. =20 +config RISCV_SBI_MPXY_MBOX + tristate "RISC-V SBI Message Proxy (MPXY) Mailbox" + depends on RISCV_SBI + default RISCV + help + Mailbox driver implementation for RISC-V SBI Message Proxy (MPXY) + extension. This mailbox driver is used to send messages to the + remote processor through the SBI implementation (M-mode firmware + or HS-mode hypervisor). Say Y here if you want to have this support. + If unsure say N. + endif diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 13a3448b3271..46689c1277f8 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -72,3 +72,5 @@ obj-$(CONFIG_QCOM_CPUCP_MBOX) +=3D qcom-cpucp-mbox.o obj-$(CONFIG_QCOM_IPCC) +=3D qcom-ipcc.o =20 obj-$(CONFIG_THEAD_TH1520_MBOX) +=3D mailbox-th1520.o + +obj-$(CONFIG_RISCV_SBI_MPXY_MBOX) +=3D riscv-sbi-mpxy-mbox.o diff --git a/drivers/mailbox/riscv-sbi-mpxy-mbox.c b/drivers/mailbox/riscv-= sbi-mpxy-mbox.c new file mode 100644 index 000000000000..129710f947ae --- /dev/null +++ b/drivers/mailbox/riscv-sbi-mpxy-mbox.c @@ -0,0 +1,988 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RISC-V SBI Message Proxy (MPXY) mailbox controller driver + * + * Copyright (C) 2025 Ventana Micro Systems Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* =3D=3D=3D=3D=3D=3D SBI MPXY extension data structures =3D=3D=3D=3D=3D= =3D */ + +/* SBI MPXY MSI related channel attributes */ +struct sbi_mpxy_msi_info { + /* Lower 32-bits of the MSI target address */ + u32 msi_addr_lo; + /* Upper 32-bits of the MSI target address */ + u32 msi_addr_hi; + /* MSI data value */ + u32 msi_data; +}; + +/* + * SBI MPXY standard channel attributes. + * + * NOTE: The sequence of attribute fields are as-per the + * defined sequence in the attribute table in spec (or + * as-per the enum sbi_mpxy_attribute_id). + */ +struct sbi_mpxy_channel_attrs { + /* Message protocol ID */ + u32 msg_proto_id; + /* Message protocol version */ + u32 msg_proto_version; + /* Message protocol maximum message length */ + u32 msg_max_len; + /* Message protocol message send timeout in microseconds */ + u32 msg_send_timeout; + /* Message protocol message completion timeout in microseconds */ + u32 msg_completion_timeout; + /* Bit array for channel capabilities */ + u32 capability; + /* SSE event ID */ + u32 sse_event_id; + /* MSI enable/disable control knob */ + u32 msi_control; + /* Channel MSI info */ + struct sbi_mpxy_msi_info msi_info; + /* Events state control */ + u32 events_state_ctrl; +}; + +/* + * RPMI specific SBI MPXY channel attributes. + * + * NOTE: The sequence of attribute fields are as-per the + * defined sequence in the attribute table in spec (or + * as-per the enum sbi_mpxy_rpmi_attribute_id). + */ +struct sbi_mpxy_rpmi_channel_attrs { + /* RPMI service group ID */ + u32 servicegroup_id; + /* RPMI service group version */ + u32 servicegroup_version; + /* RPMI implementation ID */ + u32 impl_id; + /* RPMI implementation version */ + u32 impl_version; +}; + +/* SBI MPXY channel IDs data in shared memory */ +struct sbi_mpxy_channel_ids_data { + /* Remaining number of channel ids */ + __le32 remaining; + /* Returned channel ids in current function call */ + __le32 returned; + /* Returned channel id array */ + __le32 channel_array[]; +}; + +/* SBI MPXY notification data in shared memory */ +struct sbi_mpxy_notification_data { + /* Remaining number of notification events */ + __le32 remaining; + /* Number of notification events returned */ + __le32 returned; + /* Number of notification events lost */ + __le32 lost; + /* Reserved for future use */ + __le32 reserved; + /* Returned channel id array */ + u8 events_data[]; +}; + +/* =3D=3D=3D=3D=3D=3D MPXY data structures & helper routines =3D=3D=3D=3D= =3D=3D */ + +/* MPXY Per-CPU or local context */ +struct mpxy_local { + /* Shared memory base address */ + void *shmem; + /* Shared memory physical address */ + phys_addr_t shmem_phys_addr; + /* Flag representing whether shared memory is active or not */ + bool shmem_active; +}; + +static DEFINE_PER_CPU(struct mpxy_local, mpxy_local); +static unsigned long mpxy_shmem_size; +static bool mpxy_shmem_init_done; + +static int mpxy_get_channel_count(u32 *channel_count) +{ + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + struct sbi_mpxy_channel_ids_data *sdata =3D mpxy->shmem; + u32 remaining, returned; + struct sbiret sret; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!channel_count) + return -EINVAL; + + get_cpu(); + + /* Get the remaining and returned fields to calculate total */ + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_GET_CHANNEL_IDS, + 0, 0, 0, 0, 0, 0); + if (sret.error) + goto err_put_cpu; + + remaining =3D le32_to_cpu(sdata->remaining); + returned =3D le32_to_cpu(sdata->returned); + *channel_count =3D remaining + returned; + +err_put_cpu: + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static int mpxy_get_channel_ids(u32 channel_count, u32 *channel_ids) +{ + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + struct sbi_mpxy_channel_ids_data *sdata =3D mpxy->shmem; + u32 remaining, returned, count, start_index =3D 0; + struct sbiret sret; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!channel_count || !channel_ids) + return -EINVAL; + + get_cpu(); + + do { + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_GET_CHANNEL_IDS, + start_index, 0, 0, 0, 0, 0); + if (sret.error) + goto err_put_cpu; + + remaining =3D le32_to_cpu(sdata->remaining); + returned =3D le32_to_cpu(sdata->returned); + + count =3D returned < (channel_count - start_index) ? + returned : (channel_count - start_index); + memcpy_from_le32(&channel_ids[start_index], sdata->channel_array, count); + start_index +=3D count; + } while (remaining && start_index < channel_count); + +err_put_cpu: + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static int mpxy_read_attrs(u32 channel_id, u32 base_attrid, u32 attr_count, + u32 *attrs_buf) +{ + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + struct sbiret sret; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!attr_count || !attrs_buf) + return -EINVAL; + + get_cpu(); + + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_READ_ATTRS, + channel_id, base_attrid, attr_count, 0, 0, 0); + if (sret.error) + goto err_put_cpu; + + memcpy_from_le32(attrs_buf, (__le32 *)mpxy->shmem, attr_count); + +err_put_cpu: + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static int mpxy_write_attrs(u32 channel_id, u32 base_attrid, u32 attr_coun= t, + u32 *attrs_buf) +{ + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + struct sbiret sret; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!attr_count || !attrs_buf) + return -EINVAL; + + get_cpu(); + + memcpy_to_le32((__le32 *)mpxy->shmem, attrs_buf, attr_count); + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_WRITE_ATTRS, + channel_id, base_attrid, attr_count, 0, 0, 0); + + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static int mpxy_send_message_with_resp(u32 channel_id, u32 msg_id, + void *tx, unsigned long tx_len, + void *rx, unsigned long max_rx_len, + unsigned long *rx_len) +{ + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + unsigned long rx_bytes; + struct sbiret sret; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!tx && tx_len) + return -EINVAL; + + get_cpu(); + + /* Message protocols allowed to have no data in messages */ + if (tx_len) + memcpy(mpxy->shmem, tx, tx_len); + + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_SEND_MSG_WITH_RESP, + channel_id, msg_id, tx_len, 0, 0, 0); + if (rx && !sret.error) { + rx_bytes =3D sret.value; + if (rx_bytes > max_rx_len) { + put_cpu(); + return -ENOSPC; + } + + memcpy(rx, mpxy->shmem, rx_bytes); + if (rx_len) + *rx_len =3D rx_bytes; + } + + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static int mpxy_send_message_without_resp(u32 channel_id, u32 msg_id, + void *tx, unsigned long tx_len) +{ + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + struct sbiret sret; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!tx && tx_len) + return -EINVAL; + + get_cpu(); + + /* Message protocols allowed to have no data in messages */ + if (tx_len) + memcpy(mpxy->shmem, tx, tx_len); + + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP, + channel_id, msg_id, tx_len, 0, 0, 0); + + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static int mpxy_get_notifications(u32 channel_id, + struct sbi_mpxy_notification_data *notif_data, + unsigned long *events_data_len) +{ + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + struct sbiret sret; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!notif_data || !events_data_len) + return -EINVAL; + + get_cpu(); + + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_GET_NOTIFICATION_EVENTS, + channel_id, 0, 0, 0, 0, 0); + if (sret.error) + goto err_put_cpu; + + memcpy(notif_data, mpxy->shmem, sret.value + 16); + *events_data_len =3D sret.value; + +err_put_cpu: + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static int mpxy_get_shmem_size(unsigned long *shmem_size) +{ + struct sbiret sret; + + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_GET_SHMEM_SIZE, + 0, 0, 0, 0, 0, 0); + if (sret.error) + return sbi_err_map_linux_errno(sret.error); + if (shmem_size) + *shmem_size =3D sret.value; + return 0; +} + +static int mpxy_setup_shmem(unsigned int cpu) +{ + struct page *shmem_page; + struct mpxy_local *mpxy; + struct sbiret sret; + + mpxy =3D per_cpu_ptr(&mpxy_local, cpu); + if (mpxy->shmem_active) + return 0; + + shmem_page =3D alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(mpxy_shmem_= size)); + if (!shmem_page) + return -ENOMEM; + + /* + * Linux setup of shmem is done in mpxy OVERWRITE mode. + * flags[1:0] =3D 00b + */ + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_SET_SHMEM, + page_to_phys(shmem_page), 0, 0, 0, 0, 0); + if (sret.error) { + free_pages((unsigned long)page_to_virt(shmem_page), + get_order(mpxy_shmem_size)); + return sbi_err_map_linux_errno(sret.error); + } + + mpxy->shmem =3D page_to_virt(shmem_page); + mpxy->shmem_phys_addr =3D page_to_phys(shmem_page); + mpxy->shmem_active =3D true; + + return 0; +} + +/* =3D=3D=3D=3D=3D=3D MPXY mailbox data structures =3D=3D=3D=3D=3D=3D */ + +/* MPXY mailbox channel */ +struct mpxy_mbox_channel { + struct mpxy_mbox *mbox; + u32 channel_id; + struct sbi_mpxy_channel_attrs attrs; + struct sbi_mpxy_rpmi_channel_attrs rpmi_attrs; + struct sbi_mpxy_notification_data *notif; + u32 max_xfer_len; + bool have_events_state; + u32 msi_index; + u32 msi_irq; + bool started; +}; + +/* MPXY mailbox */ +struct mpxy_mbox { + struct device *dev; + u32 channel_count; + struct mpxy_mbox_channel *channels; + u32 msi_count; + struct mpxy_mbox_channel **msi_index_to_channel; + struct mbox_controller controller; +}; + +/* =3D=3D=3D=3D=3D=3D MPXY RPMI processing =3D=3D=3D=3D=3D=3D */ + +static void mpxy_mbox_send_rpmi_data(struct mpxy_mbox_channel *mchan, + struct rpmi_mbox_message *msg) +{ + int rc =3D 0; + + switch (msg->type) { + case RPMI_MBOX_MSG_TYPE_GET_ATTRIBUTE: + switch (msg->attr.id) { + case RPMI_MBOX_ATTR_SPEC_VERSION: + msg->attr.value =3D mchan->attrs.msg_proto_version; + break; + case RPMI_MBOX_ATTR_MAX_MSG_DATA_SIZE: + msg->attr.value =3D mchan->max_xfer_len; + break; + case RPMI_MBOX_ATTR_SERVICEGROUP_ID: + msg->attr.value =3D mchan->rpmi_attrs.servicegroup_id; + break; + case RPMI_MBOX_ATTR_SERVICEGROUP_VERSION: + msg->attr.value =3D mchan->rpmi_attrs.servicegroup_version; + break; + case RPMI_MBOX_ATTR_IMPL_ID: + msg->attr.value =3D mchan->rpmi_attrs.impl_id; + break; + case RPMI_MBOX_ATTR_IMPL_VERSION: + msg->attr.value =3D mchan->rpmi_attrs.impl_version; + break; + default: + rc =3D -EOPNOTSUPP; + break; + } + break; + case RPMI_MBOX_MSG_TYPE_SET_ATTRIBUTE: + /* None of the RPMI linux mailbox attributes are writeable */ + rc =3D -EOPNOTSUPP; + break; + case RPMI_MBOX_MSG_TYPE_SEND_WITH_RESPONSE: + if ((!msg->data.request && msg->data.request_len) || + (msg->data.request && + msg->data.request_len > mchan->max_xfer_len) || + (!msg->data.response && msg->data.max_response_len)) { + rc =3D -EINVAL; + break; + } + if (!(mchan->attrs.capability & SBI_MPXY_CHAN_CAP_SEND_WITH_RESP)) { + rc =3D -EIO; + break; + } + rc =3D mpxy_send_message_with_resp(mchan->channel_id, + msg->data.service_id, + msg->data.request, + msg->data.request_len, + msg->data.response, + msg->data.max_response_len, + &msg->data.out_response_len); + break; + case RPMI_MBOX_MSG_TYPE_SEND_WITHOUT_RESPONSE: + if ((!msg->data.request && msg->data.request_len) || + (msg->data.request && + msg->data.request_len > mchan->max_xfer_len)) { + rc =3D -EINVAL; + break; + } + if (!(mchan->attrs.capability & SBI_MPXY_CHAN_CAP_SEND_WITHOUT_RESP)) { + rc =3D -EIO; + break; + } + rc =3D mpxy_send_message_without_resp(mchan->channel_id, + msg->data.service_id, + msg->data.request, + msg->data.request_len); + break; + default: + rc =3D -EOPNOTSUPP; + break; + } + + msg->error =3D rc; +} + +static void mpxy_mbox_peek_rpmi_data(struct mbox_chan *chan, + struct mpxy_mbox_channel *mchan, + struct sbi_mpxy_notification_data *notif, + unsigned long events_data_len) +{ + struct rpmi_notification_event *event; + unsigned long pos =3D 0, event_size; + struct rpmi_mbox_message msg; + + while ((pos < events_data_len) && !(pos & 0x3) && + ((events_data_len - pos) <=3D sizeof(*event))) { + event =3D (struct rpmi_notification_event *)(notif->events_data + pos); + + msg.type =3D RPMI_MBOX_MSG_TYPE_NOTIFICATION_EVENT; + msg.notif.event_datalen =3D le16_to_cpu(event->event_datalen); + msg.notif.event_id =3D event->event_id; + msg.notif.event_data =3D event->event_data; + msg.error =3D 0; + + event_size =3D sizeof(*event) + msg.notif.event_datalen; + if (event_size > (events_data_len - pos)) { + event_size =3D events_data_len - pos; + goto skip_event; + } + if (event_size & 0x3) + goto skip_event; + + mbox_chan_received_data(chan, &msg); + +skip_event: + pos +=3D event_size; + } +} + +static int mpxy_mbox_read_rpmi_attrs(struct mpxy_mbox_channel *mchan) +{ + return mpxy_read_attrs(mchan->channel_id, + SBI_MPXY_ATTR_MSGPROTO_ATTR_START, + sizeof(mchan->rpmi_attrs) / sizeof(u32), + (u32 *)&mchan->rpmi_attrs); +} + +/* =3D=3D=3D=3D=3D=3D MPXY mailbox callbacks =3D=3D=3D=3D=3D=3D */ + +static int mpxy_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct mpxy_mbox_channel *mchan =3D chan->con_priv; + + if (mchan->attrs.msg_proto_id =3D=3D SBI_MPXY_MSGPROTO_RPMI_ID) { + mpxy_mbox_send_rpmi_data(mchan, data); + return 0; + } + + return -EOPNOTSUPP; +} + +static bool mpxy_mbox_peek_data(struct mbox_chan *chan) +{ + struct mpxy_mbox_channel *mchan =3D chan->con_priv; + struct sbi_mpxy_notification_data *notif =3D mchan->notif; + bool have_notifications =3D false; + unsigned long data_len; + int rc; + + if (!(mchan->attrs.capability & SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS)) + return false; + + do { + rc =3D mpxy_get_notifications(mchan->channel_id, notif, &data_len); + if (rc || !data_len) + break; + + if (mchan->attrs.msg_proto_id =3D=3D SBI_MPXY_MSGPROTO_RPMI_ID) + mpxy_mbox_peek_rpmi_data(chan, mchan, notif, data_len); + + have_notifications =3D true; + } while (1); + + return have_notifications; +} + +static irqreturn_t mpxy_mbox_irq_thread(int irq, void *dev_id) +{ + mpxy_mbox_peek_data(dev_id); + return IRQ_HANDLED; +} + +static int mpxy_mbox_setup_msi(struct mbox_chan *chan, + struct mpxy_mbox_channel *mchan) +{ + struct device *dev =3D mchan->mbox->dev; + int rc; + + /* Do nothing if MSI not supported */ + if (mchan->msi_irq =3D=3D U32_MAX) + return 0; + + /* Fail if MSI already enabled */ + if (mchan->attrs.msi_control) + return -EALREADY; + + /* Request channel MSI handler */ + rc =3D request_threaded_irq(mchan->msi_irq, NULL, mpxy_mbox_irq_thread, + 0, dev_name(dev), chan); + if (rc) { + dev_err(dev, "failed to request MPXY channel 0x%x IRQ\n", + mchan->channel_id); + return rc; + } + + /* Enable channel MSI control */ + mchan->attrs.msi_control =3D 1; + rc =3D mpxy_write_attrs(mchan->channel_id, SBI_MPXY_ATTR_MSI_CONTROL, + 1, &mchan->attrs.msi_control); + if (rc) { + dev_err(dev, "enable MSI control failed for MPXY channel 0x%x\n", + mchan->channel_id); + mchan->attrs.msi_control =3D 0; + free_irq(mchan->msi_irq, chan); + return rc; + } + + return 0; +} + +static void mpxy_mbox_cleanup_msi(struct mbox_chan *chan, + struct mpxy_mbox_channel *mchan) +{ + struct device *dev =3D mchan->mbox->dev; + int rc; + + /* Do nothing if MSI not supported */ + if (mchan->msi_irq =3D=3D U32_MAX) + return; + + /* Do nothing if MSI already disabled */ + if (!mchan->attrs.msi_control) + return; + + /* Disable channel MSI control */ + mchan->attrs.msi_control =3D 0; + rc =3D mpxy_write_attrs(mchan->channel_id, SBI_MPXY_ATTR_MSI_CONTROL, + 1, &mchan->attrs.msi_control); + if (rc) { + dev_err(dev, "disable MSI control failed for MPXY channel 0x%x\n", + mchan->channel_id); + } + + /* Free channel MSI handler */ + free_irq(mchan->msi_irq, chan); +} + +static int mpxy_mbox_setup_events(struct mpxy_mbox_channel *mchan) +{ + struct device *dev =3D mchan->mbox->dev; + int rc; + + /* Do nothing if events state not supported */ + if (!mchan->have_events_state) + return 0; + + /* Fail if events state already enabled */ + if (mchan->attrs.events_state_ctrl) + return -EALREADY; + + /* Enable channel events state */ + mchan->attrs.events_state_ctrl =3D 1; + rc =3D mpxy_write_attrs(mchan->channel_id, SBI_MPXY_ATTR_EVENTS_STATE_CON= TROL, + 1, &mchan->attrs.events_state_ctrl); + if (rc) { + dev_err(dev, "enable events state failed for MPXY channel 0x%x\n", + mchan->channel_id); + mchan->attrs.events_state_ctrl =3D 0; + return rc; + } + + return 0; +} + +static void mpxy_mbox_cleanup_events(struct mpxy_mbox_channel *mchan) +{ + struct device *dev =3D mchan->mbox->dev; + int rc; + + /* Do nothing if events state not supported */ + if (!mchan->have_events_state) + return; + + /* Do nothing if events state already disabled */ + if (!mchan->attrs.events_state_ctrl) + return; + + /* Disable channel events state */ + mchan->attrs.events_state_ctrl =3D 0; + rc =3D mpxy_write_attrs(mchan->channel_id, SBI_MPXY_ATTR_EVENTS_STATE_CON= TROL, + 1, &mchan->attrs.events_state_ctrl); + if (rc) + dev_err(dev, "disable events state failed for MPXY channel 0x%x\n", + mchan->channel_id); +} + +static int mpxy_mbox_startup(struct mbox_chan *chan) +{ + struct mpxy_mbox_channel *mchan =3D chan->con_priv; + int rc; + + if (mchan->started) + return -EALREADY; + + /* Setup channel MSI */ + rc =3D mpxy_mbox_setup_msi(chan, mchan); + if (rc) + return rc; + + /* Setup channel notification events */ + rc =3D mpxy_mbox_setup_events(mchan); + if (rc) { + mpxy_mbox_cleanup_msi(chan, mchan); + return rc; + } + + /* Mark the channel as started */ + mchan->started =3D true; + + return 0; +} + +static void mpxy_mbox_shutdown(struct mbox_chan *chan) +{ + struct mpxy_mbox_channel *mchan =3D chan->con_priv; + + if (!mchan->started) + return; + + /* Mark the channel as stopped */ + mchan->started =3D false; + + /* Cleanup channel notification events */ + mpxy_mbox_cleanup_events(mchan); + + /* Cleanup channel MSI */ + mpxy_mbox_cleanup_msi(chan, mchan); +} + +static const struct mbox_chan_ops mpxy_mbox_ops =3D { + .send_data =3D mpxy_mbox_send_data, + .peek_data =3D mpxy_mbox_peek_data, + .startup =3D mpxy_mbox_startup, + .shutdown =3D mpxy_mbox_shutdown, +}; + +/* =3D=3D=3D=3D=3D=3D MPXY platform driver =3D=3D=3D=3D=3D */ + +static void mpxy_mbox_msi_write(struct msi_desc *desc, struct msi_msg *msg) +{ + struct device *dev =3D msi_desc_to_dev(desc); + struct mpxy_mbox *mbox =3D dev_get_drvdata(dev); + struct mpxy_mbox_channel *mchan; + struct sbi_mpxy_msi_info *minfo; + int rc; + + mchan =3D mbox->msi_index_to_channel[desc->msi_index]; + if (!mchan) { + dev_warn(dev, "MPXY channel not available for MSI index %d\n", + desc->msi_index); + return; + } + + minfo =3D &mchan->attrs.msi_info; + minfo->msi_addr_lo =3D msg->address_lo; + minfo->msi_addr_hi =3D msg->address_hi; + minfo->msi_data =3D msg->data; + + rc =3D mpxy_write_attrs(mchan->channel_id, SBI_MPXY_ATTR_MSI_ADDR_LO, + sizeof(*minfo) / sizeof(u32), (u32 *)minfo); + if (rc) { + dev_warn(dev, "failed to write MSI info for MPXY channel 0x%x\n", + mchan->channel_id); + } +} + +static struct mbox_chan *mpxy_mbox_fw_xlate(struct mbox_controller *ctlr, + const struct fwnode_reference_args *pa) +{ + struct mpxy_mbox *mbox =3D container_of(ctlr, struct mpxy_mbox, controlle= r); + struct mpxy_mbox_channel *mchan; + u32 i; + + if (pa->nargs !=3D 2) + return ERR_PTR(-EINVAL); + + for (i =3D 0; i < mbox->channel_count; i++) { + mchan =3D &mbox->channels[i]; + if (mchan->channel_id =3D=3D pa->args[0] && + mchan->attrs.msg_proto_id =3D=3D pa->args[1]) + return &mbox->controller.chans[i]; + } + + return ERR_PTR(-ENOENT); +} + +static int mpxy_mbox_probe(struct platform_device *pdev) +{ + u32 i, *channel_ids __free(kfree) =3D NULL; + struct device *dev =3D &pdev->dev; + struct mpxy_mbox_channel *mchan; + struct mpxy_mbox *mbox; + int msi_idx, rc; + + /* + * Initialize MPXY shared memory only once. This also ensures + * that SBI MPXY mailbox is probed only once. + */ + if (mpxy_shmem_init_done) { + dev_err(dev, "SBI MPXY mailbox already initialized\n"); + return -EALREADY; + } + + /* Probe for SBI MPXY extension */ + if (sbi_spec_version < sbi_mk_version(1, 0) || + sbi_probe_extension(SBI_EXT_MPXY) <=3D 0) { + dev_info(dev, "SBI MPXY extension not available\n"); + return -ENODEV; + } + + /* Find-out shared memory size */ + rc =3D mpxy_get_shmem_size(&mpxy_shmem_size); + if (rc) + return dev_err_probe(dev, rc, "failed to get MPXY shared memory size\n"); + + /* + * Setup MPXY shared memory on each CPU + * + * Note: Don't cleanup MPXY shared memory upon CPU power-down + * because the RPMI System MSI irqchip driver needs it to be + * available when migrating IRQs in CPU power-down path. + */ + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/sbi-mpxy-shmem", + mpxy_setup_shmem, NULL); + + /* Mark as MPXY shared memory initialization done */ + mpxy_shmem_init_done =3D true; + + /* Allocate mailbox instance */ + mbox =3D devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + mbox->dev =3D dev; + platform_set_drvdata(pdev, mbox); + + /* Find-out of number of channels */ + rc =3D mpxy_get_channel_count(&mbox->channel_count); + if (rc) + return dev_err_probe(dev, rc, "failed to get number of MPXY channels\n"); + if (!mbox->channel_count) + dev_err_probe(dev, -ENODEV, "no MPXY channels available\n"); + + /* Allocate and fetch all channel IDs */ + channel_ids =3D kcalloc(mbox->channel_count, sizeof(*channel_ids), GFP_KE= RNEL); + if (!channel_ids) + return -ENOMEM; + rc =3D mpxy_get_channel_ids(mbox->channel_count, channel_ids); + if (rc) + return dev_err_probe(dev, rc, "failed to get MPXY channel IDs\n"); + + /* Populate all channels */ + mbox->channels =3D devm_kcalloc(dev, mbox->channel_count, + sizeof(*mbox->channels), GFP_KERNEL); + if (!mbox->channels) + return -ENOMEM; + for (i =3D 0; i < mbox->channel_count; i++) { + mchan =3D &mbox->channels[i]; + mchan->mbox =3D mbox; + mchan->channel_id =3D channel_ids[i]; + + rc =3D mpxy_read_attrs(mchan->channel_id, SBI_MPXY_ATTR_MSG_PROT_ID, + sizeof(mchan->attrs) / sizeof(u32), + (u32 *)&mchan->attrs); + if (rc) { + return dev_err_probe(dev, rc, + "MPXY channel 0x%x read attrs failed\n", + mchan->channel_id); + } + + if (mchan->attrs.msg_proto_id =3D=3D SBI_MPXY_MSGPROTO_RPMI_ID) { + rc =3D mpxy_mbox_read_rpmi_attrs(mchan); + if (rc) { + return dev_err_probe(dev, rc, + "MPXY channel 0x%x read RPMI attrs failed\n", + mchan->channel_id); + } + } + + mchan->notif =3D devm_kzalloc(dev, mpxy_shmem_size, GFP_KERNEL); + if (!mchan->notif) + return -ENOMEM; + + mchan->max_xfer_len =3D min(mpxy_shmem_size, mchan->attrs.msg_max_len); + + if ((mchan->attrs.capability & SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS) && + (mchan->attrs.capability & SBI_MPXY_CHAN_CAP_EVENTS_STATE)) + mchan->have_events_state =3D true; + + if ((mchan->attrs.capability & SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS) && + (mchan->attrs.capability & SBI_MPXY_CHAN_CAP_MSI)) + mchan->msi_index =3D mbox->msi_count++; + else + mchan->msi_index =3D U32_MAX; + mchan->msi_irq =3D U32_MAX; + } + + /* Initialize mailbox controller */ + mbox->controller.txdone_irq =3D false; + mbox->controller.txdone_poll =3D false; + mbox->controller.ops =3D &mpxy_mbox_ops; + mbox->controller.dev =3D dev; + mbox->controller.num_chans =3D mbox->channel_count; + mbox->controller.fw_xlate =3D mpxy_mbox_fw_xlate; + mbox->controller.chans =3D devm_kcalloc(dev, mbox->channel_count, + sizeof(*mbox->controller.chans), + GFP_KERNEL); + if (!mbox->controller.chans) + return -ENOMEM; + for (i =3D 0; i < mbox->channel_count; i++) + mbox->controller.chans[i].con_priv =3D &mbox->channels[i]; + + /* Set the MSI domain if not available */ + if (!dev_get_msi_domain(dev)) { + /* + * The device MSI domain for OF devices is only set at the + * time of populating/creating OF device. If the device MSI + * domain is discovered later after the OF device is created + * then we need to set it explicitly before using any platform + * MSI functions. + */ + if (dev_of_node(dev)) + of_msi_configure(dev, dev_of_node(dev)); + } + + /* Setup MSIs for mailbox (if required) */ + if (mbox->msi_count) { + mbox->msi_index_to_channel =3D devm_kcalloc(dev, mbox->msi_count, + sizeof(*mbox->msi_index_to_channel), + GFP_KERNEL); + if (!mbox->msi_index_to_channel) + return -ENOMEM; + + for (msi_idx =3D 0; msi_idx < mbox->msi_count; msi_idx++) { + for (i =3D 0; i < mbox->channel_count; i++) { + mchan =3D &mbox->channels[i]; + if (mchan->msi_index =3D=3D msi_idx) { + mbox->msi_index_to_channel[msi_idx] =3D mchan; + break; + } + } + } + + rc =3D platform_device_msi_init_and_alloc_irqs(dev, mbox->msi_count, + mpxy_mbox_msi_write); + if (rc) { + return dev_err_probe(dev, rc, "Failed to allocate %d MSIs\n", + mbox->msi_count); + } + + for (i =3D 0; i < mbox->channel_count; i++) { + mchan =3D &mbox->channels[i]; + if (mchan->msi_index =3D=3D U32_MAX) + continue; + mchan->msi_irq =3D msi_get_virq(dev, mchan->msi_index); + } + } + + /* Register mailbox controller */ + rc =3D devm_mbox_controller_register(dev, &mbox->controller); + if (rc) { + dev_err_probe(dev, rc, "Registering SBI MPXY mailbox failed\n"); + if (mbox->msi_count) + platform_device_msi_free_irqs_all(dev); + return rc; + } + + dev_info(dev, "mailbox registered with %d channels\n", + mbox->channel_count); + return 0; +} + +static void mpxy_mbox_remove(struct platform_device *pdev) +{ + struct mpxy_mbox *mbox =3D platform_get_drvdata(pdev); + + if (mbox->msi_count) + platform_device_msi_free_irqs_all(mbox->dev); +} + +static const struct of_device_id mpxy_mbox_of_match[] =3D { + { .compatible =3D "riscv,sbi-mpxy-mbox" }, + {} +}; +MODULE_DEVICE_TABLE(of, mpxy_mbox_of_match); + +static struct platform_driver mpxy_mbox_driver =3D { + .driver =3D { + .name =3D "riscv-sbi-mpxy-mbox", + .of_match_table =3D mpxy_mbox_of_match, + }, + .probe =3D mpxy_mbox_probe, + .remove =3D mpxy_mbox_remove, +}; +module_platform_driver(mpxy_mbox_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Anup Patel "); +MODULE_DESCRIPTION("RISC-V SBI MPXY mailbox controller driver"); --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 328F21FF1A0 for ; Wed, 2 Jul 2025 05:15:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433309; cv=none; b=o6m/xqYVyX295nigP0cbS8sRWpC218NFzHs0VIFF5XjcENJAD5B0jqi7lugKF+9v0NDyeaqY/+NRhhQCONeEv5RnYDOPg6YOJNWnPopOnl+KhPq5xnw/DVEhJ7fR/BUWb/PEkxXq+V9HIXBgLCkG64yYLzxDDMvq1Rjkr/O/APo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433309; c=relaxed/simple; bh=psnTedHrRclNzYfKOxzNdzEC/lgie9/9OjOQXPUJ9ek=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=f5Uvj3mOv2nwivknjDXQ3HmvhacGlNweK3NIQFc895wP9nqLLRCaZB80xn7JhQxuWASZYhuai5XSpBy6RoLZlRBaMdYwdTGU0mywnNqdSluBTlaKyGYE9A92MC5p9DjlFDnHaTBUHeB8xqxL4iRF2LoyyW2Tj4VS8qkdrD6uVmQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=MS06SEOK; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="MS06SEOK" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-2353a2bc210so37509295ad.2 for ; Tue, 01 Jul 2025 22:15:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433307; x=1752038107; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UM/HZQdb2lcK8V7OkC2GVlA2nnGt1f60vmRpDyo8E4k=; b=MS06SEOKqAq2sDyiM6roZK+5IviUHYOH3c/3h7krrp9PGbPyn05DAhdsp7HfywR+OV cqqJrIp5zkghm2GCbrJxiJXnq3Wxz67kvUoK/x3Huy4WS+8KpjuFdKN+NOduUoKO8j34 n6Gcn0X9v8twNO+x51qfKLunLG6nTJ+0Yty4qzOSOfnS9tWZGzgdNaEqRK3N7bzZZ9Iu MWIqxrpOY0n6b1b08Cbl3dBQAIQK4wPELaQXeE8YBF3RSUHlx5KhH7wjSidgP+MFTgpM DmOp8sB/y/9sfB/zoZNF4QgFU3lWwnZDzpI2cZ5ZZHA/BQAC+DmLZOg+q8GzueueSYDc AWjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433307; x=1752038107; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UM/HZQdb2lcK8V7OkC2GVlA2nnGt1f60vmRpDyo8E4k=; b=sjQwh3jZ4UMMbQp4gvNBbkYDJko5Iegd2stdWP0GtGqvu+qyZp1dHJm5Z+l6rxIgE6 BWRHuGJrxaBUO5bZ+wluUhRrYpWqAWK7r/4MyxWaGdCzTosnOdMft3l/PmaxrgaDdq2C arT6NWhG3sqtaHfzImLcjUo16dE/z51QmNR0Vn5AmyaIkdBObxsaI06aZzSXHPODb3Lk 8YHnUlSArUqdojNX0nMsyziyu4AIbJlieibYnsRpRJ0NNoEOkhhh1jS9hBRRF88tZ3iF RJCNDm5uOnzfVqc/iq7sIyxR2NBrtHgRqqQKaLYhYLwaQNSRj5mUqBEvy7Sr7MIaspnk /j4A== X-Forwarded-Encrypted: i=1; AJvYcCWlX6uO8sa1Dhjvmkps4vbnk8Xp01b1DEC2hV7Yt7YvAP1sOP8DMblTo+cz3iBVRHLLiJ8FggL3dep8UGo=@vger.kernel.org X-Gm-Message-State: AOJu0Yz/hG8vypNIsnSW0QtQAh3mcLSIp6PBxvO641CbT/h1+m6PQoH5 Ur2lJc96UdeuGOUjwtzm8iXz2/lfaK9hZr8mHWvrejFMXfWNKlEW4dwU5NtFwWkwZIk= X-Gm-Gg: ASbGncte/2aT+yh5bh85H3+sZVT09WooSTHLWBhh5P1LOd76fCG3HO2VLlGnKy5MzBw 7WllgmeddqWK7g769U+5Do/SQNo+9MxY4/9Qp4oH3QIdXF+P+RcbUv0QYddFfcstulRoogTKQI6 k70GAOO3Ap2413wL0GS09kYcCMriQdYaj7QGyVttodi0wXlOm4k4MfU1nI4fN469bhG9MhINNqT vkFu/+9khFbAwGjQPbB/Tm2fgjLnBbO1tFkZyJqynX5qji6Nea5WyTCEW3/XjUFPxjrhO3L3SuM VqY/sbOnqtTmUGldst88M4XRhHyzRTxxHyL05zwVBjxYl5i9CuGRlz06jIGUukD2tNrb+AwcWak iUZuZ3d++pmbaiJFi X-Google-Smtp-Source: AGHT+IFWsFKRwiLkn4+0FNNQ8TzbjWmTlTzoQeJ28wANDKR6xWxbc9yBEEWGSmlqOiJ156vxO88y8g== X-Received: by 2002:a17:903:1988:b0:234:f580:a11 with SMTP id d9443c01a7336-23c6e4b9ba9mr22182535ad.19.1751433307410; Tue, 01 Jul 2025 22:15:07 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.14.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:15:06 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Conor Dooley Subject: [PATCH v7 08/24] dt-bindings: clock: Add RPMI clock service message proxy bindings Date: Wed, 2 Jul 2025 10:43:29 +0530 Message-ID: <20250702051345.1460497-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the RPMI clock service group based message proxy implemented by the SBI implementation (machine mode firmware or hypervisor). The RPMI clock service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Conor Dooley Signed-off-by: Anup Patel --- .../bindings/clock/riscv,rpmi-mpxy-clock.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy= -clock.yaml diff --git a/Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy-clock.= yaml b/Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy-clock.yaml new file mode 100644 index 000000000000..70ffc88d0110 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy-clock.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/riscv,rpmi-mpxy-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V RPMI clock service group based message proxy + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a + messaging protocol which is modular and extensible. The supervisor + software can send/receive RPMI messages via SBI MPXY extension [2] + or some dedicated supervisor-mode RPMI transport. + + The RPMI specification [1] defines clock service group for accessing + system clocks managed by a platform microcontroller. The SBI implementat= ion + (machine mode firmware or hypervisor) can implement an SBI MPXY channel + to allow RPMI clock service group access to the supervisor software. + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + References + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) + https://github.com/riscv-non-isa/riscv-rpmi/releases + + [2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + +properties: + compatible: + description: + Intended for use by the SBI implementation. + const: riscv,rpmi-mpxy-clock + + mboxes: + maxItems: 1 + description: + Mailbox channel of the underlying RPMI transport. + + riscv,sbi-mpxy-channel-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The SBI MPXY channel id to be used for providing RPMI access to + the supervisor software. + +required: + - compatible + - mboxes + - riscv,sbi-mpxy-channel-id + +additionalProperties: false + +examples: + - | + clock-controller { + compatible =3D "riscv,rpmi-mpxy-clock"; + mboxes =3D <&rpmi_shmem_mbox 0x8>; + riscv,sbi-mpxy-channel-id =3D <0x1000>; + }; +... --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8ED91F4613 for ; Wed, 2 Jul 2025 05:15:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433317; cv=none; b=lSbtDYTIrekBpWqwqi3CgMpGqccK33uvwXVPiSnzcoEI6z9HapRkLmSKuH/IeMb8xB6pYqn3rffst/tnOuZOOVLm5XGTZYFtoT3MqmVaS/2yuTm911eJy3IYsgXz4ggzuPzTpva7UyqmuvlQKoIONvNC3J3HdzZGbqqoBBqcgaY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433317; c=relaxed/simple; bh=gqZpMXPd6DL/+kfXUibwUL8SSmPMehps7IgssTY7RG4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pt7VSeJo9isZ+LS8bO9LrCTQZOOipDv1RPidSkYq8UCA45KX4IRWDvk9jHyX2dfiZnqWAMtQzBkcSzkXx0ltFAAQkMShxCwe3JVwB1kNjX/iUuv/4qVby1iMpBCQp/nWERHwzgra67gJUWMuCcKaJ7NA6+7/lqmlY3lljxSJfTU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=LfWGNmog; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="LfWGNmog" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-23694cec0feso63751955ad.2 for ; Tue, 01 Jul 2025 22:15:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433315; x=1752038115; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zMRC5c9xXUgo6eKv4jcoCHH6TENqo9cqAPQxW1Kbofo=; b=LfWGNmoghu3Bb7eWP2OvvY6iiv3SYTuDDT97/PY7/Iqj88voxp1xqd337LhPMSFzLc Bac6ZqEwr+aigw+NpuMb76b/s0MoLrXXBcUGs8WIgQzj0hp3TUOQuzfh8XwdYCt1XevP lhR3rtiozkdgONLTB1sMJX/dmYVZ8CG1VAiyO7MxufyRYNcglBZGfoFTANNL5eEl5H5P WohHTTHf5l6kowFaPSdnmQdg7A8Lb/TveV3Y4mbi6vauzodJ3AEYZm4LgYaCO7nN67yc 6KixI1TBL5PN/Qf9vJ4GC1iQoFqahqorC2NBIUkvMwWbgRtdMnVcDUADqm+LBBG+PFf6 Pl2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433315; x=1752038115; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zMRC5c9xXUgo6eKv4jcoCHH6TENqo9cqAPQxW1Kbofo=; b=tX5a1E7ILijZId1+ttL77kGcR54g6Pitm1hMsL4yEQwbiIXaKrxzhuGlfw6FWUf0Qs 2kJL+mDXuelp0lew2dI/pRs5JqxZXc3Qvsmp8QenfEKEUljmHH2lqDB0r55ImAnrWIMA eA3UCyRaKfW55cDYdV4P+iJR++Ica8nP9H+COBrYheSdLc15Elxg6lpTWHGeEKBRBnub yvTiof3gppfamz2e9szB4b80A6ZerDUmVPtrpSfSrZjZiq775j9pVrcO7xeqh7WBgt42 ulQBdXSVuexocMSaL3EErF4DtrJKyxOeEKAyzYmN+8pyC7vYunhsMsuxpAWFiYTPpzpO 7nzg== X-Forwarded-Encrypted: i=1; AJvYcCU82A+UHaIurx40a82RNUqi8mhG6SzHsyYY80ye1Z+po88TDKK5E+ulOc+2PmGYBFgY+OaWGHk0i6uY69U=@vger.kernel.org X-Gm-Message-State: AOJu0YyYUUn66HgDy2BSsqQAIY5HLWotdU+R+UPdrl0Hp+dKrpca3c+X YGKmjDSDFiGTgyjzlL0KxRh6eyUePSk4ddiV9NxxAPwYSLEnZUH3ei6w9TYk74hXr+0= X-Gm-Gg: ASbGncuLA5X+TYgms12quFVFSaSw5Ttzj1JUGIPPvEkgFAQ7ddSW8EHczaFXqQvOLPR UdU3AOzIdNvMmAF2StRH8LEWkTsztDYXhyLp2LbArfOl4P8TuMGbpv8mCv++vt6JHNClxwbBKK3 lC7BUgilxt6GMb4LiHxa7G4r3iBAWC7mcYfEYe9dtS9mDIk1iH/kju5rK215rFggl2Z580xckcR RTp9IhPAm0x+FSluXR8bxfg4ENHliXfknEr6COFGQGkFz88yBiq8vx4C6zngBbrkb8J1/ZO4Cag YJ19cLEqtYgtziNayDjcKvcATrkRySlIQgvoFpgYTdJhBRorrTiykmjYkCOf0Dx3NCd4Wtf5MSO 4EVtjbQUYqq7h143X X-Google-Smtp-Source: AGHT+IGMgggDnrWmfF/y7sLrYD7q8r2h5NmHNdzY2iKqbrQlHfhi5a/4jD0kNAv2DXNo1e1e/iX9VQ== X-Received: by 2002:a17:902:f792:b0:224:c46:d167 with SMTP id d9443c01a7336-23c6e501a07mr21381315ad.16.1751433315023; Tue, 01 Jul 2025 22:15:15 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:15:14 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Conor Dooley Subject: [PATCH v7 09/24] dt-bindings: clock: Add RPMI clock service controller bindings Date: Wed, 2 Jul 2025 10:43:30 +0530 Message-ID: <20250702051345.1460497-10-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the RPMI clock service group based controller for the supervisor software. The RPMI clock service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Conor Dooley Reviewed-by: Stephen Boyd Signed-off-by: Anup Patel --- .../bindings/clock/riscv,rpmi-clock.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/riscv,rpmi-cloc= k.yaml diff --git a/Documentation/devicetree/bindings/clock/riscv,rpmi-clock.yaml = b/Documentation/devicetree/bindings/clock/riscv,rpmi-clock.yaml new file mode 100644 index 000000000000..5d62bf8215c8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/riscv,rpmi-clock.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/riscv,rpmi-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V RPMI clock service group based clock controller + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a + messaging protocol which is modular and extensible. The supervisor + software can send/receive RPMI messages via SBI MPXY extension [2] + or some dedicated supervisor-mode RPMI transport. + + The RPMI specification [1] defines clock service group for accessing + system clocks managed by a platform microcontroller. The supervisor + software can access RPMI clock service group via SBI MPXY channel or + some dedicated supervisor-mode RPMI transport. + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + References + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) + https://github.com/riscv-non-isa/riscv-rpmi/releases + + [2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + +properties: + compatible: + description: + Intended for use by the supervisor software. + const: riscv,rpmi-clock + + mboxes: + maxItems: 1 + description: + Mailbox channel of the underlying RPMI transport or SBI message prox= y channel. + + "#clock-cells": + const: 1 + description: + Platform specific CLOCK_ID as defined by the RISC-V Platform Managem= ent + Interface (RPMI) specification. + +required: + - compatible + - mboxes + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller { + compatible =3D "riscv,rpmi-clock"; + mboxes =3D <&mpxy_mbox 0x1000 0x0>; + #clock-cells =3D <1>; + }; +... --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EF0F18B47E for ; Wed, 2 Jul 2025 05:15:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433326; cv=none; b=jnn++KkAFLUkcLmT7weYBSdhbCMFgl4bTj4w0b6joHGSBcsIMF8DNZMo/fYWfekUMwt7mPmgTjIkNKI6STULgWt7ZxcFtQjAQjBIsooqo11OMcd3Vctzu4Ay30WeAa8aIF0nusl3vlb+7f4zg23IZnHoNiUt9f+X+sDUv1ovUaM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433326; c=relaxed/simple; bh=Id6tbww0Iw0yYyfFd2j2dDL8Qqnp4veKQuDOdbKAY0A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Nyh14gWa/aDB3wwO2lB52CJ48n/i94vuly1AA6zQfh0DHp3tDM1p1i4E8avzVDYHSjjAH8ViybCQDeabHeox7BSisCqddPZLIlB6qXnMsv38d0DpbXAcsIoosjcTiAfnNn4vc7YcjHUFvsbtS7WDLZk2NwkNOZ23j0MKWNhER4Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=ZzvtVDz1; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="ZzvtVDz1" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-2363616a1a6so34845225ad.3 for ; Tue, 01 Jul 2025 22:15:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433323; x=1752038123; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5n+0atC0w16AKF/tFdiTeyKL33g6sh5mbVauGeHOlgc=; b=ZzvtVDz1q51Kj1/d87mufgAuoCku6tAs7g+TObS6wA8M72nWskoIn9jI3yOT7WWuFg 0hYjO1r4FChQhJbpFNwbVqwPFjRehGR1y8xN+3JlZCswZiaznp+Flw+SV62YgrpE72xR a7xdO37GH6Mlai6XbcKr1IWjrBismUhMl9FLoEMpTgX2ONpd4NJTNGffQ2aK3rN/SmFT +1bq7EctqRteS/+H0ThxT+UdY6Lk4Fym/+QKZXJXxM2tqLqA3wp5Ha7k9tdf2XxmQVGw jMUcIC/SeaKYZeparPIBvfd2hsi/0U6QD7aDEhfjWNUnnTrj3QGdJxrwIjIjqM+Wuq48 EFSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433323; x=1752038123; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5n+0atC0w16AKF/tFdiTeyKL33g6sh5mbVauGeHOlgc=; b=nj5BWT75Ng1mMt9GpAozDuQruCOFKWoNMNh1k7Ve0qOYOdbZtCXIrTFWwcYgDTofZE gEGK76dr3QONU10IgsKux9O8CNMPsZhNVDkGKf7bk4+tV57hGSvyo9CoAwq8mS2mTYcp nccKOKi4F/FZkyqqs+6ws4gUkXtWuozOnVwxtJBnnRZdjRIqvZbZnT6PFzA+ODO0pd0x d8jh8J8897KYSVaxe6J+FDigLI5r5ojS+9aUONpSaHVtnb6Ole7MRX6rzG+0AW+ts8T7 +hVJGx9EN1ZhatToor5NS4IVbo5o7tIDdxYBoBPy92N+HmRoSy8wp+odDfH+gzpJ51YQ Umvw== X-Forwarded-Encrypted: i=1; AJvYcCUzcmXh+lnMRuFPaOA7wqOC5urXMy98n6rhWTg6+KbZZZ5E0FuMyspYK7U9oLRmq391Q6R/lL9gH6JUIXM=@vger.kernel.org X-Gm-Message-State: AOJu0YycGpvOE05baYERdQycTxMHc/ZssKUGwIRb+Fyk1ha7c0tPhPRp Rs6ctZUlNeHw2AhJ3IocQkaJwguyVSvXTr6fScuStWyJni0IgI8UeNpj/8CnBccHsPU= X-Gm-Gg: ASbGnctDS24f8MZ8/0lFriqv1+9DTlDc0XUriYdHER0OVA2w3UeUhRJFjPEyngLEuM0 sn8yGE/5bzgWLGrwgFqJeCPzjIQinbjTpyQKVimtdWvBf5bNy320x2RO3iHIDzf2wZyDwQf+dJn WjteeoBk2FBcYea7PmvORSjxchP9LdYwiotyDJegX0BeWZkuKbo8qOgADjJAA7gLaSc5WSvZnxO 5RwYRyWXXJIjoTSRg4tK/7WumsHrR83ERYOsOC31mIvEpkxhKpUMKpV1vllgiAJ2ONC9qAVSY8r Qe2KxRZbcbKVtP4Ecl2S4zCpOPLGvk9yikT3QnQQiCCoqrNDtPFEwKhlTNuV1u001c1tOn+SpJ0 VtupHq5txfRk43cIr X-Google-Smtp-Source: AGHT+IE6ozAgGLAhH0L0DXt3uOj34dfovxyhl26dl0o/Tm0aCppWo70shnpeiTCw88Lyc0Udo2I1jQ== X-Received: by 2002:a17:903:198c:b0:237:ec18:ead7 with SMTP id d9443c01a7336-23c6e54fb4bmr21741635ad.24.1751433322620; Tue, 01 Jul 2025 22:15:22 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.15.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:15:22 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 10/24] clk: Add clock driver for the RISC-V RPMI clock service group Date: Wed, 2 Jul 2025 10:43:31 +0530 Message-ID: <20250702051345.1460497-11-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rahul Pathak The RPMI specification defines a clock service group which can be accessed via SBI MPXY extension or dedicated S-mode RPMI transport. Add mailbox client based clock driver for the RISC-V RPMI clock service group. Reviewed-by: Stephen Boyd Co-developed-by: Anup Patel Signed-off-by: Anup Patel Signed-off-by: Rahul Pathak Reviewed-by: Andy Shevchenko --- drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk-rpmi.c | 616 +++++++++++++++++++++ include/linux/mailbox/riscv-rpmi-message.h | 16 + include/linux/wordpart.h | 8 + 5 files changed, 649 insertions(+) create mode 100644 drivers/clk/clk-rpmi.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 19c1ed280fd7..2e385b146f8b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -493,6 +493,14 @@ config COMMON_CLK_SP7021 Not all features of the PLL are currently supported by the driver. =20 +config COMMON_CLK_RPMI + tristate "Clock driver based on RISC-V RPMI" + depends on MAILBOX + default RISCV + help + Support for clocks based on the clock service group defined by + the RISC-V platform management interface (RPMI) specification. + source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 42867cd37c33..48866e429a40 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_CLK_LS1028A_PLLDIG) +=3D clk-plldig.o obj-$(CONFIG_COMMON_CLK_PWM) +=3D clk-pwm.o obj-$(CONFIG_CLK_QORIQ) +=3D clk-qoriq.o obj-$(CONFIG_COMMON_CLK_RK808) +=3D clk-rk808.o +obj-$(CONFIG_COMMON_CLK_RPMI) +=3D clk-rpmi.o obj-$(CONFIG_COMMON_CLK_HI655X) +=3D clk-hi655x.o obj-$(CONFIG_COMMON_CLK_S2MPS11) +=3D clk-s2mps11.o obj-$(CONFIG_COMMON_CLK_SCMI) +=3D clk-scmi.o diff --git a/drivers/clk/clk-rpmi.c b/drivers/clk/clk-rpmi.c new file mode 100644 index 000000000000..e3ed130ffc0b --- /dev/null +++ b/drivers/clk/clk-rpmi.c @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RISC-V MPXY Based Clock Driver + * + * Copyright (C) 2025 Ventana Micro Systems Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RPMI_CLK_DISCRETE_MAX_NUM_RATES 16 +#define RPMI_CLK_NAME_LEN 16 + +#define to_rpmi_clk(clk) container_of(clk, struct rpmi_clk, hw) + +#define rpmi_clkrate_u64(hi, lo) make_u64_from_two_u32(hi, lo) + +enum rpmi_clk_config { + RPMI_CLK_DISABLE =3D 0, + RPMI_CLK_ENABLE =3D 1, + RPMI_CLK_CONFIG_MAX_IDX +}; + +enum rpmi_clk_type { + RPMI_CLK_DISCRETE =3D 0, + RPMI_CLK_LINEAR =3D 1, + RPMI_CLK_TYPE_MAX_IDX +}; + +struct rpmi_clk_context { + struct device *dev; + struct mbox_chan *chan; + struct mbox_client client; + u32 max_msg_data_size; +}; + +/* + * rpmi_clk_rates represents the rates format + * as specified by the RPMI specification. + * No other format conversion(eg. linear_range) is + * required to avoid to and fro conversion. + */ +union rpmi_clk_rates { + u64 discrete[RPMI_CLK_DISCRETE_MAX_NUM_RATES]; + struct { + u64 min; + u64 max; + u64 step; + } linear; +}; + +struct rpmi_clk { + struct rpmi_clk_context *context; + u32 id; + u32 num_rates; + u32 transition_latency; + enum rpmi_clk_type type; + union rpmi_clk_rates *rates; + char name[RPMI_CLK_NAME_LEN]; + struct clk_hw hw; +}; + +struct rpmi_clk_rate_discrete { + __le32 lo; + __le32 hi; +}; + +struct rpmi_clk_rate_linear { + __le32 min_lo; + __le32 min_hi; + __le32 max_lo; + __le32 max_hi; + __le32 step_lo; + __le32 step_hi; +}; + +struct rpmi_get_num_clocks_rx { + __le32 status; + __le32 num_clocks; +}; + +struct rpmi_get_attrs_tx { + __le32 clkid; +}; + +struct rpmi_get_attrs_rx { + __le32 status; + __le32 flags; + __le32 num_rates; + __le32 transition_latency; + char name[RPMI_CLK_NAME_LEN]; +}; + +struct rpmi_get_supp_rates_tx { + __le32 clkid; + __le32 clk_rate_idx; +}; + +struct rpmi_get_supp_rates_rx { + __le32 status; + __le32 flags; + __le32 remaining; + __le32 returned; + __le32 rates[]; +}; + +struct rpmi_get_rate_tx { + __le32 clkid; +}; + +struct rpmi_get_rate_rx { + __le32 status; + __le32 lo; + __le32 hi; +}; + +struct rpmi_set_rate_tx { + __le32 clkid; + __le32 flags; + __le32 lo; + __le32 hi; +}; + +struct rpmi_set_rate_rx { + __le32 status; +}; + +struct rpmi_set_config_tx { + __le32 clkid; + __le32 config; +}; + +struct rpmi_set_config_rx { + __le32 status; +}; + +static u32 rpmi_clk_get_num_clocks(struct rpmi_clk_context *context) +{ + struct rpmi_get_num_clocks_rx rx, *resp; + struct rpmi_mbox_message msg; + int ret; + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_GET_NUM_CLOCKS, + NULL, 0, &rx, sizeof(rx)); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return 0; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp || resp->status) + return 0; + + return le32_to_cpu(resp->num_clocks); +} + +static int rpmi_clk_get_attrs(u32 clkid, struct rpmi_clk *rpmi_clk) +{ + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_get_attrs_tx tx; + struct rpmi_get_attrs_rx rx, *resp; + u8 format; + int ret; + + tx.clkid =3D cpu_to_le32(clkid); + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_GET_ATTRIBUTES, + &tx, sizeof(tx), &rx, sizeof(rx)); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp) + return -EINVAL; + if (resp->status) + return rpmi_to_linux_error(le32_to_cpu(resp->status)); + + rpmi_clk->id =3D clkid; + rpmi_clk->num_rates =3D le32_to_cpu(resp->num_rates); + rpmi_clk->transition_latency =3D le32_to_cpu(resp->transition_latency); + strscpy(rpmi_clk->name, resp->name, RPMI_CLK_NAME_LEN); + + format =3D le32_to_cpu(resp->flags) & 3U; + if (format >=3D RPMI_CLK_TYPE_MAX_IDX) + return -EINVAL; + + rpmi_clk->type =3D format; + + return 0; +} + +static int rpmi_clk_get_supported_rates(u32 clkid, struct rpmi_clk *rpmi_c= lk) +{ + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_clk_rate_discrete *rate_discrete; + struct rpmi_clk_rate_linear *rate_linear; + struct rpmi_get_supp_rates_tx tx; + struct rpmi_get_supp_rates_rx *resp; + struct rpmi_mbox_message msg; + size_t clk_rate_idx; + int ret, rateidx, j; + + tx.clkid =3D cpu_to_le32(clkid); + tx.clk_rate_idx =3D 0; + + /* + * Make sure we allocate rx buffer sufficient to be accommodate all + * the rates sent in one RPMI message. + */ + struct rpmi_get_supp_rates_rx *rx __free(kfree) =3D + kzalloc(context->max_msg_data_size, GFP_KERNEL); + if (!rx) + return -ENOMEM; + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_GET_SUPPORTED_RATES, + &tx, sizeof(tx), rx, context->max_msg_data_size); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp) + return -EINVAL; + if (resp->status) + return rpmi_to_linux_error(le32_to_cpu(resp->status)); + if (!le32_to_cpu(resp->returned)) + return -EINVAL; + + if (rpmi_clk->type =3D=3D RPMI_CLK_DISCRETE) { + rate_discrete =3D (struct rpmi_clk_rate_discrete *)resp->rates; + + for (rateidx =3D 0; rateidx < le32_to_cpu(resp->returned); rateidx++) { + rpmi_clk->rates->discrete[rateidx] =3D + rpmi_clkrate_u64(le32_to_cpu(rate_discrete[rateidx].hi), + le32_to_cpu(rate_discrete[rateidx].lo)); + } + + /* + * Keep sending the request message until all + * the rates are received. + */ + clk_rate_idx =3D 0; + while (le32_to_cpu(resp->remaining)) { + clk_rate_idx +=3D le32_to_cpu(resp->returned); + tx.clk_rate_idx =3D cpu_to_le32(clk_rate_idx); + + rpmi_mbox_init_send_with_response(&msg, + RPMI_CLK_SRV_GET_SUPPORTED_RATES, + &tx, sizeof(tx), + rx, context->max_msg_data_size); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp) + return -EINVAL; + if (resp->status) + return rpmi_to_linux_error(le32_to_cpu(resp->status)); + if (!le32_to_cpu(resp->returned)) + return -EINVAL; + + for (j =3D 0; j < le32_to_cpu(resp->returned); j++) { + if (rateidx >=3D clk_rate_idx + le32_to_cpu(resp->returned)) + break; + rpmi_clk->rates->discrete[rateidx++] =3D + rpmi_clkrate_u64(le32_to_cpu(rate_discrete[j].hi), + le32_to_cpu(rate_discrete[j].lo)); + } + } + } else if (rpmi_clk->type =3D=3D RPMI_CLK_LINEAR) { + rate_linear =3D (struct rpmi_clk_rate_linear *)resp->rates; + + rpmi_clk->rates->linear.min =3D rpmi_clkrate_u64(le32_to_cpu(rate_linear= ->min_hi), + le32_to_cpu(rate_linear->min_lo)); + rpmi_clk->rates->linear.max =3D rpmi_clkrate_u64(le32_to_cpu(rate_linear= ->max_hi), + le32_to_cpu(rate_linear->max_lo)); + rpmi_clk->rates->linear.step =3D rpmi_clkrate_u64(le32_to_cpu(rate_linea= r->step_hi), + le32_to_cpu(rate_linear->step_lo)); + } + + return 0; +} + +static unsigned long rpmi_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_get_rate_tx tx; + struct rpmi_get_rate_rx rx, *resp; + int ret; + + tx.clkid =3D cpu_to_le32(rpmi_clk->id); + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_GET_RATE, + &tx, sizeof(tx), &rx, sizeof(rx)); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp) + return -EINVAL; + if (resp->status) + return rpmi_to_linux_error(le32_to_cpu(resp->status)); + + return rpmi_clkrate_u64(le32_to_cpu(resp->hi), le32_to_cpu(resp->lo)); +} + +static int rpmi_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + u64 fmin, fmax, ftmp; + + /* + * Keep the requested rate if the clock format + * is of discrete type. Let the platform which + * is actually controlling the clock handle that. + */ + if (rpmi_clk->type =3D=3D RPMI_CLK_DISCRETE) + return 0; + + fmin =3D rpmi_clk->rates->linear.min; + fmax =3D rpmi_clk->rates->linear.max; + + if (req->rate <=3D fmin) { + req->rate =3D fmin; + return 0; + } else if (req->rate >=3D fmax) { + req->rate =3D fmax; + return 0; + } + + ftmp =3D req->rate - fmin; + ftmp +=3D rpmi_clk->rates->linear.step - 1; + do_div(ftmp, rpmi_clk->rates->linear.step); + + req->rate =3D ftmp * rpmi_clk->rates->linear.step + fmin; + + return 0; +} + +static int rpmi_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_set_rate_tx tx; + struct rpmi_set_rate_rx rx, *resp; + int ret; + + tx.clkid =3D cpu_to_le32(rpmi_clk->id); + tx.lo =3D cpu_to_le32(lower_32_bits(rate)); + tx.hi =3D cpu_to_le32(upper_32_bits(rate)); + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_SET_RATE, + &tx, sizeof(tx), &rx, sizeof(rx)); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp) + return -EINVAL; + if (resp->status) + return rpmi_to_linux_error(le32_to_cpu(resp->status)); + + return 0; +} + +static int rpmi_clk_enable(struct clk_hw *hw) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_set_config_tx tx; + struct rpmi_set_config_rx rx, *resp; + int ret; + + tx.config =3D cpu_to_le32(RPMI_CLK_ENABLE); + tx.clkid =3D cpu_to_le32(rpmi_clk->id); + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_SET_CONFIG, + &tx, sizeof(tx), &rx, sizeof(rx)); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp) + return -EINVAL; + if (resp->status) + return rpmi_to_linux_error(le32_to_cpu(resp->status)); + + return 0; +} + +static void rpmi_clk_disable(struct clk_hw *hw) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_set_config_tx tx; + struct rpmi_set_config_rx rx; + + tx.config =3D cpu_to_le32(RPMI_CLK_DISABLE); + tx.clkid =3D cpu_to_le32(rpmi_clk->id); + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_SET_CONFIG, + &tx, sizeof(tx), &rx, sizeof(rx)); + + rpmi_mbox_send_message(context->chan, &msg); +} + +static const struct clk_ops rpmi_clk_ops =3D { + .recalc_rate =3D rpmi_clk_recalc_rate, + .determine_rate =3D rpmi_clk_determine_rate, + .set_rate =3D rpmi_clk_set_rate, + .prepare =3D rpmi_clk_enable, + .unprepare =3D rpmi_clk_disable, +}; + +static struct clk_hw *rpmi_clk_enumerate(struct rpmi_clk_context *context,= u32 clkid) +{ + struct device *dev =3D context->dev; + unsigned long min_rate, max_rate; + union rpmi_clk_rates *rates; + struct rpmi_clk *rpmi_clk; + struct clk_init_data init =3D {}; + struct clk_hw *clk_hw; + int ret; + + rates =3D devm_kzalloc(dev, sizeof(*rates), GFP_KERNEL); + if (!rates) + return ERR_PTR(-ENOMEM); + + rpmi_clk =3D devm_kzalloc(dev, sizeof(*rpmi_clk), GFP_KERNEL); + if (!rpmi_clk) + return ERR_PTR(-ENOMEM); + + rpmi_clk->context =3D context; + rpmi_clk->rates =3D rates; + + ret =3D rpmi_clk_get_attrs(clkid, rpmi_clk); + if (ret) + return dev_err_ptr_probe(dev, ret, + "Failed to get clk-%u attributes\n", + clkid); + + ret =3D rpmi_clk_get_supported_rates(clkid, rpmi_clk); + if (ret) + return dev_err_ptr_probe(dev, ret, + "Get supported rates failed for clk-%u\n", + clkid); + + init.flags =3D CLK_GET_RATE_NOCACHE; + init.num_parents =3D 0; + init.ops =3D &rpmi_clk_ops; + init.name =3D rpmi_clk->name; + clk_hw =3D &rpmi_clk->hw; + clk_hw->init =3D &init; + + ret =3D devm_clk_hw_register(dev, clk_hw); + if (ret) + return dev_err_ptr_probe(dev, ret, + "Unable to register clk-%u\n", + clkid); + + if (rpmi_clk->type =3D=3D RPMI_CLK_DISCRETE) { + min_rate =3D rpmi_clk->rates->discrete[0]; + max_rate =3D rpmi_clk->rates->discrete[rpmi_clk->num_rates - 1]; + } else { + min_rate =3D rpmi_clk->rates->linear.min; + max_rate =3D rpmi_clk->rates->linear.max; + } + + clk_hw_set_rate_range(clk_hw, min_rate, max_rate); + + return clk_hw; +} + +static void rpmi_clk_mbox_chan_release(void *data) +{ + struct mbox_chan *chan =3D data; + + mbox_free_channel(chan); +} + +static int rpmi_clk_probe(struct platform_device *pdev) +{ + int ret; + unsigned int num_clocks, i; + struct clk_hw_onecell_data *clk_data; + struct rpmi_clk_context *context; + struct rpmi_mbox_message msg; + struct clk_hw *hw_ptr; + struct device *dev =3D &pdev->dev; + + context =3D devm_kzalloc(dev, sizeof(*context), GFP_KERNEL); + if (!context) + return -ENOMEM; + context->dev =3D dev; + platform_set_drvdata(pdev, context); + + context->client.dev =3D context->dev; + context->client.rx_callback =3D NULL; + context->client.tx_block =3D false; + context->client.knows_txdone =3D true; + context->client.tx_tout =3D 0; + + context->chan =3D mbox_request_channel(&context->client, 0); + if (IS_ERR(context->chan)) + return PTR_ERR(context->chan); + + ret =3D devm_add_action_or_reset(dev, rpmi_clk_mbox_chan_release, context= ->chan); + if (ret) + return dev_err_probe(dev, ret, "Failed to add rpmi mbox channel cleanup\= n"); + + rpmi_mbox_init_get_attribute(&msg, RPMI_MBOX_ATTR_SPEC_VERSION); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return dev_err_probe(dev, ret, "Failed to get spec version\n"); + if (msg.attr.value < RPMI_MKVER(1, 0)) { + return dev_err_probe(dev, -EINVAL, + "msg protocol version mismatch, expected 0x%x, found 0x%x\n", + RPMI_MKVER(1, 0), msg.attr.value); + } + + rpmi_mbox_init_get_attribute(&msg, RPMI_MBOX_ATTR_SERVICEGROUP_ID); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return dev_err_probe(dev, ret, "Failed to get service group ID\n"); + if (msg.attr.value !=3D RPMI_SRVGRP_CLOCK) { + return dev_err_probe(dev, -EINVAL, + "service group match failed, expected 0x%x, found 0x%x\n", + RPMI_SRVGRP_CLOCK, msg.attr.value); + } + + rpmi_mbox_init_get_attribute(&msg, RPMI_MBOX_ATTR_SERVICEGROUP_VERSION); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return dev_err_probe(dev, ret, "Failed to get service group version\n"); + if (msg.attr.value < RPMI_MKVER(1, 0)) { + return dev_err_probe(dev, -EINVAL, + "service group version failed, expected 0x%x, found 0x%x\n", + RPMI_MKVER(1, 0), msg.attr.value); + } + + rpmi_mbox_init_get_attribute(&msg, RPMI_MBOX_ATTR_MAX_MSG_DATA_SIZE); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return dev_err_probe(dev, ret, "Failed to get max message data size\n"); + + context->max_msg_data_size =3D msg.attr.value; + num_clocks =3D rpmi_clk_get_num_clocks(context); + if (!num_clocks) + return dev_err_probe(dev, -ENODEV, "No clocks found\n"); + + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, num_clocks), + GFP_KERNEL); + if (!clk_data) + return dev_err_probe(dev, -ENOMEM, "No memory for clock data\n"); + clk_data->num =3D num_clocks; + + for (i =3D 0; i < clk_data->num; i++) { + hw_ptr =3D rpmi_clk_enumerate(context, i); + if (IS_ERR(hw_ptr)) { + return dev_err_probe(dev, PTR_ERR(hw_ptr), + "Failed to register clk-%d\n", i); + } + clk_data->hws[i] =3D hw_ptr; + } + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret) + return dev_err_probe(dev, ret, "Failed to register clock HW provider\n"); + + return 0; +} + +static const struct of_device_id rpmi_clk_of_match[] =3D { + { .compatible =3D "riscv,rpmi-clock" }, + { } +}; +MODULE_DEVICE_TABLE(of, rpmi_clk_of_match); + +static struct platform_driver rpmi_clk_driver =3D { + .driver =3D { + .name =3D "riscv-rpmi-clock", + .of_match_table =3D rpmi_clk_of_match, + }, + .probe =3D rpmi_clk_probe, +}; +module_platform_driver(rpmi_clk_driver); + +MODULE_AUTHOR("Rahul Pathak "); +MODULE_DESCRIPTION("Clock Driver based on RPMI message protocol"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mailbox/riscv-rpmi-message.h b/include/linux/mai= lbox/riscv-rpmi-message.h index 3f4c73529aa5..c90918dca367 100644 --- a/include/linux/mailbox/riscv-rpmi-message.h +++ b/include/linux/mailbox/riscv-rpmi-message.h @@ -90,6 +90,22 @@ static inline int rpmi_to_linux_error(int rpmi_error) } } =20 +/* RPMI service group IDs */ +#define RPMI_SRVGRP_CLOCK 0x00008 + +/* RPMI clock service IDs */ +enum rpmi_clock_service_id { + RPMI_CLK_SRV_ENABLE_NOTIFICATION =3D 0x01, + RPMI_CLK_SRV_GET_NUM_CLOCKS =3D 0x02, + RPMI_CLK_SRV_GET_ATTRIBUTES =3D 0x03, + RPMI_CLK_SRV_GET_SUPPORTED_RATES =3D 0x04, + RPMI_CLK_SRV_SET_CONFIG =3D 0x05, + RPMI_CLK_SRV_GET_CONFIG =3D 0x06, + RPMI_CLK_SRV_SET_RATE =3D 0x07, + RPMI_CLK_SRV_GET_RATE =3D 0x08, + RPMI_CLK_SRV_ID_MAX_COUNT +}; + /* RPMI Linux mailbox attribute IDs */ enum rpmi_mbox_attribute_id { RPMI_MBOX_ATTR_SPEC_VERSION, diff --git a/include/linux/wordpart.h b/include/linux/wordpart.h index ed8717730037..5cad9c244bf2 100644 --- a/include/linux/wordpart.h +++ b/include/linux/wordpart.h @@ -39,6 +39,14 @@ */ #define make_u32_from_two_u16(hi, lo) (((u32)(hi) << 16) | (u32)(lo)) =20 +/** + * make_u64_from_two_u32 - return u64 number by combining + * two u32 numbers. + * @hi: upper 32 bit number + * @lo: lower 32 bit number + */ +#define make_u64_from_two_u32(hi, lo) (((u64)(hi) << 32) | (u32)(lo)) + /** * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long va= lue * @x: value to repeat --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F489202C2B for ; Wed, 2 Jul 2025 05:15:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433332; cv=none; b=Og2kJup/5GIDz/RQofTYTHrDmJ5VUgjDCbt5LPKKOg55TKu0vYVy+TTbI6uIrBjdwgL25ASjKnAdE48XSKA0jJSepZkhqf840puvZGTDnPTidlI2/dRDwAfE+COeaWAaqn3X33wjTstgk4RZpIiPuMdgfSsKhLa37E0cT/JxHEw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433332; c=relaxed/simple; bh=sbelvMc++opfxCsxTvRuuhoDW5jErxOHLIiEYhi1zkg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R3VnJHDJN05XNlBgy1rHqdng2ZUY0rI/+jKhfzr94RGhNu5N7vkFJdTiCOS2Hq5m6K3kIA35KBsX0YemI1WRHj45aPXm/vUIq54xhWI2tDaKC5O1llih8JWlYRNl8j3oWiHsrcGKC1LP+CGN0IAH/+X7MEzyos8V+0U0GylDRR0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=Lsr5t3D4; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="Lsr5t3D4" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-23636167b30so37270845ad.1 for ; Tue, 01 Jul 2025 22:15:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433330; x=1752038130; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a9cEkN+1nA6DRTpT1SF2rNqhyyXGV6gcs+oqiG40Gi8=; b=Lsr5t3D40qQ1yumxUnR/nGd+nCXQCKgcMoaHusA5OcNH3o/PkOvqUZstalX15HZTtu ix/iUpfQopoHa/TfS3Qp6r3sefcs3iX6y5pmEs+tSLdc34dL/QkLeTpBDQf/qRbXietH GNsGVXNOld1YY43bOAyDmEt0j4vkwePFK5bWVzwFxdmWY+EFTsvCxYD9mC3xqRcHr1sb JoAMiM0CiEysMtY+13R4glVhln+Sa3z6tX4NNpmkFW2kivTV463OeKGo/92M3pzkPuKM IyURgHmHQuvyER9eYs/Szzv4kb4wv63bSYTOOzbsSEMzH04KSagOxpiF3B/jOMHxl74z M3dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433330; x=1752038130; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a9cEkN+1nA6DRTpT1SF2rNqhyyXGV6gcs+oqiG40Gi8=; b=QT3ou2VKiTpuYnOLY5apk+b/FRl+Sw2HYiLOxplfW59vCIlFXqpDFmgmsvBgOO3KJs ZNDvZ6T7LMwh7Srms0fW5ahtVHX4jkISI+f8esPeh2x2IKugAr5rZQj8u238VoLHv57g ytIt6vNYkxgKLFgQHsozhCwNwjmmvT6p7GlbFHGA2bphtW/rA93iBG9Ve5LlUsrLxExt Gxy6hfLjymIVoheaqi7dk5lcgHgTgA339lYKsxatZaFeWTX85niU6zNovUuo9cadR/kX ylRcxebcNty+4k8WYLhVHIFSw3yf9hMa6ekRXFWNYjG7lmE/JEExSHy7+IHWMpf3BscY A7DA== X-Forwarded-Encrypted: i=1; AJvYcCVfVlyFe7JgCIoUty8POUtwCS4RnG1eXitJrHE/GF6IFbei+JZOI71UBTmdLb61lGFRSMHdu5RFMDMx+hA=@vger.kernel.org X-Gm-Message-State: AOJu0YwW4fNsKSvo1IuxaY+Y1M4vYtCa6uSfNepLkku5VXQHFpsZW/N9 vUu2jPIYEl8Ww4OkEgvlGkXRiLOJXFlqG7i9en9Zh2giMAsOky/tUDE03044Uly4S40= X-Gm-Gg: ASbGnct9x80T/uRabwY2clU2o6RPbuSr0XAqMvbH7atIY/B2CJ5cwXJnEtvHsmxGvVF AGe6SqdSy5a5dgj0IEHc3M88T7GJrlPTwZF++95aqBWCcs6nGAOW1vT4GDa20ge85muEjYP6Obn hLR7FmhYzrLohOsLSeRztCT5hoxOp10ys4Sy20RBTQYNfU7Zh+fmnScXvMB/1+gCzmkzGCsNwry q6E7KDbk5bRL4Yn8NqYdiVwNfOocbTSmWZl/3dhKddnsLrSw3cD4HorkXfMpFqnZInPxj3TD/LZ vm2kQd2s34a5Nv1YAgFkJWYIh7ezVnhdWpr5KbFYC3983+4KPiJA2fNMUJIPU4YqqHGQGDd2sRe uRLVgsnH2vbrgPJaU X-Google-Smtp-Source: AGHT+IFkSVDLCtizadO6/SefSREM+o/lLAXhKCmmv4wW4SQI87DpfrniV0LznmsSNzm//rR3xEBV7g== X-Received: by 2002:a17:903:1983:b0:234:d7b2:2ab4 with SMTP id d9443c01a7336-23c6e4b9073mr19484855ad.17.1751433330503; Tue, 01 Jul 2025 22:15:30 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.15.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:15:30 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Atish Patra , Conor Dooley Subject: [PATCH v7 11/24] dt-bindings: Add RPMI system MSI message proxy bindings Date: Wed, 2 Jul 2025 10:43:32 +0530 Message-ID: <20250702051345.1460497-12-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the RPMI system MSI service group based message proxy implemented by the SBI implementation (machine mode firmware or hypervisor). The RPMI system MSI service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Atish Patra Reviewed-by: Conor Dooley Signed-off-by: Anup Patel --- .../riscv,rpmi-mpxy-system-msi.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,rpmi-mpxy-system-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,r= pmi-mpxy-system-msi.yaml b/Documentation/devicetree/bindings/interrupt-cont= roller/riscv,rpmi-mpxy-system-msi.yaml new file mode 100644 index 000000000000..1991f5c7446a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-mpx= y-system-msi.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,rpmi-mpxy-sy= stem-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V RPMI system MSI service group based message proxy + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a + messaging protocol which is modular and extensible. The supervisor + software can send/receive RPMI messages via SBI MPXY extension [2] + or some dedicated supervisor-mode RPMI transport. + + The RPMI specification [1] defines system MSI service group which + allow application processors to receive MSIs upon system events + such as P2A doorbell, graceful shutdown/reboot request, CPU hotplug + event, memory hotplug event, etc from the platform microcontroller. + The SBI implementation (machine mode firmware or hypervisor) can + implement an SBI MPXY channel to allow RPMI system MSI service + group access to the supervisor software. + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + References + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) + https://github.com/riscv-non-isa/riscv-rpmi/releases + + [2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + +properties: + compatible: + description: + Intended for use by the SBI implementation. + const: riscv,rpmi-mpxy-system-msi + + mboxes: + maxItems: 1 + description: + Mailbox channel of the underlying RPMI transport. + + riscv,sbi-mpxy-channel-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The SBI MPXY channel id to be used for providing RPMI access to + the supervisor software. + +required: + - compatible + - mboxes + - riscv,sbi-mpxy-channel-id + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible =3D "riscv,rpmi-mpxy-system-msi"; + mboxes =3D <&rpmi_shmem_mbox 0x2>; + riscv,sbi-mpxy-channel-id =3D <0x2000>; + }; +... --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30723202C2B for ; Wed, 2 Jul 2025 05:15:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433340; cv=none; b=uweEsCC3Vjql1wB0NzaRxY5xZkNBSsecw5PjNEh2t46PrEgQ6GbKR54Zod2/7B+QjnSbHqepWFlyOnbtJ6Ftq0NnQLpOWoY3wxS6dzk6MX3uEn7BkfqeeTX1qz1hxW61PEPsjnLLWxpjHA7oNLtUCr3ipjBlITstH3pQv3/AYZw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433340; c=relaxed/simple; bh=vvd5aEr1EHa2kYCEzZk7/ahZeLh22JQayJGJfQ0Amwk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ek4G6BtotYmoor2kjl1vZvmmUkaw3s4wQJ+vAD5TNSV0b/tiL/9SYksg5NxKvXFRcTi3gNTntOEDlwv0Qcf/eJWM6ulkZECbrY9MgPY2c2S/yM2L05bmQ1nWXe6oBJmrWgU82MFPgfJsiM8TpR/ghNWhgoCwh4iFsOT+tP5Q0NQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=deEezXLT; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="deEezXLT" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-2366e5e4dbaso62205665ad.1 for ; Tue, 01 Jul 2025 22:15:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433338; x=1752038138; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XIoG0/2CSPJ7QI1BAwRn3+gvtI7NC6tH67IoLVRWsu8=; b=deEezXLTMUc7jReGIsMaqikCJeoA+K9+Ii3ZlRcHzAvdaeg/mmcINdo7lQctiJZ3wr 1WmwoPPZlOV+maB8PecY/OnbmL+krofCpiRmDYu7EneqoHuo3ZHfbmbwuOl+BFKpPFty lsKLCQjTSa+BvIB767OHGFieY2ujl0C73M5T6mbYACuFHMwTiMsaRWwia2X/YdAu9DS3 4liqc0o/axsJb9ZSSPsq4ipC9O3syJ167sJHKdpjjsy1x+nnQAa+0xRRfwIUXh1YCtEf UNYwtb9hCF8ZStOQMjJc/qDNNw4Qf5+zHKP1QUbUDlL6b4PV59wDqVOmD/oIJ0qQlOqT wVKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433338; x=1752038138; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XIoG0/2CSPJ7QI1BAwRn3+gvtI7NC6tH67IoLVRWsu8=; b=JSGB9mQUeU3b89wrQ4JMFUVtB39RKa2Y90oTrMskXJ2pm/CO3rgCfobsDD84qPZxLG /j1GApR6kQFzCukeDOE/1e+Bp5v87PUJGAq2vOdGv5X3X3lg9ZIK/VBRNY0lAJjrcvRd 5xR3kpVPnDplPotZE+s4V8V2pbWnbFCeb90s/jOhNTzDi3YVwUDexEyxtBIyPxQlW7eX Gpwjulc1rEI8DGNDCRcaj0C5vOBhqO6XzqGw10l4RuNXz+TY3+8aOjpUN9hOHzMTUMJi YX0W8lb732qcqwC0MK3T4N80ffzXxnjDw5isBUyjP0JtNmBvdpKRMmw4EaK0DRbyvTsP bBjA== X-Forwarded-Encrypted: i=1; AJvYcCX/HDuBnj5gucvZThBWEJA9u7b7iRTf6U8o78oxgF15mMEV9sQVSUpqI62PNK+KeBfa2QS1jgsNbRlBVqM=@vger.kernel.org X-Gm-Message-State: AOJu0Ywbxwg1ojRzrW5Ke1uUMBbHrjXxMe7VtPcM1/y/R91U9YyGiUBS 2fkkqrlXGNa3Y8fwQc4VDpAQe/Z/M1Ns8Lh23pkDo0hzpFzvyu0Ik5ef9HNFWp7kfYI= X-Gm-Gg: ASbGncvfFmWDYREBLDQDx9El0g/URxn7+Z8TGqFZ95NIgmvDWA6+06q4HpO5TFb2a1w SShdnywj72eSF3/wxWBkt8uFMrWOmOVhgWmRRiO19l2LtL+QiRNg5t+h3O5eCswAbLT+7w8lLpt 2Kpdjd8WfUKCsOp7NlbK6b7LQ0CIdfVIk5cZ3ho+sCLpEsgynNShbVN/AUt7zVZ7YFMILOqkpzD pgcHPP7EZVomnNXbAqDlQkj3nnG5zyY13Bao1ODAtwnx9qRA5TTJF3jImL8C+lEKJxBUyOOJien sELONluy51B9AVmdM7APXRjdiL/8xbWu/4/XRelKDwPJxJ8210YKx1MdI1ONDtpVhQrJfoe3gNQ ArV6P0U3txC/Ng/U45pf5dWs/5XQ= X-Google-Smtp-Source: AGHT+IFGXbh9c2Bzrg+n0L83k/iOpiHjIddjs0COzT8LmyyeoGEyCI13QifJfOuXuLEn4svubKrHpw== X-Received: by 2002:a17:902:d4c5:b0:231:ad5a:fe9c with SMTP id d9443c01a7336-23c6e7eb70cmr19839295ad.15.1751433338295; Tue, 01 Jul 2025 22:15:38 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.15.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:15:37 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Atish Patra , Conor Dooley Subject: [PATCH v7 12/24] dt-bindings: Add RPMI system MSI interrupt controller bindings Date: Wed, 2 Jul 2025 10:43:33 +0530 Message-ID: <20250702051345.1460497-13-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the RPMI system MSI service group based interrupt controller for the supervisor software. The RPMI system MSI service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Atish Patra Reviewed-by: Conor Dooley Signed-off-by: Anup Patel --- .../riscv,rpmi-system-msi.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,rpmi-system-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,r= pmi-system-msi.yaml b/Documentation/devicetree/bindings/interrupt-controlle= r/riscv,rpmi-system-msi.yaml new file mode 100644 index 000000000000..b10a0532e586 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-sys= tem-msi.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,rpmi-system-= msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V RPMI system MSI service group based interrupt controller + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a + messaging protocol which is modular and extensible. The supervisor + software can send/receive RPMI messages via SBI MPXY extension [2] + or some dedicated supervisor-mode RPMI transport. + + The RPMI specification [1] defines system MSI service group which + allow application processors to receive MSIs upon system events + such as P2A doorbell, graceful shutdown/reboot request, CPU hotplug + event, memory hotplug event, etc from the platform microcontroller. + The supervisor software can access RPMI system MSI service group via + SBI MPXY channel or some dedicated supervisor-mode RPMI transport. + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + References + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) + https://github.com/riscv-non-isa/riscv-rpmi/releases + + [2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + description: + Intended for use by the supervisor software. + const: riscv,rpmi-system-msi + + mboxes: + maxItems: 1 + description: + Mailbox channel of the underlying RPMI transport or SBI message prox= y channel. + + msi-parent: true + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + +required: + - compatible + - mboxes + - msi-parent + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible =3D "riscv,rpmi-system-msi"; + mboxes =3D <&mpxy_mbox 0x2000 0x0>; + msi-parent =3D <&imsic_slevel>; + interrupt-controller; + #interrupt-cells =3D <1>; + }; +... --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D345D222596 for ; Wed, 2 Jul 2025 05:15:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433348; cv=none; b=g3ev6d6pORodexM3GlzX25qY1NCe2vn5Gt247orlnIFf0unTLgTRaEphoLDcYN6/uEuYqzEAq3SSCXGSRm5B86MChE8gv8I3XpJZTWutALEVjyTBYggipTQ1S0MN0SGBK2pccDaD/pZsEkHdm1e0IgYf3FLjOTX+XimStqAFQtw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433348; c=relaxed/simple; bh=Lt1dzy9yqik0Bteim+AtzsP8/JK538WOl/oxTcecFS4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KIj2+q9jsbPxYCTQdKz6rDc6MTgUPJR7kys3Ffr1QbPNSc0nSYo2myQCChHBNcKrgm195lnTKc4OilyBe8aG1hOmRPkberkE5glA55Zir+6WUTJmV+DHCm2JKrTumkHHaUW/nehR4Mh8jQdExZyTHCcSIpxHr57wASlamLV7N2g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=hYdos85D; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="hYdos85D" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-234fcadde3eso52619115ad.0 for ; Tue, 01 Jul 2025 22:15:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433346; x=1752038146; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=df2FyXzkxBTr99ltlso4sgxLOMKPyu9ZrXlLZcqz5Z0=; b=hYdos85Dlq9jKuS5Nxdq31t7Sv1cbRqKv0lO3/EUIblMwAWrc3tKzsppNhgD8aokZa 2TO4f4pY0LhWmyQTC1bPJLU5LyK/pXCP67IkXRT9P6A3ZmdZ/ZZXmMjkWmW6U5hxb6k1 sqfXZ1abLTluJrCdeYjHCdKFu2bHB5hYF8bAwVdZJIsVS10pMBzUUOhlE7xVMFXZiNQi BgGjGgChk6AsIyKZVH4gwO89T+nCKcBtR71AfYqgUtqKq3bolav2EZ8pq63Xdj3z8Rbt esd/nDgF8lB3PG2FrmHwrGLB91hv23aI3fjMEnzISsCqd+PgqjdtU9/mfretti3RkhiL 1KMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433346; x=1752038146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=df2FyXzkxBTr99ltlso4sgxLOMKPyu9ZrXlLZcqz5Z0=; b=a0iueOg0PCHDqD59Wyj+jA9h/Kfw9FxyQuESeKwKLP0BpHmA+3OmR4pll/buhRq79z 9A0OQihis69SnjbII8NaZRGda5rSxUMmoU5168P1Kd8SspHg+HkPhwKbteJCzJnDBanm tDfV8cGdkFKyMoYDvWSsNyO+duDisyA9K3qnxGsLOcLsZ10GEar5IXSFY8FX7kTDOAlc BSzu9A2yJSHUXdi90A3y4+PjGic5HZg7+QBNrv3xMoJPHOsoAa55XJnxu3P7vSLc5W5U gb5A1R3C4INfkoAWNX4cer8dk+uOkAJ0XgSXMyZO+NhAhXNmTpFLutNuREfWPg4dfunV +Jsw== X-Forwarded-Encrypted: i=1; AJvYcCWRKxs7YobTc9/+KGI5Ub5xLnvrMCCOQ02k+RhcnYvgH1EldMZ0o1Ne4cFx6jy0jGrghxCimlEGKviJQgI=@vger.kernel.org X-Gm-Message-State: AOJu0YxjNDMRh/5sMaTPy6FwgyZCHxT/KyoO4ytBA+SN6cqNC7mClgyB cN49kliQaq++zBBrZIdGnna/A+t4zQFsPedd5BC12BaAmfffwH8tEsCOJ0w6PHny2TI= X-Gm-Gg: ASbGnctfF/eW2ZKorCcBnWxH2qMWFxfip9G/nvS9Z8MgrPRwiboPqpP1Xwl87ct/Kqe /ANI3+kb8ulP3Pf6+1QrbaTECYh1E5nYVMFHyNbSqy50UmRTvo1K9/eazIZWzMi5m2puHe41mjF ggsg2im0g4VrVBauCIIF/fpkCU6HjSJL6u6NaMx011dD8FB/g8xjy/CXXDLKTFdpGCKXoj3UPBl EixotdEUSsZ8T7ayY2R7retOorWZMap0O83BJZCq3zam7T8kn1rVfLwtN2yGpxD/z3KLmKJHzjL 3FDDLjt+xBkTIOKINSUOpDuitPJAnMgrD1AXs6WffYgdSJI1UbuxCaKxYvshQdmdxNhmbNSGdyj MmqkLTUiFZJ/iebAr72ZXZSYzXFs= X-Google-Smtp-Source: AGHT+IHKXlJUNM5wrbDzFdMKDrEAtkb/8gAyGIxBsjnrD3QF0H8k7d9INC+T6MIOZ9N6zsBU82fkwA== X-Received: by 2002:a17:903:8cd:b0:235:e96b:191c with SMTP id d9443c01a7336-23c6e58ac8emr21059475ad.29.1751433345766; Tue, 01 Jul 2025 22:15:45 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.15.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:15:45 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 13/24] irqchip: Add driver for the RPMI system MSI service group Date: Wed, 2 Jul 2025 10:43:34 +0530 Message-ID: <20250702051345.1460497-14-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RPMI specification defines a system MSI service group which allows application processors to receive MSIs upon system events such as graceful shutdown/reboot request, CPU hotplug event, memory hotplug event, etc. Add an irqchip driver for the RISC-V RPMI system MSI service group to directly receive system MSIs in Linux kernel. Reviewed-by: Thomas Gleixner Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 7 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-rpmi-sysmsi.c | 283 +++++++++++++++++++++ include/linux/mailbox/riscv-rpmi-message.h | 13 + 4 files changed, 304 insertions(+) create mode 100644 drivers/irqchip/irq-riscv-rpmi-sysmsi.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 0d196e447142..96bf6aa55681 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -617,6 +617,13 @@ config RISCV_IMSIC select GENERIC_MSI_IRQ select IRQ_MSI_LIB =20 +config RISCV_RPMI_SYSMSI + bool + depends on MAILBOX + select IRQ_DOMAIN_HIERARCHY + select GENERIC_MSI_IRQ + default RISCV + config SIFIVE_PLIC bool depends on RISCV diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 23ca4959e6ce..4fd966aa78ab 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -103,6 +103,7 @@ obj-$(CONFIG_RISCV_INTC) +=3D irq-riscv-intc.o obj-$(CONFIG_RISCV_APLIC) +=3D irq-riscv-aplic-main.o irq-riscv-aplic-dir= ect.o obj-$(CONFIG_RISCV_APLIC_MSI) +=3D irq-riscv-aplic-msi.o obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o irq-riscv-imsic-platform.o +obj-$(CONFIG_RISCV_RPMI_SYSMSI) +=3D irq-riscv-rpmi-sysmsi.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_STARFIVE_JH8100_INTC) +=3D irq-starfive-jh8100-intc.o obj-$(CONFIG_THEAD_C900_ACLINT_SSWI) +=3D irq-thead-c900-aclint-sswi.o diff --git a/drivers/irqchip/irq-riscv-rpmi-sysmsi.c b/drivers/irqchip/irq-= riscv-rpmi-sysmsi.c new file mode 100644 index 000000000000..c42fceab71fa --- /dev/null +++ b/drivers/irqchip/irq-riscv-rpmi-sysmsi.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2025 Ventana Micro Systems Inc. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct rpmi_sysmsi_get_attrs_rx { + __le32 status; + __le32 sys_num_msi; + __le32 flag0; + __le32 flag1; +}; + +#define RPMI_SYSMSI_MSI_ATTRIBUTES_FLAG0_PREF_PRIV BIT(0) + +struct rpmi_sysmsi_set_msi_state_tx { + __le32 sys_msi_index; + __le32 sys_msi_state; +}; + +struct rpmi_sysmsi_set_msi_state_rx { + __le32 status; +}; + +#define RPMI_SYSMSI_MSI_STATE_ENABLE BIT(0) +#define RPMI_SYSMSI_MSI_STATE_PENDING BIT(1) + +struct rpmi_sysmsi_set_msi_target_tx { + __le32 sys_msi_index; + __le32 sys_msi_address_low; + __le32 sys_msi_address_high; + __le32 sys_msi_data; +}; + +struct rpmi_sysmsi_set_msi_target_rx { + __le32 status; +}; + +struct rpmi_sysmsi_priv { + struct device *dev; + struct mbox_client client; + struct mbox_chan *chan; + u32 nr_irqs; + u32 gsi_base; +}; + +static int rpmi_sysmsi_get_num_msi(struct rpmi_sysmsi_priv *priv) +{ + struct rpmi_sysmsi_get_attrs_rx rx; + struct rpmi_mbox_message msg; + int ret; + + rpmi_mbox_init_send_with_response(&msg, RPMI_SYSMSI_SRV_GET_ATTRIBUTES, + NULL, 0, &rx, sizeof(rx)); + ret =3D rpmi_mbox_send_message(priv->chan, &msg); + if (ret) + return ret; + if (rx.status) + return rpmi_to_linux_error(le32_to_cpu(rx.status)); + + return le32_to_cpu(rx.sys_num_msi); +} + +static int rpmi_sysmsi_set_msi_state(struct rpmi_sysmsi_priv *priv, + u32 sys_msi_index, u32 sys_msi_state) +{ + struct rpmi_sysmsi_set_msi_state_tx tx; + struct rpmi_sysmsi_set_msi_state_rx rx; + struct rpmi_mbox_message msg; + int ret; + + tx.sys_msi_index =3D cpu_to_le32(sys_msi_index); + tx.sys_msi_state =3D cpu_to_le32(sys_msi_state); + rpmi_mbox_init_send_with_response(&msg, RPMI_SYSMSI_SRV_SET_MSI_STATE, + &tx, sizeof(tx), &rx, sizeof(rx)); + ret =3D rpmi_mbox_send_message(priv->chan, &msg); + if (ret) + return ret; + if (rx.status) + return rpmi_to_linux_error(le32_to_cpu(rx.status)); + + return 0; +} + +static int rpmi_sysmsi_set_msi_target(struct rpmi_sysmsi_priv *priv, + u32 sys_msi_index, struct msi_msg *m) +{ + struct rpmi_sysmsi_set_msi_target_tx tx; + struct rpmi_sysmsi_set_msi_target_rx rx; + struct rpmi_mbox_message msg; + int ret; + + tx.sys_msi_index =3D cpu_to_le32(sys_msi_index); + tx.sys_msi_address_low =3D cpu_to_le32(m->address_lo); + tx.sys_msi_address_high =3D cpu_to_le32(m->address_hi); + tx.sys_msi_data =3D cpu_to_le32(m->data); + rpmi_mbox_init_send_with_response(&msg, RPMI_SYSMSI_SRV_SET_MSI_TARGET, + &tx, sizeof(tx), &rx, sizeof(rx)); + ret =3D rpmi_mbox_send_message(priv->chan, &msg); + if (ret) + return ret; + if (rx.status) + return rpmi_to_linux_error(le32_to_cpu(rx.status)); + + return 0; +} + +static void rpmi_sysmsi_irq_mask(struct irq_data *d) +{ + struct rpmi_sysmsi_priv *priv =3D irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + int ret; + + ret =3D rpmi_sysmsi_set_msi_state(priv, hwirq, 0); + if (ret) + dev_warn(priv->dev, "Failed to mask hwirq %lu (error %d)\n", hwirq, ret); + irq_chip_mask_parent(d); +} + +static void rpmi_sysmsi_irq_unmask(struct irq_data *d) +{ + struct rpmi_sysmsi_priv *priv =3D irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + int ret; + + irq_chip_unmask_parent(d); + ret =3D rpmi_sysmsi_set_msi_state(priv, hwirq, RPMI_SYSMSI_MSI_STATE_ENAB= LE); + if (ret) + dev_warn(priv->dev, "Failed to unmask hwirq %lu (error %d)\n", hwirq, re= t); +} + +static void rpmi_sysmsi_write_msg(struct irq_data *d, struct msi_msg *msg) +{ + struct rpmi_sysmsi_priv *priv =3D irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + int ret; + + /* For zeroed MSI, do nothing as of now */ + if (!msg->address_hi && !msg->address_lo && !msg->data) + return; + + ret =3D rpmi_sysmsi_set_msi_target(priv, hwirq, msg); + if (ret) + dev_warn(priv->dev, "Failed to set target for hwirq %lu (error %d)\n", h= wirq, ret); +} + +static void rpmi_sysmsi_set_desc(msi_alloc_info_t *arg, struct msi_desc *d= esc) +{ + arg->desc =3D desc; + arg->hwirq =3D desc->data.icookie.value; +} + +static int rpmi_sysmsi_translate(struct irq_domain *d, struct irq_fwspec *= fwspec, + unsigned long *hwirq, unsigned int *type) +{ + struct msi_domain_info *info =3D d->host_data; + struct rpmi_sysmsi_priv *priv =3D info->data; + + if (WARN_ON(fwspec->param_count < 1)) + return -EINVAL; + + /* For DT, gsi_base is always zero. */ + *hwirq =3D fwspec->param[0] - priv->gsi_base; + *type =3D IRQ_TYPE_NONE; + return 0; +} + +static const struct msi_domain_template rpmi_sysmsi_template =3D { + .chip =3D { + .name =3D "RPMI-SYSMSI", + .irq_mask =3D rpmi_sysmsi_irq_mask, + .irq_unmask =3D rpmi_sysmsi_irq_unmask, +#ifdef CONFIG_SMP + .irq_set_affinity =3D irq_chip_set_affinity_parent, +#endif + .irq_write_msi_msg =3D rpmi_sysmsi_write_msg, + .flags =3D IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, + }, + + .ops =3D { + .set_desc =3D rpmi_sysmsi_set_desc, + .msi_translate =3D rpmi_sysmsi_translate, + }, + + .info =3D { + .bus_token =3D DOMAIN_BUS_WIRED_TO_MSI, + .flags =3D MSI_FLAG_USE_DEV_FWNODE, + .handler =3D handle_simple_irq, + .handler_name =3D "simple", + }, +}; + +static int rpmi_sysmsi_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct rpmi_sysmsi_priv *priv; + int rc; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + priv->dev =3D dev; + + /* Setup mailbox client */ + priv->client.dev =3D priv->dev; + priv->client.rx_callback =3D NULL; + priv->client.tx_block =3D false; + priv->client.knows_txdone =3D true; + priv->client.tx_tout =3D 0; + + /* Request mailbox channel */ + priv->chan =3D mbox_request_channel(&priv->client, 0); + if (IS_ERR(priv->chan)) + return PTR_ERR(priv->chan); + + /* Get number of system MSIs */ + rc =3D rpmi_sysmsi_get_num_msi(priv); + if (rc < 1) { + mbox_free_channel(priv->chan); + if (rc) + return dev_err_probe(dev, rc, "Failed to get number of system MSIs\n"); + else + return dev_err_probe(dev, -ENODEV, "No system MSIs found\n"); + } + priv->nr_irqs =3D rc; + + /* Set the device MSI domain if not available */ + if (!dev_get_msi_domain(dev)) { + /* + * The device MSI domain for OF devices is only set at the + * time of populating/creating OF device. If the device MSI + * domain is discovered later after the OF device is created + * then we need to set it explicitly before using any platform + * MSI functions. + */ + if (dev_of_node(dev)) + of_msi_configure(dev, dev_of_node(dev)); + + if (!dev_get_msi_domain(dev)) { + mbox_free_channel(priv->chan); + return -EPROBE_DEFER; + } + } + + if (!msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, + &rpmi_sysmsi_template, + priv->nr_irqs, priv, priv)) { + mbox_free_channel(priv->chan); + return dev_err_probe(dev, -ENOMEM, "failed to create MSI irq domain\n"); + } + + dev_info(dev, "%u system MSIs registered\n", priv->nr_irqs); + return 0; +} + +static const struct of_device_id rpmi_sysmsi_match[] =3D { + { .compatible =3D "riscv,rpmi-system-msi" }, + {} +}; + +static struct platform_driver rpmi_sysmsi_driver =3D { + .driver =3D { + .name =3D "rpmi-sysmsi", + .of_match_table =3D rpmi_sysmsi_match, + }, + .probe =3D rpmi_sysmsi_probe, +}; +builtin_platform_driver(rpmi_sysmsi_driver); diff --git a/include/linux/mailbox/riscv-rpmi-message.h b/include/linux/mai= lbox/riscv-rpmi-message.h index c90918dca367..521a0c9b9b90 100644 --- a/include/linux/mailbox/riscv-rpmi-message.h +++ b/include/linux/mailbox/riscv-rpmi-message.h @@ -91,6 +91,7 @@ static inline int rpmi_to_linux_error(int rpmi_error) } =20 /* RPMI service group IDs */ +#define RPMI_SRVGRP_SYSTEM_MSI 0x00002 #define RPMI_SRVGRP_CLOCK 0x00008 =20 /* RPMI clock service IDs */ @@ -106,6 +107,18 @@ enum rpmi_clock_service_id { RPMI_CLK_SRV_ID_MAX_COUNT }; =20 +/* RPMI system MSI service IDs */ +enum rpmi_sysmsi_service_id { + RPMI_SYSMSI_SRV_ENABLE_NOTIFICATION =3D 0x01, + RPMI_SYSMSI_SRV_GET_ATTRIBUTES =3D 0x02, + RPMI_SYSMSI_SRV_GET_MSI_ATTRIBUTES =3D 0x03, + RPMI_SYSMSI_SRV_SET_MSI_STATE =3D 0x04, + RPMI_SYSMSI_SRV_GET_MSI_STATE =3D 0x05, + RPMI_SYSMSI_SRV_SET_MSI_TARGET =3D 0x06, + RPMI_SYSMSI_SRV_GET_MSI_TARGET =3D 0x07, + RPMI_SYSMSI_SRV_ID_MAX_COUNT +}; + /* RPMI Linux mailbox attribute IDs */ enum rpmi_mbox_attribute_id { RPMI_MBOX_ATTR_SPEC_VERSION, --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 148E9222596 for ; Wed, 2 Jul 2025 05:15:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433355; cv=none; b=cjp9dRPN81vl9ICvn6lbjNu95zZDV69rC91dxcAERqSpSUwgp0yDLfgCgCFHCh0EJ2P1ObFiLbD7yaKeoXM8FuIUepQjwzFNnZtQdM1fMEOd+GE+LbB0pIS2x1IkSErdfjDKWeciZ6nqaSEo9Us5P22395GS5s+PYpqqDDB4k7w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433355; c=relaxed/simple; bh=SBjQlH46dBB3U+TixQzZp78z+Lc9Dr3istOOhSNwHTo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y46l50ZMCN+2fNiLM1AU3LdWozIEwpb5VpBiYkgbCNvC9U2bnJvbatsh8/JqnHs2pjYeChcNeGMYTb6opAHC82G13guEJDTTS69Wo4DVWdk0lfaWwntrBkjXGIYus/F5IBZGN4pasrRn4j9Ew7V8+4CiQhPyb6vCQPAPMrc6Cw0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=JWsDJxY/; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="JWsDJxY/" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-23526264386so36821945ad.2 for ; Tue, 01 Jul 2025 22:15:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433353; x=1752038153; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t/zEjMktz2Q+rhDOD+xT+f8Y23symCCnfKy+4Q372EY=; b=JWsDJxY/6RZ+xJReravIEnJDJvvVkT9FPB3NbNviiVibrnf9a+IhalAicubSKGmXbt J2kqnorPJ92N3i2VM1j6Gy3oWovht3KObjPPUMKozL+DqQuEczXeovvxWMmwEN3G/iJz tV5ZA1YNhiopFPYvp6qniexikXrB37l5Wy+0CupH2FwMgPlFli29XQ9yjmG2fhHzZhBf C9rIYGpyKxRYxitZv1+dRr+gPwgqGtsuzqMFaD1zgRCODky6QNeE/B45frC4DuBjsN3h IbxpeaVhUXmyc8nx6YMnZ/6NLuu2Sr9o+EfkAQiAlpcqGG72LEO87fh383Cdgb4DNfQS kghw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433353; x=1752038153; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t/zEjMktz2Q+rhDOD+xT+f8Y23symCCnfKy+4Q372EY=; b=EZ/79pEefxO4bjr+3x64COkXqOyj33BU5139N3GiZU2T2U6lnABaDHfz3GRlWA9RWg Oo9NU55ulq7sRIgxL4zC1VSh5BdE+qCiJXir7lAi/MMUQUOrcZbFeyy1ujm1m/fZtt5y yb7tW9TmPP9Q5CxmRH5MfuAVN5/8o1g5TSgfosk7TKU6x6KXE9inxIbM48YhMxuY7N+0 Vkbu2r1PExfE8Ih8Bf/pYOkOBCip7VYlUrOZoV+OtuLrRAkb2BVbQIJ+E1Nfaz1p7ARI pJpwhdugpZ2ZUF04eLs2+u1EEJP/keAZJ3jptXc57cFF6RM3lcIvyFaMePZMcIYaUU8G uFmw== X-Forwarded-Encrypted: i=1; AJvYcCV1J8wEOunqfyHLQF2uiurbI7UThr/2T4Yt+MB08IY242UP7sq8vHEgmQ3bCgO+ugDh9BuOrN27OQR52XM=@vger.kernel.org X-Gm-Message-State: AOJu0YweebWV1XhuNuVwmhPbXG9fjicn8k74Edj46s7Zxzj6545Gb0PM /JnzGj/JwRhqtjU8Kgo9qrwvrzi17X/bnRSC5pISxkbpmCp3aLVVVM8d6VjtazPFIIs= X-Gm-Gg: ASbGncs98JL3MOHnnjdIpCWgUlyJ8E4W2edXTpN7kjjSNGPrbcK/iFInPQ0TWQFiWxr LL7HSdwRi9OLbNSlfudShVYcWHCSdz3fB81Gmspvya82TIOBWmSJNUD47yt2H162Gz3n5726bPD gkNMvfeazjRYCkQndpseCBoIhr0yCCwtC2VJo76jbv5oplRxilDS4CpOR2O+4y1pDIG+7LUp1tA yWkihkxgWBbC9Zrq6qLz/7J0WxSV89qnK6jEv6Tylu63hd5Ll94CAZCmeFkOTYjbD1NoA/PAeqZ TUzWKDCCDiS8HRp6McoC1Jp93ogea1WPjr7axtNSbZTLLWRz1jesJMrIE3hXQAleQuHaVjz876Q 009tT7BGvLgKtvG0/ X-Google-Smtp-Source: AGHT+IEOlCPfn91jehZz17KbPl2V65GbsvXkZwBM5VnlRUrlsareLdZdXrSGHc7tHPZeN4+C2VQsYQ== X-Received: by 2002:a17:902:e78d:b0:234:ba75:836 with SMTP id d9443c01a7336-23c6e4dbeb8mr15640355ad.7.1751433353221; Tue, 01 Jul 2025 22:15:53 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.15.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:15:52 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 14/24] ACPI: property: Refactor acpi_fwnode_get_reference_args() Date: Wed, 2 Jul 2025 10:43:35 +0530 Message-ID: <20250702051345.1460497-15-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L Currently acpi_fwnode_get_reference_args() calls the public function __acpi_node_get_property_reference() which ignores the nargs_prop parameter. To fix this, make __acpi_node_get_property_reference() to call the static acpi_fwnode_get_reference() so that callers of fwnode_get_reference_args() can still pass a valid property name to fetch the number of arguments. Signed-off-by: Sunil V L Signed-off-by: Anup Patel --- drivers/acpi/property.c | 101 ++++++++++++++++++++-------------------- 1 file changed, 50 insertions(+), 51 deletions(-) diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c index 436019d96027..d4863746fb11 100644 --- a/drivers/acpi/property.c +++ b/drivers/acpi/property.c @@ -882,45 +882,10 @@ static struct fwnode_handle *acpi_parse_string_ref(co= nst struct fwnode_handle *f return &dn->fwnode; } =20 -/** - * __acpi_node_get_property_reference - returns handle to the referenced o= bject - * @fwnode: Firmware node to get the property from - * @propname: Name of the property - * @index: Index of the reference to return - * @num_args: Maximum number of arguments after each reference - * @args: Location to store the returned reference with optional arguments - * (may be NULL) - * - * Find property with @name, verifify that it is a package containing at l= east - * one object reference and if so, store the ACPI device object pointer to= the - * target object in @args->adev. If the reference includes arguments, sto= re - * them in the @args->args[] array. - * - * If there's more than one reference in the property value package, @inde= x is - * used to select the one to return. - * - * It is possible to leave holes in the property value set like in the - * example below: - * - * Package () { - * "cs-gpios", - * Package () { - * ^GPIO, 19, 0, 0, - * ^GPIO, 20, 0, 0, - * 0, - * ^GPIO, 21, 0, 0, - * } - * } - * - * Calling this function with index %2 or index %3 return %-ENOENT. If the - * property does not contain any more values %-ENOENT is returned. The NULL - * entry must be single integer and preferably contain value %0. - * - * Return: %0 on success, negative error code on failure. - */ -int __acpi_node_get_property_reference(const struct fwnode_handle *fwnode, - const char *propname, size_t index, size_t num_args, - struct fwnode_reference_args *args) +static int acpi_fwnode_get_reference_args(const struct fwnode_handle *fwno= de, + const char *propname, const char *nargs_prop, + unsigned int args_count, unsigned int index, + struct fwnode_reference_args *args) { const union acpi_object *element, *end; const union acpi_object *obj; @@ -999,7 +964,7 @@ int __acpi_node_get_property_reference(const struct fwn= ode_handle *fwnode, =20 ret =3D acpi_get_ref_args(idx =3D=3D index ? args : NULL, acpi_fwnode_handle(device), - &element, end, num_args); + &element, end, args_count); if (ret < 0) return ret; =20 @@ -1017,7 +982,7 @@ int __acpi_node_get_property_reference(const struct fw= node_handle *fwnode, =20 ret =3D acpi_get_ref_args(idx =3D=3D index ? args : NULL, ref_fwnode, &element, end, - num_args); + args_count); if (ret < 0) return ret; =20 @@ -1039,6 +1004,50 @@ int __acpi_node_get_property_reference(const struct = fwnode_handle *fwnode, =20 return -ENOENT; } + +/** + * __acpi_node_get_property_reference - returns handle to the referenced o= bject + * @fwnode: Firmware node to get the property from + * @propname: Name of the property + * @index: Index of the reference to return + * @num_args: Maximum number of arguments after each reference + * @args: Location to store the returned reference with optional arguments + * (may be NULL) + * + * Find property with @name, verifify that it is a package containing at l= east + * one object reference and if so, store the ACPI device object pointer to= the + * target object in @args->adev. If the reference includes arguments, sto= re + * them in the @args->args[] array. + * + * If there's more than one reference in the property value package, @inde= x is + * used to select the one to return. + * + * It is possible to leave holes in the property value set like in the + * example below: + * + * Package () { + * "cs-gpios", + * Package () { + * ^GPIO, 19, 0, 0, + * ^GPIO, 20, 0, 0, + * 0, + * ^GPIO, 21, 0, 0, + * } + * } + * + * Calling this function with index %2 or index %3 return %-ENOENT. If the + * property does not contain any more values %-ENOENT is returned. The NULL + * entry must be single integer and preferably contain value %0. + * + * Return: %0 on success, negative error code on failure. + */ +int __acpi_node_get_property_reference(const struct fwnode_handle *fwnode, + const char *propname, size_t index, + size_t num_args, + struct fwnode_reference_args *args) +{ + return acpi_fwnode_get_reference_args(fwnode, propname, NULL, index, num_= args, args); +} EXPORT_SYMBOL_GPL(__acpi_node_get_property_reference); =20 static int acpi_data_prop_read_single(const struct acpi_device_data *data, @@ -1558,16 +1567,6 @@ acpi_fwnode_property_read_string_array(const struct = fwnode_handle *fwnode, val, nval); } =20 -static int -acpi_fwnode_get_reference_args(const struct fwnode_handle *fwnode, - const char *prop, const char *nargs_prop, - unsigned int args_count, unsigned int index, - struct fwnode_reference_args *args) -{ - return __acpi_node_get_property_reference(fwnode, prop, index, - args_count, args); -} - static const char *acpi_fwnode_get_name(const struct fwnode_handle *fwnode) { const struct acpi_device *adev; --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ACC421C19D for ; Wed, 2 Jul 2025 05:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433363; cv=none; b=ddAxnsL7yDg3Gux11/hYXXd+s5Ost57OKQ7G8ETr8TOhDCYuqMwc3XjIXp0mZ0QBTg5gqmplj8Q8Bd3rUEoPM9pyL4H+tI/qBYeKh7GdIbQJN7t+j/yGyZjhmU0H/9RURSqKE1avdSA1Cg/L6rROwTSImhfLPpa91YiGL5bh+1Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433363; c=relaxed/simple; bh=jN6vr49WydQekpKegVkjH3kRWbiat3b6Jw7xzzte404=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JwbMNVfdPKohQs8HylJQdsYr0iiIcJxwzzCBNltOGzgHshxmZnver7HFtwUVjxuhToeVSdA73PO8O9JQWK5jEuJOY580/DD/VvYu/fyQpXhMsIXLHmeuXRqTgQ3H5XeqJqztMxxDXhQ6QmXivRElz2axF8Lr05KwwJDMgDtoY7Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=TkeEvLIW; arc=none smtp.client-ip=209.85.214.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="TkeEvLIW" Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-237e6963f63so25525875ad.2 for ; Tue, 01 Jul 2025 22:16:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433361; x=1752038161; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QmlL9kMvvcYcWlU45z5MYmmVSDmE1amNKft2tyH29n8=; b=TkeEvLIWFDN+/Cx7PbRqqnWqGlFU9US+Q4PiaWrRD9Y76t41oG3Laeb507aBjoY0Ei sADyFMM2mrrlv3IK0NPUFJsgqekO15ClMFT0wW5U2lO/LV/wrudF4x8YbncksRcGkw4Z wzKhrzPifSPxhqex94PS5/bUtj0vk9zYC4k/aOq8yLo3iX9oOCnq/x2LWsqxme+83kyw lsPA99a0dLUvaA1sra0BRGmiKA3oWAChSuKmOh3QZpmRVsCdVO54gSWUR3c3TUYkOqN+ TPk4lyaQgKHIAgkuIW0HPmu7tQEDnrNv9oMba0HDWyE/qSSemVmEZYaAdgyyOISMi1tf qqQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433361; x=1752038161; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QmlL9kMvvcYcWlU45z5MYmmVSDmE1amNKft2tyH29n8=; b=De41xXDHPL814z9AkeBrQt/yTcwQs1oKHRhxwoDaxkocXljbwbPm/1dkp9+MNC85ct hB/liQ8hlZm69z5MLeqmWb9RyPlFWtzWuTE/4f7nhWcvAaURCVKzHninSyWh05JC+6gd cILD0uSH9VOJJRjjTNroT1Dwg/Et8oN6gNeRkFzwRSxC2uD6sBCukWkFebVQBKJ7lsrK TDLZXArDIljJHCw9VFol3E/V8pwT1nSj15ksmjU+YipfOJshbpgK7cSNxuH3ZyfYulqT jY3v9SKx4rc5Zlqw9Pt0kdt7LHZ1SHlnHNvk4vfK5ih9uh6CaD+VUxfl2L9HDspZgtqB yPXw== X-Forwarded-Encrypted: i=1; AJvYcCUPX5ck85LaF4nvZGg3i3ULjjzsSgAP7JBJqWizDP1XAt4VrTD+iTiQSHvFGjcynnpzrJ3jCnCkQFm8DUE=@vger.kernel.org X-Gm-Message-State: AOJu0Yzf1lFWQaRHz7UWmclbGpw7QcLNu7hDmJsMl8HTMRku+CqHKMCK iw7aYvAkXfe8heuIXcbzcmt26GhSkZmoamv/g/QMDjvDfS8F12OvC3gkBG2zBNLFXkY= X-Gm-Gg: ASbGnctnOdkCn5qTDNBUUK/aJ6ITbCpnJgwasH/KD8jTe7oNzQ96aUas/zBNNsSc4Ke cvlCi/lp/NQmbRNDj0FOUSX6L/K2Zq46T7n0jL5XaxsrlcPeew7viOx21sXYGaj62HCvrI/nWVO Le39MTRk3U23iBeLNYh/4dkdAF//hWoBhzdbkGJuNcWwBKYpG2AVGaPK9FYXnVPyCei2xMZm7RO qYTpud4QbHAuIoPBrJNUCn+6wmKIXoKOM61O6tOYQZtVmjBb6ZpHkSGXntl1I/S4u45RpmwX23I UDwytjspBSXYd1tjLgGIY2OPCnIAZDNrS5ZO1e+3UC/nVOEURbkUs0eJI6QmrfOPpw1+XZy6/b/ Y6LudycXSov8fXIvy X-Google-Smtp-Source: AGHT+IE1P7SGRwHhgK16MRfDAXrEX7DH1YLnpHg6sa/GNFGZg6KWOiAXLcWOV6zX2nV96zG+z8muGg== X-Received: by 2002:a17:903:3c47:b0:235:f143:9b07 with SMTP id d9443c01a7336-23c6e483a2fmr24735045ad.5.1751433360617; Tue, 01 Jul 2025 22:16:00 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.15.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:16:00 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 15/24] ACPI: property: Add support for cells property Date: Wed, 2 Jul 2025 10:43:36 +0530 Message-ID: <20250702051345.1460497-16-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L Currently, ACPI doesn't support cells property when fwnode_property_get_reference_args() is called. ACPI always expects the number of arguments to be passed. However, the above mentioned call being a common interface for OF and ACPI, it is better to have single calling convention which works for both. Hence, add support for cells property on the reference device to get the number of arguments dynamically. Signed-off-by: Sunil V L Signed-off-by: Anup Patel Reviewed-by: Andy Shevchenko --- drivers/acpi/property.c | 22 ++++++++++++++++++---- drivers/base/property.c | 2 +- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c index d4863746fb11..d08b0ea5c915 100644 --- a/drivers/acpi/property.c +++ b/drivers/acpi/property.c @@ -882,6 +882,17 @@ static struct fwnode_handle *acpi_parse_string_ref(con= st struct fwnode_handle *f return &dn->fwnode; } =20 +static unsigned int acpi_fwnode_get_args_count(const struct acpi_device *d= evice, + const char *nargs_prop) +{ + const union acpi_object *obj; + + if (acpi_dev_get_property(device, nargs_prop, ACPI_TYPE_INTEGER, &obj)) + return 0; + + return obj->integer.value; +} + static int acpi_fwnode_get_reference_args(const struct fwnode_handle *fwno= de, const char *propname, const char *nargs_prop, unsigned int args_count, unsigned int index, @@ -892,6 +903,7 @@ static int acpi_fwnode_get_reference_args(const struct = fwnode_handle *fwnode, const struct acpi_device_data *data; struct fwnode_handle *ref_fwnode; struct acpi_device *device; + unsigned int nargs_count; int ret, idx =3D 0; =20 data =3D acpi_device_data_of_node(fwnode); @@ -960,11 +972,12 @@ static int acpi_fwnode_get_reference_args(const struc= t fwnode_handle *fwnode, if (!device) return -EINVAL; =20 + nargs_count =3D acpi_fwnode_get_args_count(device, nargs_prop); element++; - ret =3D acpi_get_ref_args(idx =3D=3D index ? args : NULL, acpi_fwnode_handle(device), - &element, end, args_count); + &element, end, + nargs_count ? nargs_count : args_count); if (ret < 0) return ret; =20 @@ -978,11 +991,12 @@ static int acpi_fwnode_get_reference_args(const struc= t fwnode_handle *fwnode, if (!ref_fwnode) return -EINVAL; =20 + device =3D to_acpi_device_node(ref_fwnode); + nargs_count =3D acpi_fwnode_get_args_count(device, nargs_prop); element++; - ret =3D acpi_get_ref_args(idx =3D=3D index ? args : NULL, ref_fwnode, &element, end, - args_count); + nargs_count ? nargs_count : args_count); if (ret < 0) return ret; =20 diff --git a/drivers/base/property.c b/drivers/base/property.c index f626d5bbe806..6a63860579dd 100644 --- a/drivers/base/property.c +++ b/drivers/base/property.c @@ -578,7 +578,7 @@ EXPORT_SYMBOL_GPL(fwnode_property_match_property_string= ); * @prop: The name of the property * @nargs_prop: The name of the property telling the number of * arguments in the referred node. NULL if @nargs is known, - * otherwise @nargs is ignored. Only relevant on OF. + * otherwise @nargs is ignored. * @nargs: Number of arguments. Ignored if @nargs_prop is non-NULL. * @index: Index of the reference, from zero onwards. * @args: Result structure with reference and integer arguments. --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 102B622FE18 for ; Wed, 2 Jul 2025 05:16:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433370; cv=none; b=nVLgufFKVQWnwU7uzXkaESScsqtIju+XOb9EeMAWbpt7YCh0FP1sKwS+2Xpq6rqCcuI6BwMnws8aLyfVsYgFfQje1Z3orE+7fJ37GcnNs6yws/a9Eqox/zdiEwwdff6cggBmRQODq++d2iGSfbUG2cztq5/yiNLSEOPW+0wkXSE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433370; c=relaxed/simple; bh=vaT9fKqdkrP7eBvkYV5AtQjKTPo8A3kQSz0hOZrkoeM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Dxz1KDbF/EOJU5yQQXW3ZxU55u+uejxNJ0q+8QO55BHjYUscuVrW81KvjE0vUP8FlJY0ul6zBmra5ydLbJxDJXIhrVaUlM3gmCyl86bzuvi69n8UyF4PkGVZG1inBWUr9uMJYG/aLUTNhjg1Wd0gVbQB57SlMUqbVYf+hEKcZ5s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=oepCvIPh; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="oepCvIPh" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-237e6963f63so25526305ad.2 for ; Tue, 01 Jul 2025 22:16:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433368; x=1752038168; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PBceoBehx8BvgZH4kIrIZIQMdJgc3OIIxRIhQIQqZsc=; b=oepCvIPh+8/OnytSok5GnubT1nWHOdXXZ7LOkAVvKZWR9yL4hSOvdJ0KMX0V5paano WmM6ogESHX/1Z5ijmUpb8jAU76UYrgb/cteTSW8r5oP5+dm371bQqhmZncFoYsScWmMq zUYX60Nx9Mmhm5gj+X+39xuPbugYZtNlxOytdAHEHoGxaizpLax0SeGr3BnNAvQHcDDa 9iZ+B3CX33L3BV12tBq4ULdboxl9Fmg0WWq0+WSRZR7qEQ3bewrYogxHR6NhaFgPiXlU xT/aNhKy/MCB2BEMokVXagtHbZfUmmFFBdhDJfrTmYfELEPeVTYaeQIGSLgFCLej/dcW 7BBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433368; x=1752038168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PBceoBehx8BvgZH4kIrIZIQMdJgc3OIIxRIhQIQqZsc=; b=LhynJ7sSOiD5NrQG81fFgcaJ0fxmeURWCuvOUhPz9iFhHTzpEF4f1UChEMgpsi4PID HMrrYayNuKpX/LxAnPGTXqmishU/9IBfIvMK30hvvzutg3RkE+NlFWWmRQ51NO6Tap9M BQis2aseRz6R8oRtZGWvR3XSUbtGqkPvRdRy3YBm4j5+EzwhyfPMm2OE5f8jSWdAm2yM EE2CaSbFZt+K4LQQ7m5uw3uIUEeT0IsN4CtyodGoKOPlDZK0/Ug6yT4bCDEcEIlQy+bT /2R+Nt8kRCsqvDjCDmgB+OEK6XsQem9dMYUa8FlhdWZDSJaeNVY2HGXN7NWJu0cZQQOd dzEg== X-Forwarded-Encrypted: i=1; AJvYcCXNUpz+UHYDh2bRCKvOqGszogpUvZuXulDBbyLB4+agzTHWVTeUoOHNiL6lBuO2aD62pl6PBoxaIHUB/Pw=@vger.kernel.org X-Gm-Message-State: AOJu0YzGQKgX141pYYx0KtJFSj3kAMPTFlye/cnBpvb3KDcXiZhZgYIf gkv5iT5vej58eudpJpH9jcjLEZbxtewtN3U23OA//Rihq3lReQVFlf3ef0p+EMtiO070OZI9vAO YX7TP X-Gm-Gg: ASbGncvYoM+csyPViyLLxT4h0DuW+shxixp9Z0D+3XuoLhWWlf6eSSbR1+Ff/CGXNu/ y1LzsID64aBs1YsX/LKW/zWoDG5UQAP3JQAOAWToNnm2y44Uk+m+KLNm34wc1TH38o5RR86fqCd ZmZND3Pndc3+x4ZaD6a5/UP1dVzoV6kywU8v5TRxr6jcMyyz7iYeHbxfDE/xyUTfWUq6JbGHstJ fLi/gjVSZS6v6Ci2SOJjtf2tmZSNuv01VAaYyUjJHwuPFNhY8eXOKEyMOCzd2Pru9oqUbHxzREt jljzvl0YdXtpG2i0jNscoUkn90EZRWA/k9zcTH3V3JSC1lunrmnuyw+/q69v1S1yZ0idZEsfr6F 4TdtvqWlFmDIu4y3F X-Google-Smtp-Source: AGHT+IFKKOiOcB60DEsZKqmVfcXE0dhCOXPWFAp2kRuerlsj/aT4QarUNKrpH9hQuOyq/8oYcK2PvQ== X-Received: by 2002:a17:903:3c4d:b0:237:d486:706a with SMTP id d9443c01a7336-23c6e584257mr21721685ad.48.1751433368200; Tue, 01 Jul 2025 22:16:08 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:16:07 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Atish Patra , Anup Patel Subject: [PATCH v7 16/24] ACPI: scan: Update honor list for RPMI System MSI Date: Wed, 2 Jul 2025 10:43:37 +0530 Message-ID: <20250702051345.1460497-17-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L The RPMI System MSI interrupt controller (just like PLIC and APLIC) needs to probed prior to devices like GED which use interrupts provided by it. Also, it has dependency on the SBI MPXY mailbox device. Add HIDs of RPMI System MSI and SBI MPXY mailbox devices to the honor list so that those dependencies are handled. Reviewed-by: Atish Patra Signed-off-by: Sunil V L Signed-off-by: Anup Patel Acked-by: Rafael J. Wysocki Reviewed-by: Andy Shevchenko --- drivers/acpi/scan.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index fb1fe9f3b1a3..54181b03b345 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -858,6 +858,8 @@ static const char * const acpi_honor_dep_ids[] =3D { "INTC10CF", /* IVSC (MTL) driver must be loaded to allow i2c access to ca= mera sensors */ "RSCV0001", /* RISC-V PLIC */ "RSCV0002", /* RISC-V APLIC */ + "RSCV0005", /* RISC-V SBI MPXY MBOX */ + "RSCV0006", /* RISC-V RPMI SYSMSI */ "PNP0C0F", /* PCI Link Device */ NULL }; --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 825F5239E62 for ; Wed, 2 Jul 2025 05:16:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433378; cv=none; b=Q8+V4f6PtLJlNLFlMmGHG8zEl9ZmIBD/2uc1C+mKxkg2FqcFe1JECiXMvbtZWbhQkphQW/GaANfynSyjpbEgoyXfjf3apYjOrjDY12frpqg25/TY4OY2Fj3EAoNEveorUhz2XnZwk5vXwUxDxcoGidzS1UyVLAziDwifo5/tc8M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433378; c=relaxed/simple; bh=uLkW3DQcKIIgVHib4AKQIVSEPy4uT4MPjoilFNj5tRA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=p6hHIcySPpjJ2T/E76xLUd26sgv0tk2zNKi7MdcNrmCJ9OXVW03kvmUhG+G/VjXIvRhP+Q3G3PC3LNBYltiSk97jQJ4xLO0q3pc49EvZMcDwVSxph0QsXS9lbb6UBhCWv8CV7+X3mgKHv7XVu6fAR+YSEqzZKDyJg/tjsAUSAsg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=mLshOdYw; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="mLshOdYw" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-234b9dfb842so36876145ad.1 for ; Tue, 01 Jul 2025 22:16:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433376; x=1752038176; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yiu9LW4OQPcl48oQrH2DU+mLfm2FHbXqcRasNtW9C8A=; b=mLshOdYwRso9NYdA2xWmc5BHkiXVkNhdQRS7fkM+oi3HN9lYqr2zu+SU7N3RFUXsv7 6ixs635lpXrjRzRqmEGLVFAvMZYxRbbj9BnsG4/G52+rBkAwMedcv0iYG/S8r4uw3BGp OUaaVq7kS01vqrJJfNWDVrkhOV2F2ciyegq6PCPnDI8PbZS6aEYt3Ut5rNJ52eHvhi1/ Ia0j1DWBdlf+DBMsGVNyK0YGqBBmyMnrf51ZfVLtHmEMP225zyJRRLxmuy0xAPn3OAu+ xnLRVfArzUqmBP/G88cgclovYfLVBPVixhnrcpYvPXeClFjaiHKS6ZFp/YfqDN08lr3U JfzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433376; x=1752038176; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yiu9LW4OQPcl48oQrH2DU+mLfm2FHbXqcRasNtW9C8A=; b=BDVOjKrmMl6M6py7WK8/tDZa0q+ycnoXBOJA4YJDNahtnxsMs8rGArfAzut+elT5Mg rzbMmaIg2vtOqm2EMBtIcCNyp/iR1lNKToLqlx3eqdv42cyw0xh/G3QxRI8n7UPbf3up By3DEDSh2n0s8oIaXL/PaJuX35Ki9WbpuPTZFyhmSoWZkTSuqLo5rZ0vEvUhjOO0JBHX JC3mM4SBKRYHjRSTfVeBbgNipmwkBm0y2zj4GecCCfMyaV/zbK2+vZEbW6DYDGnmZJjk QOkAy8mWbLXCdqm72TbcwChY/6Wd7fSFv4Vly+3wLwMFU8Tl8r+LiTh+6qn+zK2BXTS2 /Hpg== X-Forwarded-Encrypted: i=1; AJvYcCW8+erdaOY95g3dd79qRuRqGAK8UDCxSju02gKTu4f8XFTBzAPigpyuUteMDnt3vHUvEnmqGaL1MziRIxE=@vger.kernel.org X-Gm-Message-State: AOJu0Ywp5OwEkkAzLnqfi0OmGHvW4zH48SnJyEVsqIWV0Z4sbaOQ2o65 cbTXgY1bLRG1tfXEUbOUyLyGO79nSWAtrhqHh0Apdl62ujeDgpl7d3WQ7lmB68xfiGM= X-Gm-Gg: ASbGncsU1ynNcRjdW+C9srNRofAU5TP4LJBluV+2Zxejae/FgOdZibDKR4wAnDRhFJq ugXR25HD3OH42bj8uoDi8eQ23apZtFL/blzTArOT2njqAC4ShV5khyRV4QiVgFCNpF4+GMtw0yH 7RjmEnnWjhM5RIjOdB1mCfWi0FJ0NszNErMPUASxcPnNhBDxu+7BIyG2VXevRYwgkI5fjSJG6SV FNXxz0VBCq4Sv1d0nGQ28lE86PhzPNzLpnBHFAd4WbkDGGe96HtwWC3F6BzXTItnnQHduvn3M8a eAgnfyzIhHt+AXXxrKihrGs2T/nH5XjDGaO/sR2jnauyF4zDRzygqWxQEvjAfAybo93RkGc1Vkb zf9RQpnIe5J8bjBo6 X-Google-Smtp-Source: AGHT+IHK7JJshpTCYWIRPYhBfujfdQF43fCmzueM9e8EwtFQkDR9S8tXHvcjhHdLfuN/8WzEAqudfQ== X-Received: by 2002:a17:903:948:b0:236:6f5f:cab4 with SMTP id d9443c01a7336-23c6e4d3578mr24923105ad.5.1751433375731; Tue, 01 Jul 2025 22:16:15 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.16.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:16:15 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 17/24] ACPI: RISC-V: Create interrupt controller list in sorted order Date: Wed, 2 Jul 2025 10:43:38 +0530 Message-ID: <20250702051345.1460497-18-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L Currently, the interrupt controller list is created without any order. Create the list sorted with the GSI base of the interrupt controllers. Signed-off-by: Sunil V L Signed-off-by: Anup Patel --- drivers/acpi/riscv/irq.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index cced960c2aef..33c073e2e71d 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -115,7 +115,7 @@ struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 = gsi) static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, = u32 nr_idcs, u32 id, u32 type) { - struct riscv_ext_intc_list *ext_intc_element; + struct riscv_ext_intc_list *ext_intc_element, *node; =20 ext_intc_element =3D kzalloc(sizeof(*ext_intc_element), GFP_KERNEL); if (!ext_intc_element) @@ -125,7 +125,12 @@ static int __init riscv_acpi_register_ext_intc(u32 gsi= _base, u32 nr_irqs, u32 nr ext_intc_element->nr_irqs =3D nr_irqs; ext_intc_element->nr_idcs =3D nr_idcs; ext_intc_element->id =3D id; - list_add_tail(&ext_intc_element->list, &ext_intc_list); + list_for_each_entry(node, &ext_intc_list, list) { + if (node->gsi_base < ext_intc_element->gsi_base) + break; + } + + list_add_tail(&ext_intc_element->list, &node->list); return 0; } =20 --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23A971EB5DB for ; Wed, 2 Jul 2025 05:16:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433385; cv=none; b=gDoBCkyeX+Ep46rho6dL0R17KDWMZNJZt56kNpTpm5C5ewfEJ4ml4MIBoEpoGRy7NU+fNK7V82WTaJ6dvYw6H+9AgyIJI6aXiiLEdlxINXOaF/d7nKssO58CNVPLGayMJQ/dqeiCZVTYIdnVi8nJjAcsPq6shivA7DiGxcGWIRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433385; c=relaxed/simple; bh=bDMVpDUTCKSQxIzYquuybqhsrFm52uIQJL3fLHSkHZc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YDHf32h4AJLDwg/mX7YSEaxZZvq5N755KV25IrckKNwp8C2jz4jPqOyF7c9zs2gc+YmLYydXH8mgQQEq21jEsbvix1n+lV6EnMt9DL66RIk+EeFf4jIfis+j9EbCXaP4z4PqzmC53CS1eXtM8R4amYSy478WMDzAGkfvtwyF/EU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=YecoEpnL; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="YecoEpnL" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-2350b1b9129so26384435ad.0 for ; Tue, 01 Jul 2025 22:16:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433383; x=1752038183; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P3TJh+HyLkyeQ1VqRyPxzf43XEd03uT1gCuO+kpCcOM=; b=YecoEpnLrkytMEHnkJWuucl5s/p76SZnKG/ov5Rtut0K+WitmUg3fYcgoXd8qG190F 6wD0J/i+hZmDqjLmHwiD9nCgq0lGxSUmv9Dbpu6ZEJDnK3W9Zb3OhvPOQZYUzU4F3npw FY1AJvDTSjPSOX6WQCmhpXZ1TEqLiHyVpkaGfqu5VkDOf0VwjRAGT7iEsdA5Qh5bxqp+ 3+Nlb+zyjWQWFveEClRqmKNlbwASw+g+bJVsmJvHR/B0rSuJcPDT2X4nSeVbshC2Twjt /iS1kZkqmMxOIdqySrKzbuYvp78V16YO3SBq/+UWM6d+rK17BwSDmBRDLeaoXh0yjJhs urcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433383; x=1752038183; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P3TJh+HyLkyeQ1VqRyPxzf43XEd03uT1gCuO+kpCcOM=; b=Y0Zr6kJ2tXxkE7jbOzpjQSbGX7JIRTlf0Fhbip68tYyr/CoCyuzaTZQ7hXput8cEua PVkdO1vudd42PSVEpcOL49zF+BGbkzvzymuPiTsQuE+FIZERUBxXqEiU+8+JMkePDBSD VveJNy4MsDkdu11chGh6KavnEAYAFFGUw2EH9Z3FqiRlKYyf0I4YKzfuufmS7o+gW465 uhx5QChq7RELldIDSrUeCd5OHbyJPmU/4rZDg1wOrWhnbP3Y8Lq3Q6uLK2tKaOHOGXsE cgbQzlmxG+Jv/euGPaYxFNdO4NN9psGnwpzm+vgJohxJMZ43lh0H9ptWZw3YP7zc/ZR1 eWPQ== X-Forwarded-Encrypted: i=1; AJvYcCU7yvVg+a1W7yUiKaCz0Kfh69IZM1JMJwlkrc5RAgKb4/eX0R1EhbgKdgL0Nic/clVYNVsaVq8T779Q9sM=@vger.kernel.org X-Gm-Message-State: AOJu0Yw1Yx8rbWcTvY3YPK3TlIxcdURB1yCcjrp9uo5qtL0VHKU4RaXj N7HdPdzxhYzwTf9FO3rJS1FRwvSjRbP/ZxJh7T4vbhPDUuzIPlXkZJJ2aslIFQBYsaM= X-Gm-Gg: ASbGnctXeCDeZXySkh9jsC2D0LYFX5rLej1qBNhIGwwq1qz14D0sK1yfZY/9KFbfsNO dIT3YX/8mWIIcngAarn60m9LGWTt7ru3utPOcCOM0oK7cCYsSLje0dRxdw4gpyCSWQ1DPGgA3W6 YnxiREfX1X3byQJYIVOsZ4V5Djh1hSHV/RA+q94KWqvpLojoBF2TTxdY/lz54COPQkwXOfj4gac a4JC77zmp9+iOXq0/qXl8Hyd/yRA0Lc9MhTKB1mNo8RDK/Wd0KferH2g3CxE9ij68gL1XycBgiS x0BSXBJSzJt6DBTwRVfu9KxkvcDv5bG9rX4CFmelSgTP6XOfztNylmys0CVEJzLq/a+5wxO7/Yc 6ydCT45qxFT/PH+HmYLLri3/0tWI= X-Google-Smtp-Source: AGHT+IGjcdQ5SCYBwX/q8Ua3m2HXtZ+rTtj1lRl52H5ZQqdaEzollbkuxBGMe/8i5xm2XRTqzzD/0w== X-Received: by 2002:a17:903:1b63:b0:235:2403:77c7 with SMTP id d9443c01a7336-23c6e5708bdmr18551065ad.37.1751433383171; Tue, 01 Jul 2025 22:16:23 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.16.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:16:22 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 18/24] ACPI: RISC-V: Add support to update gsi range Date: Wed, 2 Jul 2025 10:43:39 +0530 Message-ID: <20250702051345.1460497-19-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L Some RISC-V interrupt controllers like RPMI based system MSI interrupt controllers do not have MADT entry defined. These interrupt controllers exist only in the namespace. ACPI spec defines _GSB method to get the GSI base of the interrupt controller, However, there is no such standard method to get the GSI range. To support such interrupt controllers, set the GSI range of such interrupt controllers to non-overlapping range and provide API for interrupt controller driver to update it with proper value. Signed-off-by: Sunil V L Signed-off-by: Anup Patel --- arch/riscv/include/asm/irq.h | 5 +++++ drivers/acpi/riscv/irq.c | 38 ++++++++++++++++++++++++++++++++++-- 2 files changed, 41 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 7b038f3b7cb0..2caf049f09c8 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -40,6 +40,7 @@ unsigned long acpi_rintc_ext_parent_to_hartid(unsigned in= t plic_id, unsigned int unsigned int acpi_rintc_get_plic_nr_contexts(unsigned int plic_id); unsigned int acpi_rintc_get_plic_context(unsigned int plic_id, unsigned in= t ctxt_idx); int __init acpi_rintc_get_imsic_mmio_info(u32 index, struct resource *res); +int riscv_acpi_update_gsi_range(u32 gsi_base, u32 nr_irqs); =20 #else static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u3= 2 *gsi_base, @@ -74,6 +75,10 @@ static inline int __init acpi_rintc_get_imsic_mmio_info(= u32 index, struct resour return 0; } =20 +static inline int riscv_acpi_update_gsi_range(u32 gsi_base, u32 nr_irqs) +{ + return -ENODEV; +} #endif /* CONFIG_ACPI */ =20 #endif /* _ASM_RISCV_IRQ_H */ diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index 33c073e2e71d..cc1928422418 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -10,6 +10,8 @@ =20 #include "init.h" =20 +#define RISCV_ACPI_INTC_FLAG_PENDING BIT(0) + struct riscv_ext_intc_list { acpi_handle handle; u32 gsi_base; @@ -17,6 +19,7 @@ struct riscv_ext_intc_list { u32 nr_idcs; u32 id; u32 type; + u32 flag; struct list_head list; }; =20 @@ -69,6 +72,22 @@ static acpi_status riscv_acpi_update_gsi_handle(u32 gsi_= base, acpi_handle handle return AE_NOT_FOUND; } =20 +int riscv_acpi_update_gsi_range(u32 gsi_base, u32 nr_irqs) +{ + struct riscv_ext_intc_list *ext_intc_element; + + list_for_each_entry(ext_intc_element, &ext_intc_list, list) { + if (gsi_base =3D=3D ext_intc_element->gsi_base && + (ext_intc_element->flag & RISCV_ACPI_INTC_FLAG_PENDING)) { + ext_intc_element->nr_irqs =3D nr_irqs; + ext_intc_element->flag &=3D ~RISCV_ACPI_INTC_FLAG_PENDING; + return 0; + } + } + + return -ENODEV; +} + int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, u32 *id, u32 *nr_irqs, u32 *nr_idcs) { @@ -115,14 +134,22 @@ struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u3= 2 gsi) static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, = u32 nr_idcs, u32 id, u32 type) { - struct riscv_ext_intc_list *ext_intc_element, *node; + struct riscv_ext_intc_list *ext_intc_element, *node, *prev; =20 ext_intc_element =3D kzalloc(sizeof(*ext_intc_element), GFP_KERNEL); if (!ext_intc_element) return -ENOMEM; =20 ext_intc_element->gsi_base =3D gsi_base; - ext_intc_element->nr_irqs =3D nr_irqs; + + /* If nr_irqs is zero, indicate it in flag and set to max range possible = */ + if (nr_irqs) { + ext_intc_element->nr_irqs =3D nr_irqs; + } else { + ext_intc_element->flag |=3D RISCV_ACPI_INTC_FLAG_PENDING; + ext_intc_element->nr_irqs =3D U32_MAX - ext_intc_element->gsi_base; + } + ext_intc_element->nr_idcs =3D nr_idcs; ext_intc_element->id =3D id; list_for_each_entry(node, &ext_intc_list, list) { @@ -130,6 +157,13 @@ static int __init riscv_acpi_register_ext_intc(u32 gsi= _base, u32 nr_irqs, u32 nr break; } =20 + /* Adjust the previous node's GSI range if that has pending registration = */ + prev =3D list_prev_entry(node, list); + if (!list_entry_is_head(prev, &ext_intc_list, list)) { + if (prev->flag & RISCV_ACPI_INTC_FLAG_PENDING) + prev->nr_irqs =3D ext_intc_element->gsi_base - prev->gsi_base; + } + list_add_tail(&ext_intc_element->list, &node->list); return 0; } --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99DF31EB5DB for ; Wed, 2 Jul 2025 05:16:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433394; cv=none; b=I6Gx0r0abZwdwmqAkiy1A3YgO+LxuAkNgq0bKSARxVI57iQloOEqxKbcX29GTbCnR/w2a0v+cseqW8quOPEOrM7VdD/yLApFxhUeqBakL++WyecItCPiGd3B/nGE+5GdIh5R7zG8v9bKmdKruOVRHkOWab2FqUB85eE9h0yd0Xg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433394; c=relaxed/simple; bh=HmUGIQxKVHOETiXQmbQMVfvnbNgiP89D8IFlOG4Z2e8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LAltWzx8GfSnfac/6z+swGVwI6C8irn6qQcuuZLNLIOHZAGGs06hjJ7yDQ03kpulpJfSUvFziQwy8tlbujXC5dKNI7uyeBV45BFFM3BXTgIPPIx5pck5/TTPJpY8i3oDcX3KdE0ncT8PK07YxflrUe+zeSmdinQv9ASU4qgTGN4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=K3lU5Ep0; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="K3lU5Ep0" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-2350b1b9129so26385025ad.0 for ; Tue, 01 Jul 2025 22:16:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433391; x=1752038191; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R+ya0GtiFk/8ci1A3C7Dw+WSyLS2yytdeeB0s74FDG4=; b=K3lU5Ep0Y4F8NeuPHf4pkqkRimPzASxkbkyPhz9fzQrFPgbcbXShsl+y8NVck0vooV YA2xLDEj2ifdjA6Y9q4ha2LRYPIuiqbNDb7IDkhXWl7VlQw0bptDFs9VM9VtlHnrnw8M dmnC2BYAvsK+jLuGYry/m9sQ6ZtJ2uvkhkc6HIlRct/mOGRqo7cSA5pg5d2WeY3bYpwS O4EF4LztoRVRmqG83psrX3C3foc4SDJ8elf7/ASBHwxS1Z636enqfnOxff//a/6zEmYN /YWuJJHcfXY7kqDulbQJfzzjZ55fe4pTLT3S4cnb8l1/g6bS5nIj0D4G9Ev4sOUyLSyH hSeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433391; x=1752038191; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R+ya0GtiFk/8ci1A3C7Dw+WSyLS2yytdeeB0s74FDG4=; b=Rw71SeM5L/7kof/0yCxbAuHEdMsrLgc2MSGDZ4iM93IP4kvEPFRkZZlk+te0Hv4src /02Dl9igsPGeO5ovy643T5h8SKnD2MY6cfI1Ur1JN+oFu/voGMajXXN2rjsoUI7DWx1G hy/3+7HtgWj88D2LFi2ivPf4f4aArWG2XRqgX0vwzZpZB6loFvyh4i83OXqvglKW+/Tq cksSkbC4UAaYiMoD8lSKVtvCd/0+E5oANwaMh/krzPVbYyEVBdkr5X2qO4uPNEAoAJji U7jw0Sz7ihaaQpyvhALT2G/cpHyu7i/E8InXVaE4ZEuF5BT7xW6N6s2IUF/mHPy8UDMX r+GQ== X-Forwarded-Encrypted: i=1; AJvYcCWmFT6BX+ZNXbJ4dK8TWJSFYkgSlAIJMilFUzqKIFMRwqdVYRCgeNWNqIrj3hSZDuFI4igzHcaY0paQ0LU=@vger.kernel.org X-Gm-Message-State: AOJu0Ywieahe8JZ+1ZiH9LjWXpUw2x/HY2Fu8mR3DfC6z/QxsQW19gMM zfOn+dwuKTn7RAZTifmdkE9WERfkUljSSpEDP9hPlNdZAInsFc/oxrAvE+GCaD59qa0= X-Gm-Gg: ASbGncuuUBalmbBXCx5m501uSsvTeguXAWtekS9KYRF9FpiVre6NQ4A+u+J1M8Ycr0+ lYtlE0Rwr77vXOBHwVRtLkrXZG862lCIYN3qA8w+wiS/L/LDCUTZrwTCNXQ9exI4KUpiRISaQuT uETyeasn9s1F9yPADa+szFr012sC7+YzjLK3OL7dKBrbLI+38yEV/RWLr/ZQqg7S7G/RsY5Zpil +WTMArE33sAl7WJ0ITYSsAqCd0NZHDn+TZraqDIP+Ku6Oc3+DDr7olyXbfAh4nEC1El0YdCHvzi VmvwZyfVbvPWzncMdd53O6ObnrnS/IBavhbPt9P4cMGgBZbHqt9hSyzorl6YhN/aWtF1hwz/2Jw bu+5/7i95py/np6u5 X-Google-Smtp-Source: AGHT+IGVPhlwjhXki+/3hyU8U7wHE3TbWpzk5YrsdGI24+SP+ypvFn2VzK1niX3bMdBnop5rpgktYA== X-Received: by 2002:a17:903:3c6b:b0:234:9670:cc73 with SMTP id d9443c01a7336-23c6e490fc1mr24534815ad.5.1751433390748; Tue, 01 Jul 2025 22:16:30 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.16.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:16:30 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 19/24] ACPI: RISC-V: Add RPMI System MSI to GSI mapping Date: Wed, 2 Jul 2025 10:43:40 +0530 Message-ID: <20250702051345.1460497-20-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L The RPMI System MSI device will provide GSIs to downstream devices (such as GED) so add it to the RISC-V GSI to fwnode mapping. Signed-off-by: Sunil V L Signed-off-by: Anup Patel --- arch/riscv/include/asm/irq.h | 1 + drivers/acpi/riscv/irq.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 2caf049f09c8..9c9d22f5165e 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -30,6 +30,7 @@ enum riscv_irqchip_type { ACPI_RISCV_IRQCHIP_IMSIC =3D 0x01, ACPI_RISCV_IRQCHIP_PLIC =3D 0x02, ACPI_RISCV_IRQCHIP_APLIC =3D 0x03, + ACPI_RISCV_IRQCHIP_SMSI =3D 0x04, }; =20 int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index cc1928422418..d9a2154d6c6a 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -168,6 +168,33 @@ static int __init riscv_acpi_register_ext_intc(u32 gsi= _base, u32 nr_irqs, u32 nr return 0; } =20 +static acpi_status __init riscv_acpi_create_gsi_map_smsi(acpi_handle handl= e, u32 level, + void *context, void **return_value) +{ + acpi_status status; + u64 gbase; + + if (!acpi_has_method(handle, "_GSB")) { + acpi_handle_err(handle, "_GSB method not found\n"); + return AE_ERROR; + } + + status =3D acpi_evaluate_integer(handle, "_GSB", NULL, &gbase); + if (ACPI_FAILURE(status)) { + acpi_handle_err(handle, "failed to evaluate _GSB method\n"); + return status; + } + + riscv_acpi_register_ext_intc(gbase, 0, 0, 0, ACPI_RISCV_IRQCHIP_SMSI); + status =3D riscv_acpi_update_gsi_handle((u32)gbase, handle); + if (ACPI_FAILURE(status)) { + acpi_handle_err(handle, "failed to find the GSI mapping entry\n"); + return status; + } + + return AE_OK; +} + static acpi_status __init riscv_acpi_create_gsi_map(acpi_handle handle, u3= 2 level, void *context, void **return_value) { @@ -222,6 +249,9 @@ void __init riscv_acpi_init_gsi_mapping(void) =20 if (acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, riscv_acpi_aplic_parse_ma= dt, 0) > 0) acpi_get_devices("RSCV0002", riscv_acpi_create_gsi_map, NULL, NULL); + + /* Unlike PLIC/APLIC, SYSMSI doesn't have MADT */ + acpi_get_devices("RSCV0006", riscv_acpi_create_gsi_map_smsi, NULL, NULL); } =20 static acpi_handle riscv_acpi_get_gsi_handle(u32 gsi) --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF7C423ABB6 for ; Wed, 2 Jul 2025 05:16:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433400; cv=none; b=uQBPAfk40Dh/SywdTL34k7gQQJvgrA3V3mgJXHgm0V5YFgijkCBv7zFup+ThhzaYFE8H05Oa9szoA7MU/dEe+5GKSVFARmN4xrs83+FFoHSqX4e+PJweXi0bi7anxtxrW8PntzE8pHy6cjpuQTjqTSEnTWfzHdFN9Xvjaw9oVUQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433400; c=relaxed/simple; bh=bbsKQgQKotFffImznTiHFRZUkpn3l2AEmmz1a9sty/k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=k3k4SzYEGh3xNCkw6gs0O4lLSB8sU77sVcN2y1FizwGL3HmZ+9vgmsoNeim/fxvb2cDWy/1WVeQbqz6DHDakHwEoc+iXe7SFLcU6WvkBP+DXmh0UjkppjqwNT6CTOFbysfJSn1t6mvSpFk+7BYbAgyjOqW55DYlcMUcU43Xl7pA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=hBIMJ2Qx; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="hBIMJ2Qx" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-234d366e5f2so56024825ad.1 for ; Tue, 01 Jul 2025 22:16:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433398; x=1752038198; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qFaQ5Zs1hbK8MQOtKnNrpZ/cBeXTMcFHCuSD6j9WtSo=; b=hBIMJ2QxGvBn9LASwz6VN2AHYtgG3f1h+RAJXq50OgG/snVrBDiENXdK4ZvlzuX+k+ fKIRNe45LAHzrcFabnLUvcaXaDxAzGmhW6DWKe79W+8KiiEyHctLD8MxCK7Vp3xu3faO 1eSwFFlBnqOmH03Wj0mJ7F+JLWUTjYFchFFZ30nFBulWe6WMuDtI2nQfNqe4it7DJU2V O0K1sRs6tv+gpwDW1Pq/mdmChe/jGILGmBRgO08IvcmuWUjhbozAZL8IiZ2L15SwQ2Er JWOm1UIHk8/TJwxPtqV8NLiZgdJtMGiqE2CPcCdzMfNgsTI+hNaDIxZZEEsLvTocM2eD tb1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433398; x=1752038198; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qFaQ5Zs1hbK8MQOtKnNrpZ/cBeXTMcFHCuSD6j9WtSo=; b=KcyP3khshonrGY7euueezHTKuL9d0sQ8pxZDboEwXDQ5Zk7PmBwfJ7ygpver43xoDo 390DYBCtXb9R58dYHvQiAUfyfOgYNFJYpIUV3HaPjQvF3lzLZrwWY3lTUd9MOKfGkOBj HolDSMzG5OybIYkg9pgnSs0zxT9OQ9/MBxkglYyQAQ2aA6gnvJawYRf4JSPRfAZ2T5Dr f/40Yt8csNWV2XGpxHcJOk+ZO+GvMGL3qbpAO1DZ8TtkPbgiBauDcpsVQI+iu4VI30Rk mOSPkBSMXzZ6I7vvDxUUYvF9TruWVerpS4nnbQcoxd6pslmuOZwylcm+2gPNWNJvfxa4 3V8w== X-Forwarded-Encrypted: i=1; AJvYcCWY7PK7DiYfM33b6AxMITm5WPwXEFe7l7E88BlNJp5yhyQxkZPThzXK+rpA/WkghE8H75ZJaY6G3wkMIZ0=@vger.kernel.org X-Gm-Message-State: AOJu0YwSnXN2EPvsOrUtmwHgTs6Jqf7gFUnxYzIfKaFb7FuKrAGHgPET 6gTkXUyNUHRmLt9jlAyrESeQvK/zd60XcK/QjDxbZ926XRDV6b2zMoNDCS1myvuw5BE= X-Gm-Gg: ASbGncvmXUJXNhN+j640o7GA+y//hr7UgkSMXNPs/e+0MKRtmddpS4Qk6mm/nnHdRdW xGgpnVE+tFupCXa9nCUtkqzniDM15Ixcv68Kz/OeffgT1t9CYZLuKRyRaDjyhOU3vo4cY+T8Ui/ EwbF9i/yIO/4tH4oJdgzPiwJ3kfgGdsQu+bQ+au2ETGfGoK8gvOdOO4kcJNnpRh0VQywXGbGka5 SmMoLQZC7R8xamjAwfjLhxXmFaTvfZn1dAWmV/a3hfL9LoTTHBAx1YTP7Cfcsl5g+7IlyliCvEm 8TrMb52TnZJ93Q4GcCh2bDfeWEcslMrwSwBs5XTaTk2JluiUGl0KpUAlJxDXLEgWc6i93KrqLeL SQbyw0N6qk/0RG+ns X-Google-Smtp-Source: AGHT+IENCvcAnrrecQXBt5V9LFuZ+rQKh4OUv2G9tNtl1lHXMhnri6Hzogn+Hw60JHYcRZ/blVSc/g== X-Received: by 2002:a17:903:4b0c:b0:234:c549:da10 with SMTP id d9443c01a7336-23c6e5d6335mr17948045ad.47.1751433398116; Tue, 01 Jul 2025 22:16:38 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.16.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:16:37 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 20/24] irqchip/irq-riscv-imsic-early: Export imsic_acpi_get_fwnode() Date: Wed, 2 Jul 2025 10:43:41 +0530 Message-ID: <20250702051345.1460497-21-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L ACPI based loadable drivers which need MSIs will also need imsic_acpi_get_fwnode() to update the device MSI domain so export this function. Reviewed-by: Thomas Gleixner Signed-off-by: Sunil V L Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-imsic-early.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-= riscv-imsic-early.c index d9ae87808651..1dbc41d7fe80 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) "riscv-imsic: " fmt #include #include +#include #include #include #include @@ -215,6 +216,7 @@ struct fwnode_handle *imsic_acpi_get_fwnode(struct devi= ce *dev) { return imsic_acpi_fwnode; } +EXPORT_SYMBOL_GPL(imsic_acpi_get_fwnode); =20 static int __init imsic_early_acpi_init(union acpi_subtable_headers *heade= r, const unsigned long end) --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E1D823BD04 for ; Wed, 2 Jul 2025 05:16:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433407; cv=none; b=uoXundV6mcbnKcIg25lJNe1CBsKa/+0XdTvBiySAT9h+wZAkE9mbYKZgEh6+V0juA/7CCOg7g5hHOl37OrcRp8+fUEL/C09CMlS5G+tE8fNXiRuNisz13iMF4IEEdkgabqg6wAWKNYYZ5UwCX6KD2HcVqDAI9G0wF8kmaoVweMo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433407; c=relaxed/simple; bh=WWnAVv5sdX/U4PhLlvNmEa3n3L6K6Kq50t1ofY7W1Ak=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Hy7JzIE0SpnJQdMoHr9jMrORbekyg3MsFyUA8pERmCjZtAh16pPZF1+OFG6GnkSr/xgTRrYIGBv/xMyoRqqk4Sxo8NcP32b2KMYzbRyqYeEQbpslo/vYVrl18cld5fqc006R2fHCFt5Mdd1eeZW7ZTdigaaGhcZfK8KsJ+pTRe0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=DIw3K2f7; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="DIw3K2f7" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-23508d30142so49342195ad.0 for ; Tue, 01 Jul 2025 22:16:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433405; x=1752038205; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+V0Odgdog0meYxYnmF6ZJNtzVV8Khw6QA9VUe2JT1O4=; b=DIw3K2f7qx/Iyx0V+qKZbFJwWPNXV8P5tmOYgixn3frgKra7/70jEcX307v29IoilT Feo+qLPdNB5HEzXF4fGOMkCFIl1KNXOyJwo6NmpQiDEvF+Qt9XFM7Zx6t0ramVqT+9Hy IlMU1NmfPwP3oebRXEKF5jwrMY2SxIbI4nTR1dbNKGkw2bZ0x+o/X11cHW2bBKTtTRkB SCsse+Jpu9u+qF9HxCsehlB2TTb5w1UIN5S1n3dYB76Tl9rm7hKJN6NhO3bZVPuaJ+eR /fBDYhlGTNkyJwTGkc5tBeMaEXMAasKEIZ7udWW3c87hPSezGr0v4UFfXEguAAPd2yyD ZQnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433405; x=1752038205; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+V0Odgdog0meYxYnmF6ZJNtzVV8Khw6QA9VUe2JT1O4=; b=AeMnMuJOqVv2Yl6x5QR/xSF6aieeu/fgS1W31nrVtfpVuyKIyC0rj87oDdHv6c9i/e m8cxnofGhy074V4oOhWQHmYXANTVZVXc23tyBCQEj2AMpgLCsgcvQE6Gy9YS+16OT5ER ful/Xz3mx4RDkEHt2UcN5Z9f7sCkmKDuVpKoMS/O7UeZtMhEzkz3cpUYWAt398Z6a3RV IDAr9+Yj5cTQcrI/whVU3N/i6kYIKdm9R4ulxl4aRBo+3fRc69n23RNuXAxbh3K5W8yV i2iMBUDflDon8gCZqBklfdY7VLKqfqGyRLes27cI4VzmppBLmPeg5ojwOOD9JpBtCvUM /lNg== X-Forwarded-Encrypted: i=1; AJvYcCWgbDRNoc/VrtK9IbNzhVohBtA7otuCLA1tocb+SVnh/S5rV7UbIpfZhMCwvVz6Gi87Aqunwhz1KLrvs70=@vger.kernel.org X-Gm-Message-State: AOJu0Yz4fgpT0o+m24c8QAntzdK/HJSIU0TpKAtU3gX/0olHDdMDKf7p 4h2nAKPPNN5g5ozivruDQY9/baPXGtUX/Rbsh3kt+xWULVtLtYp1SpNJwI+qJ5HaYRs= X-Gm-Gg: ASbGncvrUcjyaKbs2X9QsIbHdMiRClUH1Ml1v6j8+Bl67zB9K/7SQG4HgrccaCosOrx iFdqUr09a150qBXKfbo58Ee1sEmX8q7HQFTI/EmXihwwVjlAch1ux5t9fHN3mbFwrNsE+3g3c3Q mZO+B2+i6bTRHZsIN0YJXL6+C4VlceT+9jUN/1npfbwIk0VMflqIv7CfTViak5cdXNs/Izqf2Tm WWzUTXqKkqE3dkV6QgzetNeW3s9vZP+YBilMQsCoT2UCQG4w2+e8maaYjigZI7VnlqFT5HOvQX+ blO15en++lg57hEyRwzArTSi4WRbRf/GhWI1qHSashf4bsZf1dzUyHMXOJFcJvoj24scs0pmlRR Z2C+75fgakXfHeKw5 X-Google-Smtp-Source: AGHT+IH3e0m3Z712B5FuScEtM+R3UhY2+EC/UOkyXFHE4lffL+PCS6CYNx/+xTtoNWCyksjFpU2g1g== X-Received: by 2002:a17:902:c94c:b0:235:ef67:b595 with SMTP id d9443c01a7336-23c6e56c276mr22583325ad.35.1751433405437; Tue, 01 Jul 2025 22:16:45 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:16:45 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 21/24] mailbox/riscv-sbi-mpxy: Add ACPI support Date: Wed, 2 Jul 2025 10:43:42 +0530 Message-ID: <20250702051345.1460497-22-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L Add ACPI support for the RISC-V SBI message proxy (MPXY) based mailbox driver. Signed-off-by: Sunil V L Signed-off-by: Anup Patel --- drivers/mailbox/riscv-sbi-mpxy-mbox.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/riscv-sbi-mpxy-mbox.c b/drivers/mailbox/riscv-= sbi-mpxy-mbox.c index 129710f947ae..deb269a9a844 100644 --- a/drivers/mailbox/riscv-sbi-mpxy-mbox.c +++ b/drivers/mailbox/riscv-sbi-mpxy-mbox.c @@ -5,9 +5,11 @@ * Copyright (C) 2025 Ventana Micro Systems Inc. */ =20 +#include #include #include #include +#include #include #include #include @@ -779,6 +781,7 @@ static int mpxy_mbox_probe(struct platform_device *pdev) u32 i, *channel_ids __free(kfree) =3D NULL; struct device *dev =3D &pdev->dev; struct mpxy_mbox_channel *mchan; + struct irq_domain *msi_domain; struct mpxy_mbox *mbox; int msi_idx, rc; =20 @@ -901,6 +904,8 @@ static int mpxy_mbox_probe(struct platform_device *pdev) =20 /* Set the MSI domain if not available */ if (!dev_get_msi_domain(dev)) { + struct fwnode_handle *fwnode =3D dev_fwnode(dev); + /* * The device MSI domain for OF devices is only set at the * time of populating/creating OF device. If the device MSI @@ -908,8 +913,13 @@ static int mpxy_mbox_probe(struct platform_device *pde= v) * then we need to set it explicitly before using any platform * MSI functions. */ - if (dev_of_node(dev)) + if (is_of_node(fwnode)) { of_msi_configure(dev, dev_of_node(dev)); + } else if (is_acpi_device_node(fwnode)) { + msi_domain =3D irq_find_matching_fwnode(imsic_acpi_get_fwnode(dev), + DOMAIN_BUS_PLATFORM_MSI); + dev_set_msi_domain(dev, msi_domain); + } } =20 /* Setup MSIs for mailbox (if required) */ @@ -954,6 +964,13 @@ static int mpxy_mbox_probe(struct platform_device *pde= v) return rc; } =20 +#ifdef CONFIG_ACPI + struct acpi_device *adev =3D ACPI_COMPANION(dev); + + if (adev) + acpi_dev_clear_dependencies(adev); +#endif + dev_info(dev, "mailbox registered with %d channels\n", mbox->channel_count); return 0; @@ -973,10 +990,17 @@ static const struct of_device_id mpxy_mbox_of_match[]= =3D { }; MODULE_DEVICE_TABLE(of, mpxy_mbox_of_match); =20 +static const struct acpi_device_id mpxy_mbox_acpi_match[] =3D { + { "RSCV0005" }, + {} +}; +MODULE_DEVICE_TABLE(acpi, mpxy_mbox_acpi_match); + static struct platform_driver mpxy_mbox_driver =3D { .driver =3D { .name =3D "riscv-sbi-mpxy-mbox", .of_match_table =3D mpxy_mbox_of_match, + .acpi_match_table =3D mpxy_mbox_acpi_match, }, .probe =3D mpxy_mbox_probe, .remove =3D mpxy_mbox_remove, --=20 2.43.0 From nobody Fri Dec 19 22:06:37 2025 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4629221F20 for ; Wed, 2 Jul 2025 05:16:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433415; cv=none; b=WlsBXh01T0x8c9775r95Ptu5/tpcz2IPCLeR1T1v+vCAELC/yq3LSmRDHr8E3CDyouG0ESin5/ysUsEQRp0a/gxG/rqUHtj2uMrdaDKTpGUYRoDMUqhLZdiAqn7+CQurOL4vbuDljMv2ZNLI/ugCGKNxPy9kwGVcc5gJbYtt/Do= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433415; c=relaxed/simple; bh=MnWssIe2gPHfcipP/eIFfuXpaV0J/C/5d3IRgfnAQHM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cpg6tFqY4lkbTvM+zBSJHkbSZ7ZvZqgl6eQX8buw79RsO93ImolaZXBRG0pK0HADcMaAgjbMIvgt8yarfLbswR/YGpY/kPnLTnGQOwlV4QNpT7lnRKi1xvvYWmNg3LD2poRXa3cRHT49wF6f8SeKbmNclypWca0uw7FrkAdzpXA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=VmV/HXWb; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="VmV/HXWb" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-2366e5e4dbaso62211705ad.1 for ; Tue, 01 Jul 2025 22:16:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433413; x=1752038213; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F4qfR8q3szE7n/ZgMiX3NXp6iFpiigvvy3GXc1Xt1a0=; b=VmV/HXWbgXKfhol/oezCExwtDqo8rz8f8/fOQyRbSDWyE3eCoUDcjykVIz9WVdvBm9 8s8Eje0kJ6oCZwZtBeqhFpbtapJjE3QHvjmmv2/bHBtbWWH+pQ4kDZHqZAwdsJrApwAx J9WRExciZ6/7bUpCjuSAejwzE3Nn80cg6G9Gx7CbuFMPk0UOCs9Ym+gjBNX7LY5l+ss6 tykg1iCyevJP7dCAoAW9mYPRAOFWn/wxp3jouytad0wUka8qCX8pNleiJEHiCSSnbN0K mJ3clnoQbzE9KhiC577HTsz2TLllDVz7pNqffsaiAYv8LFpn8r1vUzjzgQDvee/zV3e8 EHCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433413; x=1752038213; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F4qfR8q3szE7n/ZgMiX3NXp6iFpiigvvy3GXc1Xt1a0=; b=U+FfyN+sM2AohOsYgH+3MYG5xaPMnuq687FzzM5E4x0NOpO47PHzjmhv7DiZPoDY4J 9NhI56QKz2+lBNElPyYW0vcb8ISGZTGNVkV/5zxSYH5jXZAra4tnZ5gQqa7UWPWvxHp+ IrBuF9W2iV5Xg4a1zG8FJF4yCAr5pDlLr3Om4WuDCK4zEzdm6E4dvLDmRJpEG45o9ZaX 3iiKF3par6Q1xaIgEcwWtTLlngSYXXUI0K59Gzx93FlBSvJiik5vF0Ik//iN2VnA5zyG cEMBS1AfgzkzCi0lvPsVsl47gIEIrWIhwxldNaZXzDl4xUhx6vBwbuSNR02kKMDu5O3k Djgg== X-Forwarded-Encrypted: i=1; AJvYcCXMt5AzIgUB4AFBbJXJKDdoEtkNyMrXH2jF9OMhpPBcl2Tnxow40haDRypX8lEgQE6IppZTumXEQ5s7wRs=@vger.kernel.org X-Gm-Message-State: AOJu0Yw0Bxhzr81gbMDSTBEaa0Vs/TrtehZx2GiRHmIgxpOtTq+qzsIU wr+8evJ9b6qRg6K6GphAoPMDaLOtRql0ylPTN0nyn6h1I1COO/Z1ACAjuWATxd75R9k= X-Gm-Gg: ASbGncvoNQ53vXmFUKMl5//qpBaie7haPU3ATJhIfYSpirCJjHayGeCWXVJ3d/Vb9uh OV1aITQ1LEOJE6mJ2dAvbPCMCnkov/3OW28DdbDVCXM3U7Rwsg4r6FGVI7QmETZwBWXJb1/BAgG M5PQ/VdUnXa4dqzKrjymI73Oefgz75e73xLdX4lXgfiEY7IpNTU6LLFULkJKDUPPQACm5tPTWv8 FEBeL7nCLzVJM1xZghiL4RY0Xh2jMAV3jbIU1z1JYelY3NzAnLFYbkwB68prjtUDZnO5xsUY0xL TwlwhgHKYF8y6hPf8A3F6SZWU8hnN3UqWvwmpNnva2SF3OvYZYZFJBF6UMFSINpFQlo/4zBrG3s bTYpPFdfqVgKWjozniTUt4/52Ghw= X-Google-Smtp-Source: AGHT+IEB3xOr/KqlSjqwIoxg7iMcYneYBHYIFdD/yKkygLO37mz3QttZMjHHl/DW5Dvd44FsOdfqIA== X-Received: by 2002:a17:902:f542:b0:235:e1e4:edb0 with SMTP id d9443c01a7336-23c6e83ea60mr21119575ad.22.1751433412835; Tue, 01 Jul 2025 22:16:52 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.16.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:16:52 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 22/24] irqchip/riscv-rpmi-sysmsi: Add ACPI support Date: Wed, 2 Jul 2025 10:43:43 +0530 Message-ID: <20250702051345.1460497-23-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L Add ACPI support for the RISC-V RPMI system MSI based irqchip driver. Reviewed-by: Thomas Gleixner Signed-off-by: Sunil V L Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-riscv-rpmi-sysmsi.c | 47 +++++++++++++++++++++++-- 2 files changed, 45 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 96bf6aa55681..dfa8cc0e23dd 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -619,7 +619,7 @@ config RISCV_IMSIC =20 config RISCV_RPMI_SYSMSI bool - depends on MAILBOX + depends on RISCV && MAILBOX select IRQ_DOMAIN_HIERARCHY select GENERIC_MSI_IRQ default RISCV diff --git a/drivers/irqchip/irq-riscv-rpmi-sysmsi.c b/drivers/irqchip/irq-= riscv-rpmi-sysmsi.c index c42fceab71fa..6b64a93d3c87 100644 --- a/drivers/irqchip/irq-riscv-rpmi-sysmsi.c +++ b/drivers/irqchip/irq-riscv-rpmi-sysmsi.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright (C) 2025 Ventana Micro Systems Inc. */ =20 +#include #include #include #include @@ -9,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -209,6 +211,8 @@ static int rpmi_sysmsi_probe(struct platform_device *pd= ev) { struct device *dev =3D &pdev->dev; struct rpmi_sysmsi_priv *priv; + struct fwnode_handle *fwnode; + u32 id; int rc; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -239,6 +243,22 @@ static int rpmi_sysmsi_probe(struct platform_device *p= dev) } priv->nr_irqs =3D rc; =20 + fwnode =3D dev_fwnode(dev); + if (is_acpi_node(fwnode)) { + u32 nr_irqs; + + rc =3D riscv_acpi_get_gsi_info(fwnode, &priv->gsi_base, &id, + &nr_irqs, NULL); + if (rc) { + dev_err(dev, "failed to find GSI mapping\n"); + return rc; + } + + /* Update with actual GSI range */ + if (nr_irqs !=3D priv->nr_irqs) + riscv_acpi_update_gsi_range(priv->gsi_base, priv->nr_irqs); + } + /* Set the device MSI domain if not available */ if (!dev_get_msi_domain(dev)) { /* @@ -248,8 +268,15 @@ static int rpmi_sysmsi_probe(struct platform_device *p= dev) * then we need to set it explicitly before using any platform * MSI functions. */ - if (dev_of_node(dev)) + if (is_of_node(fwnode)) { of_msi_configure(dev, dev_of_node(dev)); + } else if (is_acpi_device_node(fwnode)) { + struct irq_domain *msi_domain; + + msi_domain =3D irq_find_matching_fwnode(imsic_acpi_get_fwnode(dev), + DOMAIN_BUS_PLATFORM_MSI); + dev_set_msi_domain(dev, msi_domain); + } =20 if (!dev_get_msi_domain(dev)) { mbox_free_channel(priv->chan); @@ -264,6 +291,13 @@ static int rpmi_sysmsi_probe(struct platform_device *p= dev) return dev_err_probe(dev, -ENOMEM, "failed to create MSI irq domain\n"); } =20 +#ifdef CONFIG_ACPI + struct acpi_device *adev =3D ACPI_COMPANION(dev); + + if (adev) + acpi_dev_clear_dependencies(adev); +#endif + dev_info(dev, "%u system MSIs registered\n", priv->nr_irqs); return 0; } @@ -273,10 +307,17 @@ static const struct of_device_id rpmi_sysmsi_match[] = =3D { {} }; =20 +static const struct acpi_device_id acpi_rpmi_sysmsi_match[] =3D { + { "RSCV0006" }, + {} +}; +MODULE_DEVICE_TABLE(acpi, acpi_rpmi_sysmsi_match); + static struct platform_driver rpmi_sysmsi_driver =3D { .driver =3D { - .name =3D "rpmi-sysmsi", - .of_match_table =3D rpmi_sysmsi_match, + .name =3D "rpmi-sysmsi", + .of_match_table =3D rpmi_sysmsi_match, + .acpi_match_table =3D acpi_rpmi_sysmsi_match, }, .probe =3D rpmi_sysmsi_probe, }; --=20 2.43.0 From nobody Fri Dec 19 22:06:38 2025 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EC932222BF for ; Wed, 2 Jul 2025 05:17:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433422; cv=none; b=W2ROP7V2gKwf0DwbHHelLV1leR+Vc+Gfo+umH5pqECOL3zLPUkLCnnyPUkfirFxNwO0jyYp9KCf9RTOc9ovmfMkQmfK+ZLITSrVpZ/mwRcrzwRnxiaJbN7WPchiIT2rZl81y5vLQzvPeIgLK244Qtu6t0rkxK6e/48Q79z0RkPU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433422; c=relaxed/simple; bh=do4xgD3FIKiBFCXHybdwqmJMFTQfLzd5+SYEVnCmQ8U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R/9987RZeZhHKdB3N+7/cMqOEJ+A66yJCoZXoiDVAKF0guPIpPJ/vxe9yimeVGGxHdNqSITfj42gmyq3PE4RS6pi0znnM7wIR9rJgBMj/xEgzr5NkplaLb2EgfuBp3mAk/L4R+zAmqy9y3k1z9YawQ05M7IO4vw3EEKbOz7ZbLY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=j6qTJYgW; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="j6qTJYgW" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-235a3dd4f0dso40032345ad.0 for ; Tue, 01 Jul 2025 22:17:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433420; x=1752038220; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nCKZPLGMv6q3Gia2CuwihlvGGifXlgSwREijf4CMFzo=; b=j6qTJYgWn7Bn4SY4oOXUfOx7Ll6iG61yqpCkufzYBsuXoBQjCSrnvR49A+Sxtkw6ld U1rJ4u11AOYlvn/kqE1UMy1H519B6+ZZowWg14NQiVAoHqipUewsMuKnHo2iguVkTKPZ hOdK1Dqn2sa3Bm7OBw1tidJ0EFqS5gE8W6svzOffBZKow9XGx4dRPQhJRJF7piCgmej6 gz1u5bdkGuFCHmbJyQjQmV7uJ5uOd8uH4UQk4Tds4HJ0uGoLaKfMU8qg1ovwN3QpYDc3 D+Pi9szeu2ibS3HsxpqMX5GFJnLo5BxpkARLGjFO2e92fELwMxyxpMV6Ki4JwVkzDZve NhrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433420; x=1752038220; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nCKZPLGMv6q3Gia2CuwihlvGGifXlgSwREijf4CMFzo=; b=KhSyO7GjqpwWj3h4tTFw394Q0kmSlNNXSDWP9Kmnr1TnrdpPHI9eshv6jHh0amLBbR fpssbQyWs0U824l1jUchLO27KY8HuO4yK496IN7H8ZI7jqpyK1LgRZV/y2JRIPyIEFHl 9n2LRyUc8wYdD6UUwleoByMp7z9bjKbpq6kcbn29nQgsys2bdsoS59sFZFakYKYBGTz9 9SEOWImTZMESkzDrOuuJ4uOrpzU1EpPWBeMWsj2xB8irf/PQVXLpVeIeT14bk/HNzr1+ LEqEqIiaFskLlhBSMikTODFUwfSCDOvqDTwZCiq9d6uB2Tv3HD5AreoP6z3znFER8/Yd ctjQ== X-Forwarded-Encrypted: i=1; AJvYcCXHXOlLBkLHD7EYl0g0rD+9mC+RrMlFTLd3UvY3vDrItq5w8fMWHo/6gVVTgY4UsLVVCLl8Zm3FI2Y8amw=@vger.kernel.org X-Gm-Message-State: AOJu0YwZSzZ+cRgYeA8OOjxuC0D6tIJPrn6cWtLoZnrWzRt8MPdddnzP FbdXS/MSLIJjTwh3fjBi9wslSPoYh8HfnpcAFS5xitIqpjHPqnbqMrZVyinMZs8C4+4= X-Gm-Gg: ASbGncv2uu9JjqxF6xxD/rK6HwotVdRFfulYj4Ppax5rdmrLJTYspz0RbzfCKi40Hht OX2MZzA/KYWsPRz7490DkHIkf9/VIUcBxoRjhFcUaESRRXDW/L5n/hLaR0lPVwIRIDeKjT0FbBZ sh15brF0pafXfvWTO8ChGgfcj5qFCYhKxqtUpXtv4p/tzqlgLo1cY8jwR0Cne6K4FNlu+Q/DnXu h52RMPorYhFQM4LpLb0paGaZbM6Zv6cRZEpeka2+hSR87KA0827G19A4yhPYNm0i9LWiW1WpzdR /KeJHG/zDIYLEecE/d6H0nf950vJC9GXmjmXTmvhfcGhqUEgmouGYVnBYKOJ0ngdt+VTjqkHUzf xTxzN2mx69fHB95ry X-Google-Smtp-Source: AGHT+IHlJ+t9cxCWGd2RS36udv84be8wQSLtZiGp/SQb5nMAYqyEcYkpZ750MfgqwwlAexTx+Vl7eQ== X-Received: by 2002:a17:903:1a27:b0:235:eb8d:7fff with SMTP id d9443c01a7336-23c6e58df66mr23872195ad.28.1751433420424; Tue, 01 Jul 2025 22:17:00 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.16.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:16:59 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 23/24] RISC-V: Enable GPIO keyboard and event device in RV64 defconfig Date: Wed, 2 Jul 2025 10:43:44 +0530 Message-ID: <20250702051345.1460497-24-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The GPIO keyboard and event device can be used to receive graceful shutdown or reboot input keys so let us enable it by default for RV64 (just like ARM64). Signed-off-by: Anup Patel --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index fe8bd8afb418..bd5f97e1d1a0 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -138,6 +138,8 @@ CONFIG_MICREL_PHY=3Dy CONFIG_MICROSEMI_PHY=3Dy CONFIG_MOTORCOMM_PHY=3Dy CONFIG_INPUT_MOUSEDEV=3Dy +CONFIG_INPUT_EVDEV=3Dy +CONFIG_KEYBOARD_GPIO=3Dy CONFIG_KEYBOARD_SUN4I_LRADC=3Dm CONFIG_SERIAL_8250=3Dy CONFIG_SERIAL_8250_CONSOLE=3Dy --=20 2.43.0 From nobody Fri Dec 19 22:06:38 2025 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0106221FD6 for ; Wed, 2 Jul 2025 05:17:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433430; cv=none; b=b21Swm4XdCcjNFQzPI1Qp9s3ZHxSeBjHp2fC2LU91+7DWeKZR/VTZxahugS+Ukac9M8PJO3GcauPp1RcLF6OHCPtdeiuwBfvh8WfuFW6xgqhUSK3pCXh3KItyDw9EDUMbuQYqBGZy5Wu7wTCaQmv+wZafSPkAMkda3VkvzAGPQw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751433430; c=relaxed/simple; bh=SIZVTA1dBlDgHWuqKkMeHUlssl6BYErjNhZuMkc2v6w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cRWxRUl/mJ19c47ol1g7XCXRdh4q4hYk35tqZXK9E/tgCdTS2GfdJKVwgHmSDvpNFo+epsj+34BX+EwgJVhOt05BVZqKe6Qo00OEPCoekyTHzO7JHk2JZEr4yGD6T3kncOd5bpG0AlgLhap9s2WdmAhqWBEpxeYi3duy9ehkrZ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=CUCd63pG; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="CUCd63pG" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-2353a2bc210so37520445ad.2 for ; Tue, 01 Jul 2025 22:17:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751433428; x=1752038228; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t84+O6WBdBY0SCc3BtWc+Gw5ZYyMJomoxrVu9jQtsgg=; b=CUCd63pGeGu4fUzMEvMVeiJTYiKkqwGwjNi21xlBefLtX/hUB1ogxNyQDNZrl/P1iN feJFYgm2b18q4Oirn5PGBEtFyvn8x70pW1I/3mFb7UdRn4q6TSlB2blJ4sChn8XmSCwQ s9rfXaikuXMpNZC6KVi7uZd7oO7glF9aCF2bZSSN9WdahH3lF5mQcDtLFoueSnSu/kJy N1t3yG3FX4dQQGGY49xs4MfXUexnM3TNJ8Ii88lno/lERrej6ydoNqAAhs1FJQ7pGOFs iZWFGRlI5ugSEG9Zsb3a7mzq/ytyNK2FTow2ak7ocZnGoWxWw67Ag6VCrpW/4gcrz6m4 vvaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751433428; x=1752038228; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t84+O6WBdBY0SCc3BtWc+Gw5ZYyMJomoxrVu9jQtsgg=; b=OUne4m/CuOkLe2zuzoHMx8i0NSCHlTYjSUrE6zB4yudqGeo2QBhyIkTbcn1wFAj3Cc XdWWc1Eenbui9j6gvU6T9V4hm5VtQBBu/iC9klJJQPOEiF/W81kd/5pYRxFU79KHaCNk ol+kbPTJAiVex6BTSiADUNVufvYa58GapeQ4kl9B/L/gsIZHq/UwgRv8KftlRROaKyjc wIJpZCkrWZuLT1ZbX+jB8TWjPwZrmrw9RpzSJizDcp32G/fTQn3j+MFtF1O4hfWpOQ+M MUHwFBKrb2u5Z48fzR0Q0PTa7FuJ1g/95rQs0zWpDltVw+1OOhzVu+eos3ZiOLbAVShk RZhQ== X-Forwarded-Encrypted: i=1; AJvYcCXaAe40/Uke2VQbA9kNKvlHjNCPk+9Vg+zpIYDqS9o+6Zsf0Gu7Ls0h7ld6IaJVLW+apJYRfneNSgiy8P0=@vger.kernel.org X-Gm-Message-State: AOJu0Yyp3TFQUGJLh98Jq7Ot0uZWYc3FZjNEv/az1E1IpKLPiGYeKVW3 mveCZ85PkBIMfTp4fwX4YpQ3yTQP+EA/Sfp7ODNjSHOefxMc9Dt+8B8rFh6clJyU4OE= X-Gm-Gg: ASbGncudIJNt+f5UGanxtNwKoIDgA0s8SYlaOZzo8mAQWzWWErY6P9EFA43Ma1Zy744 Mby3SP7wP/Pn99L4nQWkmMhXvOrrpQtVscaWGphMyA7dbg+FuXzWtoHAbxsbsk6e7HuyIaCHuR0 WaoV5+BHvTDP1PpZIdNbg2a4IYAYh1ngFJxzX61xtE21ZFOLfW4RKf1lZV57gVELZzrNNSEb55p vCv/QIPu/NfUhJSTz9J5HQvvrhyoRQDnHgnUiIkM31lsWIdOWoh2X3zZ7/QpJeHdG6JNJgh+wf7 cpAXOx8fh1a+XZgt+p7PYKYm0+ZQxGzX7Qtn5xB6/eHIIkWdTgNoziEd9Lh+Zywdiu2qW7Ti4uw dhOwcxgc08hMn6dIK X-Google-Smtp-Source: AGHT+IHF9jCGgWd1zPtdr7P6gyUcMpmB+BURtwnVFT7vtNKBR1DlMS0ym17Nq8ulkiJ1AGOTzoV1rA== X-Received: by 2002:a17:902:cf4f:b0:235:27b6:a897 with SMTP id d9443c01a7336-23c6e552a2bmr15106685ad.34.1751433427932; Tue, 01 Jul 2025 22:17:07 -0700 (PDT) Received: from localhost.localdomain ([14.141.91.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c6fe31933sm4719595ad.220.2025.07.01.22.17.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 22:17:07 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v7 24/24] MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers Date: Wed, 2 Jul 2025 10:43:45 +0530 Message-ID: <20250702051345.1460497-25-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com> References: <20250702051345.1460497-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Rahul and myself as maintainers for RISC-V RPMI and MPXY drivers. Signed-off-by: Anup Patel --- MAINTAINERS | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4bac4ea21b64..c22434a2756b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21397,6 +21397,21 @@ F: drivers/perf/riscv_pmu.c F: drivers/perf/riscv_pmu_legacy.c F: drivers/perf/riscv_pmu_sbi.c =20 +RISC-V RPMI AND MPXY DRIVERS +M: Rahul Pathak +M: Anup Patel +L: linux-riscv@lists.infradead.org +F: Documentation/devicetree/bindings/clock/riscv,rpmi-clock.yaml +F: Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy-clock.yaml +F: Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-mpxy-= system-msi.yaml +F: Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-syste= m-msi.yaml +F: Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml +F: Documentation/devicetree/bindings/mailbox/riscv,sbi-mpxy-mbox.yaml +F: drivers/clk/clk-rpmi.c +F: drivers/irqchip/irq-riscv-rpmi-sysmsi.c +F: drivers/mailbox/riscv-sbi-mpxy-mbox.c +F: include/linux/mailbox/riscv-rpmi-message.h + RISC-V SPACEMIT SoC Support M: Yixun Lan L: linux-riscv@lists.infradead.org --=20 2.43.0