From nobody Wed Oct 8 05:19:37 2025 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D74871519A6 for ; Wed, 2 Jul 2025 01:33:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751420018; cv=none; b=jb2C+AVo4W5ZOq2Zbuv5o+XxjPAEShDJNcsa52mayE4eqZiN0qL3/IAv/CmViNhsmzTrz0KocgQNiM9sKbPCWpR6f/PaonB2GSUnIEuiqZXTORP1AJ7FBzX7EDUMIGqCaJw4QEvvFi8yMLJ5W/pYZOZezrTiwNWxIyrK12CceB8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751420018; c=relaxed/simple; bh=FOQoi89NUv54CfgsP9AV7d7jkdFwueCr9s+C4BSQtMk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=Kbi86Te36u3wo7+7IiZRzOuC/p2nGoBO+pXNYe5ZeqXlaPIOtiwLrhN7/J2Vcp8l7DOmWu2Hmwd0If7wpFA9+/TTLLy7aacY3eyoT0GrS4NPF0zFIu+fDa0vZGGfTUZDkXsoPKKTd7JCvHsnZ+20eRrH3vp+BsBAQlw8aHTTQBA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=E3A6/9j9; arc=none smtp.client-ip=203.254.224.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="E3A6/9j9" Received: from epcas2p2.samsung.com (unknown [182.195.41.54]) by mailout3.samsung.com (KnoxPortal) with ESMTP id 20250702013334epoutp03a4fec35b8f6fd9d70763b38f6a6a1fa7~OSzksXsJo2361423614epoutp03a for ; Wed, 2 Jul 2025 01:33:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout3.samsung.com 20250702013334epoutp03a4fec35b8f6fd9d70763b38f6a6a1fa7~OSzksXsJo2361423614epoutp03a DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1751420014; bh=e8uOO/gv79Kb1+qWVAngQIMnnEJqThV7WDw1WnemYmM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E3A6/9j9EFYSrOwl2OEHkn59Ghts1Mifwm/H2Xl9lEU+ptdoN3dv1oeZ93bcVv2P0 lOU9fe1wpGL3nhGfDUS0cg+oBm6Z8TU0VhPQl/hdIz/22IJU7bGA1SWScJQAKGsd+2 tgoITgCQ3ZjU+Kgq9QhBVWU0YafeZpx7yxqWCI48= Received: from epsnrtp02.localdomain (unknown [182.195.42.154]) by epcas2p3.samsung.com (KnoxPortal) with ESMTPS id 20250702013333epcas2p34183624e903d9a57745a17e5e1975fe7~OSzkTl1pV1430414304epcas2p3t; Wed, 2 Jul 2025 01:33:33 +0000 (GMT) Received: from epcas2p4.samsung.com (unknown [182.195.36.101]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4bX2V461pkz2SSKj; Wed, 2 Jul 2025 01:33:32 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas2p1.samsung.com (KnoxPortal) with ESMTPA id 20250702013332epcas2p159e663ba3bde9f5bf28ccd743c211fd8~OSzjAH4wL0297502975epcas2p1f; Wed, 2 Jul 2025 01:33:32 +0000 (GMT) Received: from asswp146.dsn.sec.samsung.com (unknown [10.229.19.146]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250702013332epsmtip2a6a84522c61cf883db518b17369feb0a~OSzi8lg5Z2705927059epsmtip2Q; Wed, 2 Jul 2025 01:33:32 +0000 (GMT) From: Sowon Na To: robh@kernel.org, krzk@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, alim.akhtar@samsung.com, kishon@kernel.org Cc: krzk+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, sowon.na@samsung.com Subject: [PATCH 1/5] phy: samsung-ufs: update calibration settings for EVT2 Date: Wed, 2 Jul 2025 10:33:07 +0900 Message-ID: <20250702013316.2837427-2-sowon.na@samsung.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250702013316.2837427-1-sowon.na@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250702013332epcas2p159e663ba3bde9f5bf28ccd743c211fd8 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250702013332epcas2p159e663ba3bde9f5bf28ccd743c211fd8 References: <20250702013316.2837427-1-sowon.na@samsung.com> The hardware EVT version for exynosautov920 has been updated, with EVT2 confirmed as the final production version. Accordingly, this patch updates the UFS PHY calibration settings to match EVT2 hardware characteristics. This ensures stable operation and optimal performance on the finalized EVT2 hardware revision. Tested on exynosautov920 EVT2. Signed-off-by: Sowon Na --- drivers/phy/samsung/phy-exynosautov920-ufs.c | 39 +++++++------------- drivers/phy/samsung/phy-samsung-ufs.h | 1 - 2 files changed, 14 insertions(+), 26 deletions(-) diff --git a/drivers/phy/samsung/phy-exynosautov920-ufs.c b/drivers/phy/sam= sung/phy-exynosautov920-ufs.c index 21ef79c42f95..5ff9fc3a0615 100644 --- a/drivers/phy/samsung/phy-exynosautov920-ufs.c +++ b/drivers/phy/samsung/phy-exynosautov920-ufs.c @@ -12,8 +12,7 @@ #define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) #define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e =20 -#define EXYNOSAUTOV920_CDR_LOCK_OFFSET 0xce4 - +#define EXYNOSAUTOV920_CAL_DONE_OFFSET 0xce0 #define PHY_EXYNOSAUTOV920_LANE_OFFSET 0x200 #define PHY_TRSV_REG_CFG_AUTOV920(o, v, d) \ PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_EXYNOSAUTOV920_LANE_OFFSET) @@ -32,7 +31,7 @@ static const struct samsung_ufs_phy_cfg exynosautov920_pr= e_init_cfg[] =3D { PHY_TRSV_REG_CFG_AUTOV920(0x202, 0x06, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x203, 0x0a, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x204, 0x00, PWR_MODE_ANY), - PHY_TRSV_REG_CFG_AUTOV920(0x205, 0x10, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV920(0x205, 0x11, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x207, 0x0c, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x2e1, 0xc0, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x22d, 0xf8, PWR_MODE_ANY), @@ -46,6 +45,7 @@ static const struct samsung_ufs_phy_cfg exynosautov920_pr= e_init_cfg[] =3D { PHY_TRSV_REG_CFG_AUTOV920(0x23e, 0x14, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x23f, 0x13, PWR_MODE_ANY), =20 + PHY_TRSV_REG_CFG_AUTOV920(0x36e, 0x05, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x240, 0x4a, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x243, 0x40, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x244, 0x02, PWR_MODE_ANY), @@ -76,6 +76,10 @@ static const struct samsung_ufs_phy_cfg exynosautov920_p= re_init_cfg[] =3D { PHY_TRSV_REG_CFG_AUTOV920(0x2bc, 0x06, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x2bd, 0x06, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x2be, 0x06, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV920(0x2e4, 0x1a, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV920(0x2ed, 0x25, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV920(0x269, 0x1a, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV920(0x2f4, 0x2f, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x34b, 0x01, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x34c, 0x24, PWR_MODE_ANY), PHY_TRSV_REG_CFG_AUTOV920(0x34d, 0x23, PWR_MODE_ANY), @@ -107,40 +111,25 @@ static const struct samsung_ufs_phy_cfg exynosautov92= 0_post_pwr_hs_cfg[] =3D { =20 #define DELAY_IN_US 40 #define RETRY_CNT 100 -#define EXYNOSAUTOV920_CDR_LOCK_MASK 0x8 +#define EXYNOSAUTOV920_CAL_DONE_MASK 0x8 =20 -int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane) +static int exynosautov920_ufs_phy_wait_for_cal(struct phy *phy, u8 lane) { struct samsung_ufs_phy *ufs_phy =3D get_samsung_ufs_phy(phy); u32 reg, i; =20 - struct samsung_ufs_phy_cfg cfg[4] =3D { - PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x10, PWR_MODE_ANY), - PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x18, PWR_MODE_ANY), - PHY_TRSV_REG_CFG_AUTOV920(0x246, 0x01, PWR_MODE_ANY), - END_UFS_PHY_CFG, - }; - for (i =3D 0; i < RETRY_CNT; i++) { udelay(DELAY_IN_US); =20 - reg =3D readl(ufs_phy->reg_pma + EXYNOSAUTOV920_CDR_LOCK_OFFSET + + reg =3D readl(ufs_phy->reg_pma + EXYNOSAUTOV920_CAL_DONE_OFFSET + (PHY_APB_ADDR(PHY_EXYNOSAUTOV920_LANE_OFFSET) * lane)); =20 - if ((reg & EXYNOSAUTOV920_CDR_LOCK_MASK) - =3D=3D EXYNOSAUTOV920_CDR_LOCK_MASK) { - samsung_ufs_phy_config(ufs_phy, &cfg[2], lane); + if ((reg & EXYNOSAUTOV920_CAL_DONE_MASK) + =3D=3D EXYNOSAUTOV920_CAL_DONE_MASK) return 0; - } - - udelay(DELAY_IN_US); - - /* Disable and enable CDR */ - samsung_ufs_phy_config(ufs_phy, &cfg[0], lane); - samsung_ufs_phy_config(ufs_phy, &cfg[1], lane); } =20 - dev_err(ufs_phy->dev, "failed to get phy cdr lock\n"); + dev_err(ufs_phy->dev, "failed to wait for cal done\n"); return -ETIMEDOUT; } =20 @@ -164,5 +153,5 @@ const struct samsung_ufs_phy_drvdata exynosautov920_ufs= _phy =3D { .clk_list =3D exynosautov920_ufs_phy_clks, .num_clks =3D ARRAY_SIZE(exynosautov920_ufs_phy_clks), .cdr_lock_status_offset =3D EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_ST= ATUS, - .wait_for_cdr =3D exynosautov920_ufs_phy_wait_cdr_lock, + .wait_for_cal =3D exynosautov920_ufs_phy_wait_for_cal, }; diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/ph= y-samsung-ufs.h index a28f148081d1..895741e800da 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.h +++ b/drivers/phy/samsung/phy-samsung-ufs.h @@ -143,7 +143,6 @@ static inline void samsung_ufs_phy_ctrl_isol( } =20 int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane); -int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane); void samsung_ufs_phy_config(struct samsung_ufs_phy *phy, const struct samsung_ufs_phy_cfg *cfg, u8 lane); =20 --=20 2.45.2 From nobody Wed Oct 8 05:19:37 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7449151991 for ; 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charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250702013332epcas2p4fe456c285c96c143d96f98b31d9b5255 References: <20250702013316.2837427-1-sowon.na@samsung.com> Add samsung,exynosautov920-ufs compatible for ExynosAutov920 SoC. Signed-off-by: Sowon Na Acked-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar --- Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml = b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml index b4e744ebffd1..52485912d29a 100644 --- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml @@ -19,6 +19,7 @@ properties: - samsung,exynos7-ufs - samsung,exynosautov9-ufs - samsung,exynosautov9-ufs-vh + - samsung,exynosautov920-ufs - tesla,fsd-ufs =20 reg: --=20 2.45.2 From nobody Wed Oct 8 05:19:37 2025 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 015B31527B4 for ; Wed, 2 Jul 2025 01:33:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250702013332epcas2p4ea41cc442d42fd7b2c742e1d08b26182 References: <20250702013316.2837427-1-sowon.na@samsung.com> Add hsi2 compatible for ExynosAutov920 ufs shareability register to set io coherency of the ExynosAutov920 ufs. Signed-off-by: Sowon Na --- .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml index d27ed6c9d61e..d8b302f97547 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml @@ -30,6 +30,7 @@ properties: - samsung,exynos8895-fsys1-sysreg - samsung,exynos8895-peric0-sysreg - samsung,exynos8895-peric1-sysreg + - samsung,exynosautov920-hsi2-sysreg - samsung,exynosautov920-peric0-sysreg - samsung,exynosautov920-peric1-sysreg - tesla,fsd-cam-sysreg --=20 2.45.2 From nobody Wed Oct 8 05:19:37 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 872671624E1 for ; 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Wed, 2 Jul 2025 01:33:33 +0000 (GMT) Received: from epcas2p1.samsung.com (unknown [182.195.36.99]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4bX2V50B51z2SSKt; Wed, 2 Jul 2025 01:33:33 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas2p3.samsung.com (KnoxPortal) with ESMTPA id 20250702013332epcas2p3fc1442b0c8f8b92c9cdc8dd0398ebcb6~OSzjQtsGE1201012010epcas2p3A; Wed, 2 Jul 2025 01:33:32 +0000 (GMT) Received: from asswp146.dsn.sec.samsung.com (unknown [10.229.19.146]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250702013332epsmtip25685b13de179e059b7486107c8b990b9~OSzjMwUUK2820728207epsmtip2l; Wed, 2 Jul 2025 01:33:32 +0000 (GMT) From: Sowon Na To: robh@kernel.org, krzk@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, alim.akhtar@samsung.com, kishon@kernel.org Cc: krzk+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, sowon.na@samsung.com Subject: [PATCH 4/5] scsi: ufs: exynos: add support for ExynosAutov920 SoC Date: Wed, 2 Jul 2025 10:33:10 +0900 Message-ID: <20250702013316.2837427-5-sowon.na@samsung.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250702013316.2837427-1-sowon.na@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250702013332epcas2p3fc1442b0c8f8b92c9cdc8dd0398ebcb6 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250702013332epcas2p3fc1442b0c8f8b92c9cdc8dd0398ebcb6 References: <20250702013316.2837427-1-sowon.na@samsung.com> Add a dedicated compatible and drv_data with associated hooks for ExynosAutov920 SoC, Samsung Autotomotive SoC series. ExynosAutov920 has the UFSHCI 3.1 compliant UFS controller. Signed-off-by: Sowon Na --- drivers/ufs/host/ufs-exynos.c | 130 +++++++++++++++++++++++++++++++--- 1 file changed, 120 insertions(+), 10 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 3e545af536e5..32b087099ff9 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -97,6 +97,10 @@ #define UFS_EXYNOSAUTO_RD_SHARABLE BIT(1) #define UFS_EXYNOSAUTO_SHARABLE (UFS_EXYNOSAUTO_WR_SHARABLE | \ UFS_EXYNOSAUTO_RD_SHARABLE) +#define UFS_EXYNOSAUTOV920_WR_SHARABLE BIT(3) +#define UFS_EXYNOSAUTOV920_RD_SHARABLE BIT(2) +#define UFS_EXYNOSAUTOV920_SHARABLE (UFS_EXYNOSAUTOV920_WR_SHARABLE |\ + UFS_EXYNOSAUTOV920_RD_SHARABLE) #define UFS_GS101_WR_SHARABLE BIT(1) #define UFS_GS101_RD_SHARABLE BIT(0) #define UFS_GS101_SHARABLE (UFS_GS101_WR_SHARABLE | \ @@ -417,6 +421,95 @@ static int exynos7_ufs_post_pwr_change(struct exynos_u= fs *ufs, return 0; } =20 +static int exynosautov920_ufs_pre_link(struct exynos_ufs *ufs) +{ + struct ufs_hba *hba =3D ufs->hba; + int i; + u32 tx_line_reset_period, rx_line_reset_period; + + rx_line_reset_period =3D (RX_LINE_RESET_TIME * ufs->mclk_rate) + / NSEC_PER_MSEC; + tx_line_reset_period =3D (TX_LINE_RESET_TIME * ufs->mclk_rate) + / NSEC_PER_MSEC; + + unipro_writel(ufs, 0x5f, 0x44); + + ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x202), 0x02); + + for_each_ufs_rx_lane(ufs, i) { + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), + DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), + (rx_line_reset_period >> 16) & 0xFF); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), + (rx_line_reset_period >> 8) & 0xFF); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), + (rx_line_reset_period) & 0xFF); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x69); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); + } + + for_each_ufs_tx_lane(ufs, i) { + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), + DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), + 0x02); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), + (tx_line_reset_period >> 16) & 0xFF); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), + (tx_line_reset_period >> 8) & 0xFF); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), + (tx_line_reset_period) & 0xFF); + + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7f, i), 0x0); + } + + ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000); + + return 0; +} + +static int exynosautov920_ufs_post_link(struct exynos_ufs *ufs) +{ + struct ufs_hba *hba =3D ufs->hba; + + ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15a4), 0x3e8); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x0); + + return 0; +} + +static int exynosautov920_ufs_pre_pwr_change(struct exynos_ufs *ufs, + struct ufs_pa_layer_attr *pwr) +{ + struct ufs_hba *hba =3D ufs->hba; + + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15d4), 0x1); + + ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064); + ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224); + ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); + + unipro_writel(ufs, 8064, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0); + unipro_writel(ufs, 28224, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1); + unipro_writel(ufs, 20160, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2); + unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0); + unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1); + unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2); + + return 0; +} + /* * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w * Control should be disabled in the below cases @@ -951,16 +1044,6 @@ static int exynos_ufs_phy_init(struct exynos_ufs *ufs) struct phy *generic_phy =3D ufs->phy; int ret =3D 0; =20 - if (ufs->avail_ln_rx =3D=3D 0 || ufs->avail_ln_tx =3D=3D 0) { - ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES), - &ufs->avail_ln_rx); - ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES), - &ufs->avail_ln_tx); - WARN(ufs->avail_ln_rx !=3D ufs->avail_ln_tx, - "available data lane is not equal(rx:%d, tx:%d)\n", - ufs->avail_ln_rx, ufs->avail_ln_tx); - } - phy_set_bus_width(generic_phy, ufs->avail_ln_rx); =20 if (generic_phy->power_count) { @@ -1065,6 +1148,16 @@ static int exynos_ufs_pre_link(struct ufs_hba *hba) /* unipro */ exynos_ufs_config_unipro(ufs); =20 + if (ufs->avail_ln_rx =3D=3D 0 || ufs->avail_ln_tx =3D=3D 0) { + ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES), + &ufs->avail_ln_rx); + ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES), + &ufs->avail_ln_tx); + WARN(ufs->avail_ln_rx !=3D ufs->avail_ln_tx, + "available data lane is not equal(rx:%d, tx:%d)\n", + ufs->avail_ln_rx, ufs->avail_ln_tx); + } + if (ufs->drv_data->pre_link) ufs->drv_data->pre_link(ufs); =20 @@ -2183,6 +2276,21 @@ static const struct exynos_ufs_drv_data gs101_ufs_dr= vs =3D { .suspend =3D gs101_ufs_suspend, }; =20 +static const struct exynos_ufs_drv_data exynosautov920_ufs_drvs =3D { + .uic_attr =3D &exynos7_uic_attr, + .quirks =3D UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, + .opts =3D EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | + EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | + EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX | + EXYNOS_UFS_OPT_TIMER_TICK_SELECT, + .iocc_mask =3D UFS_EXYNOSAUTOV920_SHARABLE, + .drv_init =3D exynosauto_ufs_drv_init, + .post_hce_enable =3D exynosauto_ufs_post_hce_enable, + .pre_link =3D exynosautov920_ufs_pre_link, + .post_link =3D exynosautov920_ufs_post_link, + .pre_pwr_change =3D exynosautov920_ufs_pre_pwr_change, +}; + static const struct of_device_id exynos_ufs_of_match[] =3D { { .compatible =3D "google,gs101-ufs", .data =3D &gs101_ufs_drvs }, @@ -2192,6 +2300,8 @@ static const struct of_device_id exynos_ufs_of_match[= ] =3D { .data =3D &exynosauto_ufs_drvs }, { .compatible =3D "samsung,exynosautov9-ufs-vh", .data =3D &exynosauto_ufs_vh_drvs }, + { .compatible =3D "samsung,exynosautov920-ufs", + .data =3D &exynosautov920_ufs_drvs }, { .compatible =3D "tesla,fsd-ufs", .data =3D &fsd_ufs_drvs }, {}, --=20 2.45.2 From nobody Wed Oct 8 05:19:37 2025 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97D4317A2EB for ; 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Wed, 2 Jul 2025 01:33:34 +0000 (GMT) Received: from epcas2p2.samsung.com (unknown [182.195.36.70]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4bX2V52jVSz2SSKs; Wed, 2 Jul 2025 01:33:33 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas2p3.samsung.com (KnoxPortal) with ESMTPA id 20250702013332epcas2p39f6fce695eee06f912f5861fe459fbd5~OSzjUh5eo0547705477epcas2p3F; Wed, 2 Jul 2025 01:33:32 +0000 (GMT) Received: from asswp146.dsn.sec.samsung.com (unknown [10.229.19.146]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250702013332epsmtip2402243e2ee4768654a4eb374e4f5a21a~OSzjQ5WMj2822028220epsmtip2j; Wed, 2 Jul 2025 01:33:32 +0000 (GMT) From: Sowon Na To: robh@kernel.org, krzk@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, alim.akhtar@samsung.com, kishon@kernel.org Cc: krzk+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, sowon.na@samsung.com Subject: [PATCH 5/5] arm64: dts: exynosautov920: enable support for ufs device Date: Wed, 2 Jul 2025 10:33:11 +0900 Message-ID: <20250702013316.2837427-6-sowon.na@samsung.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250702013316.2837427-1-sowon.na@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250702013332epcas2p39f6fce695eee06f912f5861fe459fbd5 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250702013332epcas2p39f6fce695eee06f912f5861fe459fbd5 References: <20250702013316.2837427-1-sowon.na@samsung.com> The exynosautov920 uses v3.1 UFS device. Add ufs node for ExynosAutov920 SoC. And enable ufs_phy and ufs devices with ufs_fixed_vcc_reg regulator for ExynosAutov920 SADK. Signed-off-by: Sowon Na --- .../boot/dts/exynos/exynosautov920-sadk.dts | 17 ++++++++++++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 27 +++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm6= 4/boot/dts/exynos/exynosautov920-sadk.dts index a397f068ed53..f979cc1ae6a1 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts @@ -52,6 +52,14 @@ memory@80000000 { <0x8 0x80000000 0x1 0xfba00000>, <0xa 0x00000000 0x2 0x00000000>; }; + + ufs_fixed_vcc_reg: regulator-0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "ufs-vcc"; + gpio =3D <&gpg3 2 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; }; =20 &pinctrl_alive { @@ -83,6 +91,15 @@ &usi_0 { status =3D "okay"; }; =20 +&ufs_0 { + status =3D "okay"; + vcc-supply =3D <&ufs_fixed_vcc_reg>; +}; + +&ufs_0_phy { + status =3D "okay"; +}; + &xtcxo { clock-frequency =3D <38400000>; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/bo= ot/dts/exynos/exynosautov920.dtsi index 0fdf2062930a..f787c28fb0d5 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1426,6 +1426,12 @@ cmu_hsi2: clock-controller@16b00000 { "ethernet"; }; =20 + syscon_hsi2: syscon@16c00000 { + compatible =3D "samsung,exynosautov920-hsi2-sysreg", + "syscon"; + reg =3D <0x16c00000 0x800>; + }; + pinctrl_hsi2: pinctrl@16c10000 { compatible =3D "samsung,exynosautov920-pinctrl"; reg =3D <0x16c10000 0x10000>; @@ -1438,6 +1444,27 @@ pinctrl_hsi2ufs: pinctrl@16d20000 { interrupts =3D ; }; =20 + ufs_0: ufs@16e00000 { + compatible =3D "samsung,exynosautov920-ufs"; + reg =3D <0x16e00000 0x100>, + <0x16e01100 0x400>, + <0x16e80000 0x8000>, + <0x16d08000 0x800>; + reg-names =3D "hci", "vs_hci", "unipro", "ufsp"; + interrupts =3D ; + clocks =3D <&cmu_hsi2 CLK_MOUT_HSI2_UFS_EMBD_USER>, + <&cmu_hsi2 CLK_MOUT_HSI2_NOC_UFS_USER>; + clock-names =3D "core_clk", "sclk_unipro_main"; + freq-table-hz =3D <0 0>, <0 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ufs_rst_n &ufs_refclk_out>; + phys =3D <&ufs_0_phy>; + phy-names =3D "ufs-phy"; + samsung,sysreg =3D <&syscon_hsi2 0x710>; + dma-coherent; + status =3D "disabled"; + }; + ufs_0_phy: phy@16e04000 { compatible =3D "samsung,exynosautov920-ufs-phy"; reg =3D <0x16e04000 0x4000>; --=20 2.45.2