From nobody Wed Oct 8 07:18:10 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7C9724CE08; Wed, 2 Jul 2025 00:57:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751417861; cv=none; b=osmHEaGPht3LDZDCqzFuJPecXbqEvpJgqrzFOv8UdqLNoV3SOHNvHOrmLJDzx8cGeQrpqMtja6rrHeeHtXn9+GN0cgw1wsY+eOLj2zh5wlK70j7rPQH/I53XO7MYuUxOH1BV0InIwVj3pIqzBoeFfQC0CG/xwtMIl2OSwYiWVZI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751417861; c=relaxed/simple; bh=fQBAnkI5rjMDZQo6P8/3QVUINwHo/QDB3Xt13H5B0vc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pTvwpMm7T6b6yTEzD1y/o6zhm7/sb5rfdig/b0rTzepNulfbkjfiyqVZ7YGVT7JdIz2jNcwfw4TyG44pYwRG+80yMJxDfbODzWUdvXNaN7KyJNmMMF/RYYnPlrZhNWbKTVhxqUwSQ0vEXlFN5GLIldt4/NL206UWeZjX87N+PFc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: J5+YdmRNSKOnN3uomudF6w== X-CSE-MsgGUID: oWfC5T+vSCu7irK4krP6oA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 02 Jul 2025 09:57:38 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.9]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id C1FA740E798E; Wed, 2 Jul 2025 09:57:32 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, richardcochran@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, biju.das.jz@bp.renesas.com, john.madieu@gmail.com, John Madieu Subject: [PATCH v4 4/4] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces Date: Wed, 2 Jul 2025 02:57:06 +0200 Message-ID: <20250702005706.1200059-5-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702005706.1200059-1-john.madieu.xa@bp.renesas.com> References: <20250702005706.1200059-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E SMAR= C EVK Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven --- Changes: v2: No changes but resending without dt-bindings patch v3: Updates mdio separately, based on phandles instead of node redefinition v4: - Update pinmux to add OEN support - Drops Tb and Rb tags initially collected .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3e-smarc-som.dtsi index f99a09d04ddd..f930e98a7ea9 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -26,6 +26,8 @@ / { compatible =3D "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r= 9a09g047"; =20 aliases { + ethernet0 =3D ð0; + ethernet1 =3D ð1; i2c2 =3D &i2c2; mmc0 =3D &sdhi0; mmc2 =3D &sdhi2; @@ -77,6 +79,24 @@ &audio_extal_clk { clock-frequency =3D <48000000>; }; =20 +ð0 { + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + + pinctrl-0 =3D <ð0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +ð1 { + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + + pinctrl-0 =3D <ð1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + &gpu { status =3D "okay"; mali-supply =3D <®_vdd0p8v_others>; @@ -102,7 +122,98 @@ raa215300: pmic@12 { }; }; =20 +&mdio0 { + phy0: ethernet-phy@7 { + compatible =3D "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + interrupts-extended =3D <&icu 3 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-psec =3D <1400>; + txc-skew-psec =3D <1400>; + rxdv-skew-psec =3D <0>; + txdv-skew-psec =3D <0>; + rxd0-skew-psec =3D <0>; + rxd1-skew-psec =3D <0>; + rxd2-skew-psec =3D <0>; + rxd3-skew-psec =3D <0>; + txd0-skew-psec =3D <0>; + txd1-skew-psec =3D <0>; + txd2-skew-psec =3D <0>; + txd3-skew-psec =3D <0>; + }; +}; + +&mdio1 { + phy1: ethernet-phy@7 { + compatible =3D "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + interrupts-extended =3D <&icu 16 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-psec =3D <1400>; + txc-skew-psec =3D <1400>; + rxdv-skew-psec =3D <0>; + txdv-skew-psec =3D <0>; + rxd0-skew-psec =3D <0>; + rxd1-skew-psec =3D <0>; + rxd2-skew-psec =3D <0>; + rxd3-skew-psec =3D <0>; + txd0-skew-psec =3D <0>; + txd1-skew-psec =3D <0>; + txd2-skew-psec =3D <0>; + txd3-skew-psec =3D <0>; + }; +}; + &pinctrl { + eth0_pins: eth0 { + clk0 { + pinmux =3D ; /* TXC */ + output-enable; + }; + + ctrl0 { + pinmux =3D , /* MDC */ + , /* MDIO */ + , /* PHY_INTR (IRQ2) */ + , /* RXD3 */ + , /* RXD2 */ + , /* RXD1 */ + , /* RXD0 */ + , /* RXC */ + , /* RX_CTL */ + , /* TXD3 */ + , /* TXD2 */ + , /* TXD1 */ + , /* TXD0 */ + ; /* TX_CTL */ + }; + }; + + eth1_pins: eth1 { + clk1 { + pinmux =3D ; /* TXC */ + output-enable; + }; + + ctrl1 { + + pinmux =3D , /* MDC */ + , /* MDIO */ + , /* PHY_INTR (IRQ15) */ + , /* RXD3 */ + , /* RXD2 */ + , /* RXD1 */ + , /* RXD0 */ + , /* RXC */ + , /* RX_CTL */ + , /* TXD3 */ + , /* TXD2 */ + , /* TXD1 */ + , /* TXD0 */ + ; /* TX_CTL */ + }; + }; + i2c2_pins: i2c { pinmux =3D , /* SCL2 */ ; /* SDA2 */ --=20 2.25.1