From nobody Wed Oct 8 05:36:32 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5069276410; Wed, 2 Jul 2025 00:57:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751417844; cv=none; b=Bglt1wtoh3sWVzwgPbrvK0+Y9fGLvV6j94aSmKUGRZLZND72TY3+KAta0zVqEjwWLaTbUkOlrlnyIcj895Ru4KscWSEOm6/aiqANzV13uDeXun/IHSDC0B3roZsn34nqO8zn6DG7R7E90okgHsWQuoHyR1JT72NlTOkykT6P4FQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751417844; c=relaxed/simple; bh=Pmf3kwOp2PpfHsWOcpmEm+BfwBL1PBgL+xNY6gRVrD4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jboIfttxTRc9v7vWgEEaJ9lent9gQLB94Bjt4vYKR27gTmcmlWzRWuDwMe00zo8ASF9jDi8hP89pAajk7kl9A2HNKkFSGBZTBxxlVRavP8WtZJngnE5y8v4nB0NH7TeViya2WnRxHi+Ih92e5tb+uOfqq6gt04a5e/4pDBcDPpk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: u0hCSKKVR36JbZaRhYm9wg== X-CSE-MsgGUID: SB3kh3jHRm2mbnBka4rmIw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 02 Jul 2025 09:57:20 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.9]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id B9CF640E7741; Wed, 2 Jul 2025 09:57:15 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, richardcochran@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, biju.das.jz@bp.renesas.com, john.madieu@gmail.com, John Madieu Subject: [PATCH v4 1/4] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs Date: Wed, 2 Jul 2025 02:57:03 +0200 Message-ID: <20250702005706.1200059-2-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702005706.1200059-1-john.madieu.xa@bp.renesas.com> References: <20250702005706.1200059-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1) IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux clocks needed by these two GBETH IPs. Reviewed-by: Biju Das Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven --- Changes: v2: No changes but resending without dt-bindings patch v3:=20 Uses underscores instead of dashes in clock names v4: - Renames clock names to match V2Hs - Uses DEF_MOD_MUX_EXTERNAL instead of DEF_MOD for Tx and Rx clks - Drops Tested-by tag from Biju drivers/clk/renesas/r9a09g047-cpg.c | 64 +++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a0= 9g047-cpg.c index 21699999cedd..c23cb434a218 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -29,6 +29,7 @@ enum clk_ids { CLK_PLLDTY, CLK_PLLCA55, CLK_PLLVDO, + CLK_PLLETH, =20 /* Internal Core Clocks */ CLK_PLLCM33_DIV3, @@ -46,6 +47,15 @@ enum clk_ids { CLK_PLLDTY_ACPU, CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU_DIV4, + CLK_PLLDTY_DIV8, + CLK_PLLETH_DIV_250_FIX, + CLK_PLLETH_DIV_125_FIX, + CLK_CSDIV_PLLETH_GBE0, + CLK_CSDIV_PLLETH_GBE1, + CLK_SMUX2_GBE0_TXCLK, + CLK_SMUX2_GBE0_RXCLK, + CLK_SMUX2_GBE1_TXCLK, + CLK_SMUX2_GBE1_RXCLK, CLK_PLLDTY_DIV16, CLK_PLLVDO_CRU0, CLK_PLLVDO_GPU, @@ -85,7 +95,18 @@ static const struct clk_div_table dtable_2_64[] =3D { {0, 0}, }; =20 +static const struct clk_div_table dtable_2_100[] =3D { + {0, 2}, + {1, 10}, + {2, 100}, + {0, 0}, +}; + /* Mux clock tables */ +static const char * const smux2_gbe0_rxclk[] =3D { ".plleth_gbe0", "et0_rx= clk" }; +static const char * const smux2_gbe0_txclk[] =3D { ".plleth_gbe0", "et0_rx= clk" }; +static const char * const smux2_gbe1_rxclk[] =3D { ".plleth_gbe1", "et1_rx= clk" }; +static const char * const smux2_gbe1_txclk[] =3D { ".plleth_gbe1", "et1_tx= clk" }; static const char * const smux2_xspi_clk0[] =3D { ".pllcm33_div3", ".pllcm= 33_div4" }; static const char * const smux2_xspi_clk1[] =3D { ".smux2_xspi_clk0", ".pl= lcm33_div5" }; =20 @@ -100,6 +121,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] = __initconst =3D { DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), + DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), =20 /* Internal Core Clocks */ @@ -122,6 +144,18 @@ static const struct cpg_core_clk r9a09g047_core_clks[]= __initconst =3D { DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dta= ble_2_64), DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, = 2), DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, = 4), + DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8), + + DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4), + DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_F= IX, 1, 2), + DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, CLK_PLLETH_DIV_250_FIX, + CSDIV0_DIVCTL0, dtable_2_100), + DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, CLK_PLLETH_DIV_250_FIX, + CSDIV0_DIVCTL1, dtable_2_100), + DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_= gbe0_txclk), + DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_= gbe0_rxclk), + DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_= gbe1_txclk), + DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_= gbe1_rxclk), DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), =20 DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dta= ble_2_4), @@ -139,6 +173,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[]= __initconst =3D { CDDIV1_DIVCTL3, dtable_1_8), DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1,= 1), DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2), + DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I, + CLK_PLLETH_DIV_125_FIX, 1, 1), + DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I, + CLK_PLLETH_DIV_125_FIX, 1, 1), }; =20 static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst =3D { @@ -214,6 +252,30 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[]= __initconst =3D { BUS_MSTOP(8, BIT(4))), DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, BUS_MSTOP(8, BIT(4))), + DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, = 24, + BUS_MSTOP(8, BIT(5)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, = 25, + BUS_MSTOP(8, BIT(5)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10= , 5, 26, + BUS_MSTOP(8, BIT(5)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11= , 5, 27, + BUS_MSTOP(8, BIT(5)), 1), + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28, + BUS_MSTOP(8, BIT(5))), + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29, + BUS_MSTOP(8, BIT(5))), + DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5,= 30, + BUS_MSTOP(8, BIT(6)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5,= 31, + BUS_MSTOP(8, BIT(6)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0,= 6, 0, + BUS_MSTOP(8, BIT(6)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1,= 6, 1, + BUS_MSTOP(8, BIT(6)), 1), + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2, + BUS_MSTOP(8, BIT(6))), + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, + BUS_MSTOP(8, BIT(6))), DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, BUS_MSTOP(9, BIT(4))), DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, @@ -255,6 +317,8 @@ static const struct rzv2h_reset r9a09g047_resets[] __in= itconst =3D { DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ + DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ + DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ --=20 2.25.1 From nobody Wed Oct 8 05:36:32 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BA9C64CE08; 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dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: hZPHJrtoTNe1F2XWklxQ9Q== X-CSE-MsgGUID: O0TUo7fSSuyzMs96njVo6Q== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 02 Jul 2025 09:57:26 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.9]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8DC9640E7741; Wed, 2 Jul 2025 09:57:21 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, richardcochran@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, biju.das.jz@bp.renesas.com, john.madieu@gmail.com Subject: [PATCH v4 2/4] pinctrl: renesas: rzg2l: Pass OEN pin names Date: Wed, 2 Jul 2025 02:57:04 +0200 Message-ID: <20250702005706.1200059-3-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702005706.1200059-1-john.madieu.xa@bp.renesas.com> References: <20250702005706.1200059-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Pass the OEN pin names via the SoC-specific hardware configuration structure to allow reuse of rzv2h_oen_read() and rzv2h_oen_write() on multiple SoCs. On the RZ/V2H(P) and RZ/G3E SoCs, the PFC_OEN register is located at the same offset. However, the register controls different pins on each SoC. Hardcoding the pin names in the common logic prevents reusability. Extend struct rzg2l_hwcfg to include an array of OEN pin names and its length. Use these values in rzv2h_pin_to_oen_bit() to determine the bit position dynamically based on the active SoC. This enables shared handling of OEN register access while accounting for SoC-specific pin mappings. Signed-off-by: Lad Prabhakar --- Changes: v4: new patch drivers/pinctrl/renesas/pinctrl-rzg2l.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 78fa08ff0faa..792ca70bd9d1 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -257,6 +257,8 @@ enum rzg2l_iolh_index { * @func_base: base number for port function (see register PFC) * @oen_max_pin: the maximum pin number supporting output enable * @oen_max_port: the maximum port number supporting output enable + * @oen_pin_names: array of pin names for output enable + * @oen_pin_names_len: length of the oen_pin_names array */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; @@ -269,6 +271,8 @@ struct rzg2l_hwcfg { u8 func_base; u8 oen_max_pin; u8 oen_max_port; + const char * const *oen_pin_names; + u8 oen_pin_names_len; }; =20 struct rzg2l_dedicated_configs { @@ -1213,14 +1217,11 @@ static int rzv2h_bias_param_to_hw(enum pin_config_p= aram param) =20 static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _= pin) { - static const char * const pin_names[] =3D { "ET0_TXC_TXCLK", "ET1_TXC_TXC= LK", - "XSPI0_RESET0N", "XSPI0_CS0N", - "XSPI0_CKN", "XSPI0_CKP" }; const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[_pin]; unsigned int i; =20 - for (i =3D 0; i < ARRAY_SIZE(pin_names); i++) { - if (!strcmp(pin_desc->name, pin_names[i])) + for (i =3D 0; i < pctrl->data->hwcfg->oen_pin_names_len; i++) { + if (!strcmp(pin_desc->name, pctrl->data->hwcfg->oen_pin_names[i])) return i; } =20 @@ -3277,11 +3278,18 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { .oen_max_port =3D 7, /* P7_1 is the maximum OEN port. */ }; =20 +static const char * const rzv2h_oen_pin_names[] =3D { + "ET0_TXC_TXCLK", "ET1_TXC_TXCLK", "XSPI0_RESET0N", "XSPI0_CS0N", + "XSPI0_CKN", "XSPI0_CKP" +}; + static const struct rzg2l_hwcfg rzv2h_hwcfg =3D { .regs =3D { .pwpr =3D 0x3c04, }, .tint_start_index =3D 17, + .oen_pin_names =3D rzv2h_oen_pin_names, + .oen_pin_names_len =3D ARRAY_SIZE(rzv2h_oen_pin_names), }; =20 static struct rzg2l_pinctrl_data r9a07g043_data =3D { --=20 2.25.1 From nobody Wed Oct 8 05:36:32 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 834594CE08; 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dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 8Rk1S18fRMqKRm7qqoC1Gw== X-CSE-MsgGUID: Sje2jBtMT1uFs0aUznFt+w== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 02 Jul 2025 09:57:32 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.9]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1DB9640E798E; Wed, 2 Jul 2025 09:57:26 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, richardcochran@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, biju.das.jz@bp.renesas.com, john.madieu@gmail.com Subject: [PATCH v4 3/4] pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC Date: Wed, 2 Jul 2025 02:57:05 +0200 Message-ID: <20250702005706.1200059-4-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702005706.1200059-1-john.madieu.xa@bp.renesas.com> References: <20250702005706.1200059-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support to configure the PFC_OEN register on the RZ/G3E SoC for specific pins that require direction control via output-enable. On the RZ/G3E SoC, certain pins such as TXC_TXCLK must be switchable between input and output modes depending on the PHY interface mode (MII or RGMII). This behavior maps to the `output-enable` property in the device tree and requires configuring the PFC_OEN register. Update the r9a09g047_variable_pin_cfg array to include PB1, PE1, PL0, PL1, PL2, and PL4 with PIN_CFG_OEN flags to indicate support for this feature. Define a new rzg3e_hwcfg structure with SoC-specific pin names used for OEN bit mapping. Signed-off-by: Lad Prabhakar --- Changes: v4: new patch drivers/pinctrl/renesas/pinctrl-rzg2l.c | 45 ++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 792ca70bd9d1..00847a743d1f 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -398,6 +398,14 @@ static const u64 r9a09g047_variable_pin_cfg[] =3D { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 0, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 2, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 4, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 5, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 7, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= IEN), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS), @@ -406,6 +414,14 @@ static const u64 r9a09g047_variable_pin_cfg[] =3D { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 0, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 2, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 4, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 5, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 7, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= IEN), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= IEN), @@ -425,6 +441,14 @@ static const u64 r9a09g047_variable_pin_cfg[] =3D { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 5, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 7, RZV2H_MPXED_PIN_FUNCS), }; =20 static const u64 r9a09g057_variable_pin_cfg[] =3D { @@ -2052,17 +2076,17 @@ static const u64 r9a09g047_gpio_configs[] =3D { RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */ 0x0, RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ - RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */ RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */ RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ - RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */ RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */ RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ 0x0, RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */ - RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x35), /* PL */ RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */ 0x0, 0x0, @@ -3283,6 +3307,19 @@ static const char * const rzv2h_oen_pin_names[] =3D { "XSPI0_CKN", "XSPI0_CKP" }; =20 +static const char * const rzg3e_oen_pin_names[] =3D { + "PB1", "PE1", "PL4", "PL1", "PL2", "PL0" +}; + +static const struct rzg2l_hwcfg rzg3e_hwcfg =3D { + .regs =3D { + .pwpr =3D 0x3c04, + }, + .tint_start_index =3D 17, + .oen_pin_names =3D rzg3e_oen_pin_names, + .oen_pin_names_len =3D ARRAY_SIZE(rzg3e_oen_pin_names), +}; + static const struct rzg2l_hwcfg rzv2h_hwcfg =3D { .regs =3D { .pwpr =3D 0x3c04, @@ -3352,7 +3389,7 @@ static struct rzg2l_pinctrl_data r9a09g047_data =3D { .dedicated_pins =3D rzg3e_dedicated_pins, .n_port_pins =3D ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins =3D ARRAY_SIZE(rzg3e_dedicated_pins), - .hwcfg =3D &rzv2h_hwcfg, + .hwcfg =3D &rzg3e_hwcfg, .variable_pin_cfg =3D r9a09g047_variable_pin_cfg, .n_variable_pin_cfg =3D ARRAY_SIZE(r9a09g047_variable_pin_cfg), .num_custom_params =3D ARRAY_SIZE(renesas_rzv2h_custom_bindings), --=20 2.25.1 From nobody Wed Oct 8 05:36:32 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7C9724CE08; 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dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: J5+YdmRNSKOnN3uomudF6w== X-CSE-MsgGUID: oWfC5T+vSCu7irK4krP6oA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 02 Jul 2025 09:57:38 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.9]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id C1FA740E798E; Wed, 2 Jul 2025 09:57:32 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, richardcochran@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, biju.das.jz@bp.renesas.com, john.madieu@gmail.com, John Madieu Subject: [PATCH v4 4/4] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces Date: Wed, 2 Jul 2025 02:57:06 +0200 Message-ID: <20250702005706.1200059-5-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702005706.1200059-1-john.madieu.xa@bp.renesas.com> References: <20250702005706.1200059-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E SMAR= C EVK Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven --- Changes: v2: No changes but resending without dt-bindings patch v3: Updates mdio separately, based on phandles instead of node redefinition v4: - Update pinmux to add OEN support - Drops Tb and Rb tags initially collected .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3e-smarc-som.dtsi index f99a09d04ddd..f930e98a7ea9 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -26,6 +26,8 @@ / { compatible =3D "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r= 9a09g047"; =20 aliases { + ethernet0 =3D ð0; + ethernet1 =3D ð1; i2c2 =3D &i2c2; mmc0 =3D &sdhi0; mmc2 =3D &sdhi2; @@ -77,6 +79,24 @@ &audio_extal_clk { clock-frequency =3D <48000000>; }; =20 +ð0 { + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + + pinctrl-0 =3D <ð0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +ð1 { + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + + pinctrl-0 =3D <ð1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + &gpu { status =3D "okay"; mali-supply =3D <®_vdd0p8v_others>; @@ -102,7 +122,98 @@ raa215300: pmic@12 { }; }; =20 +&mdio0 { + phy0: ethernet-phy@7 { + compatible =3D "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + interrupts-extended =3D <&icu 3 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-psec =3D <1400>; + txc-skew-psec =3D <1400>; + rxdv-skew-psec =3D <0>; + txdv-skew-psec =3D <0>; + rxd0-skew-psec =3D <0>; + rxd1-skew-psec =3D <0>; + rxd2-skew-psec =3D <0>; + rxd3-skew-psec =3D <0>; + txd0-skew-psec =3D <0>; + txd1-skew-psec =3D <0>; + txd2-skew-psec =3D <0>; + txd3-skew-psec =3D <0>; + }; +}; + +&mdio1 { + phy1: ethernet-phy@7 { + compatible =3D "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + interrupts-extended =3D <&icu 16 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-psec =3D <1400>; + txc-skew-psec =3D <1400>; + rxdv-skew-psec =3D <0>; + txdv-skew-psec =3D <0>; + rxd0-skew-psec =3D <0>; + rxd1-skew-psec =3D <0>; + rxd2-skew-psec =3D <0>; + rxd3-skew-psec =3D <0>; + txd0-skew-psec =3D <0>; + txd1-skew-psec =3D <0>; + txd2-skew-psec =3D <0>; + txd3-skew-psec =3D <0>; + }; +}; + &pinctrl { + eth0_pins: eth0 { + clk0 { + pinmux =3D ; /* TXC */ + output-enable; + }; + + ctrl0 { + pinmux =3D , /* MDC */ + , /* MDIO */ + , /* PHY_INTR (IRQ2) */ + , /* RXD3 */ + , /* RXD2 */ + , /* RXD1 */ + , /* RXD0 */ + , /* RXC */ + , /* RX_CTL */ + , /* TXD3 */ + , /* TXD2 */ + , /* TXD1 */ + , /* TXD0 */ + ; /* TX_CTL */ + }; + }; + + eth1_pins: eth1 { + clk1 { + pinmux =3D ; /* TXC */ + output-enable; + }; + + ctrl1 { + + pinmux =3D , /* MDC */ + , /* MDIO */ + , /* PHY_INTR (IRQ15) */ + , /* RXD3 */ + , /* RXD2 */ + , /* RXD1 */ + , /* RXD0 */ + , /* RXC */ + , /* RX_CTL */ + , /* TXD3 */ + , /* TXD2 */ + , /* TXD1 */ + , /* TXD0 */ + ; /* TX_CTL */ + }; + }; + i2c2_pins: i2c { pinmux =3D , /* SCL2 */ ; /* SDA2 */ --=20 2.25.1