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Wed, 02 Jul 2025 09:05:25 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5629533q005667 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Jul 2025 09:05:03 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 2 Jul 2025 02:04:58 -0700 From: Taniya Das Date: Wed, 2 Jul 2025 14:34:21 +0530 Subject: [PATCH v11 01/10] clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250702-qcs615-mm-v10-clock-controllers-v11-1-9c216e1615ab@quicinc.com> References: <20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com> In-Reply-To: <20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Catalin Marinas" , Will Deacon CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ILQ_LBKPQLtx8rh7BKxJELHv-0lSN_3t X-Authority-Analysis: v=2.4 cv=YPWfyQGx c=1 sm=1 tr=0 ts=6864f655 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=rpD9z14lcGW1emOW4AAA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: ILQ_LBKPQLtx8rh7BKxJELHv-0lSN_3t X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAyMDA3MyBTYWx0ZWRfX5O+VoeTtRzWf zr14BfET5ubgcksEhv2a9+6VzFnkv30MP8fhvYfa3BRzU5mGX9YZianB6XSabmkhK2PSO82xntn VVBAFfY1u+Df+DATyDoX+9Oo67++b7P9zPX8F/hOViMIIRk7S0QOgYWvtns9PU1i7H8pidTpNNW Z2IkvfnclSFscI53tgqX90byCsblKVdZRpFEyMw5+dNakQ1GPZZXBNMeZ/V7HNjB4OiaK/AWzMg 123gQDKkjNyQDrLP9iyJyBWAsSLZATwkVCn+dFTwrxcszrETSlPICzsKulWzUKGrGOPibtSmHpI bm7l/v3mj+AC7ERD0yP/LsM81zA7CpjOdeDnkTyWXpaDH/v0zxcC9tX45EPcQDff/ImsLEstpft jof3OJ2lXv4iluBbhWt6YFIuhFvF2O1C+RiqfpXV4Ks7Kl1XTAoA6yv/xcRqVtj6wEnTEuzf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-02_01,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 adultscore=0 priorityscore=1501 bulkscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507020073 The alpha PLLs which slew to a new frequency at runtime would require the PLL to calibrate at the mid point of the VCO. Add the new PLL ops which can support the slewing of the PLL to a new frequency. Reviewed-by: Imran Shaik Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-alpha-pll.c | 192 +++++++++++++++++++++++++++++++++++= ---- drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 175 insertions(+), 18 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index d8e1cd1263317814da2d0414600988de4b87c56f..fec6eb376e2707deda11609fe5d= 0d45082048a0b 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -790,6 +790,29 @@ static int clk_alpha_pll_update_latch(struct clk_alpha= _pll *pll, return __clk_alpha_pll_update_latch(pll); } =20 +static void clk_alpha_pll_update_configs(struct clk_alpha_pll *pll, const = struct pll_vco *vco, + u32 l, u64 alpha, u32 alpha_width, bool alpha_en) +{ + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + + if (alpha_width > ALPHA_BITWIDTH) + alpha <<=3D alpha_width - ALPHA_BITWIDTH; + + if (alpha_width > 32) + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(alpha= )); + + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(alpha)); + + if (vco) { + regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_VCO_MASK << PLL_VCO_SHIFT, + vco->val << PLL_VCO_SHIFT); + } + + if (alpha_en) + regmap_set_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_ALPHA_EN); +} + static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate, int (*is_enabled)(struct clk_hw *)) @@ -807,24 +830,7 @@ static int __clk_alpha_pll_set_rate(struct clk_hw *hw,= unsigned long rate, return -EINVAL; } =20 - regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); - - if (alpha_width > ALPHA_BITWIDTH) - a <<=3D alpha_width - ALPHA_BITWIDTH; - - if (alpha_width > 32) - regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); - - regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); - - if (vco) { - regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), - PLL_VCO_MASK << PLL_VCO_SHIFT, - vco->val << PLL_VCO_SHIFT); - } - - regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), - PLL_ALPHA_EN, PLL_ALPHA_EN); + clk_alpha_pll_update_configs(pll, vco, l, a, alpha_width, true); =20 return clk_alpha_pll_update_latch(pll, is_enabled); } @@ -3017,3 +3023,153 @@ void qcom_clk_alpha_pll_configure(struct clk_alpha_= pll *pll, struct regmap *regm } } EXPORT_SYMBOL_GPL(qcom_clk_alpha_pll_configure); + +static int clk_alpha_pll_slew_update(struct clk_alpha_pll *pll) +{ + u32 val; + int ret; + + regmap_set_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE); + regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); + + ret =3D wait_for_pll_update(pll); + if (ret) + return ret; + /* + * Hardware programming mandates a wait of at least 570ns before polling = the LOCK + * detect bit. Have a delay of 1us just to be safe. + */ + udelay(1); + + return wait_for_pll_enable_lock(pll); +} + +static int clk_alpha_pll_slew_set_rate(struct clk_hw *hw, unsigned long ra= te, + unsigned long parent_rate) +{ + struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); + const struct pll_vco *curr_vco, *vco; + unsigned long freq_hz; + u64 a; + u32 l; + + freq_hz =3D alpha_pll_round_rate(rate, parent_rate, &l, &a, ALPHA_REG_BIT= WIDTH); + if (freq_hz !=3D rate) { + pr_err("alpha_pll: Call clk_set_rate with rounded rates!\n"); + return -EINVAL; + } + + curr_vco =3D alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); + if (!curr_vco) { + pr_err("alpha pll: not in a valid vco range\n"); + return -EINVAL; + } + + vco =3D alpha_pll_find_vco(pll, freq_hz); + if (!vco) { + pr_err("alpha pll: not in a valid vco range\n"); + return -EINVAL; + } + + /* + * Dynamic pll update will not support switching frequencies across + * vco ranges. In those cases fall back to normal alpha set rate. + */ + if (curr_vco->val !=3D vco->val) + return clk_alpha_pll_set_rate(hw, rate, parent_rate); + + clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, false); + + /* Ensure that the write above goes before slewing the PLL */ + mb(); + + if (clk_hw_is_enabled(hw)) + return clk_alpha_pll_slew_update(pll); + + return 0; +} + +/* + * Slewing plls should be bought up at frequency which is in the middle of= the + * desired VCO range. So after bringing up the pll at calibration freq, se= t it + * back to desired frequency(that was set by previous clk_set_rate). + */ +static int clk_alpha_pll_calibrate(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); + struct clk_hw *parent; + const struct pll_vco *vco; + unsigned long calibration_freq, freq_hz; + u64 a; + u32 l; + int rc; + + parent =3D clk_hw_get_parent(hw); + if (!parent) { + pr_err("alpha pll: no valid parent found\n"); + return -EINVAL; + } + + vco =3D alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); + if (!vco) { + pr_err("alpha pll: not in a valid vco range\n"); + return -EINVAL; + } + + /* + * As during slewing plls vco_sel won't be allowed to change, vco table + * should have only one entry table, i.e. index =3D 0, find the + * calibration frequency. + */ + calibration_freq =3D (pll->vco_table[0].min_freq + pll->vco_table[0].max_= freq) / 2; + + freq_hz =3D alpha_pll_round_rate(calibration_freq, clk_hw_get_rate(parent= ), + &l, &a, ALPHA_REG_BITWIDTH); + if (freq_hz !=3D calibration_freq) { + pr_err("alpha_pll: call clk_set_rate with rounded rates!\n"); + return -EINVAL; + } + + clk_alpha_pll_update_configs(pll, vco, l, a, ALPHA_REG_BITWIDTH, false); + + /* Bringup the pll at calibration frequency */ + rc =3D clk_alpha_pll_enable(hw); + if (rc) { + pr_err("alpha pll calibration failed\n"); + return rc; + } + + /* + * PLL is already running at calibration frequency. + * So slew pll to the previously set frequency. + */ + freq_hz =3D alpha_pll_round_rate(clk_hw_get_rate(hw), + clk_hw_get_rate(parent), &l, &a, ALPHA_REG_BITWIDTH); + + pr_debug("pll %s: setting back to required rate %lu, freq_hz %ld\n", + clk_hw_get_name(hw), clk_hw_get_rate(hw), freq_hz); + + clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, true); + + return clk_alpha_pll_slew_update(pll); +} + +static int clk_alpha_pll_slew_enable(struct clk_hw *hw) +{ + int rc; + + rc =3D clk_alpha_pll_calibrate(hw); + if (rc) + return rc; + + return clk_alpha_pll_enable(hw); +} + +const struct clk_ops clk_alpha_pll_slew_ops =3D { + .enable =3D clk_alpha_pll_slew_enable, + .disable =3D clk_alpha_pll_disable, + .recalc_rate =3D clk_alpha_pll_recalc_rate, + .round_rate =3D clk_alpha_pll_round_rate, + .set_rate =3D clk_alpha_pll_slew_set_rate, +}; +EXPORT_SYMBOL(clk_alpha_pll_slew_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index 7f35aaa7a35d88411beb11fd2be5d5dd5bfbe066..ff41aeab0ab9844cd4e43c9b8e1= ba0b50205e48e 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -206,6 +206,7 @@ extern const struct clk_ops clk_alpha_pll_rivian_evo_op= s; #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_o= ps =20 extern const struct clk_ops clk_alpha_pll_regera_ops; +extern const struct clk_ops clk_alpha_pll_slew_ops; =20 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *reg= map, const struct alpha_pll_config *config); --=20 2.34.1 From nobody Wed Oct 8 04:22:01 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5255323C51B; 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Wed, 02 Jul 2025 09:05:24 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5629588S026362 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Jul 2025 09:05:08 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 2 Jul 2025 02:05:03 -0700 From: Taniya Das Date: Wed, 2 Jul 2025 14:34:22 +0530 Subject: [PATCH v11 02/10] dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250702-qcs615-mm-v10-clock-controllers-v11-2-9c216e1615ab@quicinc.com> References: <20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com> In-Reply-To: <20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Catalin Marinas" , Will Deacon CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , , Taniya Das , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: CorIlRvsvRNNI5fDt3Kj6eqSYIvyYtm9 X-Authority-Analysis: v=2.4 cv=RJCzH5i+ c=1 sm=1 tr=0 ts=6864f654 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=VwQbUJbxAAAA:8 a=Ql2orbCSbd2v8qn6OVgA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: CorIlRvsvRNNI5fDt3Kj6eqSYIvyYtm9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAyMDA3MyBTYWx0ZWRfX6qSgBcwlOEwG PtivvBBMmFjGRRUzSLaqBbEhFYUieWGWTyxnl4VaEQBlOoBFf8G6Ma+RyA/GagR77gPDPlsEOpj 4QPFucsZeFvtq77XiOuBghtMoseejCH3JMonha8HgIXa3zfSsRY0RfzZu1VDj1Dntg/GTIRfDVD 7ubfcLht6rmHPbW4ujjsE+DbNzNPctzEuU2Lv18+h261x4q+TibR6WQ9SuhGz1yzthnHGd9rZzO eRdwYWPpfPzj3lLvfqgsBuiwzRdT3BSN6p8ozGhychN+jCJpgSt63OkrtvwYFOBZ2h/4h+XfWLg PBwLgTVhLLos/Hv6CBagqxjlfuCaE4+BZU0KCiV6brdIXLI7Z1tQU7ADMSZOKWGRwx1Frl7VWQC OhvIOGMXWjI29RAjL0tHEfbuc407VqGDmpt9lJNl01Ip8FeCgKirNWq+DSHhe2bagsV2gMVE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-02_01,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 priorityscore=1501 mlxlogscore=999 adultscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 phishscore=0 bulkscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507020073 Add DT bindings for the Camera clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm6350-camcc.yaml | 11 ++- include/dt-bindings/clock/qcom,qcs615-camcc.h | 110 +++++++++++++++++= ++++ 2 files changed, 118 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml index c03b30f64f359abd03e61a543522c81ce542e274..e31cd4300f7db7f5dd3d71fc4a1= 0ad6cc6537fde 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml @@ -8,16 +8,21 @@ title: Qualcomm Camera Clock & Reset Controller on SM6350 =20 maintainers: - Konrad Dybcio + - Taniya Das =20 description: | Qualcomm camera clock control module provides the clocks, resets and po= wer - domains on SM6350. + domains on SM6350 and QCS615 SoC. =20 - See also:: include/dt-bindings/clock/qcom,sm6350-camcc.h + See also: + include/dt-bindings/clock/qcom,qcs615-camcc.h + include/dt-bindings/clock/qcom,sm6350-camcc.h =20 properties: compatible: - const: qcom,sm6350-camcc + enum: + - qcom,qcs615-camcc + - qcom,sm6350-camcc =20 clocks: items: diff --git a/include/dt-bindings/clock/qcom,qcs615-camcc.h b/include/dt-bin= dings/clock/qcom,qcs615-camcc.h new file mode 100644 index 0000000000000000000000000000000000000000..aec57dddc06735a5c6c48a1e93a= 8c498bdb8726a --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs615-camcc.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_QCS615_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_QCS615_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_AREG_CLK 1 +#define CAM_CC_BPS_AXI_CLK 2 +#define CAM_CC_BPS_CLK 3 +#define CAM_CC_BPS_CLK_SRC 4 +#define CAM_CC_CAMNOC_ATB_CLK 5 +#define CAM_CC_CAMNOC_AXI_CLK 6 +#define CAM_CC_CCI_CLK 7 +#define CAM_CC_CCI_CLK_SRC 8 +#define CAM_CC_CORE_AHB_CLK 9 +#define CAM_CC_CPAS_AHB_CLK 10 +#define CAM_CC_CPHY_RX_CLK_SRC 11 +#define CAM_CC_CSI0PHYTIMER_CLK 12 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 13 +#define CAM_CC_CSI1PHYTIMER_CLK 14 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 15 +#define CAM_CC_CSI2PHYTIMER_CLK 16 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 17 +#define CAM_CC_CSIPHY0_CLK 18 +#define CAM_CC_CSIPHY1_CLK 19 +#define CAM_CC_CSIPHY2_CLK 20 +#define CAM_CC_FAST_AHB_CLK_SRC 21 +#define CAM_CC_ICP_ATB_CLK 22 +#define CAM_CC_ICP_CLK 23 +#define CAM_CC_ICP_CLK_SRC 24 +#define CAM_CC_ICP_CTI_CLK 25 +#define CAM_CC_ICP_TS_CLK 26 +#define CAM_CC_IFE_0_AXI_CLK 27 +#define CAM_CC_IFE_0_CLK 28 +#define CAM_CC_IFE_0_CLK_SRC 29 +#define CAM_CC_IFE_0_CPHY_RX_CLK 30 +#define CAM_CC_IFE_0_CSID_CLK 31 +#define CAM_CC_IFE_0_CSID_CLK_SRC 32 +#define CAM_CC_IFE_0_DSP_CLK 33 +#define CAM_CC_IFE_1_AXI_CLK 34 +#define CAM_CC_IFE_1_CLK 35 +#define CAM_CC_IFE_1_CLK_SRC 36 +#define CAM_CC_IFE_1_CPHY_RX_CLK 37 +#define CAM_CC_IFE_1_CSID_CLK 38 +#define CAM_CC_IFE_1_CSID_CLK_SRC 39 +#define CAM_CC_IFE_1_DSP_CLK 40 +#define CAM_CC_IFE_LITE_CLK 41 +#define CAM_CC_IFE_LITE_CLK_SRC 42 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 43 +#define CAM_CC_IFE_LITE_CSID_CLK 44 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 45 +#define CAM_CC_IPE_0_AHB_CLK 46 +#define CAM_CC_IPE_0_AREG_CLK 47 +#define CAM_CC_IPE_0_AXI_CLK 48 +#define CAM_CC_IPE_0_CLK 49 +#define CAM_CC_IPE_0_CLK_SRC 50 +#define CAM_CC_JPEG_CLK 51 +#define CAM_CC_JPEG_CLK_SRC 52 +#define CAM_CC_LRME_CLK 53 +#define CAM_CC_LRME_CLK_SRC 54 +#define CAM_CC_MCLK0_CLK 55 +#define CAM_CC_MCLK0_CLK_SRC 56 +#define CAM_CC_MCLK1_CLK 57 +#define CAM_CC_MCLK1_CLK_SRC 58 +#define CAM_CC_MCLK2_CLK 59 +#define CAM_CC_MCLK2_CLK_SRC 60 +#define CAM_CC_MCLK3_CLK 61 +#define CAM_CC_MCLK3_CLK_SRC 62 +#define CAM_CC_PLL0 63 +#define CAM_CC_PLL1 64 +#define CAM_CC_PLL2 65 +#define CAM_CC_PLL2_OUT_AUX2 66 +#define CAM_CC_PLL3 67 +#define CAM_CC_SLOW_AHB_CLK_SRC 68 +#define CAM_CC_SOC_AHB_CLK 69 +#define CAM_CC_SYS_TMR_CLK 70 + +/* CAM_CC power domains */ +#define BPS_GDSC 0 +#define IFE_0_GDSC 1 +#define IFE_1_GDSC 2 +#define IPE_0_GDSC 3 +#define TITAN_TOP_GDSC 4 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_CAMNOC_BCR 1 +#define CAM_CC_CCI_BCR 2 +#define CAM_CC_CPAS_BCR 3 +#define CAM_CC_CSI0PHY_BCR 4 +#define CAM_CC_CSI1PHY_BCR 5 +#define CAM_CC_CSI2PHY_BCR 6 +#define CAM_CC_ICP_BCR 7 +#define CAM_CC_IFE_0_BCR 8 +#define CAM_CC_IFE_1_BCR 9 +#define CAM_CC_IFE_LITE_BCR 10 +#define CAM_CC_IPE_0_BCR 11 +#define CAM_CC_JPEG_BCR 12 +#define CAM_CC_LRME_BCR 13 +#define CAM_CC_MCLK0_BCR 14 +#define CAM_CC_MCLK1_BCR 15 +#define CAM_CC_MCLK2_BCR 16 +#define CAM_CC_MCLK3_BCR 17 +#define CAM_CC_TITAN_TOP_BCR 18 + +#endif --=20 2.34.1 From nobody Wed Oct 8 04:22:01 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05A54245023; 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Wed, 02 Jul 2025 09:05:31 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56295EFF005994 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Jul 2025 09:05:14 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 2 Jul 2025 02:05:08 -0700 From: Taniya Das Date: Wed, 2 Jul 2025 14:34:23 +0530 Subject: [PATCH v11 03/10] clk: qcom: camcc-qcs615: Add QCS615 camera clock controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250702-qcs615-mm-v10-clock-controllers-v11-3-9c216e1615ab@quicinc.com> References: <20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com> In-Reply-To: <20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Catalin Marinas" , Will Deacon CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , , Taniya Das , Bryan O'Donoghue , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=Z+PsHGRA c=1 sm=1 tr=0 ts=6864f65b cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=75a0eyr4C_q1bDnl5JEA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAyMDA3MyBTYWx0ZWRfX47y4MMDX8nT0 Y2rPvI1J317XYSPKzAEP9dVkXRrH09rwxbHWnhYRgPOtBhtJchAVTHog28a6DuVaWVR8VthH/lX v68uCXrTo5upSUYvBoApuGZsHFGqVRzwfxHdUAXVN4W0LSWi70HYvuSKhaSYLrmKR7qKAfYXKAq 66VnOiLyBUiqEws1PToWful5V/nrqITHLxbbGVXhKiVnbnRdl49cHFtEKEiUFShRtAStgqOQo7u 8BdM3JjAverk37v2e1nYgwNQKsoNVSmhQLqhKAnw6g+u+H17GpVtt1mEygi1+mbUN0NeC9Kp5nk h2m2+M/ScZbuNlU3XS+5m8uyVLkY9WsuKqOqMxwGvUdkJIjKpHcS4gmoHZwfS588bpFrIy9UviN eSMZ7p6oqThMkv0AeKXGXZOzsnLJFQ/a0k5NYq/thoYvVw22rUV7GV2O1Vwi5/t/dnraFodq X-Proofpoint-GUID: H5vk3v4NfZXqHAyx3ysGWDKlkvIiPiZg X-Proofpoint-ORIG-GUID: H5vk3v4NfZXqHAyx3ysGWDKlkvIiPiZg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-02_01,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 spamscore=0 adultscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507020073 Add support for the camera clock controller for camera clients to be able to request for camcc clocks on QCS615 platform. Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/camcc-qcs615.c | 1597 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1608 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 36d6e6e1e7f0162d53f02f39125f4593517e0dba..f4c9fb2b4fb027261bc4eac2eeb= 3e84dc6aae877 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -493,6 +493,16 @@ config QCM_DISPCC_2290 Say Y if you want to support display devices and functionality such as splash screen. =20 +config QCS_CAMCC_615 + tristate "QCS615 Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCS_GCC_615 + help + Support for the camera clock controller on Qualcomm Technologies, Inc + QCS615 devices. + Say Y if you want to support camera devices and functionality such as + capturing pictures. + config QCS_GCC_404 tristate "QCS404 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ab59434338bb6d6f49b0af94ff0f85cb386a16db..c5f97e0dccd2b72b1bed9ea8e93= f0cdee301912a 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) +=3D clk-rpmh.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) +=3D clk-smd-rpm.o obj-$(CONFIG_QCM_GCC_2290) +=3D gcc-qcm2290.o obj-$(CONFIG_QCM_DISPCC_2290) +=3D dispcc-qcm2290.o +obj-$(CONFIG_QCS_CAMCC_615) +=3D camcc-qcs615.o obj-$(CONFIG_QCS_GCC_404) +=3D gcc-qcs404.o obj-$(CONFIG_QCS_GCC_615) +=3D gcc-qcs615.o obj-$(CONFIG_QCS_GCC_8300) +=3D gcc-qcs8300.o diff --git a/drivers/clk/qcom/camcc-qcs615.c b/drivers/clk/qcom/camcc-qcs61= 5.c new file mode 100644 index 0000000000000000000000000000000000000000..c063a3bfacd006af0fcbdbd9afb= aa22ab83bcf8e --- /dev/null +++ b/drivers/clk/qcom/camcc-qcs615.c @@ -0,0 +1,1597 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, +}; + +enum { + P_BI_TCXO, + P_CAM_CC_PLL0_OUT_AUX, + P_CAM_CC_PLL1_OUT_AUX, + P_CAM_CC_PLL2_OUT_AUX2, + P_CAM_CC_PLL2_OUT_EARLY, + P_CAM_CC_PLL3_OUT_MAIN, +}; + +static const struct pll_vco brammo_vco[] =3D { + { 500000000, 1250000000, 0 }, +}; + +static const struct pll_vco spark_vco[] =3D { + { 1000000000, 2100000000, 0 }, + { 750000000, 1500000000, 1 }, + { 500000000, 1000000000, 2 }, + { 300000000, 500000000, 3 }, + { 550000000, 1100000000, 4 }, +}; + +/* 600MHz configuration VCO - 2 */ +static const struct alpha_pll_config cam_cc_pll0_config =3D { + .l =3D 0x1f, + .alpha_hi =3D 0x40, + .alpha_en_mask =3D BIT(24), + .vco_val =3D BIT(21), + .vco_mask =3D GENMASK(21, 20), + .aux_output_mask =3D BIT(1), + .config_ctl_val =3D 0x4001055b, + .test_ctl_hi_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, +}; + +static struct clk_alpha_pll cam_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &cam_cc_pll0_config, + .vco_table =3D spark_vco, + .num_vco =3D ARRAY_SIZE(spark_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_ops, + }, + }, +}; + +/* 808MHz configuration VCO - 2 */ +static struct alpha_pll_config cam_cc_pll1_config =3D { + .l =3D 0x2a, + .alpha_hi =3D 0x15, + .alpha =3D 0x55555555, + .alpha_en_mask =3D BIT(24), + .vco_val =3D BIT(21), + .vco_mask =3D GENMASK(21, 20), + .aux_output_mask =3D BIT(1), + .config_ctl_val =3D 0x4001055b, + .test_ctl_hi_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, +}; + +static struct clk_alpha_pll cam_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &cam_cc_pll1_config, + .vco_table =3D spark_vco, + .num_vco =3D ARRAY_SIZE(spark_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_ops, + }, + }, +}; + +/* 960MHz configuration VCO - 0 */ +static struct alpha_pll_config cam_cc_pll2_config =3D { + .l =3D 0x32, + .vco_val =3D 0x0, + .vco_mask =3D GENMASK(21, 20), + .early_output_mask =3D BIT(3), + .aux2_output_mask =3D BIT(2), + .post_div_val =3D 0x1 << 8, + .post_div_mask =3D 0x3 << 8, + .config_ctl_val =3D 0x04289, + .test_ctl_val =3D 0x08000000, + .test_ctl_mask =3D 0x08000000, +}; + +static struct clk_alpha_pll cam_cc_pll2 =3D { + .offset =3D 0x2000, + .config =3D &cam_cc_pll2_config, + .vco_table =3D brammo_vco, + .num_vco =3D ARRAY_SIZE(brammo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux2[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux2 =3D { + .offset =3D 0x2000, + .post_div_shift =3D 8, + .post_div_table =3D post_div_table_cam_cc_pll2_out_aux2, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux2), + .width =3D 2, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll2_out_aux2", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll2.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_ops, + }, +}; + +/* 1080MHz configuration - VCO - 0 */ +static struct alpha_pll_config cam_cc_pll3_config =3D { + .l =3D 0x38, + .alpha_hi =3D 0x40, + .alpha_en_mask =3D BIT(24), + .vco_val =3D 0x0, + .vco_mask =3D GENMASK(21, 20), + .main_output_mask =3D BIT(0), + .config_ctl_val =3D 0x4001055b, + .test_ctl_hi_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, +}; + +static struct clk_alpha_pll cam_cc_pll3 =3D { + .offset =3D 0x3000, + .config =3D &cam_cc_pll3_config, + .vco_table =3D spark_vco, + .num_vco =3D ARRAY_SIZE(spark_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll3", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_ops, + }, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL1_OUT_AUX, 2 }, + { P_CAM_CC_PLL0_OUT_AUX, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll1.clkr.hw }, + { .hw =3D &cam_cc_pll0.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EARLY, 4 }, + { P_CAM_CC_PLL3_OUT_MAIN, 5 }, + { P_CAM_CC_PLL0_OUT_AUX, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll2.clkr.hw }, + { .hw =3D &cam_cc_pll3.clkr.hw }, + { .hw =3D &cam_cc_pll0.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL1_OUT_AUX, 2 }, + { P_CAM_CC_PLL2_OUT_EARLY, 4 }, + { P_CAM_CC_PLL3_OUT_MAIN, 5 }, + { P_CAM_CC_PLL0_OUT_AUX, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll1.clkr.hw }, + { .hw =3D &cam_cc_pll2.clkr.hw }, + { .hw =3D &cam_cc_pll3.clkr.hw }, + { .hw =3D &cam_cc_pll0.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_AUX2, 1 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll2_out_aux2.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL3_OUT_MAIN, 5 }, + { P_CAM_CC_PLL0_OUT_AUX, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll3.clkr.hw }, + { .hw =3D &cam_cc_pll0.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_AUX, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL1_OUT_AUX, 2 }, + { P_CAM_CC_PLL3_OUT_MAIN, 5 }, + { P_CAM_CC_PLL0_OUT_AUX, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll1.clkr.hw }, + { .hw =3D &cam_cc_pll3.clkr.hw }, + { .hw =3D &cam_cc_pll0.clkr.hw }, +}; + +static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] =3D { + F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), + F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), + F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), + F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), + F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_AUX, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_bps_clk_src =3D { + .cmd_rcgr =3D 0x6010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_bps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_bps_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_clk_src[] =3D { + F(37500000, P_CAM_CC_PLL0_OUT_AUX, 16, 0, 0), + F(50000000, P_CAM_CC_PLL0_OUT_AUX, 12, 0, 0), + F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cci_clk_src =3D { + .cmd_rcgr =3D 0xb0d8, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_5, + .freq_tbl =3D ftbl_cam_cc_cci_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_clk_src", + .parent_data =3D cam_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_5), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] =3D { + F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), + F(269333333, P_CAM_CC_PLL1_OUT_AUX, 3, 0, 0), + F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), + F(384000000, P_CAM_CC_PLL2_OUT_EARLY, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src =3D { + .cmd_rcgr =3D 0x9064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_2, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cphy_rx_clk_src", + .parent_data =3D cam_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] =3D { + F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), + F(269333333, P_CAM_CC_PLL1_OUT_AUX, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src =3D { + .cmd_rcgr =3D 0x5004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi0phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src =3D { + .cmd_rcgr =3D 0x5028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi1phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src =3D { + .cmd_rcgr =3D 0x504c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi2phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] =3D { + F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_AUX, 2, 0, 0), + F(404000000, P_CAM_CC_PLL1_OUT_AUX, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src =3D { + .cmd_rcgr =3D 0x603c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_fast_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_fast_ahb_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] =3D { + F(240000000, P_CAM_CC_PLL0_OUT_AUX, 2.5, 0, 0), + F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), + F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), + F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), + F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_AUX, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_icp_clk_src =3D { + .cmd_rcgr =3D 0xb088, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_icp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] =3D { + F(240000000, P_CAM_CC_PLL0_OUT_AUX, 2.5, 0, 0), + F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), + F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), + F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_AUX, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_0_clk_src =3D { + .cmd_rcgr =3D 0x9010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_4, + .freq_tbl =3D ftbl_cam_cc_ife_0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_clk_src", + .parent_data =3D cam_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_4), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] =3D { + F(100000000, P_CAM_CC_PLL0_OUT_AUX, 6, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), + F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), + F(404000000, P_CAM_CC_PLL1_OUT_AUX, 2, 0, 0), + F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), + F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_0_csid_clk_src =3D { + .cmd_rcgr =3D 0x903c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_2, + .freq_tbl =3D ftbl_cam_cc_ife_0_csid_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_csid_clk_src", + .parent_data =3D cam_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_1_clk_src =3D { + .cmd_rcgr =3D 0xa010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_4, + .freq_tbl =3D ftbl_cam_cc_ife_0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_clk_src", + .parent_data =3D cam_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_4), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_1_csid_clk_src =3D { + .cmd_rcgr =3D 0xa034, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_2, + .freq_tbl =3D ftbl_cam_cc_ife_0_csid_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_csid_clk_src", + .parent_data =3D cam_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src =3D { + .cmd_rcgr =3D 0xb004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_4, + .freq_tbl =3D ftbl_cam_cc_ife_0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_clk_src", + .parent_data =3D cam_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_4), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src =3D { + .cmd_rcgr =3D 0xb024, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_2, + .freq_tbl =3D ftbl_cam_cc_ife_0_csid_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_csid_clk_src", + .parent_data =3D cam_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ipe_0_clk_src =3D { + .cmd_rcgr =3D 0x7010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_icp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_0_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] =3D { + F(66666667, P_CAM_CC_PLL0_OUT_AUX, 9, 0, 0), + F(133333333, P_CAM_CC_PLL0_OUT_AUX, 4.5, 0, 0), + F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), + F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), + F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_AUX, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_jpeg_clk_src =3D { + .cmd_rcgr =3D 0xb04c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_jpeg_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_jpeg_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] =3D { + F(200000000, P_CAM_CC_PLL0_OUT_AUX, 3, 0, 0), + F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_AUX, 2, 0, 0), + F(404000000, P_CAM_CC_PLL1_OUT_AUX, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_lrme_clk_src =3D { + .cmd_rcgr =3D 0xb0f8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_6, + .freq_tbl =3D ftbl_cam_cc_lrme_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_lrme_clk_src", + .parent_data =3D cam_cc_parent_data_6, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_6), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_CAM_CC_PLL2_OUT_AUX2, 10, 1, 2), + F(34285714, P_CAM_CC_PLL2_OUT_AUX2, 14, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_mclk0_clk_src =3D { + .cmd_rcgr =3D 0x4004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_3, + .freq_tbl =3D ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk0_clk_src", + .parent_data =3D cam_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk1_clk_src =3D { + .cmd_rcgr =3D 0x4024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_3, + .freq_tbl =3D ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk1_clk_src", + .parent_data =3D cam_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk2_clk_src =3D { + .cmd_rcgr =3D 0x4044, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_3, + .freq_tbl =3D ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk2_clk_src", + .parent_data =3D cam_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk3_clk_src =3D { + .cmd_rcgr =3D 0x4064, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_3, + .freq_tbl =3D ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk3_clk_src", + .parent_data =3D cam_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] =3D { + F(80000000, P_CAM_CC_PLL0_OUT_AUX, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src =3D { + .cmd_rcgr =3D 0x6058, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_slow_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_slow_ahb_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch cam_cc_bps_ahb_clk =3D { + .halt_reg =3D 0x6070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_bps_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_areg_clk =3D { + .halt_reg =3D 0x6054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_bps_areg_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_axi_clk =3D { + .halt_reg =3D 0x6038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_bps_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_clk =3D { + .halt_reg =3D 0x6028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_bps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_bps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_clk =3D { + .halt_reg =3D 0xb124, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb124, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_clk =3D { + .halt_reg =3D 0xb0f0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb0f0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_core_ahb_clk =3D { + .halt_reg =3D 0xb144, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb144, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_core_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ahb_clk =3D { + .halt_reg =3D 0xb11c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb11c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cpas_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk =3D { + .halt_reg =3D 0x501c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x501c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi0phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk =3D { + .halt_reg =3D 0x5040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi1phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi2phytimer_clk =3D { + .halt_reg =3D 0x5064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi2phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk =3D { + .halt_reg =3D 0x5020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk =3D { + .halt_reg =3D 0x5044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy2_clk =3D { + .halt_reg =3D 0x5068, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_clk =3D { + .halt_reg =3D 0xb0a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb0a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_icp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_axi_clk =3D { + .halt_reg =3D 0x9080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_clk =3D { + .halt_reg =3D 0x9028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_cphy_rx_clk =3D { + .halt_reg =3D 0x907c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x907c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_cphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_csid_clk =3D { + .halt_reg =3D 0x9054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_csid_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_csid_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_dsp_clk =3D { + .halt_reg =3D 0x9038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_dsp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_axi_clk =3D { + .halt_reg =3D 0xa058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_clk =3D { + .halt_reg =3D 0xa028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_cphy_rx_clk =3D { + .halt_reg =3D 0xa054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_cphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_csid_clk =3D { + .halt_reg =3D 0xa04c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa04c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_csid_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_csid_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_dsp_clk =3D { + .halt_reg =3D 0xa030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_dsp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk =3D { + .halt_reg =3D 0xb01c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk =3D { + .halt_reg =3D 0xb044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_cphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk =3D { + .halt_reg =3D 0xb03c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb03c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_csid_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_ahb_clk =3D { + .halt_reg =3D 0x7040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x7040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_areg_clk =3D { + .halt_reg =3D 0x703c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x703c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_0_areg_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_axi_clk =3D { + .halt_reg =3D 0x7038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x7038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_0_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_clk =3D { + .halt_reg =3D 0x7028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x7028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_clk =3D { + .halt_reg =3D 0xb064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_jpeg_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_lrme_clk =3D { + .halt_reg =3D 0xb110, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb110, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_lrme_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_lrme_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk0_clk =3D { + .halt_reg =3D 0x401c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x401c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_mclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk1_clk =3D { + .halt_reg =3D 0x403c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x403c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_mclk1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk2_clk =3D { + .halt_reg =3D 0x405c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x405c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_mclk2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk3_clk =3D { + .halt_reg =3D 0x407c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x407c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_mclk3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_soc_ahb_clk =3D { + .halt_reg =3D 0xb140, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb140, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_soc_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sys_tmr_clk =3D { + .halt_reg =3D 0xb0a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb0a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sys_tmr_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc titan_top_gdsc =3D { + .gdscr =3D 0xb134, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "titan_top_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR, +}; + +static struct gdsc bps_gdsc =3D { + .gdscr =3D 0x6004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "bps_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &titan_top_gdsc.pd, + .flags =3D POLL_CFG_GDSCR, +}; + +static struct gdsc ife_0_gdsc =3D { + .gdscr =3D 0x9004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "ife_0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &titan_top_gdsc.pd, + .flags =3D POLL_CFG_GDSCR, +}; + +static struct gdsc ife_1_gdsc =3D { + .gdscr =3D 0xa004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "ife_1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &titan_top_gdsc.pd, + .flags =3D POLL_CFG_GDSCR, +}; + +static struct gdsc ipe_0_gdsc =3D { + .gdscr =3D 0x7004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "ipe_0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &titan_top_gdsc.pd, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *cam_cc_qcs615_clocks[] =3D { + [CAM_CC_BPS_AHB_CLK] =3D &cam_cc_bps_ahb_clk.clkr, + [CAM_CC_BPS_AREG_CLK] =3D &cam_cc_bps_areg_clk.clkr, + [CAM_CC_BPS_AXI_CLK] =3D &cam_cc_bps_axi_clk.clkr, + [CAM_CC_BPS_CLK] =3D &cam_cc_bps_clk.clkr, + [CAM_CC_BPS_CLK_SRC] =3D &cam_cc_bps_clk_src.clkr, + [CAM_CC_CAMNOC_AXI_CLK] =3D &cam_cc_camnoc_axi_clk.clkr, + [CAM_CC_CCI_CLK] =3D &cam_cc_cci_clk.clkr, + [CAM_CC_CCI_CLK_SRC] =3D &cam_cc_cci_clk_src.clkr, + [CAM_CC_CORE_AHB_CLK] =3D &cam_cc_core_ahb_clk.clkr, + [CAM_CC_CPAS_AHB_CLK] =3D &cam_cc_cpas_ahb_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] =3D &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] =3D &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] =3D &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] =3D &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] =3D &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI2PHYTIMER_CLK] =3D &cam_cc_csi2phytimer_clk.clkr, + [CAM_CC_CSI2PHYTIMER_CLK_SRC] =3D &cam_cc_csi2phytimer_clk_src.clkr, + [CAM_CC_CSIPHY0_CLK] =3D &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] =3D &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY2_CLK] =3D &cam_cc_csiphy2_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] =3D &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_ICP_CLK] =3D &cam_cc_icp_clk.clkr, + [CAM_CC_ICP_CLK_SRC] =3D &cam_cc_icp_clk_src.clkr, + [CAM_CC_IFE_0_AXI_CLK] =3D &cam_cc_ife_0_axi_clk.clkr, + [CAM_CC_IFE_0_CLK] =3D &cam_cc_ife_0_clk.clkr, + [CAM_CC_IFE_0_CLK_SRC] =3D &cam_cc_ife_0_clk_src.clkr, + [CAM_CC_IFE_0_CPHY_RX_CLK] =3D &cam_cc_ife_0_cphy_rx_clk.clkr, + [CAM_CC_IFE_0_CSID_CLK] =3D &cam_cc_ife_0_csid_clk.clkr, + [CAM_CC_IFE_0_CSID_CLK_SRC] =3D &cam_cc_ife_0_csid_clk_src.clkr, + [CAM_CC_IFE_0_DSP_CLK] =3D &cam_cc_ife_0_dsp_clk.clkr, + [CAM_CC_IFE_1_AXI_CLK] =3D &cam_cc_ife_1_axi_clk.clkr, + [CAM_CC_IFE_1_CLK] =3D &cam_cc_ife_1_clk.clkr, + [CAM_CC_IFE_1_CLK_SRC] =3D &cam_cc_ife_1_clk_src.clkr, + [CAM_CC_IFE_1_CPHY_RX_CLK] =3D &cam_cc_ife_1_cphy_rx_clk.clkr, + [CAM_CC_IFE_1_CSID_CLK] =3D &cam_cc_ife_1_csid_clk.clkr, + [CAM_CC_IFE_1_CSID_CLK_SRC] =3D &cam_cc_ife_1_csid_clk_src.clkr, + [CAM_CC_IFE_1_DSP_CLK] =3D &cam_cc_ife_1_dsp_clk.clkr, + [CAM_CC_IFE_LITE_CLK] =3D &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] =3D &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] =3D &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] =3D &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] =3D &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_0_AHB_CLK] =3D &cam_cc_ipe_0_ahb_clk.clkr, + [CAM_CC_IPE_0_AREG_CLK] =3D &cam_cc_ipe_0_areg_clk.clkr, + [CAM_CC_IPE_0_AXI_CLK] =3D &cam_cc_ipe_0_axi_clk.clkr, + [CAM_CC_IPE_0_CLK] =3D &cam_cc_ipe_0_clk.clkr, + [CAM_CC_IPE_0_CLK_SRC] =3D &cam_cc_ipe_0_clk_src.clkr, + [CAM_CC_JPEG_CLK] =3D &cam_cc_jpeg_clk.clkr, + [CAM_CC_JPEG_CLK_SRC] =3D &cam_cc_jpeg_clk_src.clkr, + [CAM_CC_LRME_CLK] =3D &cam_cc_lrme_clk.clkr, + [CAM_CC_LRME_CLK_SRC] =3D &cam_cc_lrme_clk_src.clkr, + [CAM_CC_MCLK0_CLK] =3D &cam_cc_mclk0_clk.clkr, + [CAM_CC_MCLK0_CLK_SRC] =3D &cam_cc_mclk0_clk_src.clkr, + [CAM_CC_MCLK1_CLK] =3D &cam_cc_mclk1_clk.clkr, + [CAM_CC_MCLK1_CLK_SRC] =3D &cam_cc_mclk1_clk_src.clkr, + [CAM_CC_MCLK2_CLK] =3D &cam_cc_mclk2_clk.clkr, + [CAM_CC_MCLK2_CLK_SRC] =3D &cam_cc_mclk2_clk_src.clkr, + [CAM_CC_MCLK3_CLK] =3D &cam_cc_mclk3_clk.clkr, + [CAM_CC_MCLK3_CLK_SRC] =3D &cam_cc_mclk3_clk_src.clkr, + [CAM_CC_PLL0] =3D &cam_cc_pll0.clkr, + [CAM_CC_PLL1] =3D &cam_cc_pll1.clkr, + [CAM_CC_PLL2] =3D &cam_cc_pll2.clkr, + [CAM_CC_PLL2_OUT_AUX2] =3D &cam_cc_pll2_out_aux2.clkr, + [CAM_CC_PLL3] =3D &cam_cc_pll3.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] =3D &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_SOC_AHB_CLK] =3D &cam_cc_soc_ahb_clk.clkr, + [CAM_CC_SYS_TMR_CLK] =3D &cam_cc_sys_tmr_clk.clkr, +}; + +static struct gdsc *cam_cc_qcs615_gdscs[] =3D { + [BPS_GDSC] =3D &bps_gdsc, + [IFE_0_GDSC] =3D &ife_0_gdsc, + [IFE_1_GDSC] =3D &ife_1_gdsc, + [IPE_0_GDSC] =3D &ipe_0_gdsc, + [TITAN_TOP_GDSC] =3D &titan_top_gdsc, +}; + +static const struct qcom_reset_map cam_cc_qcs615_resets[] =3D { + [CAM_CC_BPS_BCR] =3D { 0x6000 }, + [CAM_CC_CAMNOC_BCR] =3D { 0xb120 }, + [CAM_CC_CCI_BCR] =3D { 0xb0d4 }, + [CAM_CC_CPAS_BCR] =3D { 0xb118 }, + [CAM_CC_CSI0PHY_BCR] =3D { 0x5000 }, + [CAM_CC_CSI1PHY_BCR] =3D { 0x5024 }, + [CAM_CC_CSI2PHY_BCR] =3D { 0x5048 }, + [CAM_CC_ICP_BCR] =3D { 0xb074 }, + [CAM_CC_IFE_0_BCR] =3D { 0x9000 }, + [CAM_CC_IFE_1_BCR] =3D { 0xa000 }, + [CAM_CC_IFE_LITE_BCR] =3D { 0xb000 }, + [CAM_CC_IPE_0_BCR] =3D { 0x7000 }, + [CAM_CC_JPEG_BCR] =3D { 0xb048 }, + [CAM_CC_LRME_BCR] =3D { 0xb0f4 }, + [CAM_CC_MCLK0_BCR] =3D { 0x4000 }, + [CAM_CC_MCLK1_BCR] =3D { 0x4020 }, + [CAM_CC_MCLK2_BCR] =3D { 0x4040 }, + [CAM_CC_MCLK3_BCR] =3D { 0x4060 }, + [CAM_CC_TITAN_TOP_BCR] =3D { 0xb130 }, +}; + +static struct clk_alpha_pll *cam_cc_qcs615_plls[] =3D { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, +}; + +static const struct regmap_config cam_cc_qcs615_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xd004, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data cam_cc_qcs615_driver_data =3D { + .alpha_plls =3D cam_cc_qcs615_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_cc_qcs615_plls), +}; + +static const struct qcom_cc_desc cam_cc_qcs615_desc =3D { + .config =3D &cam_cc_qcs615_regmap_config, + .clks =3D cam_cc_qcs615_clocks, + .num_clks =3D ARRAY_SIZE(cam_cc_qcs615_clocks), + .resets =3D cam_cc_qcs615_resets, + .num_resets =3D ARRAY_SIZE(cam_cc_qcs615_resets), + .gdscs =3D cam_cc_qcs615_gdscs, + .num_gdscs =3D ARRAY_SIZE(cam_cc_qcs615_gdscs), + .driver_data =3D &cam_cc_qcs615_driver_data, +}; + +static const struct of_device_id cam_cc_qcs615_match_table[] =3D { + { .compatible =3D "qcom,qcs615-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_qcs615_match_table); + +static int cam_cc_qcs615_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &cam_cc_qcs615_desc); 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Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Taniya Das --- .../bindings/clock/qcom,qcs615-dispcc.yaml | 55 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,qcs615-dispcc.h | 52 ++++++++++++++++++= ++ 2 files changed, 107 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,qcs615-dispcc.yam= l b/Documentation/devicetree/bindings/clock/qcom,qcs615-dispcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..d566f19beb0d76369ebfa827222= 4d01e7ecee63c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qcs615-dispcc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das + +description: | + Qualcomm display clock control module provides the clocks, resets and po= wer + domains on QCS615. + + See also: include/dt-bindings/clock/qcom,qcs615-dispcc.h + +properties: + compatible: + const: qcom,qcs615-dispcc + + clocks: + items: + - description: Board XO source + - description: GPLL0 clock source from GCC + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Pixel clock from DSI PHY1 + - description: Display port PLL link clock + - description: Display port PLL VCO DIV clock + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + clock-controller@af00000 { + compatible =3D "qcom,qcs615-dispcc"; + reg =3D <0x0af00000 0x20000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dp_phy 0>, + <&mdss_dp_vco 0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,qcs615-dispcc.h b/include/dt-bi= ndings/clock/qcom,qcs615-dispcc.h new file mode 100644 index 0000000000000000000000000000000000000000..9a29945c5762ce06285a2f4e6a5= 5c13bfaadc5c2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs615-dispcc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_QCS615_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_QCS615_H + +/* DISP_CC clocks */ +#define DISP_CC_MDSS_AHB_CLK 0 +#define DISP_CC_MDSS_AHB_CLK_SRC 1 +#define DISP_CC_MDSS_BYTE0_CLK 2 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 5 +#define DISP_CC_MDSS_DP_AUX_CLK 6 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 7 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 8 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 9 +#define DISP_CC_MDSS_DP_LINK_CLK 10 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 11 +#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 12 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 13 +#define DISP_CC_MDSS_DP_PIXEL1_CLK 14 +#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 15 +#define DISP_CC_MDSS_DP_PIXEL_CLK 16 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17 +#define DISP_CC_MDSS_ESC0_CLK 18 +#define DISP_CC_MDSS_ESC0_CLK_SRC 19 +#define DISP_CC_MDSS_MDP_CLK 20 +#define DISP_CC_MDSS_MDP_CLK_SRC 21 +#define DISP_CC_MDSS_MDP_LUT_CLK 22 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23 +#define DISP_CC_MDSS_PCLK0_CLK 24 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 25 +#define DISP_CC_MDSS_ROT_CLK 26 +#define DISP_CC_MDSS_ROT_CLK_SRC 27 +#define DISP_CC_MDSS_RSCC_AHB_CLK 28 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 29 +#define DISP_CC_MDSS_VSYNC_CLK 30 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 31 +#define DISP_CC_PLL0 32 +#define DISP_CC_XO_CLK 33 + +/* DISP_CC power domains */ +#define MDSS_CORE_GDSC 0 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + +#endif --=20 2.34.1 From nobody Wed Oct 8 04:22:01 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4750241682; 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Wed, 02 Jul 2025 09:05:27 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56295OkC006551 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Jul 2025 09:05:24 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 2 Jul 2025 02:05:19 -0700 From: Taniya Das Date: Wed, 2 Jul 2025 14:34:25 +0530 Subject: [PATCH v11 05/10] clk: qcom: dispcc-qcs615: Add QCS615 display clock controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250702-qcs615-mm-v10-clock-controllers-v11-5-9c216e1615ab@quicinc.com> References: <20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com> In-Reply-To: <20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Catalin Marinas" , Will Deacon CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , , Taniya Das , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=C4TpyRP+ c=1 sm=1 tr=0 ts=6864f657 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=c25-7s5_q1pB3N3cfEQA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: -6d9yqeaAFYQO4M5s9cHy5UGaWeJ_vy9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAyMDA3MyBTYWx0ZWRfX77o/bS7WYah7 9h1LdrhDvjDVH8yFCwVzV7PHavpboVNo/S9+tIFmgY3oGm13WQgTFcWlIdMp7KerOk4YDLLGjRJ I+zdFStCu6uwlMjb0ME4f+T16Jy7hryTJEtO1cd58fVYrisfEOn0gXppaSPsQEDQARffVdvU8ZO Qjup/gt4KmsZWQgiCG+BcS9U+F9XbA2ablt+MUHeI5y09WBbm47kWJ55/cdhdM1Yg/yh8Koeu+o BGHRiE9fpYipCsKVZRivoLYZ2nJqPV6jrFUhkuiKmV3vW4vQcssjpSsUF9fIshzvHlXth9rjK/1 kdB9JA8bhuchhmh/ilCZIgKrBU9ANcQUapP2sDMyeSVzTTDkiDWAszoFOkaUDNWajFQBSpkAexL NdaSFAVYt4s14yQJrjMdgQEMBxxnaesTstIBdISNqH4Qsxzlgcbt/aH4mWSsU5TJ8Z/WURw9 X-Proofpoint-GUID: -6d9yqeaAFYQO4M5s9cHy5UGaWeJ_vy9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-02_01,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507020073 Add support for the display clock controller for display clients to be able to request for the clocks on QCS615 platform. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-qcs615.c | 792 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 802 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index f4c9fb2b4fb027261bc4eac2eeb3e84dc6aae877..19f105a1e33a705ddc11fd6fe22= 6a4a2a5cea9a2 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -493,6 +493,15 @@ config QCM_DISPCC_2290 Say Y if you want to support display devices and functionality such as splash screen. =20 +config QCS_DISPCC_615 + tristate "QCS615 Display Clock Controller" + select QCM_GCC_615 + help + Support for the display clock controller on Qualcomm Technologies, Inc + QCS615 devices. + Say Y if you want to support display devices and functionality such as + splash screen. + config QCS_CAMCC_615 tristate "QCS615 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index c5f97e0dccd2b72b1bed9ea8e93f0cdee301912a..4783f217543cb09ea25e9a537f5= 128b0fa89dec2 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) +=3D clk-rpmh.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) +=3D clk-smd-rpm.o obj-$(CONFIG_QCM_GCC_2290) +=3D gcc-qcm2290.o obj-$(CONFIG_QCM_DISPCC_2290) +=3D dispcc-qcm2290.o +obj-$(CONFIG_QCS_DISPCC_615) +=3D dispcc-qcs615.o obj-$(CONFIG_QCS_CAMCC_615) +=3D camcc-qcs615.o obj-$(CONFIG_QCS_GCC_404) +=3D gcc-qcs404.o obj-$(CONFIG_QCS_GCC_615) +=3D gcc-qcs615.o diff --git a/drivers/clk/qcom/dispcc-qcs615.c b/drivers/clk/qcom/dispcc-qcs= 615.c new file mode 100644 index 0000000000000000000000000000000000000000..4a6d7846609882d8d788fe1c1cd= 8386cdfe37136 --- /dev/null +++ b/drivers/clk/qcom/dispcc-qcs615.c @@ -0,0 +1,792 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0, + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DSI1_PHY_PLL_OUT_DSICLK, + DT_DP_PHY_PLL_LINK_CLK, + DT_DP_PHY_PLL_VCO_DIV_CLK, +}; + +enum { + P_BI_TCXO, + P_DISP_CC_PLL0_OUT_MAIN, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_GPLL0_OUT_MAIN, +}; + +static const struct pll_vco disp_cc_pll_vco[] =3D { + { 500000000, 1000000000, 2 }, +}; + +/* 576MHz configuration VCO - 2 */ +static struct alpha_pll_config disp_cc_pll0_config =3D { + .l =3D 0x1e, + .vco_val =3D BIT(21), + .vco_mask =3D GENMASK(21, 20), + .main_output_mask =3D BIT(0), + .config_ctl_val =3D 0x4001055b, + .test_ctl_hi_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, +}; + +static struct clk_alpha_pll disp_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &disp_cc_pll0_config, + .vco_table =3D disp_cc_pll_vco, + .num_vco =3D ARRAY_SIZE(disp_cc_pll_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_slew_ops, + }, + }, +}; + +static const struct parent_map disp_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map disp_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map disp_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &disp_cc_pll0.clkr.hw }, + { .index =3D DT_GPLL0 }, +}; + +static const struct parent_map disp_cc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_GPLL0 }, +}; + +static const struct parent_map disp_cc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_DSICLK }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x2170, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_4, + .freq_tbl =3D ftbl_disp_cc_mdss_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb_clk_src", + .parent_data =3D disp_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_4), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src =3D { + .cmd_rcgr =3D 0x20c0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux1_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src =3D { + .cmd_rcgr =3D 0x2158, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_mdss_dp_aux1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_aux_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src =3D { + .cmd_rcgr =3D 0x2110, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_crypto_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src =3D { + .cmd_rcgr =3D 0x20f4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_link_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x2140, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_pixel1_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src =3D { + .cmd_rcgr =3D 0x2128, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_pixel_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src =3D { + .cmd_rcgr =3D 0x20dc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .freq_tbl =3D ftbl_disp_cc_mdss_dp_aux1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_esc0_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(307000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src =3D { + .cmd_rcgr =3D 0x2078, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_3, + .freq_tbl =3D ftbl_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_clk_src", + .parent_data =3D disp_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src =3D { + .cmd_rcgr =3D 0x2060, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_5, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk0_clk_src", + .parent_data =3D disp_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_rot_clk_src =3D { + .cmd_rcgr =3D 0x2090, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_3, + .freq_tbl =3D ftbl_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_rot_clk_src", + .parent_data =3D disp_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src =3D { + .cmd_rcgr =3D 0x20a8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_mdss_dp_aux1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_vsync_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src =3D { + .reg =3D 0x20d8, + .shift =3D 0, + .width =3D 2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src =3D { + .reg =3D 0x210c, + .shift =3D 0, + .width =3D 2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk =3D { + .halt_reg =3D 0x2048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk =3D { + .halt_reg =3D 0x2024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk =3D { + .halt_reg =3D 0x2028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_aux_clk =3D { + .halt_reg =3D 0x2044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk =3D { + .halt_reg =3D 0x2038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk =3D { + .halt_reg =3D 0x2030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_intf_clk =3D { + .halt_reg =3D 0x2034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel1_clk =3D { + .halt_reg =3D 0x2040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel_clk =3D { + .halt_reg =3D 0x203c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x203c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_pixel_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk =3D { + .halt_reg =3D 0x202c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x202c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_esc0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk =3D { + .halt_reg =3D 0x2008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk =3D { + .halt_reg =3D 0x2018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_lut_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk =3D { + .halt_reg =3D 0x4004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk =3D { + .halt_reg =3D 0x2004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rot_clk =3D { + .halt_reg =3D 0x2010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_rot_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_rot_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_ahb_clk =3D { + .halt_reg =3D 0x400c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x400c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_rscc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_vsync_clk =3D { + .halt_reg =3D 0x4008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_rscc_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk =3D { + .halt_reg =3D 0x2020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mdss_core_gdsc =3D { + .gdscr =3D 0x3000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "mdss_core_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL | POLL_CFG_GDSCR, +}; + +static struct clk_regmap *disp_cc_qcs615_clocks[] =3D { + [DISP_CC_MDSS_AHB_CLK] =3D &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] =3D &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_CLK] =3D &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] =3D &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =3D &disp_cc_mdss_byte0_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] =3D &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK] =3D &disp_cc_mdss_dp_aux_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK_SRC] =3D &disp_cc_mdss_dp_aux_clk_src.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK] =3D &disp_cc_mdss_dp_crypto_clk.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] =3D &disp_cc_mdss_dp_crypto_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_CLK] =3D &disp_cc_mdss_dp_link_clk.clkr, + [DISP_CC_MDSS_DP_LINK_CLK_SRC] =3D &disp_cc_mdss_dp_link_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =3D &disp_cc_mdss_dp_link_div_clk_src.= clkr, + [DISP_CC_MDSS_DP_LINK_INTF_CLK] =3D &disp_cc_mdss_dp_link_intf_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK] =3D &disp_cc_mdss_dp_pixel1_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] =3D &disp_cc_mdss_dp_pixel1_clk_src.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK] =3D &disp_cc_mdss_dp_pixel_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] =3D &disp_cc_mdss_dp_pixel_clk_src.clkr, + [DISP_CC_MDSS_ESC0_CLK] =3D &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] =3D &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_MDP_CLK] =3D &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] =3D &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] =3D &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] =3D &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] =3D &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] =3D &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_ROT_CLK] =3D &disp_cc_mdss_rot_clk.clkr, + [DISP_CC_MDSS_ROT_CLK_SRC] =3D &disp_cc_mdss_rot_clk_src.clkr, + [DISP_CC_MDSS_RSCC_AHB_CLK] =3D &disp_cc_mdss_rscc_ahb_clk.clkr, + [DISP_CC_MDSS_RSCC_VSYNC_CLK] =3D &disp_cc_mdss_rscc_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK] =3D &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] =3D &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_PLL0] =3D &disp_cc_pll0.clkr, +}; + +static struct gdsc *disp_cc_qcs615_gdscs[] =3D { + [MDSS_CORE_GDSC] =3D &mdss_core_gdsc, +}; + +static struct clk_alpha_pll *disp_cc_qcs615_plls[] =3D { + &disp_cc_pll0, +}; + +static u32 disp_cc_qcs615_critical_cbcrs[] =3D { + 0x6054, /* DISP_CC_XO_CLK */ +}; + +static const struct regmap_config disp_cc_qcs615_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x10000, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data disp_cc_qcs615_driver_data =3D { + .alpha_plls =3D disp_cc_qcs615_plls, + .num_alpha_plls =3D ARRAY_SIZE(disp_cc_qcs615_plls), + .clk_cbcrs =3D disp_cc_qcs615_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(disp_cc_qcs615_critical_cbcrs), +}; + +static const struct qcom_cc_desc disp_cc_qcs615_desc =3D { + .config =3D &disp_cc_qcs615_regmap_config, + .clks =3D disp_cc_qcs615_clocks, + .num_clks =3D ARRAY_SIZE(disp_cc_qcs615_clocks), + .gdscs =3D disp_cc_qcs615_gdscs, + .num_gdscs =3D ARRAY_SIZE(disp_cc_qcs615_gdscs), + .driver_data =3D &disp_cc_qcs615_driver_data, +}; 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Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Taniya Das --- .../bindings/clock/qcom,qcs615-gpucc.yaml | 49 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,qcs615-gpucc.h | 39 +++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,qcs615-gpucc.yaml= b/Documentation/devicetree/bindings/clock/qcom,qcs615-gpucc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..5f7d83d1a7be301dd38709f6916= 7d7cb9319f076 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qcs615-gpucc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on QCS615 Qualcomm SoCs. + + See also: include/dt-bindings/clock/qcom,qcs615-gpucc.h + +properties: + compatible: + const: qcom,qcs615-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 GPUCC div branch source + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + clock-controller@5090000 { + compatible =3D "qcom,qcs615-gpucc"; + reg =3D <0x5090000 0x9000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,qcs615-gpucc.h b/include/dt-bin= dings/clock/qcom,qcs615-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..6d8394b90d59074b93a26a9c027= 407a14b050b27 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs615-gpucc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H + +/* GPU_CC clocks */ +#define CRC_DIV_PLL0 0 +#define CRC_DIV_PLL1 1 +#define GPU_CC_PLL0 2 +#define GPU_CC_PLL1 3 +#define GPU_CC_CRC_AHB_CLK 4 +#define GPU_CC_CX_GFX3D_CLK 5 +#define GPU_CC_CX_GFX3D_SLV_CLK 6 +#define GPU_CC_CX_GMU_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_GFX3D_CLK 12 +#define GPU_CC_GX_GFX3D_CLK_SRC 13 +#define GPU_CC_GX_GMU_CLK 14 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 15 +#define GPU_CC_SLEEP_CLK 16 + +/* GPU_CC power domains */ +#define CX_GDSC 0 +#define GX_GDSC 1 + +/* GPU_CC resets */ +#define GPU_CC_CX_BCR 0 +#define GPU_CC_GFX3D_AON_BCR 1 +#define GPU_CC_GMU_BCR 2 +#define GPU_CC_GX_BCR 3 +#define GPU_CC_XO_BCR 4 + +#endif --=20 2.34.1 From nobody Wed Oct 8 04:22:01 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA8EE246BC1; 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Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-qcs615.c | 531 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 540 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 19f105a1e33a705ddc11fd6fe226a4a2a5cea9a2..204319dc23b58ca816bafb967ff= 84eb3c069170a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -548,6 +548,14 @@ config QCS_GCC_615 Say Y if you want to use multimedia devices or peripheral devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc. =20 +config QCS_GPUCC_615 + tristate "QCS615 Graphics clock controller" + select QCS_GCC_615 + help + Support for the graphics clock controller on QCS615 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SC_CAMCC_7180 tristate "SC7180 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 4783f217543cb09ea25e9a537f5128b0fa89dec2..35b7f038647a6ed183a4a5ee3ec= aefa23525b119 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_QCS_CAMCC_615) +=3D camcc-qcs615.o obj-$(CONFIG_QCS_GCC_404) +=3D gcc-qcs404.o obj-$(CONFIG_QCS_GCC_615) +=3D gcc-qcs615.o obj-$(CONFIG_QCS_GCC_8300) +=3D gcc-qcs8300.o +obj-$(CONFIG_QCS_GPUCC_615) +=3D gpucc-qcs615.o obj-$(CONFIG_QCS_Q6SSTOP_404) +=3D q6sstop-qcs404.o obj-$(CONFIG_QCS_TURING_404) +=3D turingcc-qcs404.o obj-$(CONFIG_QDU_ECPRICC_1000) +=3D ecpricc-qdu1000.o diff --git a/drivers/clk/qcom/gpucc-qcs615.c b/drivers/clk/qcom/gpucc-qcs61= 5.c new file mode 100644 index 0000000000000000000000000000000000000000..ec6739c08425a96cb8f81e3dc0c= b306937032632 --- /dev/null +++ b/drivers/clk/qcom/gpucc-qcs615.c @@ -0,0 +1,531 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_2X_CLK, + P_CRC_DIV_PLL0_OUT_AUX2, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_AUX, + P_CRC_DIV_PLL1_OUT_AUX2, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static const struct pll_vco gpu_cc_pll0_vco[] =3D { + { 1000000000, 2100000000, 0 }, +}; + +static struct pll_vco gpu_cc_pll1_vco[] =3D { + { 500000000, 1000000000, 2 }, +}; + +/* 1020MHz configuration VCO - 0 */ +static struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x35, + .config_ctl_val =3D 0x4001055b, + .test_ctl_hi_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, + .alpha_hi =3D 0x20, + .alpha =3D 0x00, + .alpha_en_mask =3D BIT(24), + .vco_val =3D 0x0, + .vco_mask =3D GENMASK(21, 20), + .aux2_output_mask =3D BIT(2), +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &gpu_cc_pll0_config, + .vco_table =3D gpu_cc_pll0_vco, + .num_vco =3D ARRAY_SIZE(gpu_cc_pll0_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_slew_ops, + }, + }, +}; + +/* 930MHz configuration VCO - 2 */ +static struct alpha_pll_config gpu_cc_pll1_config =3D { + .l =3D 0x30, + .config_ctl_val =3D 0x4001055b, + .test_ctl_hi_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, + .alpha_hi =3D 0x70, + .alpha =3D 0x00, + .alpha_en_mask =3D BIT(24), + .vco_val =3D BIT(21), + .vco_mask =3D GENMASK(21, 20), + .aux2_output_mask =3D BIT(2), +}; + +static struct clk_alpha_pll gpu_cc_pll1 =3D { + .offset =3D 0x100, + .config =3D &gpu_cc_pll1_config, + .vco_table =3D gpu_cc_pll1_vco, + .num_vco =3D ARRAY_SIZE(gpu_cc_pll1_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_slew_ops, + }, + } +}; + +/* Clock Ramp Controller */ +static struct clk_fixed_factor crc_div_pll0 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "crc_div_pll0", + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gpu_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +/* Clock Ramp Controller */ +static struct clk_fixed_factor crc_div_pll1 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "crc_div_pll1", + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gpu_cc_pll1.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_2X_CLK, 1 }, + { P_CRC_DIV_PLL0_OUT_AUX2, 2 }, + { P_GPU_CC_PLL1_OUT_AUX, 3 }, + { P_CRC_DIV_PLL1_OUT_AUX2, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &crc_div_pll0.hw }, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .hw =3D &crc_div_pll1.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x1120, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_0, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] =3D { + F(290000000, P_CRC_DIV_PLL1_OUT_AUX2, 1, 0, 0), + F(350000000, P_CRC_DIV_PLL1_OUT_AUX2, 1, 0, 0), + F(435000000, P_CRC_DIV_PLL1_OUT_AUX2, 1, 0, 0), + F(500000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0), + F(550000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0), + F(650000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0), + F(700000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0), + F(745000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0), + F(845000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0), + F(895000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src =3D { + .cmd_rcgr =3D 0x101c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_gx_gfx3d_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_gfx3d_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk =3D { + .halt_reg =3D 0x107c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x107c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_crc_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk =3D { + .halt_reg =3D 0x10a4, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x10a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gfx3d_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_slv_clk =3D { + .halt_reg =3D 0x10a8, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x10a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gfx3d_slv_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x1098, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1098, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk =3D { + .halt_reg =3D 0x108c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x108c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_snoc_dvm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk =3D { + .halt_reg =3D 0x1004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cxo_aon_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x109c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x109c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cxo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk =3D { + .halt_reg =3D 0x1054, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x1054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_gfx3d_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk =3D { + .halt_reg =3D 0x1064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { + .halt_reg =3D 0x5000, + .halt_check =3D BRANCH_VOTED, + .clkr =3D { + .enable_reg =3D 0x5000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk =3D { + .halt_reg =3D 0x1090, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_hw *gpu_cc_qcs615_hws[] =3D { + [CRC_DIV_PLL0] =3D &crc_div_pll0.hw, + [CRC_DIV_PLL1] =3D &crc_div_pll1.hw, +}; + +static struct gdsc cx_gdsc =3D { + .gdscr =3D 0x106c, + .gds_hw_ctrl =3D 0x1540, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x8, + .pd =3D { + .name =3D "cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR, +}; + +static struct gdsc gx_gdsc =3D { + .gdscr =3D 0x100c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR, +}; + +static struct clk_regmap *gpu_cc_qcs615_clocks[] =3D { + [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] =3D &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GFX3D_SLV_CLK] =3D &gpu_cc_cx_gfx3d_slv_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] =3D &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] =3D &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_GFX3D_CLK] =3D &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] =3D &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_GX_GMU_CLK] =3D &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] =3D &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] =3D &gpu_cc_sleep_clk.clkr, +}; + +static struct gdsc *gpu_cc_qcs615_gdscs[] =3D { + [CX_GDSC] =3D &cx_gdsc, + [GX_GDSC] =3D &gx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_qcs615_resets[] =3D { + [GPU_CC_CX_BCR] =3D { 0x1068 }, + [GPU_CC_GFX3D_AON_BCR] =3D { 0x10a0 }, + [GPU_CC_GMU_BCR] =3D { 0x111c }, + [GPU_CC_GX_BCR] =3D { 0x1008 }, + [GPU_CC_XO_BCR] =3D { 0x1000 }, +}; + +static struct clk_alpha_pll *gpu_cc_qcs615_plls[] =3D { + &gpu_cc_pll0, + &gpu_cc_pll1, +}; + +static u32 gpu_cc_qcs615_critical_cbcrs[] =3D { + 0x1078, /* GPU_CC_AHB_CLK */ +}; + +static const struct regmap_config gpu_cc_qcs615_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x7008, + .fast_io =3D true, +}; + +static void clk_qcs615_regs_crc_configure(struct device *dev, struct regma= p *regmap) +{ + /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */ + regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg, 0xff0, 0xff= 0); + + /* + * After POR, Clock Ramp Controller(CRC) will be in bypass mode. + * Software needs to do the following operation to enable the CRC + * for GFX3D clock and divide the input clock by div by 2. + */ + regmap_update_bits(regmap, 0x1028, 0x00015011, 0x00015011); + regmap_update_bits(regmap, 0x1024, 0x00800000, 0x00800000); +} + +static struct qcom_cc_driver_data gpu_cc_qcs615_driver_data =3D { + .alpha_plls =3D gpu_cc_qcs615_plls, + .num_alpha_plls =3D ARRAY_SIZE(gpu_cc_qcs615_plls), + .clk_cbcrs =3D gpu_cc_qcs615_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gpu_cc_qcs615_critical_cbcrs), + .clk_regs_configure =3D clk_qcs615_regs_crc_configure, +}; + +static const struct qcom_cc_desc gpu_cc_qcs615_desc =3D { + .config =3D &gpu_cc_qcs615_regmap_config, + .clks =3D gpu_cc_qcs615_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_qcs615_clocks), + .clk_hws =3D gpu_cc_qcs615_hws, + .num_clk_hws =3D ARRAY_SIZE(gpu_cc_qcs615_hws), + .resets =3D gpu_cc_qcs615_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_qcs615_resets), + .gdscs =3D gpu_cc_qcs615_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_qcs615_gdscs), + .driver_data =3D &gpu_cc_qcs615_driver_data, +}; + +static const struct of_device_id gpu_cc_qcs615_match_table[] =3D { + { .compatible =3D "qcom,qcs615-gpucc" }, + { } +}; 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Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Taniya Das --- .../bindings/clock/qcom,qcs615-videocc.yaml | 47 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,qcs615-videocc.h | 30 ++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,qcs615-videocc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,qcs615-videocc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..f51b69de10478d1fcc246e4324d= c74bc87b435eb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qcs615-videocc.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das + +description: | + Qualcomm video clock control module provides clocks, resets and power + domains on QCS615 Qualcomm SoCs. + + See also: include/dt-bindings/clock/qcom,qcs615-videocc.h + +properties: + compatible: + const: qcom,qcs615-videocc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + clock-controller@ab00000 { + compatible =3D "qcom,qcs615-videocc"; + reg =3D <0xab00000 0x10000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,qcs615-videocc.h b/include/dt-b= indings/clock/qcom,qcs615-videocc.h new file mode 100644 index 0000000000000000000000000000000000000000..0ca3efb21103d7e0b09ab9c042b= e761bcbc5960d --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs615-videocc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_QCS615_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_QCS615_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_SLEEP_CLK 0 +#define VIDEO_CC_SLEEP_CLK_SRC 1 +#define VIDEO_CC_VCODEC0_AXI_CLK 2 +#define VIDEO_CC_VCODEC0_CORE_CLK 3 +#define VIDEO_CC_VENUS_AHB_CLK 4 +#define VIDEO_CC_VENUS_CLK_SRC 5 +#define VIDEO_CC_VENUS_CTL_AXI_CLK 6 +#define VIDEO_CC_VENUS_CTL_CORE_CLK 7 +#define VIDEO_CC_XO_CLK 8 +#define VIDEO_PLL0 9 + +/* VIDEO_CC power domains */ +#define VCODEC0_GDSC 0 +#define VENUS_GDSC 1 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_VCODEC0_BCR 1 +#define VIDEO_CC_VENUS_BCR 2 + +#endif --=20 2.34.1 From nobody Wed Oct 8 04:22:01 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B82D24BBE4; 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Wed, 02 Jul 2025 09:05:47 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56295kql003200 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Jul 2025 09:05:46 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 2 Jul 2025 02:05:40 -0700 From: Taniya Das Date: Wed, 2 Jul 2025 14:34:29 +0530 Subject: [PATCH v11 09/10] clk: qcom: videocc-qcs615: Add QCS615 video clock controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250702-qcs615-mm-v10-clock-controllers-v11-9-9c216e1615ab@quicinc.com> References: <20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com> In-Reply-To: <20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Catalin Marinas" , Will Deacon CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , , Taniya Das , Bryan O'Donoghue , Dmitry Baryshkov X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=CY4I5Krl c=1 sm=1 tr=0 ts=6864f66b cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=qYpWxANyOF6Ti2HRg9EA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: Mup8iGh0vLdjNSswidHUf3PgTqL5ShvP X-Proofpoint-GUID: Mup8iGh0vLdjNSswidHUf3PgTqL5ShvP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAyMDA3MyBTYWx0ZWRfX1Til56AGCo+E Sq/SWUr99GDvk29chYN9/PtLbi8jvJYj6Vgvz19F8P+YpCoI3m4TG64XQAu9lhobZnQX3QfCIk/ Tn6OMrCdqF0nvppyQYAZrAIltNDbBcvUrOzMpWi+JWORz8/G0waJvZIgBsqMnbGqRd2Ir+qZARd vtCCGkzDY+8CmA0ImPqdRMpuAw7BhMLfsz7g4R77uyIh9xBUpHfhYMuJMmEpW95Fu5VxM23V6MU T/alPcgYr7f7UchbXYpjeIvDmUmZT0S9D35ZU0v0Clwr/nV/K815eDmnOE4rsCbz0RYNiH6ZuDy 1YoqvyqpDuM52bQ96h3XM6znHilDow3ohwJbdURtwlb0K0deVVNP0ZJKfuscLBc3CC8/dscUyG1 sTxIgeQHWydnTDceUSxh+2xk3fU8E/S5KVnkhHWjwPqPlYTb9MQA+nhhhZxp/UMVZpaNSLt1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-02_01,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 lowpriorityscore=0 mlxscore=0 phishscore=0 suspectscore=0 bulkscore=0 malwarescore=0 impostorscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507020073 Add support for the video clock controller for video clients to be able to request for the clocks on QCS615 platform. Reviewed-by: Bryan O'Donoghue Reviewed-by: Dmitry Baryshkov Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-qcs615.c | 338 ++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 347 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 204319dc23b58ca816bafb967ff84eb3c069170a..759b24d2c55066b641b1eaf8115= 7aa024e641e92 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -556,6 +556,14 @@ config QCS_GPUCC_615 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. =20 +config QCS_VIDEOCC_615 + tristate "QCS615 Video Clock Controller" + select QCS_GCC_615 + help + Support for the video clock controller on QCS615 devices. + Say Y if you want to support video devices and functionality such as + video encode and decode. + config SC_CAMCC_7180 tristate "SC7180 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 35b7f038647a6ed183a4a5ee3ecaefa23525b119..2af0dae787dbacf3a97fd423e73= d15bacfed85ba 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -79,6 +79,7 @@ obj-$(CONFIG_QCS_GCC_404) +=3D gcc-qcs404.o obj-$(CONFIG_QCS_GCC_615) +=3D gcc-qcs615.o obj-$(CONFIG_QCS_GCC_8300) +=3D gcc-qcs8300.o obj-$(CONFIG_QCS_GPUCC_615) +=3D gpucc-qcs615.o +obj-$(CONFIG_QCS_VIDEOCC_615) +=3D videocc-qcs615.o obj-$(CONFIG_QCS_Q6SSTOP_404) +=3D q6sstop-qcs404.o obj-$(CONFIG_QCS_TURING_404) +=3D turingcc-qcs404.o obj-$(CONFIG_QDU_ECPRICC_1000) +=3D ecpricc-qdu1000.o diff --git a/drivers/clk/qcom/videocc-qcs615.c b/drivers/clk/qcom/videocc-q= cs615.c new file mode 100644 index 0000000000000000000000000000000000000000..1b41fa44c17ea05d637f2cd8dd8= c5b9b94faeeb1 --- /dev/null +++ b/drivers/clk/qcom/videocc-qcs615.c @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_SLEEP_CLK, + P_VIDEO_PLL0_OUT_AUX, + P_VIDEO_PLL0_OUT_AUX2, + P_VIDEO_PLL0_OUT_MAIN, +}; + +static const struct pll_vco video_cc_pll0_vco[] =3D { + { 500000000, 1000000000, 2 }, +}; + +/* 600MHz configuration VCO - 2 */ +static struct alpha_pll_config video_pll0_config =3D { + .l =3D 0x1f, + .alpha_hi =3D 0x40, + .alpha =3D 0x00, + .alpha_en_mask =3D BIT(24), + .vco_val =3D BIT(21), + .vco_mask =3D GENMASK(21, 20), + .main_output_mask =3D BIT(0), + .config_ctl_val =3D 0x4001055b, + .test_ctl_hi_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, +}; + +static struct clk_alpha_pll video_pll0 =3D { + .offset =3D 0x42c, + .config =3D &video_pll0_config, + .vco_table =3D video_cc_pll0_vco, + .num_vco =3D ARRAY_SIZE(video_cc_pll0_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_slew_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0_ao[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL0_OUT_MAIN, 1 }, + { P_VIDEO_PLL0_OUT_AUX, 2 }, + { P_VIDEO_PLL0_OUT_AUX2, 3 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_pll0.clkr.hw }, + { .hw =3D &video_pll0.clkr.hw }, + { .hw =3D &video_pll0.clkr.hw }, +}; + +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0xaf8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_sleep_clk_src", + .parent_data =3D video_cc_parent_data_0_ao, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0_ao), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_venus_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(133333333, P_VIDEO_PLL0_OUT_MAIN, 4.5, 0, 0), + F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0), + F(300000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), + F(380000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), + F(410000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), + F(460000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_venus_clk_src =3D { + .cmd_rcgr =3D 0x7f0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_venus_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_venus_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch video_cc_sleep_clk =3D { + .halt_reg =3D 0xb18, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb18, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "video_cc_sleep_clk", + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &video_cc_sleep_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_vcodec0_axi_clk =3D { + .halt_reg =3D 0x8f0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8f0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_vcodec0_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_vcodec0_core_clk =3D { + .halt_reg =3D 0x890, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x890, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_vcodec0_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_venus_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_venus_ahb_clk =3D { + .halt_reg =3D 0x9b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_venus_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_venus_ctl_axi_clk =3D { + .halt_reg =3D 0x8d0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_venus_ctl_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_venus_ctl_core_clk =3D { + .halt_reg =3D 0x850, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x850, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_venus_ctl_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_venus_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc vcodec0_gdsc =3D { + .gdscr =3D 0x874, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "vcodec0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR, +}; + +static struct gdsc venus_gdsc =3D { + .gdscr =3D 0x814, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "venus_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR, +}; + +static struct clk_regmap *video_cc_qcs615_clocks[] =3D { + [VIDEO_CC_SLEEP_CLK] =3D &video_cc_sleep_clk.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] =3D &video_cc_sleep_clk_src.clkr, + [VIDEO_CC_VCODEC0_AXI_CLK] =3D &video_cc_vcodec0_axi_clk.clkr, + [VIDEO_CC_VCODEC0_CORE_CLK] =3D &video_cc_vcodec0_core_clk.clkr, + [VIDEO_CC_VENUS_AHB_CLK] =3D &video_cc_venus_ahb_clk.clkr, + [VIDEO_CC_VENUS_CLK_SRC] =3D &video_cc_venus_clk_src.clkr, + [VIDEO_CC_VENUS_CTL_AXI_CLK] =3D &video_cc_venus_ctl_axi_clk.clkr, + [VIDEO_CC_VENUS_CTL_CORE_CLK] =3D &video_cc_venus_ctl_core_clk.clkr, + [VIDEO_PLL0] =3D &video_pll0.clkr, +}; + +static struct gdsc *video_cc_qcs615_gdscs[] =3D { + [VCODEC0_GDSC] =3D &vcodec0_gdsc, + [VENUS_GDSC] =3D &venus_gdsc, +}; + +static const struct qcom_reset_map video_cc_qcs615_resets[] =3D { + [VIDEO_CC_INTERFACE_BCR] =3D { 0x8b0 }, + [VIDEO_CC_VCODEC0_BCR] =3D { 0x870 }, + [VIDEO_CC_VENUS_BCR] =3D { 0x810 }, +}; + +static struct clk_alpha_pll *video_cc_qcs615_plls[] =3D { + &video_pll0, +}; + +static u32 video_cc_qcs615_critical_cbcrs[] =3D { + 0xab8, /* VIDEO_CC_XO_CLK */ +}; + +static const struct regmap_config video_cc_qcs615_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xb94, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data video_cc_qcs615_driver_data =3D { + .alpha_plls =3D video_cc_qcs615_plls, + .num_alpha_plls =3D ARRAY_SIZE(video_cc_qcs615_plls), + .clk_cbcrs =3D video_cc_qcs615_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(video_cc_qcs615_critical_cbcrs), +}; + +static const struct qcom_cc_desc video_cc_qcs615_desc =3D { + .config =3D &video_cc_qcs615_regmap_config, + .clks =3D video_cc_qcs615_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_qcs615_clocks), + .resets =3D video_cc_qcs615_resets, + .num_resets =3D ARRAY_SIZE(video_cc_qcs615_resets), + .gdscs =3D video_cc_qcs615_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_qcs615_gdscs), + .driver_data =3D &video_cc_qcs615_driver_data, +}; + +static const struct of_device_id video_cc_qcs615_match_table[] =3D { + { .compatible =3D "qcom,qcs615-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_qcs615_match_table); + +static int video_cc_qcs615_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &video_cc_qcs615_desc); +} + +static struct platform_driver video_cc_qcs615_driver =3D { + .probe =3D video_cc_qcs615_probe, + .driver =3D { + .name =3D "videocc-qcs615", + .of_match_table =3D video_cc_qcs615_match_table, + }, +}; + +module_platform_driver(video_cc_qcs615_driver); + +MODULE_DESCRIPTION("QTI VIDEOCC QCS615 Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Wed Oct 8 04:22:01 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BC4C2417F9; Wed, 2 Jul 2025 09:06:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Taniya Das --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index e071f8f45607dbfd8e00b915b27999949ee0fc88..3c5c1901ca5670d1bfd0a6edd73= f0591ccb9c76f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1375,11 +1375,15 @@ CONFIG_MSM_GCC_8998=3Dy CONFIG_MSM_MMCC_8998=3Dm CONFIG_QCM_GCC_2290=3Dy CONFIG_QCM_DISPCC_2290=3Dm +CONFIG_QCS_DISPCC_615=3Dm +CONFIG_QCS_CAMCC_615=3Dm CONFIG_QCS_GCC_404=3Dy CONFIG_QCS_GCC_615=3Dy CONFIG_QCS_GCC_8300=3Dy CONFIG_SC_CAMCC_7280=3Dm CONFIG_SA_CAMCC_8775P=3Dm +CONFIG_QCS_GPUCC_615=3Dm +CONFIG_QCS_VIDEOCC_615=3Dm CONFIG_QDU_GCC_1000=3Dy CONFIG_SC_CAMCC_8280XP=3Dm CONFIG_SC_DISPCC_7280=3Dm --=20 2.34.1