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Wysocki" , Viresh Kumar , "Manivannan Sadhasivam" CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=C4TpyRP+ c=1 sm=1 tr=0 ts=6864f83d cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=DiV1PRyO1OqbfoddZsgA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: oFIdV9bGupx95wzsfz4OQCO4mLgK8x-8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAyMDA3MyBTYWx0ZWRfXx/BABAaQOrb3 GX8Sq+nQY4UmVALeakIWYVIJXcVArQsWnixVpgiL4biC4R+ZgX0NoHS2upE8DUK65TipvADXGG9 GLKob6EeoEcVD1c+6KKnLnA1Q6+Ln9GdtPDXPyJfYF4XzI3QPLZoQNr8uG59oLyIgKSnakk8Py6 ngYr21AOYQyhXN7HpOweG128V+psWRZXITx4eRIJWrNxOcceS9b3Vf0YFc81ay+/FupUPjbvS80 QJTbsUbcYtqbhT1/dH3/m5ljy5bvEJR9CkWyjj2aBpCk/Zsb+W0c1gnpgwWmRNUBNq8E3k29+41 iKRely7VoM3yjouPcVTt/CpFf+vPFhTksZHgws+V5Tp0vW3Yy72h3ToBm5Cx6gygYHOebGP2Pls sbyCRuEPuf2wLh8aEY/50mcTrzze/qz92F1hNwWg5tzIo374WmTB0so2smRiAWIJyqI6u66M X-Proofpoint-GUID: oFIdV9bGupx95wzsfz4OQCO4mLgK8x-8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-02_01,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1011 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=882 adultscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507020073 Document compatible for cpufreq hardware on Qualcomm QCS615 platform. Signed-off-by: Taniya Das Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index e0242bed33420a39b8a8cff4229ba9eee994ca30..2d42fc3d8ef811368c990977173= f41b26535e0c8 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -22,6 +22,7 @@ properties: items: - enum: - qcom,qcm2290-cpufreq-hw + - qcom,qcs615-cpufreq-hw - qcom,sc7180-cpufreq-hw - qcom,sc8180x-cpufreq-hw - qcom,sdm670-cpufreq-hw @@ -132,6 +133,7 @@ allOf: compatible: contains: enum: + - qcom,qcs615-cpufreq-hw - qcom,qdu1000-cpufreq-epss - qcom,sa8255p-cpufreq-epss - qcom,sa8775p-cpufreq-epss --=20 2.34.1 From nobody Wed Oct 8 04:07:52 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB447244677; Wed, 2 Jul 2025 09:13:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751447624; cv=none; b=j8iX1LIDfIoXGn803l9IyV0Pkbi3Ea8HWg/yHuSenGQdppHwAo5fF8ipWHSCPHJq08kmjJJMmcULj5c5fL3UxhuVVy/d0cQKfNcqUyNXbkA1gAfa3IRe+GV5QEG3K3lnqg6i9JlwCjvbB3O1qDCtewmPuAP5pA7r3UC/cWkIcGk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751447624; c=relaxed/simple; bh=F9aw+M2A0XOl2cvlq+Dj0zzzF9TuStc3hA0w/gK6pLw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=eNCe+ouf8Sr2EscsKBkBeqzfO1LxvytvFthxENB7Qz+86FQgUrD+KZClROcHzDr2cYucLMiIkxOnXFnJmy7HGtKqCrZ5kaFUqn80SEFQL5v1zYD2VZ3FNqPcrylboTcy6JiwrmfxtMxoMQ9s2eGFFseF1a7Z8A8YlW3H3r8NthA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=I5EujZ8N; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="I5EujZ8N" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5622sKuw022911; Wed, 2 Jul 2025 09:13:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pfAY1xYh35AyzP143dg0JapGVaCvTDRwPasaJr2uRl8=; b=I5EujZ8NNn675vDN c1Mi0PLMmyzsnRaSUVCJZkIYTjEtkmYS8KPygCAxNKE87ErNMO1FdVkO9wWe0Ce0 aV1dXOP8hOL/4e8fX7LmlSaGaw9tD2WTIqDJun0S6pz+yc7J57/erOXkhya1P5t6 rXGADROiZQr/4ZkpAGwzpLZy9kM1RhX4sxzPCyRQVPDltbE+/MJpp+jR2CUJZcq9 HysqMdLTWtRONeW1WOVN1drQL9hEURaMRHdn4Hpb3LBZJjmFFCebHsGpX3kM2plo BbNtVxPdKqfs1Yfv32j1/q96qQtuiMjCN6l9FjOfm01e19zzSYo+mXaZh7EIYzWj XUEXzg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47mhxn2n9a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 02 Jul 2025 09:13:38 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5629DbCd025866 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Jul 2025 09:13:37 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 2 Jul 2025 02:13:32 -0700 From: Taniya Das Date: Wed, 2 Jul 2025 14:43:10 +0530 Subject: [PATCH v5 2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250702-qcs615-mm-cpu-dt-v4-v5-2-df24896cbb26@quicinc.com> References: <20250702-qcs615-mm-cpu-dt-v4-v5-0-df24896cbb26@quicinc.com> In-Reply-To: <20250702-qcs615-mm-cpu-dt-v4-v5-0-df24896cbb26@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. 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Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index bfbb210354922766a03fe05e6d117ea21d118081..5adf409d7ce7226042c759cc83c= eca331097ae37 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -3,7 +3,11 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. */ =20 +#include +#include #include +#include +#include #include #include #include @@ -1506,6 +1510,18 @@ data-pins { }; }; =20 + gpucc: clock-controller@5090000 { + compatible =3D "qcom,qcs615-gpucc"; + reg =3D <0 0x05090000 0 0x9000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + stm@6002000 { compatible =3D "arm,coresight-stm", "arm,primecell"; reg =3D <0x0 0x06002000 0x0 0x1000>, @@ -3317,6 +3333,41 @@ gem_noc: interconnect@9680000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + videocc: clock-controller@ab00000 { + compatible =3D "qcom,qcs615-videocc"; + reg =3D <0 0x0ab00000 0 0x10000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + camcc: clock-controller@ad00000 { + compatible =3D "qcom,qcs615-camcc"; + reg =3D <0 0x0ad00000 0 0x10000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; 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Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index 5adf409d7ce7226042c759cc83ceca331097ae37..142338069a74cc6c263e17d84ef= a22ccd0c26813 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -36,6 +36,8 @@ cpu0: cpu@0 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_0>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; =20 l2_0: l2-cache { @@ -56,6 +58,8 @@ cpu1: cpu@100 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_100>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_100: l2-cache { compatible =3D "cache"; @@ -75,6 +79,8 @@ cpu2: cpu@200 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_200>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_200: l2-cache { compatible =3D "cache"; @@ -94,6 +100,8 @@ cpu3: cpu@300 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_300>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_300: l2-cache { compatible =3D "cache"; @@ -113,6 +121,8 @@ cpu4: cpu@400 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_400>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_400: l2-cache { compatible =3D "cache"; @@ -132,6 +142,8 @@ cpu5: cpu@500 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_500>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_500: l2-cache { compatible =3D "cache"; @@ -151,6 +163,8 @@ cpu6: cpu@600 { capacity-dmips-mhz =3D <1740>; dynamic-power-coefficient =3D <404>; next-level-cache =3D <&l2_600>; + clocks =3D <&cpufreq_hw 1>; + qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; =20 l2_600: l2-cache { @@ -171,6 +185,8 @@ cpu7: cpu@700 { capacity-dmips-mhz =3D <1740>; dynamic-power-coefficient =3D <404>; next-level-cache =3D <&l2_700>; + clocks =3D <&cpufreq_hw 1>; + qcom,freq-domain =3D <&cpufreq_hw 1>; =20 l2_700: l2-cache { compatible =3D "cache"; @@ -3891,6 +3907,19 @@ glink_edge: glink-edge { qcom,remote-pid =3D <2>; }; }; + + cpufreq_hw: cpufreq@18323000 { + compatible =3D "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw"; + reg =3D <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; + reg-names =3D "freq-domain0", "freq-domain1"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; + + #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; + }; + }; =20 arch_timer: timer { --=20 2.34.1