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Wed, 02 Jul 2025 08:27:21 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:26:07 +0200 Subject: [PATCH 09/26] clk: amlogic: gxbb-ao: naming consistency alignment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-9-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9775; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=zCYXCSSXQjziG+h/5aIsAP+nLV6vpqnZUuUAtdeaR3M=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoZU++XefazoyZ/Qm0mWo5gHhVpfZQgxU3CWjPs sOcC3TCm+qJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaGVPvgAKCRDm/A8cN/La hUV4D/9SH6Ryl59OqhIOhiV3bYl47W+94El4y+cQsB9GojDP1aT53b7aI+mOfHFcm/Erjnp2PIw RfviCT+FB6dbxSXlVkGT23zNLtlepabH3z6vkCgREZ1qk2y3oy5SYEgiN2DugFEf72iOPKXoN3n 6aLcW4/UBmV4oQ7SJ8hcL4PQtpAY+OEnJLu5etoxKe2apmu7qi+VIQNxv09zsu3nbhJzHiIV8CD S4HtxpZ73+IYH1zysDPEz7wqeTqGPwvJzobmeQIOUn1RHLCkALRE3ZwPNlLNYLq4t2sFr928Wvq c+LUbo4aR+RzYICrGBOpgeWMvSbOb9BhP3ydNQRIlsP79WZmk9mMJ0aZdii4tXQAsf6yGGZm1N6 VDIJo366RECi19bjMb+5TrQNwAyOYl0LoAIdQnVNL4Ga5+wCG6QYP16ZcQxBBYMWGrbEoQvZ3YI CiNFWwGs1L5Ux55XMTIE3S4+ilVFBcXafU6ejcfCjSJNn9h+e1CEvpjaSEcIJ7QRhFmyF9I6KiF TR03KcEIYe2+ec5rPrgRMP3cft3ofaQ+8Tx3duP3HP1oWRbxB1nslYk0c5Ozo8x8WupsPARsyir 27Gf9jhGPLY2IzQe9PXCSK1lgvvsfHbm1Z5tbz2aYWVrxOyi9YXo1picAvc04urU+qrrWR7iWYW +ZtbGkFjmKEPteQ== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet --- drivers/clk/meson/gxbb-aoclk.c | 104 ++++++++++++++++++++-----------------= ---- 1 file changed, 52 insertions(+), 52 deletions(-) diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index f075fbd450f34bac9b2f9f969930337d3831a893..11b11fa7791eb1903938c0d3ee4= 6121a23b94a46 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c @@ -23,14 +23,14 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define GXBB_AO_GATE(_name, _bit) \ -static struct clk_regmap _name##_ao =3D { \ +#define GXBB_AO_PCLK(_name, _bit) \ +static struct clk_regmap gxbb_ao_##_name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D AO_RTI_GEN_CNTL_REG0, \ .bit_idx =3D (_bit), \ }, \ .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name "_ao", \ + .name =3D "gxbb_ao_" #_name, \ .ops =3D &clk_regmap_gate_ops, \ .parent_data =3D &(const struct clk_parent_data) { \ .fw_name =3D "mpeg-clk", \ @@ -40,14 +40,14 @@ static struct clk_regmap _name##_ao =3D { \ }, \ } =20 -GXBB_AO_GATE(remote, 0); -GXBB_AO_GATE(i2c_master, 1); -GXBB_AO_GATE(i2c_slave, 2); -GXBB_AO_GATE(uart1, 3); -GXBB_AO_GATE(uart2, 5); -GXBB_AO_GATE(ir_blaster, 6); +GXBB_AO_PCLK(remote, 0); +GXBB_AO_PCLK(i2c_master, 1); +GXBB_AO_PCLK(i2c_slave, 2); +GXBB_AO_PCLK(uart1, 3); +GXBB_AO_PCLK(uart2, 5); +GXBB_AO_PCLK(ir_blaster, 6); =20 -static struct clk_regmap ao_cts_oscin =3D { +static struct clk_regmap gxbb_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTI_PWR_CNTL_REG0, .bit_idx =3D 6, @@ -62,7 +62,7 @@ static struct clk_regmap ao_cts_oscin =3D { }, }; =20 -static struct clk_regmap ao_32k_pre =3D { +static struct clk_regmap gxbb_ao_32k_pre =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTC_ALT_CLK_CNTL0, .bit_idx =3D 31, @@ -70,7 +70,7 @@ static struct clk_regmap ao_32k_pre =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "ao_32k_pre", .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { &ao_cts_oscin.hw }, + .parent_hws =3D (const struct clk_hw *[]) { &gxbb_ao_cts_oscin.hw }, .num_parents =3D 1, }, }; @@ -85,7 +85,7 @@ static const struct meson_clk_dualdiv_param gxbb_32k_div_= table[] =3D { }, {} }; =20 -static struct clk_regmap ao_32k_div =3D { +static struct clk_regmap gxbb_ao_32k_div =3D { .data =3D &(struct meson_clk_dualdiv_data){ .n1 =3D { .reg_off =3D AO_RTC_ALT_CLK_CNTL0, @@ -117,12 +117,12 @@ static struct clk_regmap ao_32k_div =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "ao_32k_div", .ops =3D &meson_clk_dualdiv_ops, - .parent_hws =3D (const struct clk_hw *[]) { &ao_32k_pre.hw }, + .parent_hws =3D (const struct clk_hw *[]) { &gxbb_ao_32k_pre.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap ao_32k_sel =3D { +static struct clk_regmap gxbb_ao_32k_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTC_ALT_CLK_CNTL1, .mask =3D 0x1, @@ -133,15 +133,15 @@ static struct clk_regmap ao_32k_sel =3D { .name =3D "ao_32k_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &ao_32k_div.hw, - &ao_32k_pre.hw + &gxbb_ao_32k_div.hw, + &gxbb_ao_32k_pre.hw }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap ao_32k =3D { +static struct clk_regmap gxbb_ao_32k =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTC_ALT_CLK_CNTL0, .bit_idx =3D 30, @@ -149,13 +149,13 @@ static struct clk_regmap ao_32k =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "ao_32k", .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { &ao_32k_sel.hw }, + .parent_hws =3D (const struct clk_hw *[]) { &gxbb_ao_32k_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap ao_cts_rtc_oscin =3D { +static struct clk_regmap gxbb_ao_cts_rtc_oscin =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTI_PWR_CNTL_REG0, .mask =3D 0x7, @@ -170,14 +170,14 @@ static struct clk_regmap ao_cts_rtc_oscin =3D { { .fw_name =3D "ext-32k-0", }, { .fw_name =3D "ext-32k-1", }, { .fw_name =3D "ext-32k-2", }, - { .hw =3D &ao_32k.hw }, + { .hw =3D &gxbb_ao_32k.hw }, }, .num_parents =3D 4, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap ao_clk81 =3D { +static struct clk_regmap gxbb_ao_clk81 =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTI_PWR_CNTL_REG0, .mask =3D 0x1, @@ -189,14 +189,14 @@ static struct clk_regmap ao_clk81 =3D { .ops =3D &clk_regmap_mux_ro_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "mpeg-clk", }, - { .hw =3D &ao_cts_rtc_oscin.hw }, + { .hw =3D &gxbb_ao_cts_rtc_oscin.hw }, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap ao_cts_cec =3D { +static struct clk_regmap gxbb_ao_cts_cec =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_CRT_CLK_CNTL1, .mask =3D 0x1, @@ -221,14 +221,14 @@ static struct clk_regmap ao_cts_cec =3D { */ .parent_data =3D (const struct clk_parent_data []) { { .name =3D "fixme", .index =3D -1, }, - { .hw =3D &ao_cts_rtc_oscin.hw }, + { .hw =3D &gxbb_ao_cts_rtc_oscin.hw }, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const unsigned int gxbb_aoclk_reset[] =3D { +static const unsigned int gxbb_ao_reset[] =3D { [RESET_AO_REMOTE] =3D 16, [RESET_AO_I2C_MASTER] =3D 18, [RESET_AO_I2C_SLAVE] =3D 19, @@ -237,50 +237,50 @@ static const unsigned int gxbb_aoclk_reset[] =3D { [RESET_AO_IR_BLASTER] =3D 23, }; =20 -static struct clk_hw *gxbb_aoclk_hw_clks[] =3D { - [CLKID_AO_REMOTE] =3D &remote_ao.hw, - [CLKID_AO_I2C_MASTER] =3D &i2c_master_ao.hw, - [CLKID_AO_I2C_SLAVE] =3D &i2c_slave_ao.hw, - [CLKID_AO_UART1] =3D &uart1_ao.hw, - [CLKID_AO_UART2] =3D &uart2_ao.hw, - [CLKID_AO_IR_BLASTER] =3D &ir_blaster_ao.hw, - [CLKID_AO_CEC_32K] =3D &ao_cts_cec.hw, - [CLKID_AO_CTS_OSCIN] =3D &ao_cts_oscin.hw, - [CLKID_AO_32K_PRE] =3D &ao_32k_pre.hw, - [CLKID_AO_32K_DIV] =3D &ao_32k_div.hw, - [CLKID_AO_32K_SEL] =3D &ao_32k_sel.hw, - [CLKID_AO_32K] =3D &ao_32k.hw, - [CLKID_AO_CTS_RTC_OSCIN] =3D &ao_cts_rtc_oscin.hw, - [CLKID_AO_CLK81] =3D &ao_clk81.hw, +static struct clk_hw *gxbb_ao_hw_clks[] =3D { + [CLKID_AO_REMOTE] =3D &gxbb_ao_remote.hw, + [CLKID_AO_I2C_MASTER] =3D &gxbb_ao_i2c_master.hw, + [CLKID_AO_I2C_SLAVE] =3D &gxbb_ao_i2c_slave.hw, + [CLKID_AO_UART1] =3D &gxbb_ao_uart1.hw, + [CLKID_AO_UART2] =3D &gxbb_ao_uart2.hw, + [CLKID_AO_IR_BLASTER] =3D &gxbb_ao_ir_blaster.hw, + [CLKID_AO_CEC_32K] =3D &gxbb_ao_cts_cec.hw, + [CLKID_AO_CTS_OSCIN] =3D &gxbb_ao_cts_oscin.hw, + [CLKID_AO_32K_PRE] =3D &gxbb_ao_32k_pre.hw, + [CLKID_AO_32K_DIV] =3D &gxbb_ao_32k_div.hw, + [CLKID_AO_32K_SEL] =3D &gxbb_ao_32k_sel.hw, + [CLKID_AO_32K] =3D &gxbb_ao_32k.hw, + [CLKID_AO_CTS_RTC_OSCIN] =3D &gxbb_ao_cts_rtc_oscin.hw, + [CLKID_AO_CLK81] =3D &gxbb_ao_clk81.hw, }; =20 -static const struct meson_aoclk_data gxbb_aoclkc_data =3D { +static const struct meson_aoclk_data gxbb_ao_clkc_data =3D { .reset_reg =3D AO_RTI_GEN_CNTL_REG0, - .num_reset =3D ARRAY_SIZE(gxbb_aoclk_reset), - .reset =3D gxbb_aoclk_reset, + .num_reset =3D ARRAY_SIZE(gxbb_ao_reset), + .reset =3D gxbb_ao_reset, .hw_clks =3D { - .hws =3D gxbb_aoclk_hw_clks, - .num =3D ARRAY_SIZE(gxbb_aoclk_hw_clks), + .hws =3D gxbb_ao_hw_clks, + .num =3D ARRAY_SIZE(gxbb_ao_hw_clks), }, }; =20 -static const struct of_device_id gxbb_aoclkc_match_table[] =3D { +static const struct of_device_id gxbb_ao_clkc_match_table[] =3D { { .compatible =3D "amlogic,meson-gx-aoclkc", - .data =3D &gxbb_aoclkc_data, + .data =3D &gxbb_ao_clkc_data, }, { } }; -MODULE_DEVICE_TABLE(of, gxbb_aoclkc_match_table); +MODULE_DEVICE_TABLE(of, gxbb_ao_clkc_match_table); =20 -static struct platform_driver gxbb_aoclkc_driver =3D { +static struct platform_driver gxbb_ao_clkc_driver =3D { .probe =3D meson_aoclkc_probe, .driver =3D { .name =3D "gxbb-aoclkc", - .of_match_table =3D gxbb_aoclkc_match_table, + .of_match_table =3D gxbb_ao_clkc_match_table, }, }; -module_platform_driver(gxbb_aoclkc_driver); +module_platform_driver(gxbb_ao_clkc_driver); =20 MODULE_DESCRIPTION("Amlogic GXBB Always-ON Clock Controller driver"); MODULE_LICENSE("GPL"); --=20 2.47.2