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Wed, 02 Jul 2025 08:27:19 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:26:05 +0200 Subject: [PATCH 07/26] clk: amlogic: g12a-ao: naming consistency alignment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-7-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=16330; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=BsDu7/Vg0WHtN39FndrGjMoc90Hoc0+X58Lv9FeO4RQ=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoZU+9h7P8ICiND7ba6ymWgC5onAbiTMEm5yt08 W8HqknbJ3uJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaGVPvQAKCRDm/A8cN/La hbWAD/4u8dcP+a8IX5wX6ILqSuVAa0mOoWUAyajDMCogZbg5BQ8vJh0RcDFLFcaQ/4/L4RBcLjc /4wxgQz2I8DAOITsQI99XrT3+0FjvLqlkcdByP5aJ6u4Oz8zgolME1MCDrzGuYNtI35ttsNIhZO GEk8JepNd6lXVA0hdcbdYRkeSVsCTl8Cq0UWHh019Kem7ficqF9uh7YFtqcyKnGpN/XHFE+a9KY fuhj1Wi9/QX9zU74qZrARsba4zPI6tEcpVAxYwbVSxNfRRlMmJ7IENlUsPd02e67mJLFG4iZIUY l/rmUOgbzcyFsedg0iSorX6Nxopw7QoBr9QClYJL+htuFY8ePYpRLtdcie0OfyT+WFAH/P5ZHJL xLCzABb4cd06XydCUFLdZ7gGlV/k1YuU99Jc3+CC9R/9h94yy/wIFeRGzoEh2wqY2L+ytIlwlad AafFzRWfYBjWr0L7TqV9LGhAlxRE7Kw2GoG/nBn6Qi0FJInArD2kGsg5p1PicX4W+yOy9JISrYk EU+l8qkoP/ejzFyWxl0XQ38gjKFM3GCDEoKg8YDzNe40fLQNpjl+TzRWXk5LmE8b/Ky/caPv1JD DQZrBik6lfi1viXT+AwrK1V/DZwjYoWN8r1brxlec6vfif0Xmd7u3aJMyyOqsJumUf5Qm6jx63G ll1srfS0NEnBHPA== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet --- drivers/clk/meson/g12a-aoclk.c | 207 +++++++++++++++++++++----------------= ---- 1 file changed, 107 insertions(+), 100 deletions(-) diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c index 4095a1b2bb80ee430f8aeb56cbcf5ed549188781..3eaf1db16f45a0adf0acd901ed7= ae1f51a9c8dc1 100644 --- a/drivers/clk/meson/g12a-aoclk.c +++ b/drivers/clk/meson/g12a-aoclk.c @@ -43,8 +43,8 @@ * bootloader. The goal is to remove this flag at some point. * Actually removing it will require some extensive test to be done safely. */ -#define AXG_AO_GATE(_name, _reg, _bit) \ -static struct clk_regmap g12a_aoclk_##_name =3D { \ +#define G12A_AO_PCLK(_name, _reg, _bit) \ +static struct clk_regmap g12a_ao_##_name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D (_reg), \ .bit_idx =3D (_bit), \ @@ -60,23 +60,24 @@ static struct clk_regmap g12a_aoclk_##_name =3D { \ }, \ } =20 -AXG_AO_GATE(ahb, AO_CLK_GATE0, 0); -AXG_AO_GATE(ir_in, AO_CLK_GATE0, 1); -AXG_AO_GATE(i2c_m0, AO_CLK_GATE0, 2); -AXG_AO_GATE(i2c_s0, AO_CLK_GATE0, 3); -AXG_AO_GATE(uart, AO_CLK_GATE0, 4); -AXG_AO_GATE(prod_i2c, AO_CLK_GATE0, 5); -AXG_AO_GATE(uart2, AO_CLK_GATE0, 6); -AXG_AO_GATE(ir_out, AO_CLK_GATE0, 7); -AXG_AO_GATE(saradc, AO_CLK_GATE0, 8); -AXG_AO_GATE(mailbox, AO_CLK_GATE0_SP, 0); -AXG_AO_GATE(m3, AO_CLK_GATE0_SP, 1); -AXG_AO_GATE(ahb_sram, AO_CLK_GATE0_SP, 2); -AXG_AO_GATE(rti, AO_CLK_GATE0_SP, 3); -AXG_AO_GATE(m4_fclk, AO_CLK_GATE0_SP, 4); -AXG_AO_GATE(m4_hclk, AO_CLK_GATE0_SP, 5); +G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0); +G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1); +G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2); +G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3); +G12A_AO_PCLK(uart, AO_CLK_GATE0, 4); +G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5); +G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6); +G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7); +G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8); =20 -static struct clk_regmap g12a_aoclk_cts_oscin =3D { +G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0); +G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1); +G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2); +G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3); +G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4); +G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5); + +static struct clk_regmap g12a_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTI_PWR_CNTL_REG0, .bit_idx =3D 14, @@ -103,22 +104,22 @@ static const struct meson_clk_dualdiv_param g12a_32k_= div_table[] =3D { =20 /* 32k_by_oscin clock */ =20 -static struct clk_regmap g12a_aoclk_32k_by_oscin_pre =3D { +static struct clk_regmap g12a_ao_32k_by_oscin_pre =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTC_ALT_CLK_CNTL0, .bit_idx =3D 31, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_32k_by_oscin_pre", + .name =3D "ao_32k_by_oscin_pre", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_cts_oscin.hw + &g12a_ao_cts_oscin.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap g12a_aoclk_32k_by_oscin_div =3D { +static struct clk_regmap g12a_ao_32k_by_oscin_div =3D { .data =3D &(struct meson_clk_dualdiv_data){ .n1 =3D { .reg_off =3D AO_RTC_ALT_CLK_CNTL0, @@ -148,16 +149,16 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_div = =3D { .table =3D g12a_32k_div_table, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_32k_by_oscin_div", + .name =3D "ao_32k_by_oscin_div", .ops =3D &meson_clk_dualdiv_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_32k_by_oscin_pre.hw + &g12a_ao_32k_by_oscin_pre.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap g12a_aoclk_32k_by_oscin_sel =3D { +static struct clk_regmap g12a_ao_32k_by_oscin_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTC_ALT_CLK_CNTL1, .mask =3D 0x1, @@ -165,27 +166,27 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_32k_by_oscin_sel", + .name =3D "ao_32k_by_oscin_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_32k_by_oscin_div.hw, - &g12a_aoclk_32k_by_oscin_pre.hw, + &g12a_ao_32k_by_oscin_div.hw, + &g12a_ao_32k_by_oscin_pre.hw, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap g12a_aoclk_32k_by_oscin =3D { +static struct clk_regmap g12a_ao_32k_by_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTC_ALT_CLK_CNTL0, .bit_idx =3D 30, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_32k_by_oscin", + .name =3D "ao_32k_by_oscin", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_32k_by_oscin_sel.hw + &g12a_ao_32k_by_oscin_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -194,22 +195,22 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin =3D { =20 /* cec clock */ =20 -static struct clk_regmap g12a_aoclk_cec_pre =3D { +static struct clk_regmap g12a_ao_cec_pre =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_CEC_CLK_CNTL_REG0, .bit_idx =3D 31, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_cec_pre", + .name =3D "ao_cec_pre", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_cts_oscin.hw + &g12a_ao_cts_oscin.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap g12a_aoclk_cec_div =3D { +static struct clk_regmap g12a_ao_cec_div =3D { .data =3D &(struct meson_clk_dualdiv_data){ .n1 =3D { .reg_off =3D AO_CEC_CLK_CNTL_REG0, @@ -239,16 +240,16 @@ static struct clk_regmap g12a_aoclk_cec_div =3D { .table =3D g12a_32k_div_table, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_cec_div", + .name =3D "ao_cec_div", .ops =3D &meson_clk_dualdiv_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_cec_pre.hw + &g12a_ao_cec_pre.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap g12a_aoclk_cec_sel =3D { +static struct clk_regmap g12a_ao_cec_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_CEC_CLK_CNTL_REG1, .mask =3D 0x1, @@ -256,34 +257,34 @@ static struct clk_regmap g12a_aoclk_cec_sel =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_cec_sel", + .name =3D "ao_cec_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_cec_div.hw, - &g12a_aoclk_cec_pre.hw, + &g12a_ao_cec_div.hw, + &g12a_ao_cec_pre.hw, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap g12a_aoclk_cec =3D { +static struct clk_regmap g12a_ao_cec =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_CEC_CLK_CNTL_REG0, .bit_idx =3D 30, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_cec", + .name =3D "ao_cec", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_cec_sel.hw + &g12a_ao_cec_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap g12a_aoclk_cts_rtc_oscin =3D { +static struct clk_regmap g12a_ao_cts_rtc_oscin =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTI_PWR_CNTL_REG0, .mask =3D 0x1, @@ -291,10 +292,10 @@ static struct clk_regmap g12a_aoclk_cts_rtc_oscin =3D= { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_cts_rtc_oscin", + .name =3D "ao_cts_rtc_oscin", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { - { .hw =3D &g12a_aoclk_32k_by_oscin.hw }, + { .hw =3D &g12a_ao_32k_by_oscin.hw }, { .fw_name =3D "ext-32k-0", }, }, .num_parents =3D 2, @@ -302,7 +303,7 @@ static struct clk_regmap g12a_aoclk_cts_rtc_oscin =3D { }, }; =20 -static struct clk_regmap g12a_aoclk_clk81 =3D { +static struct clk_regmap g12a_ao_clk81 =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTI_PWR_CNTL_REG0, .mask =3D 0x1, @@ -310,68 +311,74 @@ static struct clk_regmap g12a_aoclk_clk81 =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ + /* + * NOTE: this is one of the infamous clock the pwm driver + * can request directly by its global name. It's wrong but + * there is not much we can do about it until the support + * for the old pwm bindings is dropped + */ .name =3D "g12a_ao_clk81", .ops =3D &clk_regmap_mux_ro_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "mpeg-clk", }, - { .hw =3D &g12a_aoclk_cts_rtc_oscin.hw }, + { .hw =3D &g12a_ao_cts_rtc_oscin.hw }, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap g12a_aoclk_saradc_mux =3D { +static struct clk_regmap g12a_ao_saradc_mux =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_SAR_CLK, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_saradc_mux", + .name =3D "ao_saradc_mux", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "xtal", }, - { .hw =3D &g12a_aoclk_clk81.hw }, + { .hw =3D &g12a_ao_clk81.hw }, }, .num_parents =3D 2, }, }; =20 -static struct clk_regmap g12a_aoclk_saradc_div =3D { +static struct clk_regmap g12a_ao_saradc_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D AO_SAR_CLK, .shift =3D 0, .width =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_saradc_div", + .name =3D "ao_saradc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_saradc_mux.hw + &g12a_ao_saradc_mux.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap g12a_aoclk_saradc_gate =3D { +static struct clk_regmap g12a_ao_saradc_gate =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D AO_SAR_CLK, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_saradc_gate", + .name =3D "ao_saradc_gate", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_saradc_div.hw + &g12a_ao_saradc_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const unsigned int g12a_aoclk_reset[] =3D { +static const unsigned int g12a_ao_reset[] =3D { [RESET_AO_IR_IN] =3D 16, [RESET_AO_UART] =3D 17, [RESET_AO_I2C_M] =3D 18, @@ -381,65 +388,65 @@ static const unsigned int g12a_aoclk_reset[] =3D { [RESET_AO_IR_OUT] =3D 23, }; =20 -static struct clk_hw *g12a_aoclk_hw_clks[] =3D { - [CLKID_AO_AHB] =3D &g12a_aoclk_ahb.hw, - [CLKID_AO_IR_IN] =3D &g12a_aoclk_ir_in.hw, - [CLKID_AO_I2C_M0] =3D &g12a_aoclk_i2c_m0.hw, - [CLKID_AO_I2C_S0] =3D &g12a_aoclk_i2c_s0.hw, - [CLKID_AO_UART] =3D &g12a_aoclk_uart.hw, - [CLKID_AO_PROD_I2C] =3D &g12a_aoclk_prod_i2c.hw, - [CLKID_AO_UART2] =3D &g12a_aoclk_uart2.hw, - [CLKID_AO_IR_OUT] =3D &g12a_aoclk_ir_out.hw, - [CLKID_AO_SAR_ADC] =3D &g12a_aoclk_saradc.hw, - [CLKID_AO_MAILBOX] =3D &g12a_aoclk_mailbox.hw, - [CLKID_AO_M3] =3D &g12a_aoclk_m3.hw, - [CLKID_AO_AHB_SRAM] =3D &g12a_aoclk_ahb_sram.hw, - [CLKID_AO_RTI] =3D &g12a_aoclk_rti.hw, - [CLKID_AO_M4_FCLK] =3D &g12a_aoclk_m4_fclk.hw, - [CLKID_AO_M4_HCLK] =3D &g12a_aoclk_m4_hclk.hw, - [CLKID_AO_CLK81] =3D &g12a_aoclk_clk81.hw, - [CLKID_AO_SAR_ADC_SEL] =3D &g12a_aoclk_saradc_mux.hw, - [CLKID_AO_SAR_ADC_DIV] =3D &g12a_aoclk_saradc_div.hw, - [CLKID_AO_SAR_ADC_CLK] =3D &g12a_aoclk_saradc_gate.hw, - [CLKID_AO_CTS_OSCIN] =3D &g12a_aoclk_cts_oscin.hw, - [CLKID_AO_32K_PRE] =3D &g12a_aoclk_32k_by_oscin_pre.hw, - [CLKID_AO_32K_DIV] =3D &g12a_aoclk_32k_by_oscin_div.hw, - [CLKID_AO_32K_SEL] =3D &g12a_aoclk_32k_by_oscin_sel.hw, - [CLKID_AO_32K] =3D &g12a_aoclk_32k_by_oscin.hw, - [CLKID_AO_CEC_PRE] =3D &g12a_aoclk_cec_pre.hw, - [CLKID_AO_CEC_DIV] =3D &g12a_aoclk_cec_div.hw, - [CLKID_AO_CEC_SEL] =3D &g12a_aoclk_cec_sel.hw, - [CLKID_AO_CEC] =3D &g12a_aoclk_cec.hw, - [CLKID_AO_CTS_RTC_OSCIN] =3D &g12a_aoclk_cts_rtc_oscin.hw, +static struct clk_hw *g12a_ao_hw_clks[] =3D { + [CLKID_AO_AHB] =3D &g12a_ao_ahb.hw, + [CLKID_AO_IR_IN] =3D &g12a_ao_ir_in.hw, + [CLKID_AO_I2C_M0] =3D &g12a_ao_i2c_m0.hw, + [CLKID_AO_I2C_S0] =3D &g12a_ao_i2c_s0.hw, + [CLKID_AO_UART] =3D &g12a_ao_uart.hw, + [CLKID_AO_PROD_I2C] =3D &g12a_ao_prod_i2c.hw, + [CLKID_AO_UART2] =3D &g12a_ao_uart2.hw, + [CLKID_AO_IR_OUT] =3D &g12a_ao_ir_out.hw, + [CLKID_AO_SAR_ADC] =3D &g12a_ao_saradc.hw, + [CLKID_AO_MAILBOX] =3D &g12a_ao_mailbox.hw, + [CLKID_AO_M3] =3D &g12a_ao_m3.hw, + [CLKID_AO_AHB_SRAM] =3D &g12a_ao_ahb_sram.hw, + [CLKID_AO_RTI] =3D &g12a_ao_rti.hw, + [CLKID_AO_M4_FCLK] =3D &g12a_ao_m4_fclk.hw, + [CLKID_AO_M4_HCLK] =3D &g12a_ao_m4_hclk.hw, + [CLKID_AO_CLK81] =3D &g12a_ao_clk81.hw, + [CLKID_AO_SAR_ADC_SEL] =3D &g12a_ao_saradc_mux.hw, + [CLKID_AO_SAR_ADC_DIV] =3D &g12a_ao_saradc_div.hw, + [CLKID_AO_SAR_ADC_CLK] =3D &g12a_ao_saradc_gate.hw, + [CLKID_AO_CTS_OSCIN] =3D &g12a_ao_cts_oscin.hw, + [CLKID_AO_32K_PRE] =3D &g12a_ao_32k_by_oscin_pre.hw, + [CLKID_AO_32K_DIV] =3D &g12a_ao_32k_by_oscin_div.hw, + [CLKID_AO_32K_SEL] =3D &g12a_ao_32k_by_oscin_sel.hw, + [CLKID_AO_32K] =3D &g12a_ao_32k_by_oscin.hw, + [CLKID_AO_CEC_PRE] =3D &g12a_ao_cec_pre.hw, + [CLKID_AO_CEC_DIV] =3D &g12a_ao_cec_div.hw, + [CLKID_AO_CEC_SEL] =3D &g12a_ao_cec_sel.hw, + [CLKID_AO_CEC] =3D &g12a_ao_cec.hw, + [CLKID_AO_CTS_RTC_OSCIN] =3D &g12a_ao_cts_rtc_oscin.hw, }; =20 -static const struct meson_aoclk_data g12a_aoclkc_data =3D { +static const struct meson_aoclk_data g12a_ao_clkc_data =3D { .reset_reg =3D AO_RTI_GEN_CNTL_REG0, - .num_reset =3D ARRAY_SIZE(g12a_aoclk_reset), - .reset =3D g12a_aoclk_reset, + .num_reset =3D ARRAY_SIZE(g12a_ao_reset), + .reset =3D g12a_ao_reset, .hw_clks =3D { - .hws =3D g12a_aoclk_hw_clks, - .num =3D ARRAY_SIZE(g12a_aoclk_hw_clks), + .hws =3D g12a_ao_hw_clks, + .num =3D ARRAY_SIZE(g12a_ao_hw_clks), }, }; =20 -static const struct of_device_id g12a_aoclkc_match_table[] =3D { +static const struct of_device_id g12a_ao_clkc_match_table[] =3D { { .compatible =3D "amlogic,meson-g12a-aoclkc", - .data =3D &g12a_aoclkc_data, + .data =3D &g12a_ao_clkc_data, }, { } }; -MODULE_DEVICE_TABLE(of, g12a_aoclkc_match_table); +MODULE_DEVICE_TABLE(of, g12a_ao_clkc_match_table); =20 -static struct platform_driver g12a_aoclkc_driver =3D { +static struct platform_driver g12a_ao_clkc_driver =3D { .probe =3D meson_aoclkc_probe, .driver =3D { .name =3D "g12a-aoclkc", - .of_match_table =3D g12a_aoclkc_match_table, + .of_match_table =3D g12a_ao_clkc_match_table, }, }; -module_platform_driver(g12a_aoclkc_driver); +module_platform_driver(g12a_ao_clkc_driver); =20 MODULE_DESCRIPTION("Amlogic G12A Always-ON Clock Controller driver"); MODULE_LICENSE("GPL"); --=20 2.47.2