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Wed, 02 Jul 2025 08:27:15 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:26:01 +0200 Subject: [PATCH 03/26] clk: amlogic: axg-ao: naming consistency alignment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-3-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10920; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=1IvHyI1bjjxPKpLk03HL+ct5ZNMHSy2xdey6fod754c=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoZU+5KF0rmce/op3Zg9Js+LvwL+6nmECdDWMyE lC5z2yigISJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaGVPuQAKCRDm/A8cN/La hWRDEACpUEiSnvz3yj+hAPAnLm+8aJNj/17s9/l2eMyIh+RdVuwLUTfPrdK47kGuRVNqoOGXWc8 C9/PzdTGmzx5rpld6WEyheLWJOhPtds96EPwxO271qieDpOuGyaRBoV+hyIpW5dRzeUgU1f286b S4h41fFVAfx+So0MWEZqrYKvaHuApxGf9k6RK/7EB16Z2JnP917e6jLHixOjtA9L9LPszPU7pQN /NmEnKZQDUT3rjmptoOyjlWUmvWX2KR9a89PGJb8+oFdGAsjoV6f6O3UXwfin1G6Wgu3rTZl/QY RxudlxK0VPgcjQnzOKtmz2sqd+enkV6vn314pVYpjRNo50wDb0pvCyLc2i4nteCSZF0jkQ8uC5R vQP5BTIsFQ7z6xbMqh89RQdmZY48Yh98NP8sGF4WxUImV7EJJHsG5CXHLkDTLLzYV5D3OnAtC2g mKby3K/mprCeMofak3rx0JSI0nPp/genQyqgIlQ2AlGSTfHA5e0J4aJ683WoZwnZ6iGYTIRj0U8 o9o20bWm2lWPa8VKKL+4MfGd2c4AUMZJDbSohVnAfKw+SOol9Ttis2dt90CvMyibzvQZBJ4V+F3 lmJT4z43ceMa5xf1hU3sONxB6zSkPnhb6wWQUHbTcVu0KaxrHCCOlySj7AX9XpDyNQhv1BFADA0 3LDKyl5e+A69mtw== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg-aoclk.c | 116 ++++++++++++++++++++++----------------= ---- 1 file changed, 61 insertions(+), 55 deletions(-) diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c index cd5d0b5ebdb237a74129b44410318748e48780d1..a0c58dc8e950a05c340c3427af4= f6ff7661fa84e 100644 --- a/drivers/clk/meson/axg-aoclk.c +++ b/drivers/clk/meson/axg-aoclk.c @@ -35,7 +35,7 @@ #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 #define AXG_AO_GATE(_name, _bit) \ -static struct clk_regmap axg_aoclk_##_name =3D { \ +static struct clk_regmap axg_ao_##_name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D (AO_RTI_GEN_CNTL_REG0), \ .bit_idx =3D (_bit), \ @@ -59,7 +59,7 @@ AXG_AO_GATE(uart2, 5); AXG_AO_GATE(ir_blaster, 6); AXG_AO_GATE(saradc, 7); =20 -static struct clk_regmap axg_aoclk_cts_oscin =3D { +static struct clk_regmap axg_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTI_PWR_CNTL_REG0, .bit_idx =3D 14, @@ -74,7 +74,7 @@ static struct clk_regmap axg_aoclk_cts_oscin =3D { }, }; =20 -static struct clk_regmap axg_aoclk_32k_pre =3D { +static struct clk_regmap axg_ao_32k_pre =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTC_ALT_CLK_CNTL0, .bit_idx =3D 31, @@ -83,7 +83,7 @@ static struct clk_regmap axg_aoclk_32k_pre =3D { .name =3D "axg_ao_32k_pre", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_aoclk_cts_oscin.hw + &axg_ao_cts_oscin.hw }, .num_parents =3D 1, }, @@ -99,7 +99,7 @@ static const struct meson_clk_dualdiv_param axg_32k_div_t= able[] =3D { }, {} }; =20 -static struct clk_regmap axg_aoclk_32k_div =3D { +static struct clk_regmap axg_ao_32k_div =3D { .data =3D &(struct meson_clk_dualdiv_data){ .n1 =3D { .reg_off =3D AO_RTC_ALT_CLK_CNTL0, @@ -132,13 +132,13 @@ static struct clk_regmap axg_aoclk_32k_div =3D { .name =3D "axg_ao_32k_div", .ops =3D &meson_clk_dualdiv_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_aoclk_32k_pre.hw + &axg_ao_32k_pre.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap axg_aoclk_32k_sel =3D { +static struct clk_regmap axg_ao_32k_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTC_ALT_CLK_CNTL1, .mask =3D 0x1, @@ -149,15 +149,15 @@ static struct clk_regmap axg_aoclk_32k_sel =3D { .name =3D "axg_ao_32k_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_aoclk_32k_div.hw, - &axg_aoclk_32k_pre.hw, + &axg_ao_32k_div.hw, + &axg_ao_32k_pre.hw, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap axg_aoclk_32k =3D { +static struct clk_regmap axg_ao_32k =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTC_ALT_CLK_CNTL0, .bit_idx =3D 30, @@ -166,14 +166,14 @@ static struct clk_regmap axg_aoclk_32k =3D { .name =3D "axg_ao_32k", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_aoclk_32k_sel.hw + &axg_ao_32k_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap axg_aoclk_cts_rtc_oscin =3D { +static struct clk_regmap axg_ao_cts_rtc_oscin =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTI_PWR_CNTL_REG0, .mask =3D 0x1, @@ -184,7 +184,7 @@ static struct clk_regmap axg_aoclk_cts_rtc_oscin =3D { .name =3D "axg_ao_cts_rtc_oscin", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { - { .hw =3D &axg_aoclk_32k.hw }, + { .hw =3D &axg_ao_32k.hw }, { .fw_name =3D "ext_32k-0", }, }, .num_parents =3D 2, @@ -192,7 +192,7 @@ static struct clk_regmap axg_aoclk_cts_rtc_oscin =3D { }, }; =20 -static struct clk_regmap axg_aoclk_clk81 =3D { +static struct clk_regmap axg_ao_clk81 =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTI_PWR_CNTL_REG0, .mask =3D 0x1, @@ -200,68 +200,74 @@ static struct clk_regmap axg_aoclk_clk81 =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ + /* + * NOTE: this is one of the infamous clock the pwm driver + * can request directly by its global name. It's wrong but + * there is not much we can do about it until the support + * for the old pwm bindings is dropped + */ .name =3D "axg_ao_clk81", .ops =3D &clk_regmap_mux_ro_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "mpeg-clk", }, - { .hw =3D &axg_aoclk_cts_rtc_oscin.hw }, + { .hw =3D &axg_ao_cts_rtc_oscin.hw }, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap axg_aoclk_saradc_mux =3D { +static struct clk_regmap axg_ao_saradc_mux =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_SAR_CLK, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "axg_ao_saradc_mux", + .name =3D "ao_saradc_mux", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "xtal", }, - { .hw =3D &axg_aoclk_clk81.hw }, + { .hw =3D &axg_ao_clk81.hw }, }, .num_parents =3D 2, }, }; =20 -static struct clk_regmap axg_aoclk_saradc_div =3D { +static struct clk_regmap axg_ao_saradc_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D AO_SAR_CLK, .shift =3D 0, .width =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "axg_ao_saradc_div", + .name =3D "ao_saradc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_aoclk_saradc_mux.hw + &axg_ao_saradc_mux.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap axg_aoclk_saradc_gate =3D { +static struct clk_regmap axg_ao_saradc_gate =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D AO_SAR_CLK, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "axg_ao_saradc_gate", + .name =3D "ao_saradc_gate", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_aoclk_saradc_div.hw + &axg_ao_saradc_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const unsigned int axg_aoclk_reset[] =3D { +static const unsigned int axg_ao_reset[] =3D { [RESET_AO_REMOTE] =3D 16, [RESET_AO_I2C_MASTER] =3D 18, [RESET_AO_I2C_SLAVE] =3D 19, @@ -270,53 +276,53 @@ static const unsigned int axg_aoclk_reset[] =3D { [RESET_AO_IR_BLASTER] =3D 23, }; =20 -static struct clk_hw *axg_aoclk_hw_clks[] =3D { - [CLKID_AO_REMOTE] =3D &axg_aoclk_remote.hw, - [CLKID_AO_I2C_MASTER] =3D &axg_aoclk_i2c_master.hw, - [CLKID_AO_I2C_SLAVE] =3D &axg_aoclk_i2c_slave.hw, - [CLKID_AO_UART1] =3D &axg_aoclk_uart1.hw, - [CLKID_AO_UART2] =3D &axg_aoclk_uart2.hw, - [CLKID_AO_IR_BLASTER] =3D &axg_aoclk_ir_blaster.hw, - [CLKID_AO_SAR_ADC] =3D &axg_aoclk_saradc.hw, - [CLKID_AO_CLK81] =3D &axg_aoclk_clk81.hw, - [CLKID_AO_SAR_ADC_SEL] =3D &axg_aoclk_saradc_mux.hw, - [CLKID_AO_SAR_ADC_DIV] =3D &axg_aoclk_saradc_div.hw, - [CLKID_AO_SAR_ADC_CLK] =3D &axg_aoclk_saradc_gate.hw, - [CLKID_AO_CTS_OSCIN] =3D &axg_aoclk_cts_oscin.hw, - [CLKID_AO_32K_PRE] =3D &axg_aoclk_32k_pre.hw, - [CLKID_AO_32K_DIV] =3D &axg_aoclk_32k_div.hw, - [CLKID_AO_32K_SEL] =3D &axg_aoclk_32k_sel.hw, - [CLKID_AO_32K] =3D &axg_aoclk_32k.hw, - [CLKID_AO_CTS_RTC_OSCIN] =3D &axg_aoclk_cts_rtc_oscin.hw, +static struct clk_hw *axg_ao_hw_clks[] =3D { + [CLKID_AO_REMOTE] =3D &axg_ao_remote.hw, + [CLKID_AO_I2C_MASTER] =3D &axg_ao_i2c_master.hw, + [CLKID_AO_I2C_SLAVE] =3D &axg_ao_i2c_slave.hw, + [CLKID_AO_UART1] =3D &axg_ao_uart1.hw, + [CLKID_AO_UART2] =3D &axg_ao_uart2.hw, + [CLKID_AO_IR_BLASTER] =3D &axg_ao_ir_blaster.hw, + [CLKID_AO_SAR_ADC] =3D &axg_ao_saradc.hw, + [CLKID_AO_CLK81] =3D &axg_ao_clk81.hw, + [CLKID_AO_SAR_ADC_SEL] =3D &axg_ao_saradc_mux.hw, + [CLKID_AO_SAR_ADC_DIV] =3D &axg_ao_saradc_div.hw, + [CLKID_AO_SAR_ADC_CLK] =3D &axg_ao_saradc_gate.hw, + [CLKID_AO_CTS_OSCIN] =3D &axg_ao_cts_oscin.hw, + [CLKID_AO_32K_PRE] =3D &axg_ao_32k_pre.hw, + [CLKID_AO_32K_DIV] =3D &axg_ao_32k_div.hw, + [CLKID_AO_32K_SEL] =3D &axg_ao_32k_sel.hw, + [CLKID_AO_32K] =3D &axg_ao_32k.hw, + [CLKID_AO_CTS_RTC_OSCIN] =3D &axg_ao_cts_rtc_oscin.hw, }; =20 -static const struct meson_aoclk_data axg_aoclkc_data =3D { +static const struct meson_aoclk_data axg_ao_clkc_data =3D { .reset_reg =3D AO_RTI_GEN_CNTL_REG0, - .num_reset =3D ARRAY_SIZE(axg_aoclk_reset), - .reset =3D axg_aoclk_reset, + .num_reset =3D ARRAY_SIZE(axg_ao_reset), + .reset =3D axg_ao_reset, .hw_clks =3D { - .hws =3D axg_aoclk_hw_clks, - .num =3D ARRAY_SIZE(axg_aoclk_hw_clks), + .hws =3D axg_ao_hw_clks, + .num =3D ARRAY_SIZE(axg_ao_hw_clks), }, }; =20 -static const struct of_device_id axg_aoclkc_match_table[] =3D { +static const struct of_device_id axg_ao_clkc_match_table[] =3D { { .compatible =3D "amlogic,meson-axg-aoclkc", - .data =3D &axg_aoclkc_data, + .data =3D &axg_ao_clkc_data, }, { } }; -MODULE_DEVICE_TABLE(of, axg_aoclkc_match_table); +MODULE_DEVICE_TABLE(of, axg_ao_clkc_match_table); =20 -static struct platform_driver axg_aoclkc_driver =3D { +static struct platform_driver axg_ao_clkc_driver =3D { .probe =3D meson_aoclkc_probe, .driver =3D { - .name =3D "axg-aoclkc", - .of_match_table =3D axg_aoclkc_match_table, + .name =3D "axg-ao-clkc", + .of_match_table =3D axg_ao_clkc_match_table, }, }; -module_platform_driver(axg_aoclkc_driver); +module_platform_driver(axg_ao_clkc_driver); =20 MODULE_DESCRIPTION("Amlogic AXG Always-ON Clock Controller driver"); MODULE_LICENSE("GPL"); --=20 2.47.2