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Wed, 02 Jul 2025 08:27:37 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:26:23 +0200 Subject: [PATCH 25/26] clk: amlogic: align s4 and c3 pwm clock descriptions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-25-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=23797; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=0XolTSN9OEuc3oqxZff5/9uDdWtVO1N6nfCdJuJ8PzE=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoZU/N3en7Oc/O38sMsx2hNRLUUGOX1T7ReZLnf uwsaFyRd1CJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaGVPzQAKCRDm/A8cN/La hYGrEACHTf4xN/DA8h7vS15XupFyMIp1q9fdcBeoKHtfzn3qICLzUdhIBzq+3Tj6AHEBMvudmI/ H1x0c0cjzh/iu2TD0p+JQeaF/RZhlwQRSmi/YZXrL8jKmwC4+OzrUfWRAgNL9kv45MZKrtBMpt8 gNI5hHEW46XFuyYY0qjcnTYqn0Vu5ha3Ill4pGjDVpgaNXMYmqNuXwfGD3HrDndkjrlDzP9rkMA 86+2iEAssPmjgAA23WW4xlK/NTMzNXRAQFRjzVhmu9IFsunjY/ZNjsToFOETU2NP/XBARPNm4Hn IeWBdNHlmbGWozc+VPpr58ykEtEb32Xy9lUa/RRMtZwWODNGgKCF1WkDsScuZ41B6Hr+QPmuM9B Mp5xymNXwNge+G4LURTLSjvV6NVxNw0Ail1T0cy+djTwuTM9j2QEOtjGzIhNTEdqS9kNXZvgqDe EmRMQZkJ2kYAPuXjKg/hn0Wq4FsxZnzFCo6ek7XRXkEc+sRM/ySQIwNKleHM1ZWu9PVAKDGMQcd iImhYGQ6vlWqroQqfElWzytyfzFgf5JYiW2FlPZgalyXjOr3AeW1NhAnoBLe3XUqzmWEbxULtKi O+y+mES7i2EcMMt1xNXis6qjmEq66Bcef3WOJZf+gLbG/VZO6tLgoNThiS5vkoD6Bm61UMGdc2p 2K9FT5XnwZspk5w== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 s4 and c3 follow exactly the same structure when it comes to PWM clocks but differ in the way these clocks are described, for no obvious reason. Align the description of the pwm clocks of these SoCs with the composite clock helpers. Signed-off-by: Jerome Brunet Reviewed-by: Chuan Liu --- drivers/clk/meson/c3-peripherals.c | 204 +++++---------- drivers/clk/meson/s4-peripherals.c | 508 +++------------------------------= ---- 2 files changed, 103 insertions(+), 609 deletions(-) diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c index 02c9820cd98655e57a290859b595cf09d39e5fe3..fd35f9b7994720d069c5f72142d= 6064790d40b60 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -48,6 +48,15 @@ #define SPIFC_CLK_CTRL 0x1a0 #define NNA_CLK_CTRL 0x220 =20 +#define C3_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ + MESON_COMP_SEL(c3_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) + +#define C3_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(c3_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define C3_COMP_GATE(_name, _reg, _bit) \ + MESON_COMP_GATE(c3_, _name, _reg, _bit, CLK_SET_RATE_PARENT) + static struct clk_regmap c3_rtc_xtal_clkin =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D RTC_BY_OSCIN_CTRL0, @@ -512,146 +521,61 @@ static const struct clk_parent_data c3_pwm_parents[]= =3D { { .fw_name =3D "fdiv3" } }; =20 -#define C3_PWM_CLK_MUX(_name, _reg, _shift) { \ - .data =3D &(struct clk_regmap_mux_data) { \ - .offset =3D _reg, \ - .mask =3D 0x3, \ - .shift =3D _shift, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name "_sel", \ - .ops =3D &clk_regmap_mux_ops, \ - .parent_data =3D c3_pwm_parents, \ - .num_parents =3D ARRAY_SIZE(c3_pwm_parents), \ - }, \ -} - -#define C3_PWM_CLK_DIV(_name, _reg, _shift) { \ - .data =3D &(struct clk_regmap_div_data) { \ - .offset =3D _reg, \ - .shift =3D _shift, \ - .width =3D 8, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name "_div", \ - .ops =3D &clk_regmap_divider_ops, \ - .parent_names =3D (const char *[]) { #_name "_sel" },\ - .num_parents =3D 1, \ - .flags =3D CLK_SET_RATE_PARENT, \ - }, \ -} - -#define C3_PWM_CLK_GATE(_name, _reg, _bit) { \ - .data =3D &(struct clk_regmap_gate_data) { \ - .offset =3D _reg, \ - .bit_idx =3D _bit, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_names =3D (const char *[]) { #_name "_div" },\ - .num_parents =3D 1, \ - .flags =3D CLK_SET_RATE_PARENT, \ - }, \ -} - -static struct clk_regmap c3_pwm_a_sel =3D - C3_PWM_CLK_MUX(pwm_a, PWM_CLK_AB_CTRL, 9); -static struct clk_regmap c3_pwm_a_div =3D - C3_PWM_CLK_DIV(pwm_a, PWM_CLK_AB_CTRL, 0); -static struct clk_regmap c3_pwm_a =3D - C3_PWM_CLK_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); - -static struct clk_regmap c3_pwm_b_sel =3D - C3_PWM_CLK_MUX(pwm_b, PWM_CLK_AB_CTRL, 25); -static struct clk_regmap c3_pwm_b_div =3D - C3_PWM_CLK_DIV(pwm_b, PWM_CLK_AB_CTRL, 16); -static struct clk_regmap c3_pwm_b =3D - C3_PWM_CLK_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); - -static struct clk_regmap c3_pwm_c_sel =3D - C3_PWM_CLK_MUX(pwm_c, PWM_CLK_CD_CTRL, 9); -static struct clk_regmap c3_pwm_c_div =3D - C3_PWM_CLK_DIV(pwm_c, PWM_CLK_CD_CTRL, 0); -static struct clk_regmap c3_pwm_c =3D - C3_PWM_CLK_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); - -static struct clk_regmap c3_pwm_d_sel =3D - C3_PWM_CLK_MUX(pwm_d, PWM_CLK_CD_CTRL, 25); -static struct clk_regmap c3_pwm_d_div =3D - C3_PWM_CLK_DIV(pwm_d, PWM_CLK_CD_CTRL, 16); -static struct clk_regmap c3_pwm_d =3D - C3_PWM_CLK_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); - -static struct clk_regmap c3_pwm_e_sel =3D - C3_PWM_CLK_MUX(pwm_e, PWM_CLK_EF_CTRL, 9); -static struct clk_regmap c3_pwm_e_div =3D - C3_PWM_CLK_DIV(pwm_e, PWM_CLK_EF_CTRL, 0); -static struct clk_regmap c3_pwm_e =3D - C3_PWM_CLK_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); - -static struct clk_regmap c3_pwm_f_sel =3D - C3_PWM_CLK_MUX(pwm_f, PWM_CLK_EF_CTRL, 25); -static struct clk_regmap c3_pwm_f_div =3D - C3_PWM_CLK_DIV(pwm_f, PWM_CLK_EF_CTRL, 16); -static struct clk_regmap c3_pwm_f =3D - C3_PWM_CLK_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); - -static struct clk_regmap c3_pwm_g_sel =3D - C3_PWM_CLK_MUX(pwm_g, PWM_CLK_GH_CTRL, 9); -static struct clk_regmap c3_pwm_g_div =3D - C3_PWM_CLK_DIV(pwm_g, PWM_CLK_GH_CTRL, 0); -static struct clk_regmap c3_pwm_g =3D - C3_PWM_CLK_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); - -static struct clk_regmap c3_pwm_h_sel =3D - C3_PWM_CLK_MUX(pwm_h, PWM_CLK_GH_CTRL, 25); -static struct clk_regmap c3_pwm_h_div =3D - C3_PWM_CLK_DIV(pwm_h, PWM_CLK_GH_CTRL, 16); -static struct clk_regmap c3_pwm_h =3D - C3_PWM_CLK_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); - -static struct clk_regmap c3_pwm_i_sel =3D - C3_PWM_CLK_MUX(pwm_i, PWM_CLK_IJ_CTRL, 9); -static struct clk_regmap c3_pwm_i_div =3D - C3_PWM_CLK_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0); -static struct clk_regmap c3_pwm_i =3D - C3_PWM_CLK_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8); - -static struct clk_regmap c3_pwm_j_sel =3D - C3_PWM_CLK_MUX(pwm_j, PWM_CLK_IJ_CTRL, 25); -static struct clk_regmap c3_pwm_j_div =3D - C3_PWM_CLK_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16); -static struct clk_regmap c3_pwm_j =3D - C3_PWM_CLK_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24); - -static struct clk_regmap c3_pwm_k_sel =3D - C3_PWM_CLK_MUX(pwm_k, PWM_CLK_KL_CTRL, 9); -static struct clk_regmap c3_pwm_k_div =3D - C3_PWM_CLK_DIV(pwm_k, PWM_CLK_KL_CTRL, 0); -static struct clk_regmap c3_pwm_k =3D - C3_PWM_CLK_GATE(pwm_k, PWM_CLK_KL_CTRL, 8); - -static struct clk_regmap c3_pwm_l_sel =3D - C3_PWM_CLK_MUX(pwm_l, PWM_CLK_KL_CTRL, 25); -static struct clk_regmap c3_pwm_l_div =3D - C3_PWM_CLK_DIV(pwm_l, PWM_CLK_KL_CTRL, 16); -static struct clk_regmap c3_pwm_l =3D - C3_PWM_CLK_GATE(pwm_l, PWM_CLK_KL_CTRL, 24); - -static struct clk_regmap c3_pwm_m_sel =3D - C3_PWM_CLK_MUX(pwm_m, PWM_CLK_MN_CTRL, 9); -static struct clk_regmap c3_pwm_m_div =3D - C3_PWM_CLK_DIV(pwm_m, PWM_CLK_MN_CTRL, 0); -static struct clk_regmap c3_pwm_m =3D - C3_PWM_CLK_GATE(pwm_m, PWM_CLK_MN_CTRL, 8); - -static struct clk_regmap c3_pwm_n_sel =3D - C3_PWM_CLK_MUX(pwm_n, PWM_CLK_MN_CTRL, 25); -static struct clk_regmap c3_pwm_n_div =3D - C3_PWM_CLK_DIV(pwm_n, PWM_CLK_MN_CTRL, 16); -static struct clk_regmap c3_pwm_n =3D - C3_PWM_CLK_GATE(pwm_n, PWM_CLK_MN_CTRL, 24); +static C3_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8); +static C3_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); + +static C3_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8); +static C3_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); + +static C3_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8); +static C3_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); + +static C3_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8); +static C3_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); + +static C3_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8); +static C3_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); + +static C3_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8); +static C3_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); + +static C3_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8); +static C3_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); + +static C3_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8); +static C3_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); + +static C3_COMP_SEL(pwm_i, PWM_CLK_IJ_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0, 8); +static C3_COMP_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8); + +static C3_COMP_SEL(pwm_j, PWM_CLK_IJ_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16, 8); +static C3_COMP_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24); + +static C3_COMP_SEL(pwm_k, PWM_CLK_KL_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_k, PWM_CLK_KL_CTRL, 0, 8); +static C3_COMP_GATE(pwm_k, PWM_CLK_KL_CTRL, 8); + +static C3_COMP_SEL(pwm_l, PWM_CLK_KL_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_l, PWM_CLK_KL_CTRL, 16, 8); +static C3_COMP_GATE(pwm_l, PWM_CLK_KL_CTRL, 24); + +static C3_COMP_SEL(pwm_m, PWM_CLK_MN_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_m, PWM_CLK_MN_CTRL, 0, 8); +static C3_COMP_GATE(pwm_m, PWM_CLK_MN_CTRL, 8); + +static C3_COMP_SEL(pwm_n, PWM_CLK_MN_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_n, PWM_CLK_MN_CTRL, 16, 8); +static C3_COMP_GATE(pwm_n, PWM_CLK_MN_CTRL, 24); =20 static const struct clk_parent_data c3_spicc_parents[] =3D { { .fw_name =3D "oscin" }, diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index 3e048e645b080f9e5982ef908e3f9c43578a0b5f..6d69b132d1e1f5950d73757c45b= 920c9c9052344 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -62,6 +62,15 @@ #define CLKCTRL_PWM_CLK_IJ_CTRL 0x190 #define CLKCTRL_DEMOD_CLK_CTRL 0x200 =20 +#define S4_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ + MESON_COMP_SEL(s4_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) + +#define S4_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(s4_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define S4_COMP_GATE(_name, _reg, _bit) \ + MESON_COMP_GATE(s4_, _name, _reg, _bit, CLK_SET_RATE_PARENT) + static struct clk_regmap s4_rtc_32k_by_oscin_clkin =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_RTC_BY_OSCIN_CTRL0, @@ -2559,484 +2568,45 @@ static const struct clk_parent_data s4_pwm_parents= [] =3D { { .fw_name =3D "fclk_div3", }, }; =20 -static struct clk_regmap s4_pwm_a_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_a_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_a_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_a_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_a_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_a =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_a_gate", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_a_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_b_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_b_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_b_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_b_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_b_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_b =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_b", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_b_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_c_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_c_mux", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_c_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_c_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_c_sel.hw - }, - .num_parents =3D 1, - }, -}; - -static struct clk_regmap s4_pwm_c =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_c", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_c_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_d_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_d_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_d_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_d_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_d_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_d =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_d", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_d_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_e_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_e_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_e_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_e_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_e_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_e =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_e", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_e_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_f_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_f_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; +static S4_COMP_SEL(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0, 8); +static S4_COMP_GATE(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8); =20 -static struct clk_regmap s4_pwm_f_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_f_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_f_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16, 8); +static S4_COMP_GATE(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24); =20 -static struct clk_regmap s4_pwm_f =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_f", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_f_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0, 8); +static S4_COMP_GATE(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8); =20 -static struct clk_regmap s4_pwm_g_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_g_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; +static S4_COMP_SEL(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16, 8); +static S4_COMP_GATE(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24); =20 -static struct clk_regmap s4_pwm_g_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_g_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_g_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0, 8); +static S4_COMP_GATE(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8); =20 -static struct clk_regmap s4_pwm_g =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_g", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_g_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16, 8); +static S4_COMP_GATE(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24); =20 -static struct clk_regmap s4_pwm_h_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_h_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; +static S4_COMP_SEL(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 0, 8); +static S4_COMP_GATE(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 8); =20 -static struct clk_regmap s4_pwm_h_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_h_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_h_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 16, 8); +static S4_COMP_GATE(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 24); =20 -static struct clk_regmap s4_pwm_h =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_h", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_h_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 0, 8); +static S4_COMP_GATE(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 8); =20 -static struct clk_regmap s4_pwm_i_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_i_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_i_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_i_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_i_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_i =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_i", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_i_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_j_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_j_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_j_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_j_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_j_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_j =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_j", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_j_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 16, 8); +static S4_COMP_GATE(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 24); =20 static struct clk_regmap s4_saradc_sel =3D { .data =3D &(struct clk_regmap_mux_data) { --=20 2.47.2