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Wed, 02 Jul 2025 08:27:37 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:26:22 +0200 Subject: [PATCH 24/26] clk: amlogic: add composite clock helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-24-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2898; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=suncESI2oSW1jGwgW8HALT/gxYfqW5NYgFG0TK2ZRwc=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoZU/M8MpgauqMch296c/UgbjKdCbz6RmqaG7+f uOBnQ9nC0yJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaGVPzAAKCRDm/A8cN/La hWnsEACSnG22dz/mQvVC16u619+gXbE7D/A+OD2TuY4CL7XBrH7HphO3oVze0AeyGJ9+rVtJiVX ssivYxqO2B7DNqkWcJovuYcX8hyDwe8UYGhQQeD5mVekxQZR7I4wRvydAqCm1BSxYzP8P3vjCk+ lBF95dmWTj0knQsem7xahxacMQMvGJDZFQ2LgXv1pz4Q4S+8H4xkSJYRIbtugP3eHNID+Y2amyi XvNA04JFI0bOG0FkToEcxsLHHn99qTf7Dle566H2NHgOneBNZWVCvCaaYAW0lIRn7ZoFYN1R7qs 3UEQL9IoK2qtEGynnokTneFzeD6z8U/KcJBk48osJBcAT+asMQQmREI0bYt/jq3DcNQY1Cm2cHT /T9DItBlCT3FVsTMib1JVK7RgHRvg8tZInVzXQoY2yCWM2s6i+KvFDT6doqHLuyh9Hr3Gj/6CjP waFGuO6dxHv5dB3vEtKtiQ5tyKkagvQ6c3ha900qhiGD/Kle2ZWK52DDairL3wXJb6d0+phn1Uf 7T4l8gXupb1X08JGdOrqZ1xYjV9uKUNECM9K4TYjF7yn7QD24AjllGAPIx5eTECYmEzTHZG8zEE 1YPty6nC3eOBIsatncgY27yluN5J+LVZprK7yvi40UNAtlMSsYrTkkr8cWVKD6a9SI6IqSMVwEA HZkuxOWcI66bCVw== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Device composite clocks tend to reproduce the usual sel/div/gate arrangement. Add macros to help define simple composite clocks in the system. The idea is _not_ to replace all instances of mux, div or gate with those macros. It is rather to use it for recurring and/or simple composite clocks, reducing controller verbosity where it makes sense. This should help reviews focus on the tricky parts. Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson-clkc-utils.h | 57 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 57 insertions(+) diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index 95d9f85f7ca22f63a16f8665d6f7a250b21bfdb8..ddadf14b4923781d8807546f35a= 1ba2e6a8a894a 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -48,4 +48,61 @@ struct clk_regmap _name =3D { \ #define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \ __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags) =20 +/* Helpers for the usual sel/div/gate composite clocks */ +#define MESON_COMP_SEL(_prefix, _name, _reg, _shift, _mask, _pdata, \ + _table, _dflags, _iflags) \ +struct clk_regmap _prefix##_name##_sel =3D { \ + .data =3D &(struct clk_regmap_mux_data) { \ + .offset =3D (_reg), \ + .mask =3D (_mask), \ + .shift =3D (_shift), \ + .flags =3D (_dflags), \ + .table =3D (_table), \ + }, \ + .hw.init =3D &(struct clk_init_data){ \ + .name =3D #_name "_sel", \ + .ops =3D &clk_regmap_mux_ops, \ + .parent_data =3D _pdata, \ + .num_parents =3D ARRAY_SIZE(_pdata), \ + .flags =3D (_iflags), \ + }, \ +} + +#define MESON_COMP_DIV(_prefix, _name, _reg, _shift, _width, \ + _dflags, _iflags) \ +struct clk_regmap _prefix##_name##_div =3D { \ + .data =3D &(struct clk_regmap_div_data) { \ + .offset =3D (_reg), \ + .shift =3D (_shift), \ + .width =3D (_width), \ + .flags =3D (_dflags), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name "_div", \ + .ops =3D &clk_regmap_divider_ops, \ + .parent_hws =3D (const struct clk_hw *[]) { \ + &_prefix##_name##_sel.hw \ + }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#define MESON_COMP_GATE(_prefix, _name, _reg, _bit, _iflags) \ +struct clk_regmap _prefix##_name =3D { \ + .data =3D &(struct clk_regmap_gate_data) { \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_hws =3D (const struct clk_hw *[]) { \ + &_prefix##_name##_div.hw \ + }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + #endif --=20 2.47.2