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Wed, 02 Jul 2025 08:27:36 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:26:21 +0200 Subject: [PATCH 23/26] clk: amlogic: use the common pclk definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-23-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9875; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=ssDaR4wz9jG+IVUW3bzaW/s+xN9zK8sGhakg0LDPY+Q=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoZU/LBSs116AIECGxYGVG9zbAYzeZGrNC4zYz8 y9OqUR0oMSJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaGVPywAKCRDm/A8cN/La hapdEAC0txIhiAF5JVyixaFEUIvo6bO+P+U90UBDfyetIF0ahvgGCX9D7yRl7QeavIOaoMwag4Q 3UVKrs+4527yuN15JKV9Bdv62cRJFTP8NMDRBgPOKCk4sPTB5IlUKLQt6+OmSdJB0FeSfP5y+00 rnU0APno9EV0jtAJx72G9wfEJfftNp6UrWDgx0Zxoa+ATLVNGENCMP2OcCuf/yh+xGcepRvOC8V ikEoH59ya9+veFEAOt+EnuMx6iqecfmSGl+UmNjSgrV6EHOvuYec7GyckTw549CprnUntPlp9EW /5zCr9ZgH7+pdNVXhULoQ3tlRhAJuHP0y6ejhABQxCP8BFOshv0YtLMdlLa9VKgYba7evpiINxt sPgwLPVt4fUajoqpA9z3zlUW2osawSj51HSiZ1FOjZdh/nEIJ5WtWl9KbPPY5FShMhg9vZqn7de 6YbSJfW5hxkOReT2LJv5QR+IJmcWOu8pjkdLbjzU2qTfyKwMOYcq0tDKhltET3RBFG2YUZmGNeD kJ6biBSRt7ok0/WdQvn0V7g9iA+LYy6cg7qOL3jhlxjxjCkum8qnVNm+iYdIDhLLgaFXSviDXUY eOVqItzszrIivJ6dDfkEYcVu1wX6oFwyXwr2UZELeJluQ6FQj3YDx92/dsKJLZZNIHE5fgI9LBt wf8vo+kqhrOiGOQ== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Replace marcros defining pclks with the common one, reducing code duplication. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg-aoclk.c | 35 +++++++++----------------- drivers/clk/meson/c3-peripherals.c | 34 +++++++------------------- drivers/clk/meson/g12a-aoclk.c | 50 +++++++++++++++-------------------= ---- drivers/clk/meson/gxbb-aoclk.c | 33 +++++++++---------------- 4 files changed, 51 insertions(+), 101 deletions(-) diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c index 74c2f51424f11cc04a80a3a4918e4de0a5d11d08..902fbd34039cc06d512f1237a1e= 5d9050fd00b4b 100644 --- a/drivers/clk/meson/axg-aoclk.c +++ b/drivers/clk/meson/axg-aoclk.c @@ -34,30 +34,19 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define AXG_AO_GATE(_name, _bit, _flags) \ -static struct clk_regmap axg_ao_##_name =3D { \ - .data =3D &(struct clk_regmap_gate_data) { \ - .offset =3D (AO_RTI_GEN_CNTL_REG0), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "axg_ao_" #_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_data =3D &(const struct clk_parent_data) { \ - .fw_name =3D "mpeg-clk", \ - }, \ - .num_parents =3D 1, \ - .flags =3D (_flags), \ - }, \ -} +static const struct clk_parent_data axg_ao_pclk_parents =3D { .fw_name =3D= "mpeg-clk" }; =20 -AXG_AO_GATE(remote, 0, CLK_IGNORE_UNUSED); -AXG_AO_GATE(i2c_master, 1, CLK_IGNORE_UNUSED); -AXG_AO_GATE(i2c_slave, 2, CLK_IGNORE_UNUSED); -AXG_AO_GATE(uart1, 3, CLK_IGNORE_UNUSED); -AXG_AO_GATE(uart2, 5, CLK_IGNORE_UNUSED); -AXG_AO_GATE(ir_blaster, 6, CLK_IGNORE_UNUSED); -AXG_AO_GATE(saradc, 7, CLK_IGNORE_UNUSED); +#define AXG_AO_GATE(_name, _bit, _flags) \ + MESON_PCLK(axg_ao_##_name, AO_RTI_GEN_CNTL_REG0, _bit, \ + &axg_ao_pclk_parents, _flags) + +static AXG_AO_GATE(remote, 0, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(i2c_master, 1, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(i2c_slave, 2, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(uart1, 3, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(uart2, 5, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(ir_blaster, 6, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(saradc, 7, CLK_IGNORE_UNUSED); =20 static struct clk_regmap axg_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c index e9c1ef99be13d0542b8a972ceffe69c8a9977118..02c9820cd98655e57a290859b59= 5cf09d39e5fe3 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -164,30 +164,13 @@ static struct clk_regmap c3_rtc_clk =3D { }, }; =20 -#define C3_PCLK(_name, _reg, _bit, _fw_name, _ops, _flags) \ -struct clk_regmap c3_##_name =3D { \ - .data =3D &(struct clk_regmap_gate_data){ \ - .offset =3D (_reg), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "c3_" #_name, \ - .ops =3D _ops, \ - .parent_data =3D &(const struct clk_parent_data) { \ - .fw_name =3D (_fw_name), \ - }, \ - .num_parents =3D 1, \ - .flags =3D (_flags), \ - }, \ -} +static const struct clk_parent_data c3_sys_pclk_parents =3D { .fw_name =3D= "sysclk" }; =20 -#define C3_SYS_PCLK(_name, _reg, _bit, _flags) \ - C3_PCLK(_name, _reg, _bit, "sysclk", \ - &clk_regmap_gate_ops, _flags) +#define C3_SYS_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, _flags) =20 -#define C3_SYS_PCLK_RO(_name, _reg, _bit) \ - C3_PCLK(_name, _reg, _bit, "sysclk", \ - &clk_regmap_gate_ro_ops, 0) +#define C3_SYS_PCLK_RO(_name, _reg, _bit) \ + MESON_PCLK_RO(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, 0) =20 static C3_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0); static C3_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0); @@ -290,9 +273,10 @@ static C3_SYS_PCLK(sys_vc9000e, SYS_CLK_EN0_REG2, 2, = 0); static C3_SYS_PCLK(sys_pwm_mn, SYS_CLK_EN0_REG2, 3, 0); static C3_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG2, 4, 0); =20 -#define C3_AXI_PCLK(_name, _reg, _bit, _flags) \ - C3_PCLK(_name, _reg, _bit, "axiclk", \ - &clk_regmap_gate_ops, _flags) +static const struct clk_parent_data c3_axi_pclk_parents =3D { .fw_name =3D= "axiclk" }; + +#define C3_AXI_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(c3_##_name, _reg, _bit, &c3_axi_pclk_parents, _flags) =20 /* * NOTE: axi_sys_nic provides the clock to the AXI bus of the system NIC. = After diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c index 45e4df393feb6f916b6e035ad71e379e6e30ee99..96981da271fa1453ebbe433e36c= ff4409661fa6a 100644 --- a/drivers/clk/meson/g12a-aoclk.c +++ b/drivers/clk/meson/g12a-aoclk.c @@ -37,22 +37,10 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define G12A_AO_PCLK(_name, _reg, _bit, _flags) \ -static struct clk_regmap g12a_ao_##_name =3D { \ - .data =3D &(struct clk_regmap_gate_data) { \ - .offset =3D (_reg), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "g12a_ao_" #_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_data =3D &(const struct clk_parent_data) { \ - .fw_name =3D "mpeg-clk", \ - }, \ - .num_parents =3D 1, \ - .flags =3D (_flags), \ - }, \ -} +static const struct clk_parent_data g12a_ao_pclk_parents =3D { .fw_name = =3D "mpeg-clk" }; + +#define G12A_AO_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(g12a_ao_##_name, _reg, _bit, &g12a_ao_pclk_parents, _flags) =20 /* * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons @@ -63,22 +51,22 @@ static struct clk_regmap g12a_ao_##_name =3D { \ * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le * for a particular clock. */ -G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(uart, AO_CLK_GATE0, 4, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(uart, AO_CLK_GATE0, 4, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8, CLK_IGNORE_UNUSED); =20 -G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5, CLK_IGNORE_UNUSED); =20 static struct clk_regmap g12a_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 2bf45fd7fe4ba0783e736fbbb126209870985b22..c7dfb3a06cb5f70c98f65bb91b9= 37e1b870b34fe 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c @@ -23,29 +23,18 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define GXBB_AO_PCLK(_name, _bit, _flags) \ -static struct clk_regmap gxbb_ao_##_name =3D { \ - .data =3D &(struct clk_regmap_gate_data) { \ - .offset =3D AO_RTI_GEN_CNTL_REG0, \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "gxbb_ao_" #_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_data =3D &(const struct clk_parent_data) { \ - .fw_name =3D "mpeg-clk", \ - }, \ - .num_parents =3D 1, \ - .flags =3D (_flags), \ - }, \ -} +static const struct clk_parent_data gxbb_ao_pclk_parents =3D { .fw_name = =3D "mpeg-clk" }; =20 -GXBB_AO_PCLK(remote, 0, CLK_IGNORE_UNUSED); -GXBB_AO_PCLK(i2c_master, 1, CLK_IGNORE_UNUSED); -GXBB_AO_PCLK(i2c_slave, 2, CLK_IGNORE_UNUSED); -GXBB_AO_PCLK(uart1, 3, CLK_IGNORE_UNUSED); -GXBB_AO_PCLK(uart2, 5, CLK_IGNORE_UNUSED); -GXBB_AO_PCLK(ir_blaster, 6, CLK_IGNORE_UNUSED); +#define GXBB_AO_PCLK(_name, _bit, _flags) \ + MESON_PCLK(gxbb_ao_##_name, AO_RTI_GEN_CNTL_REG0, _bit, \ + &gxbb_ao_pclk_parents, _flags) + +static GXBB_AO_PCLK(remote, 0, CLK_IGNORE_UNUSED); +static GXBB_AO_PCLK(i2c_master, 1, CLK_IGNORE_UNUSED); +static GXBB_AO_PCLK(i2c_slave, 2, CLK_IGNORE_UNUSED); +static GXBB_AO_PCLK(uart1, 3, CLK_IGNORE_UNUSED); +static GXBB_AO_PCLK(uart2, 5, CLK_IGNORE_UNUSED); +static GXBB_AO_PCLK(ir_blaster, 6, CLK_IGNORE_UNUSED); =20 static struct clk_regmap gxbb_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ --=20 2.47.2