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Wed, 02 Jul 2025 08:27:34 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:26:20 +0200 Subject: [PATCH 22/26] clk: amlogic: introduce a common pclk definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-22-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10081; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=UjktwdRyVGsFy6U0LeiahV0EMG/NVFT7hHKNN0gErHQ=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoZU/KiklSh5+OYIADxksPwX+ASBwG2qM8bNl4h X4PLve0xWqJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaGVPygAKCRDm/A8cN/La hUMSD/wNZ6buCptDsfX0F7i6s82vCm79tI8uZ2m2yxe+zmY55pR1VfD+UyhZbtyqF6MC4NZ+mZg nzLJ+TUc5hG9Na6/g4bBg9dgYB3dukzQ2bR3a+L1H0aXOjwRPYgARIcXqZmmR/mtkBd84wtaEod Grn9PFmYwdBMStatLSZfzie0Cmm2YIS8trYBgsAvzTPgt3dUwCe0k21RRSwLLfuto0Kvi9aPhP8 OmOgHSaz6/K+cI77ANRNX0k7D6X0cgk0Vr8w0EvB7a0LXczIACFYcLMnKLrtkUuYLyqrIzs4o2O 6Op41WcdO8NpDk9pa8TEqqC1YpCrMUzzgkXySVEcFjtLxvpn0nlj0EgvMAuvgUkJqTaNv3K9ooC yCH8gNzS3bTq0gu3XUnl+ZoWR+zsU2RojkcYUrY/R/Sqeennsg7eWVVMUDlC3i/q7/ubjFzCKEu xm7Ik1V5px603IYf1Gyia4js97dqW0nZDI23+DZQvof8revLhFuZTVFgD/Bn9vGvXZqCeRDR2iz XcYaJKkBG3vVgZLqVVIkWYr0mnrG0avnp00OBMnW26rC4JQVulPRO3fHkgzX8XX+EioG0VSzwG7 xtzOnJFdSAHtOFWoarmtmJRoJtn+gFeP4AsVBd0dThZI2DRBxXcuiqH3DwHyRV/XNSFyPmbIiKo 79aXEVaYezfxGNQ== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 All Amlogic peripheral clocks are more or less the same. The only thing that differs is the parent data. Adapt the common pclk definition so it takes clk_parent_data and can be used by all controllers. Signed-off-by: Jerome Brunet Reviewed-by: Chuan Liu --- drivers/clk/meson/a1-peripherals.c | 4 +++- drivers/clk/meson/axg.c | 4 +++- drivers/clk/meson/g12a.c | 6 ++++-- drivers/clk/meson/gxbb.c | 26 +++++++++++++++++--------- drivers/clk/meson/meson-clkc-utils.h | 12 ++++++------ drivers/clk/meson/meson8b.c | 31 ++++++++++++++++++------------- drivers/clk/meson/s4-peripherals.c | 4 +++- 7 files changed, 54 insertions(+), 33 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peri= pherals.c index a7bd3822df18f5e043e58e2d7bbcaa24345ea404..5e0d58c01405c1925a5c25ee6d0= a547fd2e69911 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -1840,8 +1840,10 @@ static struct clk_regmap a1_cecb_32k_out =3D { }, }; =20 +static const struct clk_parent_data a1_pclk_parents =3D { .hw =3D &a1_sys.= hw }; + #define A1_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(a1_##_name, _reg, _bit, &a1_sys.hw, _flags) + MESON_PCLK(a1_##_name, _reg, _bit, &a1_pclk_parents, _flags) =20 /* * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index d83482d5da6ddc09b3dfaf77c6898456ef9f0d39..e41d1ead28ce2e949cb65955fc9= ae9dc0d788c08 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -1915,8 +1915,10 @@ static struct clk_regmap axg_gen_clk =3D { }, }; =20 +static const struct clk_parent_data axg_pclk_parents =3D { .hw =3D &axg_cl= k81.hw }; + #define AXG_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(axg_##_name, _reg, _bit, &axg_clk81.hw, _flags) + MESON_PCLK(axg_##_name, _reg, _bit, &axg_pclk_parents, _flags) =20 /* * Everything Else (EE) domain gates diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 7a737bfde4e62ec3d18db570e62cc77fb415676c..edd70b1d5df8a0581ef930d599e= 633171434e34e 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -4384,11 +4384,13 @@ static struct clk_regmap sm1_nna_core_clk =3D { }, }; =20 +static const struct clk_parent_data g12a_pclk_parents =3D { .hw =3D &g12a_= clk81.hw }; + #define G12A_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw, _flags) + MESON_PCLK(_name, _reg, _bit, &g12a_pclk_parents, _flags) =20 #define G12A_PCLK_RO(_name, _reg, _bit, _flags) \ - MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw, _flags) + MESON_PCLK_RO(_name, _reg, _bit, &g12a_pclk_parents, _flags) =20 /* * Everything Else (EE) domain gates diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index e2a88dc29901fe4617427907b382e878ae6ff7ae..4c253d001be9c0604fc87bb3d6e= a5241b489948b 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -2721,8 +2721,10 @@ static struct clk_regmap gxbb_gen_clk =3D { }, }; =20 +static const struct clk_parent_data gxbb_pclk_parents =3D { .hw =3D &gxbb_= clk81.hw }; + #define GXBB_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw, _flags) + MESON_PCLK(_name, _reg, _bit, &gxbb_pclk_parents, _flags) =20 /* * Everything Else (EE) domain gates @@ -2817,14 +2819,20 @@ static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3, CL= K_IGNORE_UNUSED); static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED); =20 /* AIU gates */ -static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw, CLK_IGN= ORE_UNUSED); -static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw, CLK= _IGNORE_UNUSED); -static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw, CL= K_IGNORE_UNUSED); -static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw, CLK_= IGNORE_UNUSED); -static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw, CL= K_IGNORE_UNUSED); -static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw, CLK_= IGNORE_UNUSED); -static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw,= CLK_IGNORE_UNUSED); -static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw, CLK_IG= NORE_UNUSED); +static const struct clk_parent_data gxbb_aiu_glue_parents =3D { .hw =3D &g= xbb_aiu.hw }; +static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu_glue_parent= s, CLK_IGNORE_UNUSED); + +static const struct clk_parent_data gxbb_aiu_pclk_parents =3D { .hw =3D &g= xbb_aiu_glue.hw }; +#define GXBB_AIU_PCLK(_name, _bit, _flags) \ + MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &gxbb_aiu_pclk_parents, _flags) + +static GXBB_AIU_PCLK(gxbb_iec958, 7, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_i2s_out, 8, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_amclk, 9, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_aififo2, 10, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_mixer, 11, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_mixer_iface, 12, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_adc, 13, CLK_IGNORE_UNUSED); =20 /* Array of all clocks provided by this provider */ =20 diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index 03e38992c4c73ff4ee24f0fa99b7c34134376992..95d9f85f7ca22f63a16f8665d6f= 7a250b21bfdb8 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -27,7 +27,7 @@ struct meson_clkc_data { int meson_clkc_syscon_probe(struct platform_device *pdev); int meson_clkc_mmio_probe(struct platform_device *pdev); =20 -#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname, _flags) \ +#define __MESON_PCLK(_name, _reg, _bit, _ops, _pdata, _flags) \ struct clk_regmap _name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D (_reg), \ @@ -36,16 +36,16 @@ struct clk_regmap _name =3D { \ .hw.init =3D &(struct clk_init_data) { \ .name =3D #_name, \ .ops =3D _ops, \ - .parent_hws =3D (const struct clk_hw *[]) { _pname }, \ + .parent_data =3D (_pdata), \ .num_parents =3D 1, \ .flags =3D (_flags), \ }, \ } =20 -#define MESON_PCLK(_name, _reg, _bit, _pname, _flags) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname, _flags) +#define MESON_PCLK(_name, _reg, _bit, _pdata, _flags) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pdata, _flags) =20 -#define MESON_PCLK_RO(_name, _reg, _bit, _pname, _flags) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname, _flags) +#define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags) =20 #endif diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index a16ebbbf664cdd56b2c74db4f88a8d0a22d2ddc3..95d0b9cbd90404ee1c7ec551a27= 48665b4ef9ccd 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -2701,8 +2701,10 @@ static struct clk_regmap meson8b_cts_i958 =3D { }, }; =20 +static const struct clk_parent_data meson8b_pclk_parents =3D { .hw =3D &me= son8b_clk81.hw }; + #define MESON8B_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw, _flags) + MESON_PCLK(_name, _reg, _bit, &meson8b_pclk_parents, _flags) =20 /* * Everything Else (EE) domain gates @@ -2785,18 +2787,21 @@ static MESON8B_PCLK(meson8b_vclk2_other, HHI_GCLK_O= THER, 26, CLK_IGNORE_UNUSED); static MESON8B_PCLK(meson8b_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED); =20 /* AIU gates */ -static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw, CL= K_IGNORE_UNUSED); - -#define MESON_AIU_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw, _flags) - -static MESON_AIU_PCLK(meson8b_iec958, HHI_GCLK_MPEG1, 7, CLK_IGNORE_UNUS= ED); -static MESON_AIU_PCLK(meson8b_i2s_out, HHI_GCLK_MPEG1, 8, CLK_IGNORE_UNU= SED); -static MESON_AIU_PCLK(meson8b_amclk, HHI_GCLK_MPEG1, 9, CLK_IGNORE_UNUSE= D); -static MESON_AIU_PCLK(meson8b_aififo2, HHI_GCLK_MPEG1, 10, CLK_IGNORE_UNU= SED); -static MESON_AIU_PCLK(meson8b_mixer, HHI_GCLK_MPEG1, 11, CLK_IGNORE_UNUSE= D); -static MESON_AIU_PCLK(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12, CLK_IGNORE_= UNUSED); -static MESON_AIU_PCLK(meson8b_adc, HHI_GCLK_MPEG1, 13, CLK_IGNORE_UNUSED); +static const struct clk_parent_data meson8b_aiu_glue_parents =3D { .hw =3D= &meson8b_aiu.hw }; +static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, + &meson8b_aiu_glue_parents, CLK_IGNORE_UNUSED); + +static const struct clk_parent_data meson8b_aiu_pclk_parents =3D { .hw =3D= &meson8b_aiu_glue.hw }; +#define MESON8B_AIU_PCLK(_name, _bit, _flags) \ + MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &meson8b_aiu_pclk_parents, _flags) + +static MESON8B_AIU_PCLK(meson8b_iec958, 7, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_i2s_out, 8, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_amclk, 9, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_aififo2, 10, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_mixer, 11, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_mixer_iface, 12, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_adc, 13, CLK_IGNORE_UNUSED); =20 /* Always On (AO) domain gates */ =20 diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index 23b51d84d8de40aa540dbc6dd5db9fb627e579de..3e048e645b080f9e5982ef908e3= f9c43578a0b5f 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -3165,8 +3165,10 @@ static struct clk_regmap s4_gen_clk =3D { }, }; =20 +static const struct clk_parent_data s4_pclk_parents =3D { .hw =3D &s4_sys_= clk.hw }; + #define S4_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw, _flags) + MESON_PCLK(_name, _reg, _bit, &s4_pclk_parents, _flags) =20 /* * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons --=20 2.47.2