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Wed, 02 Jul 2025 08:27:25 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:26:10 +0200 Subject: [PATCH 12/26] clk: amlogic: s4-peripherals: naming consistency alignment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-12-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=66675; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=0iwTbwU3c4h3tACHgSyfJtBl9bT45xtnT02E/ppaego=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoZU/B8vIOGbFrfQG+ivjtQoP8p4ck00pKLcMRk QpsvOqoLmWJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaGVPwQAKCRDm/A8cN/La haZtD/41kmB6QedC41SG7x8mXbxhgj7aYYUY/P5LwU347Tfbq9k3UXfyx2w/Wa8PF35aONQyciK 3MpfSapS0/2fhQZJtyKZdfwbOUEG75/6AoTCPP5E755OtOuaaO711xGm/kgAoyo00GXsIrwUfZG pMmeNQnGgwuHH2267h57Rd3GEX+FaLjkV1/aV+lYubWaQZrlTcT6gQSYabv4G4RtbS0IfXWPxOu fc+buWaZqfyaOOx+k4QbZt5xgxV7gTsYpRYUXGTYcfgtATcrm0yFTty+JRPQSSD0VOOLbFrCpaU cs83g8kOqHzUyB7JEsIqDGr7iAkeLxNwY1hk2ezINtZTyYTRIoIdb1PRl2iJjdK4iKF82dp0Uyk TamrQ9Y2Uq6I+MoYq5LwzFXO/mzD8yLT+55yoeOVzOHpplWrr1IZm7lnT70JURVjF4v9L6IoUcr J7souRSr80Ch/Feym2FpQlnGTD7t8MA9m9PBX+PmD0e9HBdJldJaXe9Ona0wvQfdrFK+bbj25rn //+5GZ+GsElY/GbCsVDhtKgU0qX9ySR+V9xjgz3HFxJ1EbXLR6pmlEL3BqqyA2yIxq6IwJgNyY2 mNkCpupQpwcCjhewC8zhoRYSCgkP/i5frGegatsH5qIgxkWOhJGo4+1Po6dlylHHWQnIz31oxjx U0iPUak9lfHO3bg== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet Reviewed-by: Chuan Liu --- drivers/clk/meson/s4-peripherals.c | 746 ++++++++++++++++++---------------= ---- 1 file changed, 370 insertions(+), 376 deletions(-) diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index c9400cf54c84c3dc7c63d0636933951b0cac230c..9bcd35f12836de5e318fd1ad9c9= ae15a2bfc3dd7 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -182,8 +182,8 @@ static struct clk_regmap s4_rtc_clk =3D { }; =20 /* The index 5 is AXI_CLK, which is dedicated to AXI. So skip it. */ -static u32 mux_table_sys_ab_clk_sel[] =3D { 0, 1, 2, 3, 4, 6, 7 }; -static const struct clk_parent_data sys_ab_clk_parent_data[] =3D { +static u32 s4_sysclk_parents_val_table[] =3D { 0, 1, 2, 3, 4, 6, 7 }; +static const struct clk_parent_data s4_sysclk_parents[] =3D { { .fw_name =3D "xtal" }, { .fw_name =3D "fclk_div2" }, { .fw_name =3D "fclk_div3" }, @@ -205,13 +205,13 @@ static struct clk_regmap s4_sysclk_b_sel =3D { .offset =3D CLKCTRL_SYS_CLK_CTRL0, .mask =3D 0x7, .shift =3D 26, - .table =3D mux_table_sys_ab_clk_sel, + .table =3D s4_sysclk_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "sysclk_b_sel", .ops =3D &clk_regmap_mux_ro_ops, - .parent_data =3D sys_ab_clk_parent_data, - .num_parents =3D ARRAY_SIZE(sys_ab_clk_parent_data), + .parent_data =3D s4_sysclk_parents, + .num_parents =3D ARRAY_SIZE(s4_sysclk_parents), }, }; =20 @@ -251,13 +251,13 @@ static struct clk_regmap s4_sysclk_a_sel =3D { .offset =3D CLKCTRL_SYS_CLK_CTRL0, .mask =3D 0x7, .shift =3D 10, - .table =3D mux_table_sys_ab_clk_sel, + .table =3D s4_sysclk_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "sysclk_a_sel", .ops =3D &clk_regmap_mux_ro_ops, - .parent_data =3D sys_ab_clk_parent_data, - .num_parents =3D ARRAY_SIZE(sys_ab_clk_parent_data), + .parent_data =3D s4_sysclk_parents, + .num_parents =3D ARRAY_SIZE(s4_sysclk_parents), }, }; =20 @@ -523,24 +523,24 @@ static struct clk_regmap s4_cecb_32k_clkout =3D { }, }; =20 -static const struct clk_parent_data s4_sc_parent_data[] =3D { +static const struct clk_parent_data s4_sc_clk_parents[] =3D { { .fw_name =3D "fclk_div4" }, { .fw_name =3D "fclk_div3" }, { .fw_name =3D "fclk_div5" }, { .fw_name =3D "xtal", } }; =20 -static struct clk_regmap s4_sc_clk_mux =3D { +static struct clk_regmap s4_sc_clk_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_SC_CLK_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "sc_clk_mux", + .name =3D "sc_clk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_sc_parent_data, - .num_parents =3D ARRAY_SIZE(s4_sc_parent_data), + .parent_data =3D s4_sc_clk_parents, + .num_parents =3D ARRAY_SIZE(s4_sc_clk_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -555,20 +555,20 @@ static struct clk_regmap s4_sc_clk_div =3D { .name =3D "sc_clk_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_sc_clk_mux.hw + &s4_sc_clk_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_sc_clk_gate =3D { +static struct clk_regmap s4_sc_clk =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_SC_CLK_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "sc_clk_gate", + .name =3D "sc_clk", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_sc_clk_div.hw @@ -578,13 +578,13 @@ static struct clk_regmap s4_sc_clk_gate =3D { }, }; =20 -static struct clk_regmap s4_12_24M_clk_gate =3D { +static struct clk_regmap s4_12_24M =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_CLK12_24_CTRL, .bit_idx =3D 11, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "12_24m_gate", + .name =3D "12_24M", .ops =3D &clk_regmap_gate_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "xtal", } @@ -593,32 +593,32 @@ static struct clk_regmap s4_12_24M_clk_gate =3D { }, }; =20 -static struct clk_fixed_factor s4_12M_clk_div =3D { +static struct clk_fixed_factor s4_12M_div =3D { .mult =3D 1, .div =3D 2, .hw.init =3D &(struct clk_init_data){ - .name =3D "12M", + .name =3D "12M_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_12_24M_clk_gate.hw + &s4_12_24M.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_12_24M_clk =3D { +static struct clk_regmap s4_12_24M_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_CLK12_24_CTRL, .mask =3D 0x1, .shift =3D 10, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "12_24m", + .name =3D "12_24M_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_12_24M_clk_gate.hw, - &s4_12M_clk_div.hw, + &s4_12_24M.hw, + &s4_12M_div.hw, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, @@ -687,7 +687,7 @@ static struct clk_regmap s4_vid_pll =3D { }, }; =20 -static const struct clk_parent_data s4_vclk_parent_data[] =3D { +static const struct clk_parent_data s4_vclk_parents[] =3D { { .hw =3D &s4_vid_pll.hw }, { .fw_name =3D "gp0_pll", }, { .fw_name =3D "hifi_pll", }, @@ -707,8 +707,8 @@ static struct clk_regmap s4_vclk_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vclk_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vclk_parent_data), + .parent_data =3D s4_vclk_parents, + .num_parents =3D ARRAY_SIZE(s4_vclk_parents), .flags =3D 0, }, }; @@ -722,8 +722,8 @@ static struct clk_regmap s4_vclk2_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vclk2_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vclk_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vclk_parent_data), + .parent_data =3D s4_vclk_parents, + .num_parents =3D ARRAY_SIZE(s4_vclk_parents), .flags =3D 0, }, }; @@ -1071,8 +1071,8 @@ static struct clk_fixed_factor s4_vclk2_div12 =3D { }; =20 /* The 5,6,7 indexes corresponds to no real clock, so there are not used. = */ -static u32 mux_table_cts_sel[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; -static const struct clk_hw *s4_cts_parent_hws[] =3D { +static u32 s4_cts_parents_val_table[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11, 1= 2 }; +static const struct clk_hw *s4_cts_parents[] =3D { &s4_vclk_div1.hw, &s4_vclk_div2.hw, &s4_vclk_div4.hw, @@ -1090,13 +1090,13 @@ static struct clk_regmap s4_cts_enci_sel =3D { .offset =3D CLKCTRL_VID_CLK_DIV, .mask =3D 0xf, .shift =3D 28, - .table =3D mux_table_cts_sel, + .table =3D s4_cts_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_enci_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_cts_parent_hws), + .parent_hws =3D s4_cts_parents, + .num_parents =3D ARRAY_SIZE(s4_cts_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1106,13 +1106,13 @@ static struct clk_regmap s4_cts_encp_sel =3D { .offset =3D CLKCTRL_VID_CLK_DIV, .mask =3D 0xf, .shift =3D 20, - .table =3D mux_table_cts_sel, + .table =3D s4_cts_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_encp_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_cts_parent_hws), + .parent_hws =3D s4_cts_parents, + .num_parents =3D ARRAY_SIZE(s4_cts_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1122,20 +1122,20 @@ static struct clk_regmap s4_cts_vdac_sel =3D { .offset =3D CLKCTRL_VIID_CLK_DIV, .mask =3D 0xf, .shift =3D 28, - .table =3D mux_table_cts_sel, + .table =3D s4_cts_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_vdac_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_cts_parent_hws), + .parent_hws =3D s4_cts_parents, + .num_parents =3D ARRAY_SIZE(s4_cts_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; =20 /* The 5,6,7 indexes corresponds to no real clock, so there are not used. = */ -static u32 mux_table_hdmi_tx_sel[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; -static const struct clk_hw *s4_cts_hdmi_tx_parent_hws[] =3D { +static u32 s4_hdmi_tx_parents_val_table[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 1= 1, 12 }; +static const struct clk_hw *s4_hdmi_tx_parents[] =3D { &s4_vclk_div1.hw, &s4_vclk_div2.hw, &s4_vclk_div4.hw, @@ -1153,13 +1153,13 @@ static struct clk_regmap s4_hdmi_tx_sel =3D { .offset =3D CLKCTRL_HDMI_CLK_CTRL, .mask =3D 0xf, .shift =3D 16, - .table =3D mux_table_hdmi_tx_sel, + .table =3D s4_hdmi_tx_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "hdmi_tx_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_cts_hdmi_tx_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_cts_hdmi_tx_parent_hws), + .parent_hws =3D s4_hdmi_tx_parents, + .num_parents =3D ARRAY_SIZE(s4_hdmi_tx_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1229,7 +1229,7 @@ static struct clk_regmap s4_hdmi_tx =3D { }; =20 /* HDMI Clocks */ -static const struct clk_parent_data s4_hdmi_parent_data[] =3D { +static const struct clk_parent_data s4_hdmi_parents[] =3D { { .fw_name =3D "xtal", }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, @@ -1246,8 +1246,8 @@ static struct clk_regmap s4_hdmi_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "hdmi_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_hdmi_parent_data, - .num_parents =3D ARRAY_SIZE(s4_hdmi_parent_data), + .parent_data =3D s4_hdmi_parents, + .num_parents =3D ARRAY_SIZE(s4_hdmi_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1298,7 +1298,7 @@ static struct clk_regmap s4_ts_clk_div =3D { }, }; =20 -static struct clk_regmap s4_ts_clk_gate =3D { +static struct clk_regmap s4_ts_clk =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_TS_CLK_CTRL, .bit_idx =3D 8, @@ -1320,7 +1320,7 @@ static struct clk_regmap s4_ts_clk_gate =3D { * mux because it does top-to-bottom updates the each clock tree and * switches to the "inactive" one when CLK_SET_RATE_GATE is set. */ -static const struct clk_parent_data s4_mali_0_1_parent_data[] =3D { +static const struct clk_parent_data s4_mali_parents[] =3D { { .fw_name =3D "xtal", }, { .fw_name =3D "gp0_pll", }, { .fw_name =3D "hifi_pll", }, @@ -1340,8 +1340,8 @@ static struct clk_regmap s4_mali_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "mali_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_mali_0_1_parent_data, - .num_parents =3D ARRAY_SIZE(s4_mali_0_1_parent_data), + .parent_data =3D s4_mali_parents, + .num_parents =3D ARRAY_SIZE(s4_mali_parents), /* * Don't request the parent to change the rate because * all GPU frequencies can be derived from the fclk_* @@ -1394,8 +1394,8 @@ static struct clk_regmap s4_mali_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "mali_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_mali_0_1_parent_data, - .num_parents =3D ARRAY_SIZE(s4_mali_0_1_parent_data), + .parent_data =3D s4_mali_parents, + .num_parents =3D ARRAY_SIZE(s4_mali_parents), .flags =3D 0, }, }; @@ -1433,28 +1433,26 @@ static struct clk_regmap s4_mali_1 =3D { }, }; =20 -static const struct clk_hw *s4_mali_parent_hws[] =3D { - &s4_mali_0.hw, - &s4_mali_1.hw -}; - -static struct clk_regmap s4_mali_mux =3D { +static struct clk_regmap s4_mali_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_MALI_CLK_CTRL, .mask =3D 1, .shift =3D 31, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "mali", + .name =3D "mali_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_mali_parent_hws, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_mali_0.hw, + &s4_mali_1.hw, + }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 /* VDEC clocks */ -static const struct clk_parent_data s4_dec_parent_data[] =3D { +static const struct clk_parent_data s4_dec_parents[] =3D { { .fw_name =3D "fclk_div2p5", }, { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div4", }, @@ -1465,7 +1463,7 @@ static const struct clk_parent_data s4_dec_parent_dat= a[] =3D { { .fw_name =3D "xtal", } }; =20 -static struct clk_regmap s4_vdec_p0_mux =3D { +static struct clk_regmap s4_vdec_p0_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDEC_CLK_CTRL, .mask =3D 0x7, @@ -1473,10 +1471,10 @@ static struct clk_regmap s4_vdec_p0_mux =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vdec_p0_mux", + .name =3D "vdec_p0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_dec_parent_data, - .num_parents =3D ARRAY_SIZE(s4_dec_parent_data), + .parent_data =3D s4_dec_parents, + .num_parents =3D ARRAY_SIZE(s4_dec_parents), .flags =3D 0, }, }; @@ -1492,7 +1490,7 @@ static struct clk_regmap s4_vdec_p0_div =3D { .name =3D "vdec_p0_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_vdec_p0_mux.hw + &s4_vdec_p0_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1515,7 +1513,7 @@ static struct clk_regmap s4_vdec_p0 =3D { }, }; =20 -static struct clk_regmap s4_vdec_p1_mux =3D { +static struct clk_regmap s4_vdec_p1_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDEC3_CLK_CTRL, .mask =3D 0x7, @@ -1523,10 +1521,10 @@ static struct clk_regmap s4_vdec_p1_mux =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vdec_p1_mux", + .name =3D "vdec_p1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_dec_parent_data, - .num_parents =3D ARRAY_SIZE(s4_dec_parent_data), + .parent_data =3D s4_dec_parents, + .num_parents =3D ARRAY_SIZE(s4_dec_parents), .flags =3D 0, }, }; @@ -1542,7 +1540,7 @@ static struct clk_regmap s4_vdec_p1_div =3D { .name =3D "vdec_p1_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_vdec_p1_mux.hw + &s4_vdec_p1_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1565,27 +1563,25 @@ static struct clk_regmap s4_vdec_p1 =3D { }, }; =20 -static const struct clk_hw *s4_vdec_mux_parent_hws[] =3D { - &s4_vdec_p0.hw, - &s4_vdec_p1.hw -}; - -static struct clk_regmap s4_vdec_mux =3D { +static struct clk_regmap s4_vdec_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDEC3_CLK_CTRL, .mask =3D 0x1, .shift =3D 15, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vdec_mux", + .name =3D "vdec_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_vdec_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_vdec_mux_parent_hws), + .parent_hws =3D (const struct clk_hw *[]) { + &s4_vdec_p0.hw, + &s4_vdec_p1.hw, + }, + .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_hevcf_p0_mux =3D { +static struct clk_regmap s4_hevcf_p0_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDEC2_CLK_CTRL, .mask =3D 0x7, @@ -1593,10 +1589,10 @@ static struct clk_regmap s4_hevcf_p0_mux =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "hevcf_p0_mux", + .name =3D "hevcf_p0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_dec_parent_data, - .num_parents =3D ARRAY_SIZE(s4_dec_parent_data), + .parent_data =3D s4_dec_parents, + .num_parents =3D ARRAY_SIZE(s4_dec_parents), .flags =3D 0, }, }; @@ -1612,7 +1608,7 @@ static struct clk_regmap s4_hevcf_p0_div =3D { .name =3D "hevcf_p0_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_hevcf_p0_mux.hw + &s4_hevcf_p0_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1625,7 +1621,7 @@ static struct clk_regmap s4_hevcf_p0 =3D { .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "hevcf_p0_gate", + .name =3D "hevcf_p0", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_hevcf_p0_div.hw @@ -1635,7 +1631,7 @@ static struct clk_regmap s4_hevcf_p0 =3D { }, }; =20 -static struct clk_regmap s4_hevcf_p1_mux =3D { +static struct clk_regmap s4_hevcf_p1_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDEC4_CLK_CTRL, .mask =3D 0x7, @@ -1643,10 +1639,10 @@ static struct clk_regmap s4_hevcf_p1_mux =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "hevcf_p1_mux", + .name =3D "hevcf_p1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_dec_parent_data, - .num_parents =3D ARRAY_SIZE(s4_dec_parent_data), + .parent_data =3D s4_dec_parents, + .num_parents =3D ARRAY_SIZE(s4_dec_parents), .flags =3D 0, }, }; @@ -1662,7 +1658,7 @@ static struct clk_regmap s4_hevcf_p1_div =3D { .name =3D "hevcf_p1_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_hevcf_p1_mux.hw + &s4_hevcf_p1_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1685,28 +1681,26 @@ static struct clk_regmap s4_hevcf_p1 =3D { }, }; =20 -static const struct clk_hw *s4_hevcf_mux_parent_hws[] =3D { - &s4_hevcf_p0.hw, - &s4_hevcf_p1.hw -}; - -static struct clk_regmap s4_hevcf_mux =3D { +static struct clk_regmap s4_hevcf_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDEC4_CLK_CTRL, .mask =3D 0x1, .shift =3D 15, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "hevcf", + .name =3D "hevcf_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_hevcf_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_hevcf_mux_parent_hws), + .parent_hws =3D (const struct clk_hw *[]) { + &s4_hevcf_p0.hw, + &s4_hevcf_p1.hw, + }, + .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 /* VPU Clock */ -static const struct clk_parent_data s4_vpu_parent_data[] =3D { +static const struct clk_parent_data s4_vpu_parents[] =3D { { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div5", }, @@ -1726,8 +1720,8 @@ static struct clk_regmap s4_vpu_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vpu_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vpu_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vpu_parent_data), + .parent_data =3D s4_vpu_parents, + .num_parents =3D ARRAY_SIZE(s4_vpu_parents), .flags =3D 0, }, }; @@ -1770,8 +1764,8 @@ static struct clk_regmap s4_vpu_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vpu_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vpu_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vpu_parent_data), + .parent_data =3D s4_vpu_parents, + .num_parents =3D ARRAY_SIZE(s4_vpu_parents), .flags =3D 0, }, }; @@ -1823,24 +1817,24 @@ static struct clk_regmap s4_vpu =3D { }, }; =20 -static const struct clk_parent_data vpu_clkb_tmp_parent_data[] =3D { +static const struct clk_parent_data vpu_clkb_tmp_parents[] =3D { { .hw =3D &s4_vpu.hw }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div5", }, { .fw_name =3D "fclk_div7", } }; =20 -static struct clk_regmap s4_vpu_clkb_tmp_mux =3D { +static struct clk_regmap s4_vpu_clkb_tmp_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VPU_CLKB_CTRL, .mask =3D 0x3, .shift =3D 20, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vpu_clkb_tmp_mux", + .name =3D "vpu_clkb_tmp_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D vpu_clkb_tmp_parent_data, - .num_parents =3D ARRAY_SIZE(vpu_clkb_tmp_parent_data), + .parent_data =3D vpu_clkb_tmp_parents, + .num_parents =3D ARRAY_SIZE(vpu_clkb_tmp_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1855,7 +1849,7 @@ static struct clk_regmap s4_vpu_clkb_tmp_div =3D { .name =3D "vpu_clkb_tmp_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_vpu_clkb_tmp_mux.hw + &s4_vpu_clkb_tmp_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1911,7 +1905,7 @@ static struct clk_regmap s4_vpu_clkb =3D { }, }; =20 -static const struct clk_parent_data s4_vpu_clkc_parent_data[] =3D { +static const struct clk_parent_data s4_vpu_clkc_parents[] =3D { { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div5", }, @@ -1922,17 +1916,17 @@ static const struct clk_parent_data s4_vpu_clkc_par= ent_data[] =3D { { .fw_name =3D "gp0_pll", }, }; =20 -static struct clk_regmap s4_vpu_clkc_p0_mux =3D { +static struct clk_regmap s4_vpu_clkc_p0_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VPU_CLKC_CTRL, .mask =3D 0x7, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vpu_clkc_p0_mux", + .name =3D "vpu_clkc_p0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vpu_clkc_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vpu_clkc_parent_data), + .parent_data =3D s4_vpu_clkc_parents, + .num_parents =3D ARRAY_SIZE(s4_vpu_clkc_parents), .flags =3D 0, }, }; @@ -1947,7 +1941,7 @@ static struct clk_regmap s4_vpu_clkc_p0_div =3D { .name =3D "vpu_clkc_p0_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_vpu_clkc_p0_mux.hw + &s4_vpu_clkc_p0_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1970,17 +1964,17 @@ static struct clk_regmap s4_vpu_clkc_p0 =3D { }, }; =20 -static struct clk_regmap s4_vpu_clkc_p1_mux =3D { +static struct clk_regmap s4_vpu_clkc_p1_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VPU_CLKC_CTRL, .mask =3D 0x7, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vpu_clkc_p1_mux", + .name =3D "vpu_clkc_p1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vpu_clkc_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vpu_clkc_parent_data), + .parent_data =3D s4_vpu_clkc_parents, + .num_parents =3D ARRAY_SIZE(s4_vpu_clkc_parents), .flags =3D 0, }, }; @@ -1995,7 +1989,7 @@ static struct clk_regmap s4_vpu_clkc_p1_div =3D { .name =3D "vpu_clkc_p1_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_vpu_clkc_p1_mux.hw + &s4_vpu_clkc_p1_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2018,28 +2012,26 @@ static struct clk_regmap s4_vpu_clkc_p1 =3D { }, }; =20 -static const struct clk_hw *s4_vpu_mux_parent_hws[] =3D { - &s4_vpu_clkc_p0.hw, - &s4_vpu_clkc_p1.hw -}; - -static struct clk_regmap s4_vpu_clkc_mux =3D { +static struct clk_regmap s4_vpu_clkc_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VPU_CLKC_CTRL, .mask =3D 0x1, .shift =3D 31, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vpu_clkc_mux", + .name =3D "vpu_clkc_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_vpu_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_vpu_mux_parent_hws), + .parent_hws =3D (const struct clk_hw *[]) { + &s4_vpu_clkc_p0.hw, + &s4_vpu_clkc_p1.hw, + }, + .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 /* VAPB Clock */ -static const struct clk_parent_data s4_vapb_parent_data[] =3D { +static const struct clk_parent_data s4_vapb_parents[] =3D { { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div5", }, @@ -2059,8 +2051,8 @@ static struct clk_regmap s4_vapb_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vapb_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vapb_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vapb_parent_data), + .parent_data =3D s4_vapb_parents, + .num_parents =3D ARRAY_SIZE(s4_vapb_parents), .flags =3D 0, }, }; @@ -2107,8 +2099,8 @@ static struct clk_regmap s4_vapb_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vapb_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vapb_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vapb_parent_data), + .parent_data =3D s4_vapb_parents, + .num_parents =3D ARRAY_SIZE(s4_vapb_parents), .flags =3D 0, }, }; @@ -2164,13 +2156,13 @@ static struct clk_regmap s4_vapb =3D { }, }; =20 -static struct clk_regmap s4_ge2d_gate =3D { +static struct clk_regmap s4_ge2d =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_VAPBCLK_CTRL, .bit_idx =3D 30, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "ge2d_clk", + .name =3D "ge2d", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_vapb.hw }, .num_parents =3D 1, @@ -2178,24 +2170,24 @@ static struct clk_regmap s4_ge2d_gate =3D { }, }; =20 -static const struct clk_parent_data s4_esmclk_parent_data[] =3D { +static const struct clk_parent_data s4_hdcp22_esmclk_parents[] =3D { { .fw_name =3D "fclk_div7", }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div5", }, }; =20 -static struct clk_regmap s4_hdcp22_esmclk_mux =3D { +static struct clk_regmap s4_hdcp22_esmclk_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_HDCP22_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "hdcp22_esmclk_mux", + .name =3D "hdcp22_esmclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_esmclk_parent_data, - .num_parents =3D ARRAY_SIZE(s4_esmclk_parent_data), + .parent_data =3D s4_hdcp22_esmclk_parents, + .num_parents =3D ARRAY_SIZE(s4_hdcp22_esmclk_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2210,20 +2202,20 @@ static struct clk_regmap s4_hdcp22_esmclk_div =3D { .name =3D "hdcp22_esmclk_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_hdcp22_esmclk_mux.hw + &s4_hdcp22_esmclk_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_hdcp22_esmclk_gate =3D { +static struct clk_regmap s4_hdcp22_esmclk =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_HDCP22_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "hdcp22_esmclk_gate", + .name =3D "hdcp22_esmclk", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_hdcp22_esmclk_div.hw @@ -2233,24 +2225,24 @@ static struct clk_regmap s4_hdcp22_esmclk_gate =3D { }, }; =20 -static const struct clk_parent_data s4_skpclk_parent_data[] =3D { +static const struct clk_parent_data s4_hdcp22_skpclk_parents[] =3D { { .fw_name =3D "xtal", }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div5", }, }; =20 -static struct clk_regmap s4_hdcp22_skpclk_mux =3D { +static struct clk_regmap s4_hdcp22_skpclk_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_HDCP22_CTRL, .mask =3D 0x3, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "hdcp22_skpclk_mux", + .name =3D "hdcp22_skpclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_skpclk_parent_data, - .num_parents =3D ARRAY_SIZE(s4_skpclk_parent_data), + .parent_data =3D s4_hdcp22_skpclk_parents, + .num_parents =3D ARRAY_SIZE(s4_hdcp22_skpclk_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2265,20 +2257,20 @@ static struct clk_regmap s4_hdcp22_skpclk_div =3D { .name =3D "hdcp22_skpclk_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_hdcp22_skpclk_mux.hw + &s4_hdcp22_skpclk_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_hdcp22_skpclk_gate =3D { +static struct clk_regmap s4_hdcp22_skpclk =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_HDCP22_CTRL, .bit_idx =3D 24, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "hdcp22_skpclk_gate", + .name =3D "hdcp22_skpclk", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_hdcp22_skpclk_div.hw @@ -2288,7 +2280,7 @@ static struct clk_regmap s4_hdcp22_skpclk_gate =3D { }, }; =20 -static const struct clk_parent_data s4_vdin_parent_data[] =3D { +static const struct clk_parent_data s4_vdin_parents[] =3D { { .fw_name =3D "xtal", }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, @@ -2296,17 +2288,17 @@ static const struct clk_parent_data s4_vdin_parent_= data[] =3D { { .hw =3D &s4_vid_pll.hw } }; =20 -static struct clk_regmap s4_vdin_meas_mux =3D { +static struct clk_regmap s4_vdin_meas_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDIN_MEAS_CLK_CTRL, .mask =3D 0x7, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vdin_meas_mux", + .name =3D "vdin_meas_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vdin_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vdin_parent_data), + .parent_data =3D s4_vdin_parents, + .num_parents =3D ARRAY_SIZE(s4_vdin_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2321,20 +2313,20 @@ static struct clk_regmap s4_vdin_meas_div =3D { .name =3D "vdin_meas_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_vdin_meas_mux.hw + &s4_vdin_meas_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_vdin_meas_gate =3D { +static struct clk_regmap s4_vdin_meas =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_VDIN_MEAS_CLK_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "vdin_meas_gate", + .name =3D "vdin_meas", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_vdin_meas_div.hw @@ -2345,7 +2337,7 @@ static struct clk_regmap s4_vdin_meas_gate =3D { }; =20 /* EMMC/NAND clock */ -static const struct clk_parent_data s4_sd_emmc_clk0_parent_data[] =3D { +static const struct clk_parent_data s4_sd_emmc_clk0_parents[] =3D { { .fw_name =3D "xtal", }, { .fw_name =3D "fclk_div2", }, { .fw_name =3D "fclk_div3", }, @@ -2365,8 +2357,8 @@ static struct clk_regmap s4_sd_emmc_c_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_c_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(s4_sd_emmc_clk0_parent_data), + .parent_data =3D s4_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(s4_sd_emmc_clk0_parents), .flags =3D 0, }, }; @@ -2413,8 +2405,8 @@ static struct clk_regmap s4_sd_emmc_a_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_a_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(s4_sd_emmc_clk0_parent_data), + .parent_data =3D s4_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(s4_sd_emmc_clk0_parents), .flags =3D 0, }, }; @@ -2461,8 +2453,8 @@ static struct clk_regmap s4_sd_emmc_b_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_b_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(s4_sd_emmc_clk0_parent_data), + .parent_data =3D s4_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(s4_sd_emmc_clk0_parents), .flags =3D 0, }, }; @@ -2501,7 +2493,7 @@ static struct clk_regmap s4_sd_emmc_b_clk0 =3D { }; =20 /* SPICC Clock */ -static const struct clk_parent_data s4_spicc_parent_data[] =3D { +static const struct clk_parent_data s4_spicc_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &s4_sys_clk.hw }, { .fw_name =3D "fclk_div4", }, @@ -2511,17 +2503,17 @@ static const struct clk_parent_data s4_spicc_parent= _data[] =3D { { .fw_name =3D "fclk_div7", }, }; =20 -static struct clk_regmap s4_spicc0_mux =3D { +static struct clk_regmap s4_spicc0_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_SPICC_CLK_CTRL, .mask =3D 0x7, .shift =3D 7, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc0_mux", + .name =3D "spicc0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_spicc_parent_data, - .num_parents =3D ARRAY_SIZE(s4_spicc_parent_data), + .parent_data =3D s4_spicc_parents, + .num_parents =3D ARRAY_SIZE(s4_spicc_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2536,20 +2528,20 @@ static struct clk_regmap s4_spicc0_div =3D { .name =3D "spicc0_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_spicc0_mux.hw + &s4_spicc0_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_spicc0_gate =3D { +static struct clk_regmap s4_spicc0_en =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_SPICC_CLK_CTRL, .bit_idx =3D 6, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "spicc0", + .name =3D "spicc0_en", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_spicc0_div.hw @@ -2560,24 +2552,24 @@ static struct clk_regmap s4_spicc0_gate =3D { }; =20 /* PWM Clock */ -static const struct clk_parent_data s4_pwm_parent_data[] =3D { +static const struct clk_parent_data s4_pwm_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &s4_vid_pll.hw }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, }; =20 -static struct clk_regmap s4_pwm_a_mux =3D { +static struct clk_regmap s4_pwm_a_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_a_mux", + .name =3D "pwm_a_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2592,14 +2584,14 @@ static struct clk_regmap s4_pwm_a_div =3D { .name =3D "pwm_a_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_a_mux.hw + &s4_pwm_a_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_a_gate =3D { +static struct clk_regmap s4_pwm_a =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, .bit_idx =3D 8, @@ -2615,17 +2607,17 @@ static struct clk_regmap s4_pwm_a_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_b_mux =3D { +static struct clk_regmap s4_pwm_b_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, .mask =3D 0x3, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_b_mux", + .name =3D "pwm_b_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2640,20 +2632,20 @@ static struct clk_regmap s4_pwm_b_div =3D { .name =3D "pwm_b_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_b_mux.hw + &s4_pwm_b_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_b_gate =3D { +static struct clk_regmap s4_pwm_b =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, .bit_idx =3D 24, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_b_gate", + .name =3D "pwm_b", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_b_div.hw @@ -2663,7 +2655,7 @@ static struct clk_regmap s4_pwm_b_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_c_mux =3D { +static struct clk_regmap s4_pwm_c_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, .mask =3D 0x3, @@ -2672,8 +2664,8 @@ static struct clk_regmap s4_pwm_c_mux =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "pwm_c_mux", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2688,19 +2680,19 @@ static struct clk_regmap s4_pwm_c_div =3D { .name =3D "pwm_c_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_c_mux.hw + &s4_pwm_c_sel.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap s4_pwm_c_gate =3D { +static struct clk_regmap s4_pwm_c =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_c_gate", + .name =3D "pwm_c", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_c_div.hw @@ -2710,17 +2702,17 @@ static struct clk_regmap s4_pwm_c_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_d_mux =3D { +static struct clk_regmap s4_pwm_d_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, .mask =3D 0x3, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_d_mux", + .name =3D "pwm_d_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2735,20 +2727,20 @@ static struct clk_regmap s4_pwm_d_div =3D { .name =3D "pwm_d_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_d_mux.hw + &s4_pwm_d_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_d_gate =3D { +static struct clk_regmap s4_pwm_d =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, .bit_idx =3D 24, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_d_gate", + .name =3D "pwm_d", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_d_div.hw @@ -2758,17 +2750,17 @@ static struct clk_regmap s4_pwm_d_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_e_mux =3D { +static struct clk_regmap s4_pwm_e_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_e_mux", + .name =3D "pwm_e_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2783,20 +2775,20 @@ static struct clk_regmap s4_pwm_e_div =3D { .name =3D "pwm_e_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_e_mux.hw + &s4_pwm_e_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_e_gate =3D { +static struct clk_regmap s4_pwm_e =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_e_gate", + .name =3D "pwm_e", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_e_div.hw @@ -2806,17 +2798,17 @@ static struct clk_regmap s4_pwm_e_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_f_mux =3D { +static struct clk_regmap s4_pwm_f_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, .mask =3D 0x3, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_f_mux", + .name =3D "pwm_f_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2831,20 +2823,20 @@ static struct clk_regmap s4_pwm_f_div =3D { .name =3D "pwm_f_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_f_mux.hw + &s4_pwm_f_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_f_gate =3D { +static struct clk_regmap s4_pwm_f =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, .bit_idx =3D 24, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_f_gate", + .name =3D "pwm_f", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_f_div.hw @@ -2854,17 +2846,17 @@ static struct clk_regmap s4_pwm_f_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_g_mux =3D { +static struct clk_regmap s4_pwm_g_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_g_mux", + .name =3D "pwm_g_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2879,20 +2871,20 @@ static struct clk_regmap s4_pwm_g_div =3D { .name =3D "pwm_g_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_g_mux.hw + &s4_pwm_g_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_g_gate =3D { +static struct clk_regmap s4_pwm_g =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_g_gate", + .name =3D "pwm_g", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_g_div.hw @@ -2902,17 +2894,17 @@ static struct clk_regmap s4_pwm_g_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_h_mux =3D { +static struct clk_regmap s4_pwm_h_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, .mask =3D 0x3, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_h_mux", + .name =3D "pwm_h_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2927,20 +2919,20 @@ static struct clk_regmap s4_pwm_h_div =3D { .name =3D "pwm_h_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_h_mux.hw + &s4_pwm_h_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_h_gate =3D { +static struct clk_regmap s4_pwm_h =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, .bit_idx =3D 24, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_h_gate", + .name =3D "pwm_h", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_h_div.hw @@ -2950,17 +2942,17 @@ static struct clk_regmap s4_pwm_h_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_i_mux =3D { +static struct clk_regmap s4_pwm_i_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_i_mux", + .name =3D "pwm_i_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2975,20 +2967,20 @@ static struct clk_regmap s4_pwm_i_div =3D { .name =3D "pwm_i_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_i_mux.hw + &s4_pwm_i_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_i_gate =3D { +static struct clk_regmap s4_pwm_i =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_i_gate", + .name =3D "pwm_i", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_i_div.hw @@ -2998,17 +2990,17 @@ static struct clk_regmap s4_pwm_i_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_j_mux =3D { +static struct clk_regmap s4_pwm_j_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, .mask =3D 0x3, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_j_mux", + .name =3D "pwm_j_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -3023,20 +3015,20 @@ static struct clk_regmap s4_pwm_j_div =3D { .name =3D "pwm_j_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_j_mux.hw + &s4_pwm_j_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_j_gate =3D { +static struct clk_regmap s4_pwm_j =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, .bit_idx =3D 24, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_j_gate", + .name =3D "pwm_j", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_j_div.hw @@ -3046,14 +3038,14 @@ static struct clk_regmap s4_pwm_j_gate =3D { }, }; =20 -static struct clk_regmap s4_saradc_mux =3D { +static struct clk_regmap s4_saradc_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_SAR_CLK_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "saradc_mux", + .name =3D "saradc_sel", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "xtal", }, @@ -3074,20 +3066,20 @@ static struct clk_regmap s4_saradc_div =3D { .name =3D "saradc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_saradc_mux.hw + &s4_saradc_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_saradc_gate =3D { +static struct clk_regmap s4_saradc =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_SAR_CLK_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "saradc_clk", + .name =3D "saradc", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_saradc_div.hw @@ -3102,9 +3094,8 @@ static struct clk_regmap s4_saradc_gate =3D { * corresponding clock sources are not described in the clock tree and int= ernal clock * for debug, so they are skipped. */ -static u32 s4_gen_clk_mux_table[] =3D { 0, 4, 5, 7, 19, 21, 22, - 23, 24, 25, 26, 27, 28 }; -static const struct clk_parent_data s4_gen_clk_parent_data[] =3D { +static u32 s4_gen_clk_parents_val_table[] =3D { 0, 4, 5, 7, 19, 21, 22, 23= , 24, 25, 26, 27, 28 }; +static const struct clk_parent_data s4_gen_clk_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &s4_vid_pll.hw }, { .fw_name =3D "gp0_pll", }, @@ -3125,13 +3116,13 @@ static struct clk_regmap s4_gen_clk_sel =3D { .offset =3D CLKCTRL_GEN_CLK_CTRL, .mask =3D 0x1f, .shift =3D 12, - .table =3D s4_gen_clk_mux_table, + .table =3D s4_gen_clk_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "gen_clk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_gen_clk_parent_data, - .num_parents =3D ARRAY_SIZE(s4_gen_clk_parent_data), + .parent_data =3D s4_gen_clk_parents, + .num_parents =3D ARRAY_SIZE(s4_gen_clk_parents), /* * Because the GEN clock can be connected to an external pad * and may be set up directly from the device tree. Don't @@ -3174,61 +3165,64 @@ static struct clk_regmap s4_gen_clk =3D { }, }; =20 -#define MESON_GATE(_name, _reg, _bit) \ +#define S4_PCLK(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw) =20 -static MESON_GATE(s4_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0); -static MESON_GATE(s4_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1); -static MESON_GATE(s4_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4); -static MESON_GATE(s4_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6); -static MESON_GATE(s4_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13); -static MESON_GATE(s4_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14); -static MESON_GATE(s4_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16); -static MESON_GATE(s4_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24); -static MESON_GATE(s4_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25); -static MESON_GATE(s4_nand, CLKCTRL_SYS_CLK_EN0_REG0, 26); -static MESON_GATE(s4_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27); -static MESON_GATE(s4_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28); -static MESON_GATE(s4_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29); -static MESON_GATE(s4_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30); -static MESON_GATE(s4_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31); -static MESON_GATE(s4_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0); -static MESON_GATE(s4_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3); -static MESON_GATE(s4_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5); -static MESON_GATE(s4_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6); -static MESON_GATE(s4_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7); -static MESON_GATE(s4_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8); -static MESON_GATE(s4_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9); -static MESON_GATE(s4_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11); -static MESON_GATE(s4_ts_ddr, CLKCTRL_SYS_CLK_EN0_REG1, 15); -static MESON_GATE(s4_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16); -static MESON_GATE(s4_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20); -static MESON_GATE(s4_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21); -static MESON_GATE(s4_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26); -static MESON_GATE(s4_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30); -static MESON_GATE(s4_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31); -static MESON_GATE(s4_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0); -static MESON_GATE(s4_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1); -static MESON_GATE(s4_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2); -static MESON_GATE(s4_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4); -static MESON_GATE(s4_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5); -static MESON_GATE(s4_usb1_to_ddr, CLKCTRL_SYS_CLK_EN0_REG2, 8); -static MESON_GATE(s4_hdcp22, CLKCTRL_SYS_CLK_EN0_REG2, 10); -static MESON_GATE(s4_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11); -static MESON_GATE(s4_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18); -static MESON_GATE(s4_cpu_debug, CLKCTRL_SYS_CLK_EN0_REG2, 19); -static MESON_GATE(s4_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25); -static MESON_GATE(s4_demod, CLKCTRL_SYS_CLK_EN0_REG2, 27); -static MESON_GATE(s4_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28); -static MESON_GATE(s4_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30); -static MESON_GATE(s4_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7); -static MESON_GATE(s4_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8); -static MESON_GATE(s4_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9); -static MESON_GATE(s4_pwm_gh, CLKCTRL_SYS_CLK_EN0_REG3, 10); -static MESON_GATE(s4_pwm_ij, CLKCTRL_SYS_CLK_EN0_REG3, 11); +static S4_PCLK(s4_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0); +static S4_PCLK(s4_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1); +static S4_PCLK(s4_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4); +static S4_PCLK(s4_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6); +static S4_PCLK(s4_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13); +static S4_PCLK(s4_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14); +static S4_PCLK(s4_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16); +static S4_PCLK(s4_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24); +static S4_PCLK(s4_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25); +static S4_PCLK(s4_nand, CLKCTRL_SYS_CLK_EN0_REG0, 26); +static S4_PCLK(s4_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27); +static S4_PCLK(s4_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28); +static S4_PCLK(s4_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29); +static S4_PCLK(s4_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30); +static S4_PCLK(s4_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31); + +static S4_PCLK(s4_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0); +static S4_PCLK(s4_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3); +static S4_PCLK(s4_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5); +static S4_PCLK(s4_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6); +static S4_PCLK(s4_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7); +static S4_PCLK(s4_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8); +static S4_PCLK(s4_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9); +static S4_PCLK(s4_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11); +static S4_PCLK(s4_ts_ddr, CLKCTRL_SYS_CLK_EN0_REG1, 15); +static S4_PCLK(s4_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16); +static S4_PCLK(s4_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20); +static S4_PCLK(s4_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21); +static S4_PCLK(s4_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26); +static S4_PCLK(s4_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30); +static S4_PCLK(s4_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31); + +static S4_PCLK(s4_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0); +static S4_PCLK(s4_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1); +static S4_PCLK(s4_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2); +static S4_PCLK(s4_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4); +static S4_PCLK(s4_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5); +static S4_PCLK(s4_usb1_to_ddr, CLKCTRL_SYS_CLK_EN0_REG2, 8); +static S4_PCLK(s4_hdcp22, CLKCTRL_SYS_CLK_EN0_REG2, 10); +static S4_PCLK(s4_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11); +static S4_PCLK(s4_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18); +static S4_PCLK(s4_cpu_debug, CLKCTRL_SYS_CLK_EN0_REG2, 19); +static S4_PCLK(s4_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25); +static S4_PCLK(s4_demod, CLKCTRL_SYS_CLK_EN0_REG2, 27); +static S4_PCLK(s4_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28); +static S4_PCLK(s4_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30); + +static S4_PCLK(s4_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7); +static S4_PCLK(s4_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8); +static S4_PCLK(s4_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9); +static S4_PCLK(s4_pwm_gh, CLKCTRL_SYS_CLK_EN0_REG3, 10); +static S4_PCLK(s4_pwm_ij, CLKCTRL_SYS_CLK_EN0_REG3, 11); =20 /* Array of all clocks provided by this provider */ -static struct clk_hw *s4_periphs_hw_clks[] =3D { +static struct clk_hw *s4_peripherals_hw_clks[] =3D { [CLKID_RTC_32K_CLKIN] =3D &s4_rtc_32k_by_oscin_clkin.hw, [CLKID_RTC_32K_DIV] =3D &s4_rtc_32k_by_oscin_div.hw, [CLKID_RTC_32K_SEL] =3D &s4_rtc_32k_by_oscin_sel.hw, @@ -3251,12 +3245,12 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_CECB_32K_SEL_PRE] =3D &s4_cecb_32k_sel_pre.hw, [CLKID_CECB_32K_SEL] =3D &s4_cecb_32k_sel.hw, [CLKID_CECB_32K_CLKOUT] =3D &s4_cecb_32k_clkout.hw, - [CLKID_SC_CLK_SEL] =3D &s4_sc_clk_mux.hw, + [CLKID_SC_CLK_SEL] =3D &s4_sc_clk_sel.hw, [CLKID_SC_CLK_DIV] =3D &s4_sc_clk_div.hw, - [CLKID_SC] =3D &s4_sc_clk_gate.hw, - [CLKID_12_24M] =3D &s4_12_24M_clk_gate.hw, - [CLKID_12M_CLK_DIV] =3D &s4_12M_clk_div.hw, - [CLKID_12_24M_CLK_SEL] =3D &s4_12_24M_clk.hw, + [CLKID_SC] =3D &s4_sc_clk.hw, + [CLKID_12_24M] =3D &s4_12_24M.hw, + [CLKID_12M_CLK_DIV] =3D &s4_12M_div.hw, + [CLKID_12_24M_CLK_SEL] =3D &s4_12_24M_sel.hw, [CLKID_VID_PLL_DIV] =3D &s4_vid_pll_div.hw, [CLKID_VID_PLL_SEL] =3D &s4_vid_pll_sel.hw, [CLKID_VID_PLL] =3D &s4_vid_pll.hw, @@ -3298,28 +3292,28 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_HDMI_DIV] =3D &s4_hdmi_div.hw, [CLKID_HDMI] =3D &s4_hdmi.hw, [CLKID_TS_CLK_DIV] =3D &s4_ts_clk_div.hw, - [CLKID_TS] =3D &s4_ts_clk_gate.hw, + [CLKID_TS] =3D &s4_ts_clk.hw, [CLKID_MALI_0_SEL] =3D &s4_mali_0_sel.hw, [CLKID_MALI_0_DIV] =3D &s4_mali_0_div.hw, [CLKID_MALI_0] =3D &s4_mali_0.hw, [CLKID_MALI_1_SEL] =3D &s4_mali_1_sel.hw, [CLKID_MALI_1_DIV] =3D &s4_mali_1_div.hw, [CLKID_MALI_1] =3D &s4_mali_1.hw, - [CLKID_MALI_SEL] =3D &s4_mali_mux.hw, - [CLKID_VDEC_P0_SEL] =3D &s4_vdec_p0_mux.hw, + [CLKID_MALI_SEL] =3D &s4_mali_sel.hw, + [CLKID_VDEC_P0_SEL] =3D &s4_vdec_p0_sel.hw, [CLKID_VDEC_P0_DIV] =3D &s4_vdec_p0_div.hw, [CLKID_VDEC_P0] =3D &s4_vdec_p0.hw, - [CLKID_VDEC_P1_SEL] =3D &s4_vdec_p1_mux.hw, + [CLKID_VDEC_P1_SEL] =3D &s4_vdec_p1_sel.hw, [CLKID_VDEC_P1_DIV] =3D &s4_vdec_p1_div.hw, [CLKID_VDEC_P1] =3D &s4_vdec_p1.hw, - [CLKID_VDEC_SEL] =3D &s4_vdec_mux.hw, - [CLKID_HEVCF_P0_SEL] =3D &s4_hevcf_p0_mux.hw, + [CLKID_VDEC_SEL] =3D &s4_vdec_sel.hw, + [CLKID_HEVCF_P0_SEL] =3D &s4_hevcf_p0_sel.hw, [CLKID_HEVCF_P0_DIV] =3D &s4_hevcf_p0_div.hw, [CLKID_HEVCF_P0] =3D &s4_hevcf_p0.hw, - [CLKID_HEVCF_P1_SEL] =3D &s4_hevcf_p1_mux.hw, + [CLKID_HEVCF_P1_SEL] =3D &s4_hevcf_p1_sel.hw, [CLKID_HEVCF_P1_DIV] =3D &s4_hevcf_p1_div.hw, [CLKID_HEVCF_P1] =3D &s4_hevcf_p1.hw, - [CLKID_HEVCF_SEL] =3D &s4_hevcf_mux.hw, + [CLKID_HEVCF_SEL] =3D &s4_hevcf_sel.hw, [CLKID_VPU_0_SEL] =3D &s4_vpu_0_sel.hw, [CLKID_VPU_0_DIV] =3D &s4_vpu_0_div.hw, [CLKID_VPU_0] =3D &s4_vpu_0.hw, @@ -3327,18 +3321,18 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_VPU_1_DIV] =3D &s4_vpu_1_div.hw, [CLKID_VPU_1] =3D &s4_vpu_1.hw, [CLKID_VPU] =3D &s4_vpu.hw, - [CLKID_VPU_CLKB_TMP_SEL] =3D &s4_vpu_clkb_tmp_mux.hw, + [CLKID_VPU_CLKB_TMP_SEL] =3D &s4_vpu_clkb_tmp_sel.hw, [CLKID_VPU_CLKB_TMP_DIV] =3D &s4_vpu_clkb_tmp_div.hw, [CLKID_VPU_CLKB_TMP] =3D &s4_vpu_clkb_tmp.hw, [CLKID_VPU_CLKB_DIV] =3D &s4_vpu_clkb_div.hw, [CLKID_VPU_CLKB] =3D &s4_vpu_clkb.hw, - [CLKID_VPU_CLKC_P0_SEL] =3D &s4_vpu_clkc_p0_mux.hw, + [CLKID_VPU_CLKC_P0_SEL] =3D &s4_vpu_clkc_p0_sel.hw, [CLKID_VPU_CLKC_P0_DIV] =3D &s4_vpu_clkc_p0_div.hw, [CLKID_VPU_CLKC_P0] =3D &s4_vpu_clkc_p0.hw, - [CLKID_VPU_CLKC_P1_SEL] =3D &s4_vpu_clkc_p1_mux.hw, + [CLKID_VPU_CLKC_P1_SEL] =3D &s4_vpu_clkc_p1_sel.hw, [CLKID_VPU_CLKC_P1_DIV] =3D &s4_vpu_clkc_p1_div.hw, [CLKID_VPU_CLKC_P1] =3D &s4_vpu_clkc_p1.hw, - [CLKID_VPU_CLKC_SEL] =3D &s4_vpu_clkc_mux.hw, + [CLKID_VPU_CLKC_SEL] =3D &s4_vpu_clkc_sel.hw, [CLKID_VAPB_0_SEL] =3D &s4_vapb_0_sel.hw, [CLKID_VAPB_0_DIV] =3D &s4_vapb_0_div.hw, [CLKID_VAPB_0] =3D &s4_vapb_0.hw, @@ -3346,10 +3340,10 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_VAPB_1_DIV] =3D &s4_vapb_1_div.hw, [CLKID_VAPB_1] =3D &s4_vapb_1.hw, [CLKID_VAPB] =3D &s4_vapb.hw, - [CLKID_GE2D] =3D &s4_ge2d_gate.hw, - [CLKID_VDIN_MEAS_SEL] =3D &s4_vdin_meas_mux.hw, + [CLKID_GE2D] =3D &s4_ge2d.hw, + [CLKID_VDIN_MEAS_SEL] =3D &s4_vdin_meas_sel.hw, [CLKID_VDIN_MEAS_DIV] =3D &s4_vdin_meas_div.hw, - [CLKID_VDIN_MEAS] =3D &s4_vdin_meas_gate.hw, + [CLKID_VDIN_MEAS] =3D &s4_vdin_meas.hw, [CLKID_SD_EMMC_C_CLK_SEL] =3D &s4_sd_emmc_c_clk0_sel.hw, [CLKID_SD_EMMC_C_CLK_DIV] =3D &s4_sd_emmc_c_clk0_div.hw, [CLKID_SD_EMMC_C] =3D &s4_sd_emmc_c_clk0.hw, @@ -3359,42 +3353,42 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_SD_EMMC_B_CLK_SEL] =3D &s4_sd_emmc_b_clk0_sel.hw, [CLKID_SD_EMMC_B_CLK_DIV] =3D &s4_sd_emmc_b_clk0_div.hw, [CLKID_SD_EMMC_B] =3D &s4_sd_emmc_b_clk0.hw, - [CLKID_SPICC0_SEL] =3D &s4_spicc0_mux.hw, + [CLKID_SPICC0_SEL] =3D &s4_spicc0_sel.hw, [CLKID_SPICC0_DIV] =3D &s4_spicc0_div.hw, - [CLKID_SPICC0_EN] =3D &s4_spicc0_gate.hw, - [CLKID_PWM_A_SEL] =3D &s4_pwm_a_mux.hw, + [CLKID_SPICC0_EN] =3D &s4_spicc0_en.hw, + [CLKID_PWM_A_SEL] =3D &s4_pwm_a_sel.hw, [CLKID_PWM_A_DIV] =3D &s4_pwm_a_div.hw, - [CLKID_PWM_A] =3D &s4_pwm_a_gate.hw, - [CLKID_PWM_B_SEL] =3D &s4_pwm_b_mux.hw, + [CLKID_PWM_A] =3D &s4_pwm_a.hw, + [CLKID_PWM_B_SEL] =3D &s4_pwm_b_sel.hw, [CLKID_PWM_B_DIV] =3D &s4_pwm_b_div.hw, - [CLKID_PWM_B] =3D &s4_pwm_b_gate.hw, - [CLKID_PWM_C_SEL] =3D &s4_pwm_c_mux.hw, + [CLKID_PWM_B] =3D &s4_pwm_b.hw, + [CLKID_PWM_C_SEL] =3D &s4_pwm_c_sel.hw, [CLKID_PWM_C_DIV] =3D &s4_pwm_c_div.hw, - [CLKID_PWM_C] =3D &s4_pwm_c_gate.hw, - [CLKID_PWM_D_SEL] =3D &s4_pwm_d_mux.hw, + [CLKID_PWM_C] =3D &s4_pwm_c.hw, + [CLKID_PWM_D_SEL] =3D &s4_pwm_d_sel.hw, [CLKID_PWM_D_DIV] =3D &s4_pwm_d_div.hw, - [CLKID_PWM_D] =3D &s4_pwm_d_gate.hw, - [CLKID_PWM_E_SEL] =3D &s4_pwm_e_mux.hw, + [CLKID_PWM_D] =3D &s4_pwm_d.hw, + [CLKID_PWM_E_SEL] =3D &s4_pwm_e_sel.hw, [CLKID_PWM_E_DIV] =3D &s4_pwm_e_div.hw, - [CLKID_PWM_E] =3D &s4_pwm_e_gate.hw, - [CLKID_PWM_F_SEL] =3D &s4_pwm_f_mux.hw, + [CLKID_PWM_E] =3D &s4_pwm_e.hw, + [CLKID_PWM_F_SEL] =3D &s4_pwm_f_sel.hw, [CLKID_PWM_F_DIV] =3D &s4_pwm_f_div.hw, - [CLKID_PWM_F] =3D &s4_pwm_f_gate.hw, - [CLKID_PWM_G_SEL] =3D &s4_pwm_g_mux.hw, + [CLKID_PWM_F] =3D &s4_pwm_f.hw, + [CLKID_PWM_G_SEL] =3D &s4_pwm_g_sel.hw, [CLKID_PWM_G_DIV] =3D &s4_pwm_g_div.hw, - [CLKID_PWM_G] =3D &s4_pwm_g_gate.hw, - [CLKID_PWM_H_SEL] =3D &s4_pwm_h_mux.hw, + [CLKID_PWM_G] =3D &s4_pwm_g.hw, + [CLKID_PWM_H_SEL] =3D &s4_pwm_h_sel.hw, [CLKID_PWM_H_DIV] =3D &s4_pwm_h_div.hw, - [CLKID_PWM_H] =3D &s4_pwm_h_gate.hw, - [CLKID_PWM_I_SEL] =3D &s4_pwm_i_mux.hw, + [CLKID_PWM_H] =3D &s4_pwm_h.hw, + [CLKID_PWM_I_SEL] =3D &s4_pwm_i_sel.hw, [CLKID_PWM_I_DIV] =3D &s4_pwm_i_div.hw, - [CLKID_PWM_I] =3D &s4_pwm_i_gate.hw, - [CLKID_PWM_J_SEL] =3D &s4_pwm_j_mux.hw, + [CLKID_PWM_I] =3D &s4_pwm_i.hw, + [CLKID_PWM_J_SEL] =3D &s4_pwm_j_sel.hw, [CLKID_PWM_J_DIV] =3D &s4_pwm_j_div.hw, - [CLKID_PWM_J] =3D &s4_pwm_j_gate.hw, - [CLKID_SARADC_SEL] =3D &s4_saradc_mux.hw, + [CLKID_PWM_J] =3D &s4_pwm_j.hw, + [CLKID_SARADC_SEL] =3D &s4_saradc_sel.hw, [CLKID_SARADC_DIV] =3D &s4_saradc_div.hw, - [CLKID_SARADC] =3D &s4_saradc_gate.hw, + [CLKID_SARADC] =3D &s4_saradc.hw, [CLKID_GEN_SEL] =3D &s4_gen_clk_sel.hw, [CLKID_GEN_DIV] =3D &s4_gen_clk_div.hw, [CLKID_GEN] =3D &s4_gen_clk.hw, @@ -3447,27 +3441,27 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_PWM_EF] =3D &s4_pwm_ef.hw, [CLKID_PWM_GH] =3D &s4_pwm_gh.hw, [CLKID_PWM_IJ] =3D &s4_pwm_ij.hw, - [CLKID_HDCP22_ESMCLK_SEL] =3D &s4_hdcp22_esmclk_mux.hw, + [CLKID_HDCP22_ESMCLK_SEL] =3D &s4_hdcp22_esmclk_sel.hw, [CLKID_HDCP22_ESMCLK_DIV] =3D &s4_hdcp22_esmclk_div.hw, - [CLKID_HDCP22_ESMCLK] =3D &s4_hdcp22_esmclk_gate.hw, - [CLKID_HDCP22_SKPCLK_SEL] =3D &s4_hdcp22_skpclk_mux.hw, + [CLKID_HDCP22_ESMCLK] =3D &s4_hdcp22_esmclk.hw, + [CLKID_HDCP22_SKPCLK_SEL] =3D &s4_hdcp22_skpclk_sel.hw, [CLKID_HDCP22_SKPCLK_DIV] =3D &s4_hdcp22_skpclk_div.hw, - [CLKID_HDCP22_SKPCLK] =3D &s4_hdcp22_skpclk_gate.hw, + [CLKID_HDCP22_SKPCLK] =3D &s4_hdcp22_skpclk.hw, }; =20 -static const struct regmap_config clkc_regmap_config =3D { +static const struct regmap_config s4_peripherals_regmap_cfg =3D { .reg_bits =3D 32, .val_bits =3D 32, .reg_stride =3D 4, .max_register =3D CLKCTRL_DEMOD_CLK_CTRL, }; =20 -static struct meson_clk_hw_data s4_periphs_clks =3D { - .hws =3D s4_periphs_hw_clks, - .num =3D ARRAY_SIZE(s4_periphs_hw_clks), +static struct meson_clk_hw_data s4_peripherals_clks =3D { + .hws =3D s4_peripherals_hw_clks, + .num =3D ARRAY_SIZE(s4_peripherals_hw_clks), }; =20 -static int meson_s4_periphs_probe(struct platform_device *pdev) +static int s4_peripherals_clkc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct regmap *regmap; @@ -3479,41 +3473,41 @@ static int meson_s4_periphs_probe(struct platform_d= evice *pdev) return dev_err_probe(dev, PTR_ERR(base), "can't ioremap resource\n"); =20 - regmap =3D devm_regmap_init_mmio(dev, base, &clkc_regmap_config); + regmap =3D devm_regmap_init_mmio(dev, base, &s4_peripherals_regmap_cfg); if (IS_ERR(regmap)) return dev_err_probe(dev, PTR_ERR(regmap), "can't init regmap mmio region\n"); =20 - for (i =3D 0; i < s4_periphs_clks.num; i++) { + for (i =3D 0; i < s4_peripherals_clks.num; i++) { /* array might be sparse */ - if (!s4_periphs_clks.hws[i]) + if (!s4_peripherals_clks.hws[i]) continue; =20 - ret =3D devm_clk_hw_register(dev, s4_periphs_clks.hws[i]); + ret =3D devm_clk_hw_register(dev, s4_peripherals_clks.hws[i]); if (ret) return dev_err_probe(dev, ret, "clock[%d] registration failed\n", i); } =20 - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &s4_periphs_clk= s); + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &s4_peripherals= _clks); } =20 -static const struct of_device_id clkc_match_table[] =3D { +static const struct of_device_id s4_peripherals_clkc_match_table[] =3D { { .compatible =3D "amlogic,s4-peripherals-clkc", }, {} }; -MODULE_DEVICE_TABLE(of, clkc_match_table); +MODULE_DEVICE_TABLE(of, s4_peripherals_clkc_match_table); =20 -static struct platform_driver s4_driver =3D { - .probe =3D meson_s4_periphs_probe, +static struct platform_driver s4_peripherals_clkc_driver =3D { + .probe =3D s4_peripherals_clkc_probe, .driver =3D { - .name =3D "s4-periphs-clkc", - .of_match_table =3D clkc_match_table, + .name =3D "s4-peripherals-clkc", + .of_match_table =3D s4_peripherals_clkc_match_table, }, }; -module_platform_driver(s4_driver); +module_platform_driver(s4_peripherals_clkc_driver); =20 MODULE_DESCRIPTION("Amlogic S4 Peripherals Clock Controller driver"); MODULE_AUTHOR("Yu Tu "); --=20 2.47.2