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Wed, 02 Jul 2025 08:27:13 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:25:59 +0200 Subject: [PATCH 01/26] clk: amlogic: a1-peripherals: naming consistency alignment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-1-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=71075; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=kfx6yFlpS5ecUvc6HVaqoNSEOKQK8DbV8drFrmeT7L4=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoZU+3yVkDE8nnPJbZ1CAVuocjFxBFNh9wN1dYo 8lKfGQ+9ZiJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaGVPtwAKCRDm/A8cN/La hXS0D/425E2rQuD+5SLsnW5K6QxDokm8uZRc5N/4IqWdpVN+OWQZnwH1yIbDn4dsXCcOcoVct7r pQdypPylg1hQTTbuzWhFi/51l/BlTX8rFeVtPl+V8W3flA4UjnZI48c51NhCli7TEi6QEi6LWSy no2kS8sS+qXfn/jG8p0kNRM2yPRB/l0UlMK+AQHUwx8XvGdHVwznqbC4xgKxX7es1SMXKKH8SNV 5OfA67xGjlVR8z4k2Oc00D4v7AbUw069XW5zYnXubtUO+eHKJZxhH6+adVono+tbNtnkVU5RLiJ eWlKCZurzXdhhvY1Zr1ygDWMUnY3rv95aSZpP2C0b7W9iZQJzu+Ca+jOBeValIXSK2Adw22XDcj +97oXWVys6asBvG9IvxmYJxdAl/A+mTN0/K+aMi9X8kCSee4fspl76MflAMla2RoNxXLmKbL86z toM7swfqb/sBq7W+LwGSsRFPcoVgeeIORncCbmOAKUfrgofdwVvu2D+pbYcpr3QyvqW4a2CnT3O JDEUX8mbmhKEucPkVxXuUVgooy0ZVJlJ0QELNdACLbvq3+Zg+Ac2NTCD5Fe8oayxX2pfrC1QL3u aC78za328Z3hNdTlU+Vr7s1B3JHsO4Cs66uR1DVWzWhiviYcf+3vbG4BxmXMpB7NT7+dowYs5w+ 8w+Iib7ikIP1afA== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet --- drivers/clk/meson/a1-peripherals.c | 950 +++++++++++++++++++--------------= ---- 1 file changed, 476 insertions(+), 474 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peri= pherals.c index 1f5d445d44fe7501d9f20380cd2b527109564630..9e352dba54775c22126ee8bf786= 1ee1d981d6c88 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -46,7 +46,7 @@ #define PSRAM_CLK_CTRL 0xf4 #define DMC_CLK_CTRL 0xf8 =20 -static struct clk_regmap xtal_in =3D { +static struct clk_regmap a1_xtal_in =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D SYS_OSCIN_CTRL, .bit_idx =3D 0, @@ -61,7 +61,7 @@ static struct clk_regmap xtal_in =3D { }, }; =20 -static struct clk_regmap fixpll_in =3D { +static struct clk_regmap a1_fixpll_in =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D SYS_OSCIN_CTRL, .bit_idx =3D 1, @@ -76,7 +76,7 @@ static struct clk_regmap fixpll_in =3D { }, }; =20 -static struct clk_regmap usb_phy_in =3D { +static struct clk_regmap a1_usb_phy_in =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D SYS_OSCIN_CTRL, .bit_idx =3D 2, @@ -91,7 +91,7 @@ static struct clk_regmap usb_phy_in =3D { }, }; =20 -static struct clk_regmap usb_ctrl_in =3D { +static struct clk_regmap a1_usb_ctrl_in =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D SYS_OSCIN_CTRL, .bit_idx =3D 3, @@ -106,7 +106,7 @@ static struct clk_regmap usb_ctrl_in =3D { }, }; =20 -static struct clk_regmap hifipll_in =3D { +static struct clk_regmap a1_hifipll_in =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D SYS_OSCIN_CTRL, .bit_idx =3D 4, @@ -121,7 +121,7 @@ static struct clk_regmap hifipll_in =3D { }, }; =20 -static struct clk_regmap syspll_in =3D { +static struct clk_regmap a1_syspll_in =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D SYS_OSCIN_CTRL, .bit_idx =3D 5, @@ -136,7 +136,7 @@ static struct clk_regmap syspll_in =3D { }, }; =20 -static struct clk_regmap dds_in =3D { +static struct clk_regmap a1_dds_in =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D SYS_OSCIN_CTRL, .bit_idx =3D 6, @@ -151,7 +151,7 @@ static struct clk_regmap dds_in =3D { }, }; =20 -static struct clk_regmap rtc_32k_in =3D { +static struct clk_regmap a1_rtc_32k_in =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D RTC_BY_OSCIN_CTRL0, .bit_idx =3D 31, @@ -166,7 +166,7 @@ static struct clk_regmap rtc_32k_in =3D { }, }; =20 -static const struct meson_clk_dualdiv_param clk_32k_div_table[] =3D { +static const struct meson_clk_dualdiv_param a1_32k_div_table[] =3D { { .dual =3D 1, .n1 =3D 733, @@ -177,7 +177,7 @@ static const struct meson_clk_dualdiv_param clk_32k_div= _table[] =3D { {} }; =20 -static struct clk_regmap rtc_32k_div =3D { +static struct clk_regmap a1_rtc_32k_div =3D { .data =3D &(struct meson_clk_dualdiv_data){ .n1 =3D { .reg_off =3D RTC_BY_OSCIN_CTRL0, @@ -204,19 +204,19 @@ static struct clk_regmap rtc_32k_div =3D { .shift =3D 28, .width =3D 1, }, - .table =3D clk_32k_div_table, + .table =3D a1_32k_div_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "rtc_32k_div", .ops =3D &meson_clk_dualdiv_ops, .parent_hws =3D (const struct clk_hw *[]) { - &rtc_32k_in.hw + &a1_rtc_32k_in.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap rtc_32k_xtal =3D { +static struct clk_regmap a1_rtc_32k_xtal =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D RTC_BY_OSCIN_CTRL1, .bit_idx =3D 24, @@ -225,13 +225,13 @@ static struct clk_regmap rtc_32k_xtal =3D { .name =3D "rtc_32k_xtal", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &rtc_32k_in.hw + &a1_rtc_32k_in.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap rtc_32k_sel =3D { +static struct clk_regmap a1_rtc_32k_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D RTC_CTRL, .mask =3D 0x3, @@ -242,15 +242,15 @@ static struct clk_regmap rtc_32k_sel =3D { .name =3D "rtc_32k_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &rtc_32k_xtal.hw, - &rtc_32k_div.hw, + &a1_rtc_32k_xtal.hw, + &a1_rtc_32k_div.hw, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap rtc =3D { +static struct clk_regmap a1_rtc =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D RTC_BY_OSCIN_CTRL0, .bit_idx =3D 30, @@ -259,38 +259,38 @@ static struct clk_regmap rtc =3D { .name =3D "rtc", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &rtc_32k_sel.hw + &a1_rtc_32k_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static u32 mux_table_sys[] =3D { 0, 1, 2, 3, 7 }; -static const struct clk_parent_data sys_parents[] =3D { +static u32 a1_sys_parents_val_table[] =3D { 0, 1, 2, 3, 7 }; +static const struct clk_parent_data a1_sys_parents[] =3D { { .fw_name =3D "xtal" }, { .fw_name =3D "fclk_div2" }, { .fw_name =3D "fclk_div3" }, { .fw_name =3D "fclk_div5" }, - { .hw =3D &rtc.hw }, + { .hw =3D &a1_rtc.hw }, }; =20 -static struct clk_regmap sys_b_sel =3D { +static struct clk_regmap a1_sys_b_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D SYS_CLK_CTRL0, .mask =3D 0x7, .shift =3D 26, - .table =3D mux_table_sys, + .table =3D a1_sys_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "sys_b_sel", .ops =3D &clk_regmap_mux_ro_ops, - .parent_data =3D sys_parents, - .num_parents =3D ARRAY_SIZE(sys_parents), + .parent_data =3D a1_sys_parents, + .num_parents =3D ARRAY_SIZE(a1_sys_parents), }, }; =20 -static struct clk_regmap sys_b_div =3D { +static struct clk_regmap a1_sys_b_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D SYS_CLK_CTRL0, .shift =3D 16, @@ -300,14 +300,14 @@ static struct clk_regmap sys_b_div =3D { .name =3D "sys_b_div", .ops =3D &clk_regmap_divider_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sys_b_sel.hw + &a1_sys_b_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap sys_b =3D { +static struct clk_regmap a1_sys_b =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D SYS_CLK_CTRL0, .bit_idx =3D 29, @@ -316,29 +316,29 @@ static struct clk_regmap sys_b =3D { .name =3D "sys_b", .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sys_b_div.hw + &a1_sys_b_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap sys_a_sel =3D { +static struct clk_regmap a1_sys_a_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D SYS_CLK_CTRL0, .mask =3D 0x7, .shift =3D 10, - .table =3D mux_table_sys, + .table =3D a1_sys_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "sys_a_sel", .ops =3D &clk_regmap_mux_ro_ops, - .parent_data =3D sys_parents, - .num_parents =3D ARRAY_SIZE(sys_parents), + .parent_data =3D a1_sys_parents, + .num_parents =3D ARRAY_SIZE(a1_sys_parents), }, }; =20 -static struct clk_regmap sys_a_div =3D { +static struct clk_regmap a1_sys_a_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D SYS_CLK_CTRL0, .shift =3D 0, @@ -348,14 +348,14 @@ static struct clk_regmap sys_a_div =3D { .name =3D "sys_a_div", .ops =3D &clk_regmap_divider_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sys_a_sel.hw + &a1_sys_a_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap sys_a =3D { +static struct clk_regmap a1_sys_a =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D SYS_CLK_CTRL0, .bit_idx =3D 13, @@ -364,14 +364,14 @@ static struct clk_regmap sys_a =3D { .name =3D "sys_a", .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sys_a_div.hw + &a1_sys_a_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap sys =3D { +static struct clk_regmap a1_sys =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D SYS_CLK_CTRL0, .mask =3D 0x1, @@ -381,8 +381,8 @@ static struct clk_regmap sys =3D { .name =3D "sys", .ops =3D &clk_regmap_mux_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sys_a.hw, - &sys_b.hw, + &a1_sys_a.hw, + &a1_sys_b.hw, }, .num_parents =3D 2, /* @@ -398,32 +398,32 @@ static struct clk_regmap sys =3D { }, }; =20 -static u32 mux_table_dsp_ab[] =3D { 0, 1, 2, 3, 4, 7 }; -static const struct clk_parent_data dsp_ab_parent_data[] =3D { +static u32 a1_dsp_parents_val_table[] =3D { 0, 1, 2, 3, 4, 7 }; +static const struct clk_parent_data a1_dsp_parents[] =3D { { .fw_name =3D "xtal", }, { .fw_name =3D "fclk_div2", }, { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div5", }, { .fw_name =3D "hifi_pll", }, - { .hw =3D &rtc.hw }, + { .hw =3D &a1_rtc.hw }, }; =20 -static struct clk_regmap dspa_a_sel =3D { +static struct clk_regmap a1_dspa_a_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D DSPA_CLK_CTRL0, .mask =3D 0x7, .shift =3D 10, - .table =3D mux_table_dsp_ab, + .table =3D a1_dsp_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "dspa_a_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D dsp_ab_parent_data, - .num_parents =3D ARRAY_SIZE(dsp_ab_parent_data), + .parent_data =3D a1_dsp_parents, + .num_parents =3D ARRAY_SIZE(a1_dsp_parents), }, }; =20 -static struct clk_regmap dspa_a_div =3D { +static struct clk_regmap a1_dspa_a_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D DSPA_CLK_CTRL0, .shift =3D 0, @@ -433,14 +433,14 @@ static struct clk_regmap dspa_a_div =3D { .name =3D "dspa_a_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspa_a_sel.hw + &a1_dspa_a_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dspa_a =3D { +static struct clk_regmap a1_dspa_a =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D DSPA_CLK_CTRL0, .bit_idx =3D 13, @@ -449,29 +449,29 @@ static struct clk_regmap dspa_a =3D { .name =3D "dspa_a", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspa_a_div.hw + &a1_dspa_a_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dspa_b_sel =3D { +static struct clk_regmap a1_dspa_b_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D DSPA_CLK_CTRL0, .mask =3D 0x7, .shift =3D 26, - .table =3D mux_table_dsp_ab, + .table =3D a1_dsp_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "dspa_b_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D dsp_ab_parent_data, - .num_parents =3D ARRAY_SIZE(dsp_ab_parent_data), + .parent_data =3D a1_dsp_parents, + .num_parents =3D ARRAY_SIZE(a1_dsp_parents), }, }; =20 -static struct clk_regmap dspa_b_div =3D { +static struct clk_regmap a1_dspa_b_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D DSPA_CLK_CTRL0, .shift =3D 16, @@ -481,14 +481,14 @@ static struct clk_regmap dspa_b_div =3D { .name =3D "dspa_b_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspa_b_sel.hw + &a1_dspa_b_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dspa_b =3D { +static struct clk_regmap a1_dspa_b =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D DSPA_CLK_CTRL0, .bit_idx =3D 29, @@ -497,14 +497,14 @@ static struct clk_regmap dspa_b =3D { .name =3D "dspa_b", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspa_b_div.hw + &a1_dspa_b_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dspa_sel =3D { +static struct clk_regmap a1_dspa_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D DSPA_CLK_CTRL0, .mask =3D 0x1, @@ -514,15 +514,15 @@ static struct clk_regmap dspa_sel =3D { .name =3D "dspa_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspa_a.hw, - &dspa_b.hw, + &a1_dspa_a.hw, + &a1_dspa_b.hw, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dspa_en =3D { +static struct clk_regmap a1_dspa_en =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D DSPA_CLK_EN, .bit_idx =3D 1, @@ -531,14 +531,14 @@ static struct clk_regmap dspa_en =3D { .name =3D "dspa_en", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspa_sel.hw + &a1_dspa_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dspa_en_nic =3D { +static struct clk_regmap a1_dspa_en_nic =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D DSPA_CLK_EN, .bit_idx =3D 0, @@ -547,29 +547,29 @@ static struct clk_regmap dspa_en_nic =3D { .name =3D "dspa_en_nic", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspa_sel.hw + &a1_dspa_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dspb_a_sel =3D { +static struct clk_regmap a1_dspb_a_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D DSPB_CLK_CTRL0, .mask =3D 0x7, .shift =3D 10, - .table =3D mux_table_dsp_ab, + .table =3D a1_dsp_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "dspb_a_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D dsp_ab_parent_data, - .num_parents =3D ARRAY_SIZE(dsp_ab_parent_data), + .parent_data =3D a1_dsp_parents, + .num_parents =3D ARRAY_SIZE(a1_dsp_parents), }, }; =20 -static struct clk_regmap dspb_a_div =3D { +static struct clk_regmap a1_dspb_a_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D DSPB_CLK_CTRL0, .shift =3D 0, @@ -579,14 +579,14 @@ static struct clk_regmap dspb_a_div =3D { .name =3D "dspb_a_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspb_a_sel.hw + &a1_dspb_a_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dspb_a =3D { +static struct clk_regmap a1_dspb_a =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D DSPB_CLK_CTRL0, .bit_idx =3D 13, @@ -595,29 +595,29 @@ static struct clk_regmap dspb_a =3D { .name =3D "dspb_a", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspb_a_div.hw + &a1_dspb_a_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dspb_b_sel =3D { +static struct clk_regmap a1_dspb_b_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D DSPB_CLK_CTRL0, .mask =3D 0x7, .shift =3D 26, - .table =3D mux_table_dsp_ab, + .table =3D a1_dsp_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "dspb_b_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D dsp_ab_parent_data, - .num_parents =3D ARRAY_SIZE(dsp_ab_parent_data), + .parent_data =3D a1_dsp_parents, + .num_parents =3D ARRAY_SIZE(a1_dsp_parents), }, }; =20 -static struct clk_regmap dspb_b_div =3D { +static struct clk_regmap a1_dspb_b_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D DSPB_CLK_CTRL0, .shift =3D 16, @@ -627,14 +627,14 @@ static struct clk_regmap dspb_b_div =3D { .name =3D "dspb_b_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspb_b_sel.hw + &a1_dspb_b_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dspb_b =3D { +static struct clk_regmap a1_dspb_b =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D DSPB_CLK_CTRL0, .bit_idx =3D 29, @@ -643,14 +643,14 @@ static struct clk_regmap dspb_b =3D { .name =3D "dspb_b", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspb_b_div.hw + &a1_dspb_b_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dspb_sel =3D { +static struct clk_regmap a1_dspb_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D DSPB_CLK_CTRL0, .mask =3D 0x1, @@ -660,15 +660,15 @@ static struct clk_regmap dspb_sel =3D { .name =3D "dspb_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspb_a.hw, - &dspb_b.hw, + &a1_dspb_a.hw, + &a1_dspb_b.hw, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dspb_en =3D { +static struct clk_regmap a1_dspb_en =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D DSPB_CLK_EN, .bit_idx =3D 1, @@ -677,14 +677,14 @@ static struct clk_regmap dspb_en =3D { .name =3D "dspb_en", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspb_sel.hw + &a1_dspb_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dspb_en_nic =3D { +static struct clk_regmap a1_dspb_en_nic =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D DSPB_CLK_EN, .bit_idx =3D 0, @@ -693,14 +693,14 @@ static struct clk_regmap dspb_en_nic =3D { .name =3D "dspb_en_nic", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dspb_sel.hw + &a1_dspb_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap clk_24m =3D { +static struct clk_regmap a1_24m =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLK12_24_CTRL, .bit_idx =3D 11, @@ -715,20 +715,20 @@ static struct clk_regmap clk_24m =3D { }, }; =20 -static struct clk_fixed_factor clk_24m_div2 =3D { +static struct clk_fixed_factor a1_24m_div2 =3D { .mult =3D 1, .div =3D 2, .hw.init =3D &(struct clk_init_data){ .name =3D "24m_div2", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &clk_24m.hw + &a1_24m.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap clk_12m =3D { +static struct clk_regmap a1_12m =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLK12_24_CTRL, .bit_idx =3D 10, @@ -737,13 +737,13 @@ static struct clk_regmap clk_12m =3D { .name =3D "12m", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &clk_24m_div2.hw + &a1_24m_div2.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap fclk_div2_divn_pre =3D { +static struct clk_regmap a1_fclk_div2_divn_pre =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D CLK12_24_CTRL, .shift =3D 0, @@ -759,7 +759,7 @@ static struct clk_regmap fclk_div2_divn_pre =3D { }, }; =20 -static struct clk_regmap fclk_div2_divn =3D { +static struct clk_regmap a1_fclk_div2_divn =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLK12_24_CTRL, .bit_idx =3D 12, @@ -768,7 +768,7 @@ static struct clk_regmap fclk_div2_divn =3D { .name =3D "fclk_div2_divn", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fclk_div2_divn_pre.hw + &a1_fclk_div2_divn_pre.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -779,10 +779,10 @@ static struct clk_regmap fclk_div2_divn =3D { * the index 2 is sys_pll_div16, it will be implemented in the CPU clock d= river, * the index 4 is the clock measurement source, it's not supported yet */ -static u32 gen_table[] =3D { 0, 1, 3, 5, 6, 7, 8 }; -static const struct clk_parent_data gen_parent_data[] =3D { +static u32 a1_gen_parents_val_table[] =3D { 0, 1, 3, 5, 6, 7, 8 }; +static const struct clk_parent_data a1_gen_parents[] =3D { { .fw_name =3D "xtal", }, - { .hw =3D &rtc.hw }, + { .hw =3D &a1_rtc.hw }, { .fw_name =3D "hifi_pll", }, { .fw_name =3D "fclk_div2", }, { .fw_name =3D "fclk_div3", }, @@ -790,18 +790,18 @@ static const struct clk_parent_data gen_parent_data[]= =3D { { .fw_name =3D "fclk_div7", }, }; =20 -static struct clk_regmap gen_sel =3D { +static struct clk_regmap a1_gen_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D GEN_CLK_CTRL, .mask =3D 0xf, .shift =3D 12, - .table =3D gen_table, + .table =3D a1_gen_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "gen_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D gen_parent_data, - .num_parents =3D ARRAY_SIZE(gen_parent_data), + .parent_data =3D a1_gen_parents, + .num_parents =3D ARRAY_SIZE(a1_gen_parents), /* * The GEN clock can be connected to an external pad, so it * may be set up directly from the device tree. Additionally, @@ -813,7 +813,7 @@ static struct clk_regmap gen_sel =3D { }, }; =20 -static struct clk_regmap gen_div =3D { +static struct clk_regmap a1_gen_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D GEN_CLK_CTRL, .shift =3D 0, @@ -823,14 +823,14 @@ static struct clk_regmap gen_div =3D { .name =3D "gen_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &gen_sel.hw + &a1_gen_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap gen =3D { +static struct clk_regmap a1_gen =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D GEN_CLK_CTRL, .bit_idx =3D 11, @@ -839,14 +839,14 @@ static struct clk_regmap gen =3D { .name =3D "gen", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &gen_div.hw + &a1_gen_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap saradc_sel =3D { +static struct clk_regmap a1_saradc_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D SAR_ADC_CLK_CTRL, .mask =3D 0x1, @@ -857,13 +857,13 @@ static struct clk_regmap saradc_sel =3D { .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "xtal", }, - { .hw =3D &sys.hw, }, + { .hw =3D &a1_sys.hw, }, }, .num_parents =3D 2, }, }; =20 -static struct clk_regmap saradc_div =3D { +static struct clk_regmap a1_saradc_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D SAR_ADC_CLK_CTRL, .shift =3D 0, @@ -873,14 +873,14 @@ static struct clk_regmap saradc_div =3D { .name =3D "saradc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &saradc_sel.hw + &a1_saradc_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap saradc =3D { +static struct clk_regmap a1_saradc =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D SAR_ADC_CLK_CTRL, .bit_idx =3D 8, @@ -889,20 +889,20 @@ static struct clk_regmap saradc =3D { .name =3D "saradc", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &saradc_div.hw + &a1_saradc_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data pwm_abcd_parents[] =3D { +static const struct clk_parent_data a1_pwm_abcd_parents[] =3D { { .fw_name =3D "xtal", }, - { .hw =3D &sys.hw }, - { .hw =3D &rtc.hw }, + { .hw =3D &a1_sys.hw }, + { .hw =3D &a1_rtc.hw }, }; =20 -static struct clk_regmap pwm_a_sel =3D { +static struct clk_regmap a1_pwm_a_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D PWM_CLK_AB_CTRL, .mask =3D 0x1, @@ -911,12 +911,12 @@ static struct clk_regmap pwm_a_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "pwm_a_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D pwm_abcd_parents, - .num_parents =3D ARRAY_SIZE(pwm_abcd_parents), + .parent_data =3D a1_pwm_abcd_parents, + .num_parents =3D ARRAY_SIZE(a1_pwm_abcd_parents), }, }; =20 -static struct clk_regmap pwm_a_div =3D { +static struct clk_regmap a1_pwm_a_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D PWM_CLK_AB_CTRL, .shift =3D 0, @@ -926,14 +926,14 @@ static struct clk_regmap pwm_a_div =3D { .name =3D "pwm_a_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &pwm_a_sel.hw + &a1_pwm_a_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap pwm_a =3D { +static struct clk_regmap a1_pwm_a =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D PWM_CLK_AB_CTRL, .bit_idx =3D 8, @@ -942,14 +942,14 @@ static struct clk_regmap pwm_a =3D { .name =3D "pwm_a", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &pwm_a_div.hw + &a1_pwm_a_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap pwm_b_sel =3D { +static struct clk_regmap a1_pwm_b_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D PWM_CLK_AB_CTRL, .mask =3D 0x1, @@ -958,12 +958,12 @@ static struct clk_regmap pwm_b_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "pwm_b_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D pwm_abcd_parents, - .num_parents =3D ARRAY_SIZE(pwm_abcd_parents), + .parent_data =3D a1_pwm_abcd_parents, + .num_parents =3D ARRAY_SIZE(a1_pwm_abcd_parents), }, }; =20 -static struct clk_regmap pwm_b_div =3D { +static struct clk_regmap a1_pwm_b_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D PWM_CLK_AB_CTRL, .shift =3D 16, @@ -973,14 +973,14 @@ static struct clk_regmap pwm_b_div =3D { .name =3D "pwm_b_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &pwm_b_sel.hw + &a1_pwm_b_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap pwm_b =3D { +static struct clk_regmap a1_pwm_b =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D PWM_CLK_AB_CTRL, .bit_idx =3D 24, @@ -989,14 +989,14 @@ static struct clk_regmap pwm_b =3D { .name =3D "pwm_b", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &pwm_b_div.hw + &a1_pwm_b_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap pwm_c_sel =3D { +static struct clk_regmap a1_pwm_c_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D PWM_CLK_CD_CTRL, .mask =3D 0x1, @@ -1005,12 +1005,12 @@ static struct clk_regmap pwm_c_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "pwm_c_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D pwm_abcd_parents, - .num_parents =3D ARRAY_SIZE(pwm_abcd_parents), + .parent_data =3D a1_pwm_abcd_parents, + .num_parents =3D ARRAY_SIZE(a1_pwm_abcd_parents), }, }; =20 -static struct clk_regmap pwm_c_div =3D { +static struct clk_regmap a1_pwm_c_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D PWM_CLK_CD_CTRL, .shift =3D 0, @@ -1020,14 +1020,14 @@ static struct clk_regmap pwm_c_div =3D { .name =3D "pwm_c_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &pwm_c_sel.hw + &a1_pwm_c_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap pwm_c =3D { +static struct clk_regmap a1_pwm_c =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D PWM_CLK_CD_CTRL, .bit_idx =3D 8, @@ -1036,14 +1036,14 @@ static struct clk_regmap pwm_c =3D { .name =3D "pwm_c", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &pwm_c_div.hw + &a1_pwm_c_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap pwm_d_sel =3D { +static struct clk_regmap a1_pwm_d_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D PWM_CLK_CD_CTRL, .mask =3D 0x1, @@ -1052,12 +1052,12 @@ static struct clk_regmap pwm_d_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "pwm_d_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D pwm_abcd_parents, - .num_parents =3D ARRAY_SIZE(pwm_abcd_parents), + .parent_data =3D a1_pwm_abcd_parents, + .num_parents =3D ARRAY_SIZE(a1_pwm_abcd_parents), }, }; =20 -static struct clk_regmap pwm_d_div =3D { +static struct clk_regmap a1_pwm_d_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D PWM_CLK_CD_CTRL, .shift =3D 16, @@ -1067,14 +1067,14 @@ static struct clk_regmap pwm_d_div =3D { .name =3D "pwm_d_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &pwm_d_sel.hw + &a1_pwm_d_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap pwm_d =3D { +static struct clk_regmap a1_pwm_d =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D PWM_CLK_CD_CTRL, .bit_idx =3D 24, @@ -1083,21 +1083,21 @@ static struct clk_regmap pwm_d =3D { .name =3D "pwm_d", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &pwm_d_div.hw + &a1_pwm_d_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data pwm_ef_parents[] =3D { +static const struct clk_parent_data a1_pwm_ef_parents[] =3D { { .fw_name =3D "xtal", }, - { .hw =3D &sys.hw }, + { .hw =3D &a1_sys.hw }, { .fw_name =3D "fclk_div5", }, - { .hw =3D &rtc.hw }, + { .hw =3D &a1_rtc.hw }, }; =20 -static struct clk_regmap pwm_e_sel =3D { +static struct clk_regmap a1_pwm_e_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D PWM_CLK_EF_CTRL, .mask =3D 0x3, @@ -1106,12 +1106,12 @@ static struct clk_regmap pwm_e_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "pwm_e_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D pwm_ef_parents, - .num_parents =3D ARRAY_SIZE(pwm_ef_parents), + .parent_data =3D a1_pwm_ef_parents, + .num_parents =3D ARRAY_SIZE(a1_pwm_ef_parents), }, }; =20 -static struct clk_regmap pwm_e_div =3D { +static struct clk_regmap a1_pwm_e_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D PWM_CLK_EF_CTRL, .shift =3D 0, @@ -1121,14 +1121,14 @@ static struct clk_regmap pwm_e_div =3D { .name =3D "pwm_e_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &pwm_e_sel.hw + &a1_pwm_e_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap pwm_e =3D { +static struct clk_regmap a1_pwm_e =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D PWM_CLK_EF_CTRL, .bit_idx =3D 8, @@ -1137,14 +1137,14 @@ static struct clk_regmap pwm_e =3D { .name =3D "pwm_e", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &pwm_e_div.hw + &a1_pwm_e_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap pwm_f_sel =3D { +static struct clk_regmap a1_pwm_f_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D PWM_CLK_EF_CTRL, .mask =3D 0x3, @@ -1153,12 +1153,12 @@ static struct clk_regmap pwm_f_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "pwm_f_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D pwm_ef_parents, - .num_parents =3D ARRAY_SIZE(pwm_ef_parents), + .parent_data =3D a1_pwm_ef_parents, + .num_parents =3D ARRAY_SIZE(a1_pwm_ef_parents), }, }; =20 -static struct clk_regmap pwm_f_div =3D { +static struct clk_regmap a1_pwm_f_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D PWM_CLK_EF_CTRL, .shift =3D 16, @@ -1168,14 +1168,14 @@ static struct clk_regmap pwm_f_div =3D { .name =3D "pwm_f_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &pwm_f_sel.hw + &a1_pwm_f_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap pwm_f =3D { +static struct clk_regmap a1_pwm_f =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D PWM_CLK_EF_CTRL, .bit_idx =3D 24, @@ -1184,7 +1184,7 @@ static struct clk_regmap pwm_f =3D { .name =3D "pwm_f", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &pwm_f_div.hw + &a1_pwm_f_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1200,14 +1200,14 @@ static struct clk_regmap pwm_f =3D { * --------------------|/ * 24M */ -static const struct clk_parent_data spicc_spifc_parents[] =3D { +static const struct clk_parent_data a1_spi_parents[] =3D { { .fw_name =3D "fclk_div2"}, { .fw_name =3D "fclk_div3"}, { .fw_name =3D "fclk_div5"}, { .fw_name =3D "hifi_pll" }, }; =20 -static struct clk_regmap spicc_sel =3D { +static struct clk_regmap a1_spicc_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D SPICC_CLK_CTRL, .mask =3D 0x3, @@ -1216,12 +1216,12 @@ static struct clk_regmap spicc_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "spicc_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D spicc_spifc_parents, - .num_parents =3D ARRAY_SIZE(spicc_spifc_parents), + .parent_data =3D a1_spi_parents, + .num_parents =3D ARRAY_SIZE(a1_spi_parents), }, }; =20 -static struct clk_regmap spicc_div =3D { +static struct clk_regmap a1_spicc_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D SPICC_CLK_CTRL, .shift =3D 0, @@ -1231,14 +1231,14 @@ static struct clk_regmap spicc_div =3D { .name =3D "spicc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &spicc_sel.hw + &a1_spicc_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap spicc_sel2 =3D { +static struct clk_regmap a1_spicc_sel2 =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D SPICC_CLK_CTRL, .mask =3D 0x1, @@ -1248,7 +1248,7 @@ static struct clk_regmap spicc_sel2 =3D { .name =3D "spicc_sel2", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { - { .hw =3D &spicc_div.hw }, + { .hw =3D &a1_spicc_div.hw }, { .fw_name =3D "xtal", }, }, .num_parents =3D 2, @@ -1256,7 +1256,7 @@ static struct clk_regmap spicc_sel2 =3D { }, }; =20 -static struct clk_regmap spicc =3D { +static struct clk_regmap a1_spicc =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D SPICC_CLK_CTRL, .bit_idx =3D 8, @@ -1265,14 +1265,14 @@ static struct clk_regmap spicc =3D { .name =3D "spicc", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &spicc_sel2.hw + &a1_spicc_sel2.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap ts_div =3D { +static struct clk_regmap a1_ts_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D TS_CLK_CTRL, .shift =3D 0, @@ -1288,7 +1288,7 @@ static struct clk_regmap ts_div =3D { }, }; =20 -static struct clk_regmap ts =3D { +static struct clk_regmap a1_ts =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D TS_CLK_CTRL, .bit_idx =3D 8, @@ -1297,14 +1297,14 @@ static struct clk_regmap ts =3D { .name =3D "ts", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &ts_div.hw + &a1_ts_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap spifc_sel =3D { +static struct clk_regmap a1_spifc_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D SPIFC_CLK_CTRL, .mask =3D 0x3, @@ -1313,12 +1313,12 @@ static struct clk_regmap spifc_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "spifc_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D spicc_spifc_parents, - .num_parents =3D ARRAY_SIZE(spicc_spifc_parents), + .parent_data =3D a1_spi_parents, + .num_parents =3D ARRAY_SIZE(a1_spi_parents), }, }; =20 -static struct clk_regmap spifc_div =3D { +static struct clk_regmap a1_spifc_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D SPIFC_CLK_CTRL, .shift =3D 0, @@ -1328,14 +1328,14 @@ static struct clk_regmap spifc_div =3D { .name =3D "spifc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &spifc_sel.hw + &a1_spifc_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap spifc_sel2 =3D { +static struct clk_regmap a1_spifc_sel2 =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D SPIFC_CLK_CTRL, .mask =3D 0x1, @@ -1345,7 +1345,7 @@ static struct clk_regmap spifc_sel2 =3D { .name =3D "spifc_sel2", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { - { .hw =3D &spifc_div.hw }, + { .hw =3D &a1_spifc_div.hw }, { .fw_name =3D "xtal", }, }, .num_parents =3D 2, @@ -1353,7 +1353,7 @@ static struct clk_regmap spifc_sel2 =3D { }, }; =20 -static struct clk_regmap spifc =3D { +static struct clk_regmap a1_spifc =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D SPIFC_CLK_CTRL, .bit_idx =3D 8, @@ -1362,21 +1362,21 @@ static struct clk_regmap spifc =3D { .name =3D "spifc", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &spifc_sel2.hw + &a1_spifc_sel2.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data usb_bus_parents[] =3D { +static const struct clk_parent_data a1_usb_bus_parents[] =3D { { .fw_name =3D "xtal", }, - { .hw =3D &sys.hw }, + { .hw =3D &a1_sys.hw }, { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div5", }, }; =20 -static struct clk_regmap usb_bus_sel =3D { +static struct clk_regmap a1_usb_bus_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D USB_BUSCLK_CTRL, .mask =3D 0x3, @@ -1385,13 +1385,13 @@ static struct clk_regmap usb_bus_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "usb_bus_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D usb_bus_parents, - .num_parents =3D ARRAY_SIZE(usb_bus_parents), + .parent_data =3D a1_usb_bus_parents, + .num_parents =3D ARRAY_SIZE(a1_usb_bus_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap usb_bus_div =3D { +static struct clk_regmap a1_usb_bus_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D USB_BUSCLK_CTRL, .shift =3D 0, @@ -1401,14 +1401,14 @@ static struct clk_regmap usb_bus_div =3D { .name =3D "usb_bus_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &usb_bus_sel.hw + &a1_usb_bus_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap usb_bus =3D { +static struct clk_regmap a1_usb_bus =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D USB_BUSCLK_CTRL, .bit_idx =3D 8, @@ -1417,21 +1417,21 @@ static struct clk_regmap usb_bus =3D { .name =3D "usb_bus", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &usb_bus_div.hw + &a1_usb_bus_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data sd_emmc_psram_dmc_parents[] =3D { +static const struct clk_parent_data a1_sd_emmc_parents[] =3D { { .fw_name =3D "fclk_div2", }, { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div5", }, { .fw_name =3D "hifi_pll", }, }; =20 -static struct clk_regmap sd_emmc_sel =3D { +static struct clk_regmap a1_sd_emmc_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D SD_EMMC_CLK_CTRL, .mask =3D 0x3, @@ -1440,12 +1440,12 @@ static struct clk_regmap sd_emmc_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "sd_emmc_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D sd_emmc_psram_dmc_parents, - .num_parents =3D ARRAY_SIZE(sd_emmc_psram_dmc_parents), + .parent_data =3D a1_sd_emmc_parents, + .num_parents =3D ARRAY_SIZE(a1_sd_emmc_parents), }, }; =20 -static struct clk_regmap sd_emmc_div =3D { +static struct clk_regmap a1_sd_emmc_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D SD_EMMC_CLK_CTRL, .shift =3D 0, @@ -1455,14 +1455,14 @@ static struct clk_regmap sd_emmc_div =3D { .name =3D "sd_emmc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sd_emmc_sel.hw + &a1_sd_emmc_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap sd_emmc_sel2 =3D { +static struct clk_regmap a1_sd_emmc_sel2 =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D SD_EMMC_CLK_CTRL, .mask =3D 0x1, @@ -1472,7 +1472,7 @@ static struct clk_regmap sd_emmc_sel2 =3D { .name =3D "sd_emmc_sel2", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { - { .hw =3D &sd_emmc_div.hw }, + { .hw =3D &a1_sd_emmc_div.hw }, { .fw_name =3D "xtal", }, }, .num_parents =3D 2, @@ -1480,7 +1480,7 @@ static struct clk_regmap sd_emmc_sel2 =3D { }, }; =20 -static struct clk_regmap sd_emmc =3D { +static struct clk_regmap a1_sd_emmc =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D SD_EMMC_CLK_CTRL, .bit_idx =3D 8, @@ -1489,14 +1489,14 @@ static struct clk_regmap sd_emmc =3D { .name =3D "sd_emmc", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sd_emmc_sel2.hw + &a1_sd_emmc_sel2.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap psram_sel =3D { +static struct clk_regmap a1_psram_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D PSRAM_CLK_CTRL, .mask =3D 0x3, @@ -1505,12 +1505,12 @@ static struct clk_regmap psram_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "psram_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D sd_emmc_psram_dmc_parents, - .num_parents =3D ARRAY_SIZE(sd_emmc_psram_dmc_parents), + .parent_data =3D a1_sd_emmc_parents, + .num_parents =3D ARRAY_SIZE(a1_sd_emmc_parents), }, }; =20 -static struct clk_regmap psram_div =3D { +static struct clk_regmap a1_psram_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D PSRAM_CLK_CTRL, .shift =3D 0, @@ -1520,14 +1520,14 @@ static struct clk_regmap psram_div =3D { .name =3D "psram_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &psram_sel.hw + &a1_psram_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap psram_sel2 =3D { +static struct clk_regmap a1_psram_sel2 =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D PSRAM_CLK_CTRL, .mask =3D 0x1, @@ -1537,7 +1537,7 @@ static struct clk_regmap psram_sel2 =3D { .name =3D "psram_sel2", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { - { .hw =3D &psram_div.hw }, + { .hw =3D &a1_psram_div.hw }, { .fw_name =3D "xtal", }, }, .num_parents =3D 2, @@ -1545,7 +1545,7 @@ static struct clk_regmap psram_sel2 =3D { }, }; =20 -static struct clk_regmap psram =3D { +static struct clk_regmap a1_psram =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D PSRAM_CLK_CTRL, .bit_idx =3D 8, @@ -1554,14 +1554,14 @@ static struct clk_regmap psram =3D { .name =3D "psram", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &psram_sel2.hw + &a1_psram_sel2.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dmc_sel =3D { +static struct clk_regmap a1_dmc_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D DMC_CLK_CTRL, .mask =3D 0x3, @@ -1570,12 +1570,12 @@ static struct clk_regmap dmc_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "dmc_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D sd_emmc_psram_dmc_parents, - .num_parents =3D ARRAY_SIZE(sd_emmc_psram_dmc_parents), + .parent_data =3D a1_sd_emmc_parents, + .num_parents =3D ARRAY_SIZE(a1_sd_emmc_parents), }, }; =20 -static struct clk_regmap dmc_div =3D { +static struct clk_regmap a1_dmc_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D DMC_CLK_CTRL, .shift =3D 0, @@ -1585,14 +1585,14 @@ static struct clk_regmap dmc_div =3D { .name =3D "dmc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dmc_sel.hw + &a1_dmc_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dmc_sel2 =3D { +static struct clk_regmap a1_dmc_sel2 =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D DMC_CLK_CTRL, .mask =3D 0x1, @@ -1602,7 +1602,7 @@ static struct clk_regmap dmc_sel2 =3D { .name =3D "dmc_sel2", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { - { .hw =3D &dmc_div.hw }, + { .hw =3D &a1_dmc_div.hw }, { .fw_name =3D "xtal", }, }, .num_parents =3D 2, @@ -1610,7 +1610,7 @@ static struct clk_regmap dmc_sel2 =3D { }, }; =20 -static struct clk_regmap dmc =3D { +static struct clk_regmap a1_dmc =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D DMC_CLK_CTRL, .bit_idx =3D 8, @@ -1619,14 +1619,14 @@ static struct clk_regmap dmc =3D { .name =3D "dmc", .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dmc_sel2.hw + &a1_dmc_sel2.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap ceca_32k_in =3D { +static struct clk_regmap a1_ceca_32k_in =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CECA_CLK_CTRL0, .bit_idx =3D 31, @@ -1641,7 +1641,7 @@ static struct clk_regmap ceca_32k_in =3D { }, }; =20 -static struct clk_regmap ceca_32k_div =3D { +static struct clk_regmap a1_ceca_32k_div =3D { .data =3D &(struct meson_clk_dualdiv_data){ .n1 =3D { .reg_off =3D CECA_CLK_CTRL0, @@ -1668,19 +1668,19 @@ static struct clk_regmap ceca_32k_div =3D { .shift =3D 28, .width =3D 1, }, - .table =3D clk_32k_div_table, + .table =3D a1_32k_div_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "ceca_32k_div", .ops =3D &meson_clk_dualdiv_ops, .parent_hws =3D (const struct clk_hw *[]) { - &ceca_32k_in.hw + &a1_ceca_32k_in.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap ceca_32k_sel_pre =3D { +static struct clk_regmap a1_ceca_32k_sel_pre =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CECA_CLK_CTRL1, .mask =3D 0x1, @@ -1691,15 +1691,15 @@ static struct clk_regmap ceca_32k_sel_pre =3D { .name =3D "ceca_32k_sel_pre", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &ceca_32k_div.hw, - &ceca_32k_in.hw, + &a1_ceca_32k_div.hw, + &a1_ceca_32k_in.hw, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap ceca_32k_sel =3D { +static struct clk_regmap a1_ceca_32k_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CECA_CLK_CTRL1, .mask =3D 0x1, @@ -1710,14 +1710,14 @@ static struct clk_regmap ceca_32k_sel =3D { .name =3D "ceca_32k_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &ceca_32k_sel_pre.hw, - &rtc.hw, + &a1_ceca_32k_sel_pre.hw, + &a1_rtc.hw, }, .num_parents =3D 2, }, }; =20 -static struct clk_regmap ceca_32k_out =3D { +static struct clk_regmap a1_ceca_32k_out =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CECA_CLK_CTRL0, .bit_idx =3D 30, @@ -1726,14 +1726,14 @@ static struct clk_regmap ceca_32k_out =3D { .name =3D "ceca_32k_out", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &ceca_32k_sel.hw + &a1_ceca_32k_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap cecb_32k_in =3D { +static struct clk_regmap a1_cecb_32k_in =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CECB_CLK_CTRL0, .bit_idx =3D 31, @@ -1748,7 +1748,7 @@ static struct clk_regmap cecb_32k_in =3D { }, }; =20 -static struct clk_regmap cecb_32k_div =3D { +static struct clk_regmap a1_cecb_32k_div =3D { .data =3D &(struct meson_clk_dualdiv_data){ .n1 =3D { .reg_off =3D CECB_CLK_CTRL0, @@ -1775,19 +1775,19 @@ static struct clk_regmap cecb_32k_div =3D { .shift =3D 28, .width =3D 1, }, - .table =3D clk_32k_div_table, + .table =3D a1_32k_div_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cecb_32k_div", .ops =3D &meson_clk_dualdiv_ops, .parent_hws =3D (const struct clk_hw *[]) { - &cecb_32k_in.hw + &a1_cecb_32k_in.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap cecb_32k_sel_pre =3D { +static struct clk_regmap a1_cecb_32k_sel_pre =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CECB_CLK_CTRL1, .mask =3D 0x1, @@ -1798,15 +1798,15 @@ static struct clk_regmap cecb_32k_sel_pre =3D { .name =3D "cecb_32k_sel_pre", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &cecb_32k_div.hw, - &cecb_32k_in.hw, + &a1_cecb_32k_div.hw, + &a1_cecb_32k_in.hw, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap cecb_32k_sel =3D { +static struct clk_regmap a1_cecb_32k_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CECB_CLK_CTRL1, .mask =3D 0x1, @@ -1817,14 +1817,14 @@ static struct clk_regmap cecb_32k_sel =3D { .name =3D "cecb_32k_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &cecb_32k_sel_pre.hw, - &rtc.hw, + &a1_cecb_32k_sel_pre.hw, + &a1_rtc.hw, }, .num_parents =3D 2, }, }; =20 -static struct clk_regmap cecb_32k_out =3D { +static struct clk_regmap a1_cecb_32k_out =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CECB_CLK_CTRL0, .bit_idx =3D 30, @@ -1833,241 +1833,243 @@ static struct clk_regmap cecb_32k_out =3D { .name =3D "cecb_32k_out", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &cecb_32k_sel.hw + &a1_cecb_32k_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -#define MESON_GATE(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &sys.hw) - -static MESON_GATE(clktree, SYS_CLK_EN0, 0); -static MESON_GATE(reset_ctrl, SYS_CLK_EN0, 1); -static MESON_GATE(analog_ctrl, SYS_CLK_EN0, 2); -static MESON_GATE(pwr_ctrl, SYS_CLK_EN0, 3); -static MESON_GATE(pad_ctrl, SYS_CLK_EN0, 4); -static MESON_GATE(sys_ctrl, SYS_CLK_EN0, 5); -static MESON_GATE(temp_sensor, SYS_CLK_EN0, 6); -static MESON_GATE(am2axi_dev, SYS_CLK_EN0, 7); -static MESON_GATE(spicc_b, SYS_CLK_EN0, 8); -static MESON_GATE(spicc_a, SYS_CLK_EN0, 9); -static MESON_GATE(msr, SYS_CLK_EN0, 10); -static MESON_GATE(audio, SYS_CLK_EN0, 11); -static MESON_GATE(jtag_ctrl, SYS_CLK_EN0, 12); -static MESON_GATE(saradc_en, SYS_CLK_EN0, 13); -static MESON_GATE(pwm_ef, SYS_CLK_EN0, 14); -static MESON_GATE(pwm_cd, SYS_CLK_EN0, 15); -static MESON_GATE(pwm_ab, SYS_CLK_EN0, 16); -static MESON_GATE(cec, SYS_CLK_EN0, 17); -static MESON_GATE(i2c_s, SYS_CLK_EN0, 18); -static MESON_GATE(ir_ctrl, SYS_CLK_EN0, 19); -static MESON_GATE(i2c_m_d, SYS_CLK_EN0, 20); -static MESON_GATE(i2c_m_c, SYS_CLK_EN0, 21); -static MESON_GATE(i2c_m_b, SYS_CLK_EN0, 22); -static MESON_GATE(i2c_m_a, SYS_CLK_EN0, 23); -static MESON_GATE(acodec, SYS_CLK_EN0, 24); -static MESON_GATE(otp, SYS_CLK_EN0, 25); -static MESON_GATE(sd_emmc_a, SYS_CLK_EN0, 26); -static MESON_GATE(usb_phy, SYS_CLK_EN0, 27); -static MESON_GATE(usb_ctrl, SYS_CLK_EN0, 28); -static MESON_GATE(sys_dspb, SYS_CLK_EN0, 29); -static MESON_GATE(sys_dspa, SYS_CLK_EN0, 30); -static MESON_GATE(dma, SYS_CLK_EN0, 31); -static MESON_GATE(irq_ctrl, SYS_CLK_EN1, 0); -static MESON_GATE(nic, SYS_CLK_EN1, 1); -static MESON_GATE(gic, SYS_CLK_EN1, 2); -static MESON_GATE(uart_c, SYS_CLK_EN1, 3); -static MESON_GATE(uart_b, SYS_CLK_EN1, 4); -static MESON_GATE(uart_a, SYS_CLK_EN1, 5); -static MESON_GATE(sys_psram, SYS_CLK_EN1, 6); -static MESON_GATE(rsa, SYS_CLK_EN1, 8); -static MESON_GATE(coresight, SYS_CLK_EN1, 9); -static MESON_GATE(am2axi_vad, AXI_CLK_EN, 0); -static MESON_GATE(audio_vad, AXI_CLK_EN, 1); -static MESON_GATE(axi_dmc, AXI_CLK_EN, 3); -static MESON_GATE(axi_psram, AXI_CLK_EN, 4); -static MESON_GATE(ramb, AXI_CLK_EN, 5); -static MESON_GATE(rama, AXI_CLK_EN, 6); -static MESON_GATE(axi_spifc, AXI_CLK_EN, 7); -static MESON_GATE(axi_nic, AXI_CLK_EN, 8); -static MESON_GATE(axi_dma, AXI_CLK_EN, 9); -static MESON_GATE(cpu_ctrl, AXI_CLK_EN, 10); -static MESON_GATE(rom, AXI_CLK_EN, 11); -static MESON_GATE(prod_i2c, AXI_CLK_EN, 12); +#define A1_PCLK(_name, _reg, _bit) \ + MESON_PCLK(a1_##_name, _reg, _bit, &a1_sys.hw) + +static A1_PCLK(clktree, SYS_CLK_EN0, 0); +static A1_PCLK(reset_ctrl, SYS_CLK_EN0, 1); +static A1_PCLK(analog_ctrl, SYS_CLK_EN0, 2); +static A1_PCLK(pwr_ctrl, SYS_CLK_EN0, 3); +static A1_PCLK(pad_ctrl, SYS_CLK_EN0, 4); +static A1_PCLK(sys_ctrl, SYS_CLK_EN0, 5); +static A1_PCLK(temp_sensor, SYS_CLK_EN0, 6); +static A1_PCLK(am2axi_dev, SYS_CLK_EN0, 7); +static A1_PCLK(spicc_b, SYS_CLK_EN0, 8); +static A1_PCLK(spicc_a, SYS_CLK_EN0, 9); +static A1_PCLK(msr, SYS_CLK_EN0, 10); +static A1_PCLK(audio, SYS_CLK_EN0, 11); +static A1_PCLK(jtag_ctrl, SYS_CLK_EN0, 12); +static A1_PCLK(saradc_en, SYS_CLK_EN0, 13); +static A1_PCLK(pwm_ef, SYS_CLK_EN0, 14); +static A1_PCLK(pwm_cd, SYS_CLK_EN0, 15); +static A1_PCLK(pwm_ab, SYS_CLK_EN0, 16); +static A1_PCLK(cec, SYS_CLK_EN0, 17); +static A1_PCLK(i2c_s, SYS_CLK_EN0, 18); +static A1_PCLK(ir_ctrl, SYS_CLK_EN0, 19); +static A1_PCLK(i2c_m_d, SYS_CLK_EN0, 20); +static A1_PCLK(i2c_m_c, SYS_CLK_EN0, 21); +static A1_PCLK(i2c_m_b, SYS_CLK_EN0, 22); +static A1_PCLK(i2c_m_a, SYS_CLK_EN0, 23); +static A1_PCLK(acodec, SYS_CLK_EN0, 24); +static A1_PCLK(otp, SYS_CLK_EN0, 25); +static A1_PCLK(sd_emmc_a, SYS_CLK_EN0, 26); +static A1_PCLK(usb_phy, SYS_CLK_EN0, 27); +static A1_PCLK(usb_ctrl, SYS_CLK_EN0, 28); +static A1_PCLK(sys_dspb, SYS_CLK_EN0, 29); +static A1_PCLK(sys_dspa, SYS_CLK_EN0, 30); +static A1_PCLK(dma, SYS_CLK_EN0, 31); + +static A1_PCLK(irq_ctrl, SYS_CLK_EN1, 0); +static A1_PCLK(nic, SYS_CLK_EN1, 1); +static A1_PCLK(gic, SYS_CLK_EN1, 2); +static A1_PCLK(uart_c, SYS_CLK_EN1, 3); +static A1_PCLK(uart_b, SYS_CLK_EN1, 4); +static A1_PCLK(uart_a, SYS_CLK_EN1, 5); +static A1_PCLK(sys_psram, SYS_CLK_EN1, 6); +static A1_PCLK(rsa, SYS_CLK_EN1, 8); +static A1_PCLK(coresight, SYS_CLK_EN1, 9); + +static A1_PCLK(am2axi_vad, AXI_CLK_EN, 0); +static A1_PCLK(audio_vad, AXI_CLK_EN, 1); +static A1_PCLK(axi_dmc, AXI_CLK_EN, 3); +static A1_PCLK(axi_psram, AXI_CLK_EN, 4); +static A1_PCLK(ramb, AXI_CLK_EN, 5); +static A1_PCLK(rama, AXI_CLK_EN, 6); +static A1_PCLK(axi_spifc, AXI_CLK_EN, 7); +static A1_PCLK(axi_nic, AXI_CLK_EN, 8); +static A1_PCLK(axi_dma, AXI_CLK_EN, 9); +static A1_PCLK(cpu_ctrl, AXI_CLK_EN, 10); +static A1_PCLK(rom, AXI_CLK_EN, 11); +static A1_PCLK(prod_i2c, AXI_CLK_EN, 12); =20 /* Array of all clocks registered by this provider */ -static struct clk_hw *a1_periphs_hw_clks[] =3D { - [CLKID_XTAL_IN] =3D &xtal_in.hw, - [CLKID_FIXPLL_IN] =3D &fixpll_in.hw, - [CLKID_USB_PHY_IN] =3D &usb_phy_in.hw, - [CLKID_USB_CTRL_IN] =3D &usb_ctrl_in.hw, - [CLKID_HIFIPLL_IN] =3D &hifipll_in.hw, - [CLKID_SYSPLL_IN] =3D &syspll_in.hw, - [CLKID_DDS_IN] =3D &dds_in.hw, - [CLKID_SYS] =3D &sys.hw, - [CLKID_CLKTREE] =3D &clktree.hw, - [CLKID_RESET_CTRL] =3D &reset_ctrl.hw, - [CLKID_ANALOG_CTRL] =3D &analog_ctrl.hw, - [CLKID_PWR_CTRL] =3D &pwr_ctrl.hw, - [CLKID_PAD_CTRL] =3D &pad_ctrl.hw, - [CLKID_SYS_CTRL] =3D &sys_ctrl.hw, - [CLKID_TEMP_SENSOR] =3D &temp_sensor.hw, - [CLKID_AM2AXI_DIV] =3D &am2axi_dev.hw, - [CLKID_SPICC_B] =3D &spicc_b.hw, - [CLKID_SPICC_A] =3D &spicc_a.hw, - [CLKID_MSR] =3D &msr.hw, - [CLKID_AUDIO] =3D &audio.hw, - [CLKID_JTAG_CTRL] =3D &jtag_ctrl.hw, - [CLKID_SARADC_EN] =3D &saradc_en.hw, - [CLKID_PWM_EF] =3D &pwm_ef.hw, - [CLKID_PWM_CD] =3D &pwm_cd.hw, - [CLKID_PWM_AB] =3D &pwm_ab.hw, - [CLKID_CEC] =3D &cec.hw, - [CLKID_I2C_S] =3D &i2c_s.hw, - [CLKID_IR_CTRL] =3D &ir_ctrl.hw, - [CLKID_I2C_M_D] =3D &i2c_m_d.hw, - [CLKID_I2C_M_C] =3D &i2c_m_c.hw, - [CLKID_I2C_M_B] =3D &i2c_m_b.hw, - [CLKID_I2C_M_A] =3D &i2c_m_a.hw, - [CLKID_ACODEC] =3D &acodec.hw, - [CLKID_OTP] =3D &otp.hw, - [CLKID_SD_EMMC_A] =3D &sd_emmc_a.hw, - [CLKID_USB_PHY] =3D &usb_phy.hw, - [CLKID_USB_CTRL] =3D &usb_ctrl.hw, - [CLKID_SYS_DSPB] =3D &sys_dspb.hw, - [CLKID_SYS_DSPA] =3D &sys_dspa.hw, - [CLKID_DMA] =3D &dma.hw, - [CLKID_IRQ_CTRL] =3D &irq_ctrl.hw, - [CLKID_NIC] =3D &nic.hw, - [CLKID_GIC] =3D &gic.hw, - [CLKID_UART_C] =3D &uart_c.hw, - [CLKID_UART_B] =3D &uart_b.hw, - [CLKID_UART_A] =3D &uart_a.hw, - [CLKID_SYS_PSRAM] =3D &sys_psram.hw, - [CLKID_RSA] =3D &rsa.hw, - [CLKID_CORESIGHT] =3D &coresight.hw, - [CLKID_AM2AXI_VAD] =3D &am2axi_vad.hw, - [CLKID_AUDIO_VAD] =3D &audio_vad.hw, - [CLKID_AXI_DMC] =3D &axi_dmc.hw, - [CLKID_AXI_PSRAM] =3D &axi_psram.hw, - [CLKID_RAMB] =3D &ramb.hw, - [CLKID_RAMA] =3D &rama.hw, - [CLKID_AXI_SPIFC] =3D &axi_spifc.hw, - [CLKID_AXI_NIC] =3D &axi_nic.hw, - [CLKID_AXI_DMA] =3D &axi_dma.hw, - [CLKID_CPU_CTRL] =3D &cpu_ctrl.hw, - [CLKID_ROM] =3D &rom.hw, - [CLKID_PROC_I2C] =3D &prod_i2c.hw, - [CLKID_DSPA_SEL] =3D &dspa_sel.hw, - [CLKID_DSPB_SEL] =3D &dspb_sel.hw, - [CLKID_DSPA_EN] =3D &dspa_en.hw, - [CLKID_DSPA_EN_NIC] =3D &dspa_en_nic.hw, - [CLKID_DSPB_EN] =3D &dspb_en.hw, - [CLKID_DSPB_EN_NIC] =3D &dspb_en_nic.hw, - [CLKID_RTC] =3D &rtc.hw, - [CLKID_CECA_32K] =3D &ceca_32k_out.hw, - [CLKID_CECB_32K] =3D &cecb_32k_out.hw, - [CLKID_24M] =3D &clk_24m.hw, - [CLKID_12M] =3D &clk_12m.hw, - [CLKID_FCLK_DIV2_DIVN] =3D &fclk_div2_divn.hw, - [CLKID_GEN] =3D &gen.hw, - [CLKID_SARADC_SEL] =3D &saradc_sel.hw, - [CLKID_SARADC] =3D &saradc.hw, - [CLKID_PWM_A] =3D &pwm_a.hw, - [CLKID_PWM_B] =3D &pwm_b.hw, - [CLKID_PWM_C] =3D &pwm_c.hw, - [CLKID_PWM_D] =3D &pwm_d.hw, - [CLKID_PWM_E] =3D &pwm_e.hw, - [CLKID_PWM_F] =3D &pwm_f.hw, - [CLKID_SPICC] =3D &spicc.hw, - [CLKID_TS] =3D &ts.hw, - [CLKID_SPIFC] =3D &spifc.hw, - [CLKID_USB_BUS] =3D &usb_bus.hw, - [CLKID_SD_EMMC] =3D &sd_emmc.hw, - [CLKID_PSRAM] =3D &psram.hw, - [CLKID_DMC] =3D &dmc.hw, - [CLKID_SYS_A_SEL] =3D &sys_a_sel.hw, - [CLKID_SYS_A_DIV] =3D &sys_a_div.hw, - [CLKID_SYS_A] =3D &sys_a.hw, - [CLKID_SYS_B_SEL] =3D &sys_b_sel.hw, - [CLKID_SYS_B_DIV] =3D &sys_b_div.hw, - [CLKID_SYS_B] =3D &sys_b.hw, - [CLKID_DSPA_A_SEL] =3D &dspa_a_sel.hw, - [CLKID_DSPA_A_DIV] =3D &dspa_a_div.hw, - [CLKID_DSPA_A] =3D &dspa_a.hw, - [CLKID_DSPA_B_SEL] =3D &dspa_b_sel.hw, - [CLKID_DSPA_B_DIV] =3D &dspa_b_div.hw, - [CLKID_DSPA_B] =3D &dspa_b.hw, - [CLKID_DSPB_A_SEL] =3D &dspb_a_sel.hw, - [CLKID_DSPB_A_DIV] =3D &dspb_a_div.hw, - [CLKID_DSPB_A] =3D &dspb_a.hw, - [CLKID_DSPB_B_SEL] =3D &dspb_b_sel.hw, - [CLKID_DSPB_B_DIV] =3D &dspb_b_div.hw, - [CLKID_DSPB_B] =3D &dspb_b.hw, - [CLKID_RTC_32K_IN] =3D &rtc_32k_in.hw, - [CLKID_RTC_32K_DIV] =3D &rtc_32k_div.hw, - [CLKID_RTC_32K_XTAL] =3D &rtc_32k_xtal.hw, - [CLKID_RTC_32K_SEL] =3D &rtc_32k_sel.hw, - [CLKID_CECB_32K_IN] =3D &cecb_32k_in.hw, - [CLKID_CECB_32K_DIV] =3D &cecb_32k_div.hw, - [CLKID_CECB_32K_SEL_PRE] =3D &cecb_32k_sel_pre.hw, - [CLKID_CECB_32K_SEL] =3D &cecb_32k_sel.hw, - [CLKID_CECA_32K_IN] =3D &ceca_32k_in.hw, - [CLKID_CECA_32K_DIV] =3D &ceca_32k_div.hw, - [CLKID_CECA_32K_SEL_PRE] =3D &ceca_32k_sel_pre.hw, - [CLKID_CECA_32K_SEL] =3D &ceca_32k_sel.hw, - [CLKID_DIV2_PRE] =3D &fclk_div2_divn_pre.hw, - [CLKID_24M_DIV2] =3D &clk_24m_div2.hw, - [CLKID_GEN_SEL] =3D &gen_sel.hw, - [CLKID_GEN_DIV] =3D &gen_div.hw, - [CLKID_SARADC_DIV] =3D &saradc_div.hw, - [CLKID_PWM_A_SEL] =3D &pwm_a_sel.hw, - [CLKID_PWM_A_DIV] =3D &pwm_a_div.hw, - [CLKID_PWM_B_SEL] =3D &pwm_b_sel.hw, - [CLKID_PWM_B_DIV] =3D &pwm_b_div.hw, - [CLKID_PWM_C_SEL] =3D &pwm_c_sel.hw, - [CLKID_PWM_C_DIV] =3D &pwm_c_div.hw, - [CLKID_PWM_D_SEL] =3D &pwm_d_sel.hw, - [CLKID_PWM_D_DIV] =3D &pwm_d_div.hw, - [CLKID_PWM_E_SEL] =3D &pwm_e_sel.hw, - [CLKID_PWM_E_DIV] =3D &pwm_e_div.hw, - [CLKID_PWM_F_SEL] =3D &pwm_f_sel.hw, - [CLKID_PWM_F_DIV] =3D &pwm_f_div.hw, - [CLKID_SPICC_SEL] =3D &spicc_sel.hw, - [CLKID_SPICC_DIV] =3D &spicc_div.hw, - [CLKID_SPICC_SEL2] =3D &spicc_sel2.hw, - [CLKID_TS_DIV] =3D &ts_div.hw, - [CLKID_SPIFC_SEL] =3D &spifc_sel.hw, - [CLKID_SPIFC_DIV] =3D &spifc_div.hw, - [CLKID_SPIFC_SEL2] =3D &spifc_sel2.hw, - [CLKID_USB_BUS_SEL] =3D &usb_bus_sel.hw, - [CLKID_USB_BUS_DIV] =3D &usb_bus_div.hw, - [CLKID_SD_EMMC_SEL] =3D &sd_emmc_sel.hw, - [CLKID_SD_EMMC_DIV] =3D &sd_emmc_div.hw, - [CLKID_SD_EMMC_SEL2] =3D &sd_emmc_sel2.hw, - [CLKID_PSRAM_SEL] =3D &psram_sel.hw, - [CLKID_PSRAM_DIV] =3D &psram_div.hw, - [CLKID_PSRAM_SEL2] =3D &psram_sel2.hw, - [CLKID_DMC_SEL] =3D &dmc_sel.hw, - [CLKID_DMC_DIV] =3D &dmc_div.hw, - [CLKID_DMC_SEL2] =3D &dmc_sel2.hw, -}; - -static const struct regmap_config a1_periphs_regmap_cfg =3D { +static struct clk_hw *a1_peripherals_hw_clks[] =3D { + [CLKID_XTAL_IN] =3D &a1_xtal_in.hw, + [CLKID_FIXPLL_IN] =3D &a1_fixpll_in.hw, + [CLKID_USB_PHY_IN] =3D &a1_usb_phy_in.hw, + [CLKID_USB_CTRL_IN] =3D &a1_usb_ctrl_in.hw, + [CLKID_HIFIPLL_IN] =3D &a1_hifipll_in.hw, + [CLKID_SYSPLL_IN] =3D &a1_syspll_in.hw, + [CLKID_DDS_IN] =3D &a1_dds_in.hw, + [CLKID_SYS] =3D &a1_sys.hw, + [CLKID_CLKTREE] =3D &a1_clktree.hw, + [CLKID_RESET_CTRL] =3D &a1_reset_ctrl.hw, + [CLKID_ANALOG_CTRL] =3D &a1_analog_ctrl.hw, + [CLKID_PWR_CTRL] =3D &a1_pwr_ctrl.hw, + [CLKID_PAD_CTRL] =3D &a1_pad_ctrl.hw, + [CLKID_SYS_CTRL] =3D &a1_sys_ctrl.hw, + [CLKID_TEMP_SENSOR] =3D &a1_temp_sensor.hw, + [CLKID_AM2AXI_DIV] =3D &a1_am2axi_dev.hw, + [CLKID_SPICC_B] =3D &a1_spicc_b.hw, + [CLKID_SPICC_A] =3D &a1_spicc_a.hw, + [CLKID_MSR] =3D &a1_msr.hw, + [CLKID_AUDIO] =3D &a1_audio.hw, + [CLKID_JTAG_CTRL] =3D &a1_jtag_ctrl.hw, + [CLKID_SARADC_EN] =3D &a1_saradc_en.hw, + [CLKID_PWM_EF] =3D &a1_pwm_ef.hw, + [CLKID_PWM_CD] =3D &a1_pwm_cd.hw, + [CLKID_PWM_AB] =3D &a1_pwm_ab.hw, + [CLKID_CEC] =3D &a1_cec.hw, + [CLKID_I2C_S] =3D &a1_i2c_s.hw, + [CLKID_IR_CTRL] =3D &a1_ir_ctrl.hw, + [CLKID_I2C_M_D] =3D &a1_i2c_m_d.hw, + [CLKID_I2C_M_C] =3D &a1_i2c_m_c.hw, + [CLKID_I2C_M_B] =3D &a1_i2c_m_b.hw, + [CLKID_I2C_M_A] =3D &a1_i2c_m_a.hw, + [CLKID_ACODEC] =3D &a1_acodec.hw, + [CLKID_OTP] =3D &a1_otp.hw, + [CLKID_SD_EMMC_A] =3D &a1_sd_emmc_a.hw, + [CLKID_USB_PHY] =3D &a1_usb_phy.hw, + [CLKID_USB_CTRL] =3D &a1_usb_ctrl.hw, + [CLKID_SYS_DSPB] =3D &a1_sys_dspb.hw, + [CLKID_SYS_DSPA] =3D &a1_sys_dspa.hw, + [CLKID_DMA] =3D &a1_dma.hw, + [CLKID_IRQ_CTRL] =3D &a1_irq_ctrl.hw, + [CLKID_NIC] =3D &a1_nic.hw, + [CLKID_GIC] =3D &a1_gic.hw, + [CLKID_UART_C] =3D &a1_uart_c.hw, + [CLKID_UART_B] =3D &a1_uart_b.hw, + [CLKID_UART_A] =3D &a1_uart_a.hw, + [CLKID_SYS_PSRAM] =3D &a1_sys_psram.hw, + [CLKID_RSA] =3D &a1_rsa.hw, + [CLKID_CORESIGHT] =3D &a1_coresight.hw, + [CLKID_AM2AXI_VAD] =3D &a1_am2axi_vad.hw, + [CLKID_AUDIO_VAD] =3D &a1_audio_vad.hw, + [CLKID_AXI_DMC] =3D &a1_axi_dmc.hw, + [CLKID_AXI_PSRAM] =3D &a1_axi_psram.hw, + [CLKID_RAMB] =3D &a1_ramb.hw, + [CLKID_RAMA] =3D &a1_rama.hw, + [CLKID_AXI_SPIFC] =3D &a1_axi_spifc.hw, + [CLKID_AXI_NIC] =3D &a1_axi_nic.hw, + [CLKID_AXI_DMA] =3D &a1_axi_dma.hw, + [CLKID_CPU_CTRL] =3D &a1_cpu_ctrl.hw, + [CLKID_ROM] =3D &a1_rom.hw, + [CLKID_PROC_I2C] =3D &a1_prod_i2c.hw, + [CLKID_DSPA_SEL] =3D &a1_dspa_sel.hw, + [CLKID_DSPB_SEL] =3D &a1_dspb_sel.hw, + [CLKID_DSPA_EN] =3D &a1_dspa_en.hw, + [CLKID_DSPA_EN_NIC] =3D &a1_dspa_en_nic.hw, + [CLKID_DSPB_EN] =3D &a1_dspb_en.hw, + [CLKID_DSPB_EN_NIC] =3D &a1_dspb_en_nic.hw, + [CLKID_RTC] =3D &a1_rtc.hw, + [CLKID_CECA_32K] =3D &a1_ceca_32k_out.hw, + [CLKID_CECB_32K] =3D &a1_cecb_32k_out.hw, + [CLKID_24M] =3D &a1_24m.hw, + [CLKID_12M] =3D &a1_12m.hw, + [CLKID_FCLK_DIV2_DIVN] =3D &a1_fclk_div2_divn.hw, + [CLKID_GEN] =3D &a1_gen.hw, + [CLKID_SARADC_SEL] =3D &a1_saradc_sel.hw, + [CLKID_SARADC] =3D &a1_saradc.hw, + [CLKID_PWM_A] =3D &a1_pwm_a.hw, + [CLKID_PWM_B] =3D &a1_pwm_b.hw, + [CLKID_PWM_C] =3D &a1_pwm_c.hw, + [CLKID_PWM_D] =3D &a1_pwm_d.hw, + [CLKID_PWM_E] =3D &a1_pwm_e.hw, + [CLKID_PWM_F] =3D &a1_pwm_f.hw, + [CLKID_SPICC] =3D &a1_spicc.hw, + [CLKID_TS] =3D &a1_ts.hw, + [CLKID_SPIFC] =3D &a1_spifc.hw, + [CLKID_USB_BUS] =3D &a1_usb_bus.hw, + [CLKID_SD_EMMC] =3D &a1_sd_emmc.hw, + [CLKID_PSRAM] =3D &a1_psram.hw, + [CLKID_DMC] =3D &a1_dmc.hw, + [CLKID_SYS_A_SEL] =3D &a1_sys_a_sel.hw, + [CLKID_SYS_A_DIV] =3D &a1_sys_a_div.hw, + [CLKID_SYS_A] =3D &a1_sys_a.hw, + [CLKID_SYS_B_SEL] =3D &a1_sys_b_sel.hw, + [CLKID_SYS_B_DIV] =3D &a1_sys_b_div.hw, + [CLKID_SYS_B] =3D &a1_sys_b.hw, + [CLKID_DSPA_A_SEL] =3D &a1_dspa_a_sel.hw, + [CLKID_DSPA_A_DIV] =3D &a1_dspa_a_div.hw, + [CLKID_DSPA_A] =3D &a1_dspa_a.hw, + [CLKID_DSPA_B_SEL] =3D &a1_dspa_b_sel.hw, + [CLKID_DSPA_B_DIV] =3D &a1_dspa_b_div.hw, + [CLKID_DSPA_B] =3D &a1_dspa_b.hw, + [CLKID_DSPB_A_SEL] =3D &a1_dspb_a_sel.hw, + [CLKID_DSPB_A_DIV] =3D &a1_dspb_a_div.hw, + [CLKID_DSPB_A] =3D &a1_dspb_a.hw, + [CLKID_DSPB_B_SEL] =3D &a1_dspb_b_sel.hw, + [CLKID_DSPB_B_DIV] =3D &a1_dspb_b_div.hw, + [CLKID_DSPB_B] =3D &a1_dspb_b.hw, + [CLKID_RTC_32K_IN] =3D &a1_rtc_32k_in.hw, + [CLKID_RTC_32K_DIV] =3D &a1_rtc_32k_div.hw, + [CLKID_RTC_32K_XTAL] =3D &a1_rtc_32k_xtal.hw, + [CLKID_RTC_32K_SEL] =3D &a1_rtc_32k_sel.hw, + [CLKID_CECB_32K_IN] =3D &a1_cecb_32k_in.hw, + [CLKID_CECB_32K_DIV] =3D &a1_cecb_32k_div.hw, + [CLKID_CECB_32K_SEL_PRE] =3D &a1_cecb_32k_sel_pre.hw, + [CLKID_CECB_32K_SEL] =3D &a1_cecb_32k_sel.hw, + [CLKID_CECA_32K_IN] =3D &a1_ceca_32k_in.hw, + [CLKID_CECA_32K_DIV] =3D &a1_ceca_32k_div.hw, + [CLKID_CECA_32K_SEL_PRE] =3D &a1_ceca_32k_sel_pre.hw, + [CLKID_CECA_32K_SEL] =3D &a1_ceca_32k_sel.hw, + [CLKID_DIV2_PRE] =3D &a1_fclk_div2_divn_pre.hw, + [CLKID_24M_DIV2] =3D &a1_24m_div2.hw, + [CLKID_GEN_SEL] =3D &a1_gen_sel.hw, + [CLKID_GEN_DIV] =3D &a1_gen_div.hw, + [CLKID_SARADC_DIV] =3D &a1_saradc_div.hw, + [CLKID_PWM_A_SEL] =3D &a1_pwm_a_sel.hw, + [CLKID_PWM_A_DIV] =3D &a1_pwm_a_div.hw, + [CLKID_PWM_B_SEL] =3D &a1_pwm_b_sel.hw, + [CLKID_PWM_B_DIV] =3D &a1_pwm_b_div.hw, + [CLKID_PWM_C_SEL] =3D &a1_pwm_c_sel.hw, + [CLKID_PWM_C_DIV] =3D &a1_pwm_c_div.hw, + [CLKID_PWM_D_SEL] =3D &a1_pwm_d_sel.hw, + [CLKID_PWM_D_DIV] =3D &a1_pwm_d_div.hw, + [CLKID_PWM_E_SEL] =3D &a1_pwm_e_sel.hw, + [CLKID_PWM_E_DIV] =3D &a1_pwm_e_div.hw, + [CLKID_PWM_F_SEL] =3D &a1_pwm_f_sel.hw, + [CLKID_PWM_F_DIV] =3D &a1_pwm_f_div.hw, + [CLKID_SPICC_SEL] =3D &a1_spicc_sel.hw, + [CLKID_SPICC_DIV] =3D &a1_spicc_div.hw, + [CLKID_SPICC_SEL2] =3D &a1_spicc_sel2.hw, + [CLKID_TS_DIV] =3D &a1_ts_div.hw, + [CLKID_SPIFC_SEL] =3D &a1_spifc_sel.hw, + [CLKID_SPIFC_DIV] =3D &a1_spifc_div.hw, + [CLKID_SPIFC_SEL2] =3D &a1_spifc_sel2.hw, + [CLKID_USB_BUS_SEL] =3D &a1_usb_bus_sel.hw, + [CLKID_USB_BUS_DIV] =3D &a1_usb_bus_div.hw, + [CLKID_SD_EMMC_SEL] =3D &a1_sd_emmc_sel.hw, + [CLKID_SD_EMMC_DIV] =3D &a1_sd_emmc_div.hw, + [CLKID_SD_EMMC_SEL2] =3D &a1_sd_emmc_sel2.hw, + [CLKID_PSRAM_SEL] =3D &a1_psram_sel.hw, + [CLKID_PSRAM_DIV] =3D &a1_psram_div.hw, + [CLKID_PSRAM_SEL2] =3D &a1_psram_sel2.hw, + [CLKID_DMC_SEL] =3D &a1_dmc_sel.hw, + [CLKID_DMC_DIV] =3D &a1_dmc_div.hw, + [CLKID_DMC_SEL2] =3D &a1_dmc_sel2.hw, +}; + +static const struct regmap_config a1_peripherals_regmap_cfg =3D { .reg_bits =3D 32, .val_bits =3D 32, .reg_stride =3D 4, .max_register =3D DMC_CLK_CTRL, }; =20 -static struct meson_clk_hw_data a1_periphs_clks =3D { - .hws =3D a1_periphs_hw_clks, - .num =3D ARRAY_SIZE(a1_periphs_hw_clks), +static struct meson_clk_hw_data a1_peripherals_clks =3D { + .hws =3D a1_peripherals_hw_clks, + .num =3D ARRAY_SIZE(a1_peripherals_hw_clks), }; =20 -static int meson_a1_periphs_probe(struct platform_device *pdev) +static int a1_peripherals_clkc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; void __iomem *base; @@ -2079,36 +2081,36 @@ static int meson_a1_periphs_probe(struct platform_d= evice *pdev) return dev_err_probe(dev, PTR_ERR(base), "can't ioremap resource\n"); =20 - map =3D devm_regmap_init_mmio(dev, base, &a1_periphs_regmap_cfg); + map =3D devm_regmap_init_mmio(dev, base, &a1_peripherals_regmap_cfg); if (IS_ERR(map)) return dev_err_probe(dev, PTR_ERR(map), "can't init regmap mmio region\n"); =20 - for (clkid =3D 0; clkid < a1_periphs_clks.num; clkid++) { - err =3D devm_clk_hw_register(dev, a1_periphs_clks.hws[clkid]); + for (clkid =3D 0; clkid < a1_peripherals_clks.num; clkid++) { + err =3D devm_clk_hw_register(dev, a1_peripherals_clks.hws[clkid]); if (err) return dev_err_probe(dev, err, "clock[%d] registration failed\n", clkid); } =20 - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_periphs_clk= s); + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_peripherals= _clks); } =20 -static const struct of_device_id a1_periphs_clkc_match_table[] =3D { +static const struct of_device_id a1_peripherals_clkc_match_table[] =3D { { .compatible =3D "amlogic,a1-peripherals-clkc", }, {} }; -MODULE_DEVICE_TABLE(of, a1_periphs_clkc_match_table); +MODULE_DEVICE_TABLE(of, a1_peripherals_clkc_match_table); =20 -static struct platform_driver a1_periphs_clkc_driver =3D { - .probe =3D meson_a1_periphs_probe, +static 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cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jul 2025 08:27:14 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:26:00 +0200 Subject: [PATCH 02/26] clk: amlogic: a1-pll: naming consistency alignment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-2-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8963; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=V/ioS7Ec7Cg3YTVk3xhhI9osc4/59GAF44moXsR7xyM=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoZU+4k+xXNM/NC4iV1vrZpHpGmopZVtnCb0tqt pisbMy7xBCJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaGVPuAAKCRDm/A8cN/La hReOD/9CXpTsL9ZauAqvRLJMuDtAb+fuwpo2MD5qs8MkAxpcg2Ds9oT4vwOAf/FAldy6pb2zCLa 96K60+tTKuf1IHl/uxgWN8LvCyZhGNy3ugUdBieO4XedTpZaPdkrOBPYDK/yC4OtsRRgEGqAW35 QaYhhbnrKijVjawLt//EQhf88wiqhIa8aKNzMWLj0lB4QvqhTmk5ChCIpAPberW7JEsbcuQO+9p 3wP+BYdevSl7ktgH0MfVsI6xLC4bdKOM+Eca6jVNHDyM6JBEBtYbqgmQ8wgq9ayDn5ox3ccIoeW 0C436LxcG30mHCkZhH8d5w+0rffTk29vEIKVCt+f6FcnerM0O8RHk4eZRIANi0wy/yumPZ3m+z1 qPxNMW2y0KnFqGlmEO3sV4HsdpfywEtgyIZIwsWfSfXSxy9iRb223HjB6raqYxkq9hz2JxMCfZv E4yFS9oVGEb1MmzHxDy7BBEKzjRBnqfT8eQPqgqFOM5kZS0CGmU+R3j6mnSqvj7VBZk1kMuOpXS 7pNvkEAM4e10YhJxdmi4JYILyEHsiTErdX0miMuhE0JapF9vMZBM3wl+GP6Mghb6BdMy+IiDvvr reQ9Djqg7/dMSRD9Th6Bc8w8NFG/BDEupYXzGdlH6pFPqksom4Zuzyb7hEA5UL68raZuQMV33rL tbXMo/Co4+z1QVA== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet --- drivers/clk/meson/a1-pll.c | 76 +++++++++++++++++++++++-------------------= ---- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index dabd4fad1f57bdfa1d755298cd07a48d345e56a9..79ef4cbe955326ecedceb68cda7= f59bb8882b165 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -26,7 +26,7 @@ =20 #include =20 -static struct clk_regmap fixed_pll_dco =3D { +static struct clk_regmap a1_fixed_pll_dco =3D { .data =3D &(struct meson_clk_pll_data){ .en =3D { .reg_off =3D ANACTRL_FIXPLL_CTRL0, @@ -69,7 +69,7 @@ static struct clk_regmap fixed_pll_dco =3D { }, }; =20 -static struct clk_regmap fixed_pll =3D { +static struct clk_regmap a1_fixed_pll =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D ANACTRL_FIXPLL_CTRL0, .bit_idx =3D 20, @@ -78,18 +78,18 @@ static struct clk_regmap fixed_pll =3D { .name =3D "fixed_pll", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fixed_pll_dco.hw + &a1_fixed_pll_dco.hw }, .num_parents =3D 1, }, }; =20 -static const struct pll_mult_range hifi_pll_mult_range =3D { +static const struct pll_mult_range a1_hifi_pll_range =3D { .min =3D 32, .max =3D 64, }; =20 -static const struct reg_sequence hifi_init_regs[] =3D { +static const struct reg_sequence a1_hifi_pll_init_regs[] =3D { { .reg =3D ANACTRL_HIFIPLL_CTRL1, .def =3D 0x01800000 }, { .reg =3D ANACTRL_HIFIPLL_CTRL2, .def =3D 0x00001100 }, { .reg =3D ANACTRL_HIFIPLL_CTRL3, .def =3D 0x100a1100 }, @@ -97,7 +97,7 @@ static const struct reg_sequence hifi_init_regs[] =3D { { .reg =3D ANACTRL_HIFIPLL_CTRL0, .def =3D 0x01f18000 }, }; =20 -static struct clk_regmap hifi_pll =3D { +static struct clk_regmap a1_hifi_pll =3D { .data =3D &(struct meson_clk_pll_data){ .en =3D { .reg_off =3D ANACTRL_HIFIPLL_CTRL0, @@ -134,9 +134,9 @@ static struct clk_regmap hifi_pll =3D { .shift =3D 6, .width =3D 1, }, - .range =3D &hifi_pll_mult_range, - .init_regs =3D hifi_init_regs, - .init_count =3D ARRAY_SIZE(hifi_init_regs), + .range =3D &a1_hifi_pll_range, + .init_regs =3D a1_hifi_pll_init_regs, + .init_count =3D ARRAY_SIZE(a1_hifi_pll_init_regs), }, .hw.init =3D &(struct clk_init_data){ .name =3D "hifi_pll", @@ -148,20 +148,20 @@ static struct clk_regmap hifi_pll =3D { }, }; =20 -static struct clk_fixed_factor fclk_div2_div =3D { +static struct clk_fixed_factor a1_fclk_div2_div =3D { .mult =3D 1, .div =3D 2, .hw.init =3D &(struct clk_init_data){ .name =3D "fclk_div2_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fixed_pll.hw + &a1_fixed_pll.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap fclk_div2 =3D { +static struct clk_regmap a1_fclk_div2 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D ANACTRL_FIXPLL_CTRL0, .bit_idx =3D 21, @@ -170,7 +170,7 @@ static struct clk_regmap fclk_div2 =3D { .name =3D "fclk_div2", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fclk_div2_div.hw + &a1_fclk_div2_div.hw }, .num_parents =3D 1, /* @@ -186,20 +186,20 @@ static struct clk_regmap fclk_div2 =3D { }, }; =20 -static struct clk_fixed_factor fclk_div3_div =3D { +static struct clk_fixed_factor a1_fclk_div3_div =3D { .mult =3D 1, .div =3D 3, .hw.init =3D &(struct clk_init_data){ .name =3D "fclk_div3_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fixed_pll.hw + &a1_fixed_pll.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap fclk_div3 =3D { +static struct clk_regmap a1_fclk_div3 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D ANACTRL_FIXPLL_CTRL0, .bit_idx =3D 22, @@ -208,7 +208,7 @@ static struct clk_regmap fclk_div3 =3D { .name =3D "fclk_div3", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fclk_div3_div.hw + &a1_fclk_div3_div.hw }, .num_parents =3D 1, /* @@ -219,20 +219,20 @@ static struct clk_regmap fclk_div3 =3D { }, }; =20 -static struct clk_fixed_factor fclk_div5_div =3D { +static struct clk_fixed_factor a1_fclk_div5_div =3D { .mult =3D 1, .div =3D 5, .hw.init =3D &(struct clk_init_data){ .name =3D "fclk_div5_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fixed_pll.hw + &a1_fixed_pll.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap fclk_div5 =3D { +static struct clk_regmap a1_fclk_div5 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D ANACTRL_FIXPLL_CTRL0, .bit_idx =3D 23, @@ -241,7 +241,7 @@ static struct clk_regmap fclk_div5 =3D { .name =3D "fclk_div5", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fclk_div5_div.hw + &a1_fclk_div5_div.hw }, .num_parents =3D 1, /* @@ -252,20 +252,20 @@ static struct clk_regmap fclk_div5 =3D { }, }; =20 -static struct clk_fixed_factor fclk_div7_div =3D { +static struct clk_fixed_factor a1_fclk_div7_div =3D { .mult =3D 1, .div =3D 7, .hw.init =3D &(struct clk_init_data){ .name =3D "fclk_div7_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fixed_pll.hw + &a1_fixed_pll.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap fclk_div7 =3D { +static struct clk_regmap a1_fclk_div7 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D ANACTRL_FIXPLL_CTRL0, .bit_idx =3D 24, @@ -274,7 +274,7 @@ static struct clk_regmap fclk_div7 =3D { .name =3D "fclk_div7", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fclk_div7_div.hw + &a1_fclk_div7_div.hw }, .num_parents =3D 1, }, @@ -282,17 +282,17 @@ static struct clk_regmap fclk_div7 =3D { =20 /* Array of all clocks registered by this provider */ static struct clk_hw *a1_pll_hw_clks[] =3D { - [CLKID_FIXED_PLL_DCO] =3D &fixed_pll_dco.hw, - [CLKID_FIXED_PLL] =3D &fixed_pll.hw, - [CLKID_FCLK_DIV2_DIV] =3D &fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] =3D &fclk_div3_div.hw, - [CLKID_FCLK_DIV5_DIV] =3D &fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] =3D &fclk_div7_div.hw, - [CLKID_FCLK_DIV2] =3D &fclk_div2.hw, - [CLKID_FCLK_DIV3] =3D &fclk_div3.hw, - [CLKID_FCLK_DIV5] =3D &fclk_div5.hw, - [CLKID_FCLK_DIV7] =3D &fclk_div7.hw, - [CLKID_HIFI_PLL] =3D &hifi_pll.hw, + [CLKID_FIXED_PLL_DCO] =3D &a1_fixed_pll_dco.hw, + [CLKID_FIXED_PLL] =3D &a1_fixed_pll.hw, + [CLKID_FCLK_DIV2_DIV] =3D &a1_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] =3D &a1_fclk_div3_div.hw, + [CLKID_FCLK_DIV5_DIV] =3D &a1_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] =3D &a1_fclk_div7_div.hw, + [CLKID_FCLK_DIV2] =3D &a1_fclk_div2.hw, + [CLKID_FCLK_DIV3] =3D &a1_fclk_div3.hw, + [CLKID_FCLK_DIV5] =3D &a1_fclk_div5.hw, + [CLKID_FCLK_DIV7] =3D &a1_fclk_div7.hw, + [CLKID_HIFI_PLL] =3D &a1_hifi_pll.hw, }; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg-aoclk.c | 116 ++++++++++++++++++++++----------------= ---- 1 file changed, 61 insertions(+), 55 deletions(-) diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c index cd5d0b5ebdb237a74129b44410318748e48780d1..a0c58dc8e950a05c340c3427af4= f6ff7661fa84e 100644 --- a/drivers/clk/meson/axg-aoclk.c +++ b/drivers/clk/meson/axg-aoclk.c @@ -35,7 +35,7 @@ #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 #define AXG_AO_GATE(_name, _bit) \ -static struct clk_regmap axg_aoclk_##_name =3D { \ +static struct clk_regmap axg_ao_##_name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D (AO_RTI_GEN_CNTL_REG0), \ .bit_idx =3D (_bit), \ @@ -59,7 +59,7 @@ AXG_AO_GATE(uart2, 5); AXG_AO_GATE(ir_blaster, 6); AXG_AO_GATE(saradc, 7); =20 -static struct clk_regmap axg_aoclk_cts_oscin =3D { +static struct clk_regmap axg_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTI_PWR_CNTL_REG0, .bit_idx =3D 14, @@ -74,7 +74,7 @@ static struct clk_regmap axg_aoclk_cts_oscin =3D { }, }; =20 -static struct clk_regmap axg_aoclk_32k_pre =3D { +static struct clk_regmap axg_ao_32k_pre =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTC_ALT_CLK_CNTL0, .bit_idx =3D 31, @@ -83,7 +83,7 @@ static struct clk_regmap axg_aoclk_32k_pre =3D { .name =3D "axg_ao_32k_pre", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_aoclk_cts_oscin.hw + &axg_ao_cts_oscin.hw }, .num_parents =3D 1, }, @@ -99,7 +99,7 @@ static const struct meson_clk_dualdiv_param axg_32k_div_t= able[] =3D { }, {} }; =20 -static struct clk_regmap axg_aoclk_32k_div =3D { +static struct clk_regmap axg_ao_32k_div =3D { .data =3D &(struct meson_clk_dualdiv_data){ .n1 =3D { .reg_off =3D AO_RTC_ALT_CLK_CNTL0, @@ -132,13 +132,13 @@ static struct clk_regmap axg_aoclk_32k_div =3D { .name =3D "axg_ao_32k_div", .ops =3D &meson_clk_dualdiv_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_aoclk_32k_pre.hw + &axg_ao_32k_pre.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap axg_aoclk_32k_sel =3D { +static struct clk_regmap axg_ao_32k_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTC_ALT_CLK_CNTL1, .mask =3D 0x1, @@ -149,15 +149,15 @@ static struct clk_regmap axg_aoclk_32k_sel =3D { .name =3D "axg_ao_32k_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_aoclk_32k_div.hw, - &axg_aoclk_32k_pre.hw, + &axg_ao_32k_div.hw, + &axg_ao_32k_pre.hw, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap axg_aoclk_32k =3D { +static struct clk_regmap axg_ao_32k =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTC_ALT_CLK_CNTL0, .bit_idx =3D 30, @@ -166,14 +166,14 @@ static struct clk_regmap axg_aoclk_32k =3D { .name =3D "axg_ao_32k", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_aoclk_32k_sel.hw + &axg_ao_32k_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap axg_aoclk_cts_rtc_oscin =3D { +static struct clk_regmap axg_ao_cts_rtc_oscin =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTI_PWR_CNTL_REG0, .mask =3D 0x1, @@ -184,7 +184,7 @@ static struct clk_regmap axg_aoclk_cts_rtc_oscin =3D { .name =3D "axg_ao_cts_rtc_oscin", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { - { .hw =3D &axg_aoclk_32k.hw }, + { .hw =3D &axg_ao_32k.hw }, { .fw_name =3D "ext_32k-0", }, }, .num_parents =3D 2, @@ -192,7 +192,7 @@ static struct clk_regmap axg_aoclk_cts_rtc_oscin =3D { }, }; =20 -static struct clk_regmap axg_aoclk_clk81 =3D { +static struct clk_regmap axg_ao_clk81 =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTI_PWR_CNTL_REG0, .mask =3D 0x1, @@ -200,68 +200,74 @@ static struct clk_regmap axg_aoclk_clk81 =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ + /* + * NOTE: this is one of the infamous clock the pwm driver + * can request directly by its global name. It's wrong but + * there is not much we can do about it until the support + * for the old pwm bindings is dropped + */ .name =3D "axg_ao_clk81", .ops =3D &clk_regmap_mux_ro_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "mpeg-clk", }, - { .hw =3D &axg_aoclk_cts_rtc_oscin.hw }, + { .hw =3D &axg_ao_cts_rtc_oscin.hw }, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap axg_aoclk_saradc_mux =3D { +static struct clk_regmap axg_ao_saradc_mux =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_SAR_CLK, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "axg_ao_saradc_mux", + .name =3D "ao_saradc_mux", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "xtal", }, - { .hw =3D &axg_aoclk_clk81.hw }, + { .hw =3D &axg_ao_clk81.hw }, }, .num_parents =3D 2, }, }; =20 -static struct clk_regmap axg_aoclk_saradc_div =3D { +static struct clk_regmap axg_ao_saradc_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D AO_SAR_CLK, .shift =3D 0, .width =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "axg_ao_saradc_div", + .name =3D "ao_saradc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_aoclk_saradc_mux.hw + &axg_ao_saradc_mux.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap axg_aoclk_saradc_gate =3D { +static struct clk_regmap axg_ao_saradc_gate =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D AO_SAR_CLK, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "axg_ao_saradc_gate", + .name =3D "ao_saradc_gate", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_aoclk_saradc_div.hw + &axg_ao_saradc_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const unsigned int axg_aoclk_reset[] =3D { +static const unsigned int axg_ao_reset[] =3D { [RESET_AO_REMOTE] =3D 16, [RESET_AO_I2C_MASTER] =3D 18, [RESET_AO_I2C_SLAVE] =3D 19, @@ -270,53 +276,53 @@ static const unsigned int axg_aoclk_reset[] =3D { [RESET_AO_IR_BLASTER] =3D 23, }; =20 -static struct clk_hw *axg_aoclk_hw_clks[] =3D { - [CLKID_AO_REMOTE] =3D &axg_aoclk_remote.hw, - [CLKID_AO_I2C_MASTER] =3D &axg_aoclk_i2c_master.hw, - [CLKID_AO_I2C_SLAVE] =3D &axg_aoclk_i2c_slave.hw, - [CLKID_AO_UART1] =3D &axg_aoclk_uart1.hw, - [CLKID_AO_UART2] =3D &axg_aoclk_uart2.hw, - [CLKID_AO_IR_BLASTER] =3D &axg_aoclk_ir_blaster.hw, - [CLKID_AO_SAR_ADC] =3D &axg_aoclk_saradc.hw, - [CLKID_AO_CLK81] =3D &axg_aoclk_clk81.hw, - [CLKID_AO_SAR_ADC_SEL] =3D &axg_aoclk_saradc_mux.hw, - [CLKID_AO_SAR_ADC_DIV] =3D &axg_aoclk_saradc_div.hw, - [CLKID_AO_SAR_ADC_CLK] =3D &axg_aoclk_saradc_gate.hw, - [CLKID_AO_CTS_OSCIN] =3D &axg_aoclk_cts_oscin.hw, - [CLKID_AO_32K_PRE] =3D &axg_aoclk_32k_pre.hw, - [CLKID_AO_32K_DIV] =3D &axg_aoclk_32k_div.hw, - [CLKID_AO_32K_SEL] =3D &axg_aoclk_32k_sel.hw, - [CLKID_AO_32K] =3D &axg_aoclk_32k.hw, - [CLKID_AO_CTS_RTC_OSCIN] =3D &axg_aoclk_cts_rtc_oscin.hw, +static struct clk_hw *axg_ao_hw_clks[] =3D { + [CLKID_AO_REMOTE] =3D &axg_ao_remote.hw, + [CLKID_AO_I2C_MASTER] =3D &axg_ao_i2c_master.hw, + [CLKID_AO_I2C_SLAVE] =3D &axg_ao_i2c_slave.hw, + [CLKID_AO_UART1] =3D &axg_ao_uart1.hw, + [CLKID_AO_UART2] =3D &axg_ao_uart2.hw, + [CLKID_AO_IR_BLASTER] =3D &axg_ao_ir_blaster.hw, + [CLKID_AO_SAR_ADC] =3D &axg_ao_saradc.hw, + [CLKID_AO_CLK81] =3D &axg_ao_clk81.hw, + [CLKID_AO_SAR_ADC_SEL] =3D &axg_ao_saradc_mux.hw, + [CLKID_AO_SAR_ADC_DIV] =3D &axg_ao_saradc_div.hw, + [CLKID_AO_SAR_ADC_CLK] =3D &axg_ao_saradc_gate.hw, + [CLKID_AO_CTS_OSCIN] =3D &axg_ao_cts_oscin.hw, + [CLKID_AO_32K_PRE] =3D &axg_ao_32k_pre.hw, + [CLKID_AO_32K_DIV] =3D &axg_ao_32k_div.hw, + [CLKID_AO_32K_SEL] =3D &axg_ao_32k_sel.hw, + [CLKID_AO_32K] =3D &axg_ao_32k.hw, + [CLKID_AO_CTS_RTC_OSCIN] =3D &axg_ao_cts_rtc_oscin.hw, }; =20 -static const struct meson_aoclk_data axg_aoclkc_data =3D { +static const struct meson_aoclk_data axg_ao_clkc_data =3D { .reset_reg =3D AO_RTI_GEN_CNTL_REG0, - .num_reset =3D ARRAY_SIZE(axg_aoclk_reset), - .reset =3D axg_aoclk_reset, + .num_reset =3D ARRAY_SIZE(axg_ao_reset), + .reset =3D axg_ao_reset, .hw_clks =3D { - .hws =3D axg_aoclk_hw_clks, - .num =3D ARRAY_SIZE(axg_aoclk_hw_clks), + .hws =3D axg_ao_hw_clks, + .num =3D ARRAY_SIZE(axg_ao_hw_clks), }, }; =20 -static const struct of_device_id axg_aoclkc_match_table[] =3D { +static const struct of_device_id axg_ao_clkc_match_table[] =3D { { .compatible =3D "amlogic,meson-axg-aoclkc", - .data =3D &axg_aoclkc_data, + .data =3D &axg_ao_clkc_data, }, { } }; -MODULE_DEVICE_TABLE(of, axg_aoclkc_match_table); +MODULE_DEVICE_TABLE(of, axg_ao_clkc_match_table); =20 -static struct platform_driver axg_aoclkc_driver =3D { +static struct platform_driver axg_ao_clkc_driver =3D { .probe =3D meson_aoclkc_probe, .driver =3D { - .name =3D "axg-aoclkc", - .of_match_table =3D axg_aoclkc_match_table, + .name =3D "axg-ao-clkc", + .of_match_table =3D axg_ao_clkc_match_table, }, }; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 215 ++++++++++++++++++++++++--------------------= ---- 1 file changed, 107 insertions(+), 108 deletions(-) diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 564655d4d18828d37f2383b348b686a9e0aa9adf..3839dfe9c7c540c2aec731be84e= 4e6520264c525 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -333,7 +333,7 @@ static struct clk_regmap axg_gp0_pll =3D { }, }; =20 -static const struct reg_sequence axg_hifi_init_regs[] =3D { +static const struct reg_sequence axg_hifi_pll_init_regs[] =3D { { .reg =3D HHI_HIFI_PLL_CNTL1, .def =3D 0xc084b000 }, { .reg =3D HHI_HIFI_PLL_CNTL2, .def =3D 0xb75020be }, { .reg =3D HHI_HIFI_PLL_CNTL3, .def =3D 0x0a6a3a88 }, @@ -374,8 +374,8 @@ static struct clk_regmap axg_hifi_pll_dco =3D { .width =3D 1, }, .table =3D axg_gp0_pll_params_table, - .init_regs =3D axg_hifi_init_regs, - .init_count =3D ARRAY_SIZE(axg_hifi_init_regs), + .init_regs =3D axg_hifi_pll_init_regs, + .init_count =3D ARRAY_SIZE(axg_hifi_pll_init_regs), .flags =3D CLK_MESON_PLL_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ @@ -780,7 +780,7 @@ static const struct pll_params_table axg_pcie_pll_param= s_table[] =3D { { /* sentinel */ }, }; =20 -static const struct reg_sequence axg_pcie_init_regs[] =3D { +static const struct reg_sequence axg_pcie_pll_init_regs[] =3D { { .reg =3D HHI_PCIE_PLL_CNTL1, .def =3D 0x0084a2aa }, { .reg =3D HHI_PCIE_PLL_CNTL2, .def =3D 0xb75020be }, { .reg =3D HHI_PCIE_PLL_CNTL3, .def =3D 0x0a47488e }, @@ -823,8 +823,8 @@ static struct clk_regmap axg_pcie_pll_dco =3D { .width =3D 1, }, .table =3D axg_pcie_pll_params_table, - .init_regs =3D axg_pcie_init_regs, - .init_count =3D ARRAY_SIZE(axg_pcie_init_regs), + .init_regs =3D axg_pcie_pll_init_regs, + .init_count =3D ARRAY_SIZE(axg_pcie_pll_init_regs), }, .hw.init =3D &(struct clk_init_data){ .name =3D "pcie_pll_dco", @@ -935,8 +935,9 @@ static struct clk_regmap axg_pcie_cml_en1 =3D { }, }; =20 -static u32 mux_table_clk81[] =3D { 0, 2, 3, 4, 5, 6, 7 }; -static const struct clk_parent_data clk81_parent_data[] =3D { +/* clk81 is often referred as "mpeg_clk" */ +static u32 clk81_parents_val_table[] =3D { 0, 2, 3, 4, 5, 6, 7 }; +static const struct clk_parent_data clk81_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &axg_fclk_div7.hw }, { .hw =3D &axg_mpll1.hw }, @@ -946,32 +947,32 @@ static const struct clk_parent_data clk81_parent_data= [] =3D { { .hw =3D &axg_fclk_div5.hw }, }; =20 -static struct clk_regmap axg_mpeg_clk_sel =3D { +static struct clk_regmap axg_clk81_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_MPEG_CLK_CNTL, .mask =3D 0x7, .shift =3D 12, - .table =3D mux_table_clk81, + .table =3D clk81_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "mpeg_clk_sel", + .name =3D "clk81_sel", .ops =3D &clk_regmap_mux_ro_ops, - .parent_data =3D clk81_parent_data, - .num_parents =3D ARRAY_SIZE(clk81_parent_data), + .parent_data =3D clk81_parents, + .num_parents =3D ARRAY_SIZE(clk81_parents), }, }; =20 -static struct clk_regmap axg_mpeg_clk_div =3D { +static struct clk_regmap axg_clk81_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D HHI_MPEG_CLK_CNTL, .shift =3D 0, .width =3D 7, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "mpeg_clk_div", + .name =3D "clk81_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_mpeg_clk_sel.hw + &axg_clk81_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -987,14 +988,14 @@ static struct clk_regmap axg_clk81 =3D { .name =3D "clk81", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &axg_mpeg_clk_div.hw + &axg_clk81_div.hw }, .num_parents =3D 1, .flags =3D (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), }, }; =20 -static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] =3D { +static const struct clk_parent_data axg_sd_emmc_clk0_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &axg_fclk_div2.hw }, { .hw =3D &axg_fclk_div3.hw }, @@ -1018,8 +1019,8 @@ static struct clk_regmap axg_sd_emmc_b_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_b_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D axg_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(axg_sd_emmc_clk0_parent_data), + .parent_data =3D axg_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(axg_sd_emmc_clk0_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1068,8 +1069,8 @@ static struct clk_regmap axg_sd_emmc_c_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_c_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D axg_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(axg_sd_emmc_clk0_parent_data), + .parent_data =3D axg_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(axg_sd_emmc_clk0_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1110,7 +1111,7 @@ static struct clk_regmap axg_sd_emmc_c_clk0 =3D { =20 /* VPU Clock */ =20 -static const struct clk_hw *axg_vpu_parent_hws[] =3D { +static const struct clk_hw *axg_vpu_parents[] =3D { &axg_fclk_div4.hw, &axg_fclk_div3.hw, &axg_fclk_div5.hw, @@ -1126,8 +1127,8 @@ static struct clk_regmap axg_vpu_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vpu_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D axg_vpu_parent_hws, - .num_parents =3D ARRAY_SIZE(axg_vpu_parent_hws), + .parent_hws =3D axg_vpu_parents, + .num_parents =3D ARRAY_SIZE(axg_vpu_parents), /* We need a specific parent for VPU clock source, let it be set in DT */ .flags =3D CLK_SET_RATE_NO_REPARENT, }, @@ -1175,8 +1176,8 @@ static struct clk_regmap axg_vpu_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vpu_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D axg_vpu_parent_hws, - .num_parents =3D ARRAY_SIZE(axg_vpu_parent_hws), + .parent_hws =3D axg_vpu_parents, + .num_parents =3D ARRAY_SIZE(axg_vpu_parents), /* We need a specific parent for VPU clock source, let it be set in DT */ .flags =3D CLK_SET_RATE_NO_REPARENT, }, @@ -1244,8 +1245,8 @@ static struct clk_regmap axg_vapb_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vapb_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D axg_vpu_parent_hws, - .num_parents =3D ARRAY_SIZE(axg_vpu_parent_hws), + .parent_hws =3D axg_vpu_parents, + .num_parents =3D ARRAY_SIZE(axg_vpu_parents), .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; @@ -1292,8 +1293,8 @@ static struct clk_regmap axg_vapb_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vapb_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D axg_vpu_parent_hws, - .num_parents =3D ARRAY_SIZE(axg_vpu_parent_hws), + .parent_hws =3D axg_vpu_parents, + .num_parents =3D ARRAY_SIZE(axg_vpu_parents), .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; @@ -1365,7 +1366,7 @@ static struct clk_regmap axg_vapb =3D { =20 /* Video Clocks */ =20 -static const struct clk_hw *axg_vclk_parent_hws[] =3D { +static const struct clk_hw *axg_vclk_parents[] =3D { &axg_gp0_pll.hw, &axg_fclk_div4.hw, &axg_fclk_div3.hw, @@ -1384,8 +1385,8 @@ static struct clk_regmap axg_vclk_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D axg_vclk_parent_hws, - .num_parents =3D ARRAY_SIZE(axg_vclk_parent_hws), + .parent_hws =3D axg_vclk_parents, + .num_parents =3D ARRAY_SIZE(axg_vclk_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -1399,8 +1400,8 @@ static struct clk_regmap axg_vclk2_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vclk2_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D axg_vclk_parent_hws, - .num_parents =3D ARRAY_SIZE(axg_vclk_parent_hws), + .parent_hws =3D axg_vclk_parents, + .num_parents =3D ARRAY_SIZE(axg_vclk_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -1739,8 +1740,8 @@ static struct clk_fixed_factor axg_vclk2_div12 =3D { }, }; =20 -static u32 mux_table_cts_sel[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; -static const struct clk_hw *axg_cts_parent_hws[] =3D { +static u32 axg_cts_encl_parents_val_table[] =3D { 0, 1, 2, 3, 4, 8, 9, 10,= 11, 12 }; +static const struct clk_hw *axg_cts_encl_parents[] =3D { &axg_vclk_div1.hw, &axg_vclk_div2.hw, &axg_vclk_div4.hw, @@ -1758,13 +1759,13 @@ static struct clk_regmap axg_cts_encl_sel =3D { .offset =3D HHI_VIID_CLK_DIV, .mask =3D 0xf, .shift =3D 12, - .table =3D mux_table_cts_sel, + .table =3D axg_cts_encl_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_encl_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D axg_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(axg_cts_parent_hws), + .parent_hws =3D axg_cts_encl_parents, + .num_parents =3D ARRAY_SIZE(axg_cts_encl_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -1787,8 +1788,8 @@ static struct clk_regmap axg_cts_encl =3D { =20 /* MIPI DSI Host Clock */ =20 -static u32 mux_table_axg_vdin_meas[] =3D { 0, 1, 2, 3, 6, 7 }; -static const struct clk_parent_data axg_vdin_meas_parent_data[] =3D { +static u32 axg_vdin_meas_parents_val_table[] =3D { 0, 1, 2, 3, 6, 7 }; +static const struct clk_parent_data axg_vdin_meas_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &axg_fclk_div4.hw }, { .hw =3D &axg_fclk_div3.hw }, @@ -1803,13 +1804,13 @@ static struct clk_regmap axg_vdin_meas_sel =3D { .mask =3D 0x7, .shift =3D 21, .flags =3D CLK_MUX_ROUND_CLOSEST, - .table =3D mux_table_axg_vdin_meas, + .table =3D axg_vdin_meas_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "vdin_meas_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D axg_vdin_meas_parent_data, - .num_parents =3D ARRAY_SIZE(axg_vdin_meas_parent_data), + .parent_data =3D axg_vdin_meas_parents, + .num_parents =3D ARRAY_SIZE(axg_vdin_meas_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1845,9 +1846,8 @@ static struct clk_regmap axg_vdin_meas =3D { }, }; =20 -static u32 mux_table_gen_clk[] =3D { 0, 4, 5, 6, 7, 8, - 9, 10, 11, 13, 14, }; -static const struct clk_parent_data gen_clk_parent_data[] =3D { +static u32 gen_clk_parents_val_table[] =3D { 0, 4, 5, 6, 7, 8, 9, 10, 11, = 13, 14, }; +static const struct clk_parent_data gen_clk_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &axg_hifi_pll.hw }, { .hw =3D &axg_mpll0.hw }, @@ -1866,7 +1866,7 @@ static struct clk_regmap axg_gen_clk_sel =3D { .offset =3D HHI_GEN_CLK_CNTL, .mask =3D 0xf, .shift =3D 12, - .table =3D mux_table_gen_clk, + .table =3D gen_clk_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "gen_clk_sel", @@ -1877,8 +1877,8 @@ static struct clk_regmap axg_gen_clk_sel =3D { * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4, * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll */ - .parent_data =3D gen_clk_parent_data, - .num_parents =3D ARRAY_SIZE(gen_clk_parent_data), + .parent_data =3D gen_clk_parents, + .num_parents =3D ARRAY_SIZE(gen_clk_parents), }, }; =20 @@ -1915,59 +1915,59 @@ static struct clk_regmap axg_gen_clk =3D { }, }; =20 -#define MESON_GATE(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw) +#define AXG_PCLK(_name, _reg, _bit) \ + MESON_PCLK(axg_##_name, _reg, _bit, &axg_clk81.hw) =20 /* Everything Else (EE) domain gates */ -static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0); -static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2); -static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3); -static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5); -static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6); -static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7); -static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8); -static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9); -static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12); -static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13); -static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14); -static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15); -static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16); -static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17); -static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19); -static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23); -static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25); -static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26); -static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27); -static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30); - -static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0); -static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3); -static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16); -static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20); -static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21); -static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22); -static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23); -static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26); -static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29); -static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30); -static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31); - -static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1); -static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8); -static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9); -static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11); -static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25); -static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); -static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30); +static AXG_PCLK(ddr, HHI_GCLK_MPEG0, 0); +static AXG_PCLK(audio_locker, HHI_GCLK_MPEG0, 2); +static AXG_PCLK(mipi_dsi_host, HHI_GCLK_MPEG0, 3); +static AXG_PCLK(isa, HHI_GCLK_MPEG0, 5); +static AXG_PCLK(pl301, HHI_GCLK_MPEG0, 6); +static AXG_PCLK(periphs, HHI_GCLK_MPEG0, 7); +static AXG_PCLK(spicc_0, HHI_GCLK_MPEG0, 8); +static AXG_PCLK(i2c, HHI_GCLK_MPEG0, 9); +static AXG_PCLK(rng0, HHI_GCLK_MPEG0, 12); +static AXG_PCLK(uart0, HHI_GCLK_MPEG0, 13); +static AXG_PCLK(mipi_dsi_phy, HHI_GCLK_MPEG0, 14); +static AXG_PCLK(spicc_1, HHI_GCLK_MPEG0, 15); +static AXG_PCLK(pcie_a, HHI_GCLK_MPEG0, 16); +static AXG_PCLK(pcie_b, HHI_GCLK_MPEG0, 17); +static AXG_PCLK(hiu_reg, HHI_GCLK_MPEG0, 19); +static AXG_PCLK(assist_misc, HHI_GCLK_MPEG0, 23); +static AXG_PCLK(emmc_b, HHI_GCLK_MPEG0, 25); +static AXG_PCLK(emmc_c, HHI_GCLK_MPEG0, 26); +static AXG_PCLK(dma, HHI_GCLK_MPEG0, 27); +static AXG_PCLK(spi, HHI_GCLK_MPEG0, 30); + +static AXG_PCLK(audio, HHI_GCLK_MPEG1, 0); +static AXG_PCLK(eth_core, HHI_GCLK_MPEG1, 3); +static AXG_PCLK(uart1, HHI_GCLK_MPEG1, 16); +static AXG_PCLK(g2d, HHI_GCLK_MPEG1, 20); +static AXG_PCLK(usb0, HHI_GCLK_MPEG1, 21); +static AXG_PCLK(usb1, HHI_GCLK_MPEG1, 22); +static AXG_PCLK(reset, HHI_GCLK_MPEG1, 23); +static AXG_PCLK(usb_general, HHI_GCLK_MPEG1, 26); +static AXG_PCLK(ahb_arb0, HHI_GCLK_MPEG1, 29); +static AXG_PCLK(efuse, HHI_GCLK_MPEG1, 30); +static AXG_PCLK(boot_rom, HHI_GCLK_MPEG1, 31); + +static AXG_PCLK(ahb_data_bus, HHI_GCLK_MPEG2, 1); +static AXG_PCLK(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); +static AXG_PCLK(usb1_to_ddr, HHI_GCLK_MPEG2, 8); +static AXG_PCLK(usb0_to_ddr, HHI_GCLK_MPEG2, 9); +static AXG_PCLK(mmc_pclk, HHI_GCLK_MPEG2, 11); +static AXG_PCLK(vpu_intr, HHI_GCLK_MPEG2, 25); +static AXG_PCLK(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); +static AXG_PCLK(gic, HHI_GCLK_MPEG2, 30); =20 /* Always On (AO) domain gates */ =20 -static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0); -static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1); -static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2); -static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3); -static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4); +static AXG_PCLK(ao_media_cpu, HHI_GCLK_AO, 0); +static AXG_PCLK(ao_ahb_sram, HHI_GCLK_AO, 1); +static AXG_PCLK(ao_ahb_bus, HHI_GCLK_AO, 2); +static AXG_PCLK(ao_iface, HHI_GCLK_AO, 3); +static AXG_PCLK(ao_i2c, HHI_GCLK_AO, 4); =20 /* Array of all clocks provided by this provider */ =20 @@ -1980,8 +1980,8 @@ static struct clk_hw *axg_hw_clks[] =3D { [CLKID_FCLK_DIV5] =3D &axg_fclk_div5.hw, [CLKID_FCLK_DIV7] =3D &axg_fclk_div7.hw, [CLKID_GP0_PLL] =3D &axg_gp0_pll.hw, - [CLKID_MPEG_SEL] =3D &axg_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &axg_mpeg_clk_div.hw, + [CLKID_MPEG_SEL] =3D &axg_clk81_sel.hw, + [CLKID_MPEG_DIV] =3D &axg_clk81_div.hw, [CLKID_CLK81] =3D &axg_clk81.hw, [CLKID_MPLL0] =3D &axg_mpll0.hw, [CLKID_MPLL1] =3D &axg_mpll1.hw, @@ -2117,21 +2117,20 @@ static const struct meson_eeclkc_data axg_clkc_data= =3D { }, }; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet Reviewed-by: Chuan Liu --- drivers/clk/meson/c3-peripherals.c | 1261 ++++++++++++++++++--------------= ---- 1 file changed, 630 insertions(+), 631 deletions(-) diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c index a25e7d5dc6691d2d4a852e3d3da2b36f251cc141..a09cb1435ab108b2dcc209c6557= bcd1988c4ba1a 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -48,7 +48,7 @@ #define SPIFC_CLK_CTRL 0x1a0 #define NNA_CLK_CTRL 0x220 =20 -static struct clk_regmap rtc_xtal_clkin =3D { +static struct clk_regmap c3_rtc_xtal_clkin =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D RTC_BY_OSCIN_CTRL0, .bit_idx =3D 31, @@ -63,12 +63,12 @@ static struct clk_regmap rtc_xtal_clkin =3D { }, }; =20 -static const struct meson_clk_dualdiv_param rtc_32k_div_table[] =3D { +static const struct meson_clk_dualdiv_param c3_rtc_32k_div_table[] =3D { { 733, 732, 8, 11, 1 }, { /* sentinel */ } }; =20 -static struct clk_regmap rtc_32k_div =3D { +static struct clk_regmap c3_rtc_32k_div =3D { .data =3D &(struct meson_clk_dualdiv_data) { .n1 =3D { .reg_off =3D RTC_BY_OSCIN_CTRL0, @@ -95,39 +95,39 @@ static struct clk_regmap rtc_32k_div =3D { .shift =3D 28, .width =3D 1, }, - .table =3D rtc_32k_div_table, + .table =3D c3_rtc_32k_div_table, }, .hw.init =3D &(struct clk_init_data) { .name =3D "rtc_32k_div", .ops =3D &meson_clk_dualdiv_ops, .parent_hws =3D (const struct clk_hw *[]) { - &rtc_xtal_clkin.hw + &c3_rtc_xtal_clkin.hw }, .num_parents =3D 1, }, }; =20 -static const struct clk_parent_data rtc_32k_mux_parent_data[] =3D { - { .hw =3D &rtc_32k_div.hw }, - { .hw =3D &rtc_xtal_clkin.hw } +static const struct clk_parent_data c3_rtc_32k_parents[] =3D { + { .hw =3D &c3_rtc_32k_div.hw }, + { .hw =3D &c3_rtc_xtal_clkin.hw } }; =20 -static struct clk_regmap rtc_32k_mux =3D { +static struct clk_regmap c3_rtc_32k_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D RTC_BY_OSCIN_CTRL1, .mask =3D 0x1, .shift =3D 24, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "rtc_32k_mux", + .name =3D "rtc_32k_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D rtc_32k_mux_parent_data, - .num_parents =3D ARRAY_SIZE(rtc_32k_mux_parent_data), + .parent_data =3D c3_rtc_32k_parents, + .num_parents =3D ARRAY_SIZE(c3_rtc_32k_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap rtc_32k =3D { +static struct clk_regmap c3_rtc_32k =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D RTC_BY_OSCIN_CTRL0, .bit_idx =3D 30, @@ -136,20 +136,20 @@ static struct clk_regmap rtc_32k =3D { .name =3D "rtc_32k", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &rtc_32k_mux.hw + &c3_rtc_32k_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data rtc_clk_mux_parent_data[] =3D { +static const struct clk_parent_data c3_rtc_clk_parents[] =3D { { .fw_name =3D "oscin" }, - { .hw =3D &rtc_32k.hw }, + { .hw =3D &c3_rtc_32k.hw }, { .fw_name =3D "pad_osc" } }; =20 -static struct clk_regmap rtc_clk =3D { +static struct clk_regmap c3_rtc_clk =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D RTC_CTRL, .mask =3D 0x3, @@ -158,62 +158,62 @@ static struct clk_regmap rtc_clk =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "rtc_clk", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D rtc_clk_mux_parent_data, - .num_parents =3D ARRAY_SIZE(rtc_clk_mux_parent_data), + .parent_data =3D c3_rtc_clk_parents, + .num_parents =3D ARRAY_SIZE(c3_rtc_clk_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -#define C3_CLK_GATE(_name, _reg, _bit, _fw_name, _ops, _flags) \ -struct clk_regmap _name =3D { \ +#define C3_PCLK(_name, _reg, _bit, _fw_name, _ops, _flags) \ +struct clk_regmap c3_##_name =3D { \ .data =3D &(struct clk_regmap_gate_data){ \ .offset =3D (_reg), \ .bit_idx =3D (_bit), \ }, \ .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name, \ + .name =3D "c3_" #_name, \ .ops =3D _ops, \ .parent_data =3D &(const struct clk_parent_data) { \ - .fw_name =3D #_fw_name, \ + .fw_name =3D (_fw_name), \ }, \ .num_parents =3D 1, \ .flags =3D (_flags), \ }, \ } =20 -#define C3_SYS_GATE(_name, _reg, _bit, _flags) \ - C3_CLK_GATE(_name, _reg, _bit, sysclk, \ - &clk_regmap_gate_ops, _flags) +#define C3_SYS_PCLK(_name, _reg, _bit, _flags) \ + C3_PCLK(_name, _reg, _bit, "sysclk", \ + &clk_regmap_gate_ops, _flags) =20 -#define C3_SYS_GATE_RO(_name, _reg, _bit) \ - C3_CLK_GATE(_name, _reg, _bit, sysclk, \ - &clk_regmap_gate_ro_ops, 0) +#define C3_SYS_PCLK_RO(_name, _reg, _bit) \ + C3_PCLK(_name, _reg, _bit, "sysclk", \ + &clk_regmap_gate_ro_ops, 0) =20 -static C3_SYS_GATE(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0); -static C3_SYS_GATE(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0); -static C3_SYS_GATE(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4, 0); -static C3_SYS_GATE(sys_ctrl, SYS_CLK_EN0_REG0, 5, 0); -static C3_SYS_GATE(sys_ts_pll, SYS_CLK_EN0_REG0, 6, 0); +static C3_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0); +static C3_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0); +static C3_SYS_PCLK(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4, 0); +static C3_SYS_PCLK(sys_ctrl, SYS_CLK_EN0_REG0, 5, 0); +static C3_SYS_PCLK(sys_ts_pll, SYS_CLK_EN0_REG0, 6, 0); =20 /* * NOTE: sys_dev_arb provides the clock to the ETH and SPICC arbiters that * access the AXI bus. */ -static C3_SYS_GATE(sys_dev_arb, SYS_CLK_EN0_REG0, 7, 0); +static C3_SYS_PCLK(sys_dev_arb, SYS_CLK_EN0_REG0, 7, 0); =20 /* * FIXME: sys_mmc_pclk provides the clock for the DDR PHY, DDR will only be * initialized in bl2, and this clock should not be touched in linux. */ -static C3_SYS_GATE_RO(sys_mmc_pclk, SYS_CLK_EN0_REG0, 8); +static C3_SYS_PCLK_RO(sys_mmc_pclk, SYS_CLK_EN0_REG0, 8); =20 /* * NOTE: sys_cpu_ctrl provides the clock for CPU controller. After clock is * disabled, cpu_clk and other key CPU-related configurations cannot take = effect. */ -static C3_SYS_GATE(sys_cpu_ctrl, SYS_CLK_EN0_REG0, 11, CLK_IS_CRITICAL); -static C3_SYS_GATE(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12, 0); -static C3_SYS_GATE(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13, 0); +static C3_SYS_PCLK(sys_cpu_ctrl, SYS_CLK_EN0_REG0, 11, CLK_IS_CRITICAL); +static C3_SYS_PCLK(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12, 0); +static C3_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13, 0); =20 /* * NOTE: sys_irq_ctrl provides the clock for IRQ controller. The IRQ contr= oller @@ -221,18 +221,18 @@ static C3_SYS_GATE(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13= , 0); * AOCPU. If the clock is disabled, interrupt-related functions will occur= s an * exception. */ -static C3_SYS_GATE(sys_irq_ctrl, SYS_CLK_EN0_REG0, 14, CLK_IS_CRITICAL); -static C3_SYS_GATE(sys_msr_clk, SYS_CLK_EN0_REG0, 15, 0); -static C3_SYS_GATE(sys_rom, SYS_CLK_EN0_REG0, 16, 0); -static C3_SYS_GATE(sys_uart_f, SYS_CLK_EN0_REG0, 17, 0); -static C3_SYS_GATE(sys_cpu_apb, SYS_CLK_EN0_REG0, 18, 0); -static C3_SYS_GATE(sys_rsa, SYS_CLK_EN0_REG0, 19, 0); -static C3_SYS_GATE(sys_sar_adc, SYS_CLK_EN0_REG0, 20, 0); -static C3_SYS_GATE(sys_startup, SYS_CLK_EN0_REG0, 21, 0); -static C3_SYS_GATE(sys_secure, SYS_CLK_EN0_REG0, 22, 0); -static C3_SYS_GATE(sys_spifc, SYS_CLK_EN0_REG0, 23, 0); -static C3_SYS_GATE(sys_nna, SYS_CLK_EN0_REG0, 25, 0); -static C3_SYS_GATE(sys_eth_mac, SYS_CLK_EN0_REG0, 26, 0); +static C3_SYS_PCLK(sys_irq_ctrl, SYS_CLK_EN0_REG0, 14, CLK_IS_CRITICAL); +static C3_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 15, 0); +static C3_SYS_PCLK(sys_rom, SYS_CLK_EN0_REG0, 16, 0); +static C3_SYS_PCLK(sys_uart_f, SYS_CLK_EN0_REG0, 17, 0); +static C3_SYS_PCLK(sys_cpu_apb, SYS_CLK_EN0_REG0, 18, 0); +static C3_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG0, 19, 0); +static C3_SYS_PCLK(sys_sar_adc, SYS_CLK_EN0_REG0, 20, 0); +static C3_SYS_PCLK(sys_startup, SYS_CLK_EN0_REG0, 21, 0); +static C3_SYS_PCLK(sys_secure, SYS_CLK_EN0_REG0, 22, 0); +static C3_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 23, 0); +static C3_SYS_PCLK(sys_nna, SYS_CLK_EN0_REG0, 25, 0); +static C3_SYS_PCLK(sys_eth_mac, SYS_CLK_EN0_REG0, 26, 0); =20 /* * FIXME: sys_gic provides the clock for GIC(Generic Interrupt Controller). @@ -240,8 +240,8 @@ static C3_SYS_GATE(sys_eth_mac, SYS_CLK_EN0_REG0, 26, = 0); * used by our GIC is the public driver in kernel, and there is no managem= ent * clock in the driver. */ -static C3_SYS_GATE(sys_gic, SYS_CLK_EN0_REG0, 27, CLK_IS_CRITICAL); -static C3_SYS_GATE(sys_rama, SYS_CLK_EN0_REG0, 28, 0); +static C3_SYS_PCLK(sys_gic, SYS_CLK_EN0_REG0, 27, CLK_IS_CRITICAL); +static C3_SYS_PCLK(sys_rama, SYS_CLK_EN0_REG0, 28, 0); =20 /* * NOTE: sys_big_nic provides the clock to the control bus of the NIC(Netw= ork @@ -249,84 +249,84 @@ static C3_SYS_GATE(sys_rama, SYS_CLK_EN0_REG0, 28, 0= ); * SPIFC, CAPU, JTAG, EMMC, SDIO, sec_top, USB, Audio, ETH, SPICC) in the * system. After clock is disabled, The NIC cannot work. */ -static C3_SYS_GATE(sys_big_nic, SYS_CLK_EN0_REG0, 29, CLK_IS_CRITICAL); -static C3_SYS_GATE(sys_ramb, SYS_CLK_EN0_REG0, 30, 0); -static C3_SYS_GATE(sys_audio_pclk, SYS_CLK_EN0_REG0, 31, 0); -static C3_SYS_GATE(sys_pwm_kl, SYS_CLK_EN0_REG1, 0, 0); -static C3_SYS_GATE(sys_pwm_ij, SYS_CLK_EN0_REG1, 1, 0); -static C3_SYS_GATE(sys_usb, SYS_CLK_EN0_REG1, 2, 0); -static C3_SYS_GATE(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3, 0); -static C3_SYS_GATE(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4, 0); -static C3_SYS_GATE(sys_pwm_ab, SYS_CLK_EN0_REG1, 5, 0); -static C3_SYS_GATE(sys_pwm_cd, SYS_CLK_EN0_REG1, 6, 0); -static C3_SYS_GATE(sys_pwm_ef, SYS_CLK_EN0_REG1, 7, 0); -static C3_SYS_GATE(sys_pwm_gh, SYS_CLK_EN0_REG1, 8, 0); -static C3_SYS_GATE(sys_spicc_1, SYS_CLK_EN0_REG1, 9, 0); -static C3_SYS_GATE(sys_spicc_0, SYS_CLK_EN0_REG1, 10, 0); -static C3_SYS_GATE(sys_uart_a, SYS_CLK_EN0_REG1, 11, 0); -static C3_SYS_GATE(sys_uart_b, SYS_CLK_EN0_REG1, 12, 0); -static C3_SYS_GATE(sys_uart_c, SYS_CLK_EN0_REG1, 13, 0); -static C3_SYS_GATE(sys_uart_d, SYS_CLK_EN0_REG1, 14, 0); -static C3_SYS_GATE(sys_uart_e, SYS_CLK_EN0_REG1, 15, 0); -static C3_SYS_GATE(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16, 0); -static C3_SYS_GATE(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17, 0); -static C3_SYS_GATE(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18, 0); -static C3_SYS_GATE(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19, 0); -static C3_SYS_GATE(sys_i2c_s_a, SYS_CLK_EN0_REG1, 20, 0); -static C3_SYS_GATE(sys_rtc, SYS_CLK_EN0_REG1, 21, 0); -static C3_SYS_GATE(sys_ge2d, SYS_CLK_EN0_REG1, 22, 0); -static C3_SYS_GATE(sys_isp, SYS_CLK_EN0_REG1, 23, 0); -static C3_SYS_GATE(sys_gpv_isp_nic, SYS_CLK_EN0_REG1, 24, 0); -static C3_SYS_GATE(sys_gpv_cve_nic, SYS_CLK_EN0_REG1, 25, 0); -static C3_SYS_GATE(sys_mipi_dsi_host, SYS_CLK_EN0_REG1, 26, 0); -static C3_SYS_GATE(sys_mipi_dsi_phy, SYS_CLK_EN0_REG1, 27, 0); -static C3_SYS_GATE(sys_eth_phy, SYS_CLK_EN0_REG1, 28, 0); -static C3_SYS_GATE(sys_acodec, SYS_CLK_EN0_REG1, 29, 0); -static C3_SYS_GATE(sys_dwap, SYS_CLK_EN0_REG1, 30, 0); -static C3_SYS_GATE(sys_dos, SYS_CLK_EN0_REG1, 31, 0); -static C3_SYS_GATE(sys_cve, SYS_CLK_EN0_REG2, 0, 0); -static C3_SYS_GATE(sys_vout, SYS_CLK_EN0_REG2, 1, 0); -static C3_SYS_GATE(sys_vc9000e, SYS_CLK_EN0_REG2, 2, 0); -static C3_SYS_GATE(sys_pwm_mn, SYS_CLK_EN0_REG2, 3, 0); -static C3_SYS_GATE(sys_sd_emmc_b, SYS_CLK_EN0_REG2, 4, 0); - -#define C3_AXI_GATE(_name, _reg, _bit, _flags) \ - C3_CLK_GATE(_name, _reg, _bit, axiclk, \ - &clk_regmap_gate_ops, _flags) +static C3_SYS_PCLK(sys_big_nic, SYS_CLK_EN0_REG0, 29, CLK_IS_CRITICAL); +static C3_SYS_PCLK(sys_ramb, SYS_CLK_EN0_REG0, 30, 0); +static C3_SYS_PCLK(sys_audio_pclk, SYS_CLK_EN0_REG0, 31, 0); +static C3_SYS_PCLK(sys_pwm_kl, SYS_CLK_EN0_REG1, 0, 0); +static C3_SYS_PCLK(sys_pwm_ij, SYS_CLK_EN0_REG1, 1, 0); +static C3_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 2, 0); +static C3_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3, 0); +static C3_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4, 0); +static C3_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG1, 5, 0); +static C3_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG1, 6, 0); +static C3_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG1, 7, 0); +static C3_SYS_PCLK(sys_pwm_gh, SYS_CLK_EN0_REG1, 8, 0); +static C3_SYS_PCLK(sys_spicc_1, SYS_CLK_EN0_REG1, 9, 0); +static C3_SYS_PCLK(sys_spicc_0, SYS_CLK_EN0_REG1, 10, 0); +static C3_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 11, 0); +static C3_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 12, 0); +static C3_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 13, 0); +static C3_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 14, 0); +static C3_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 15, 0); +static C3_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16, 0); +static C3_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17, 0); +static C3_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18, 0); +static C3_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19, 0); +static C3_SYS_PCLK(sys_i2c_s_a, SYS_CLK_EN0_REG1, 20, 0); +static C3_SYS_PCLK(sys_rtc, SYS_CLK_EN0_REG1, 21, 0); +static C3_SYS_PCLK(sys_ge2d, SYS_CLK_EN0_REG1, 22, 0); +static C3_SYS_PCLK(sys_isp, SYS_CLK_EN0_REG1, 23, 0); +static C3_SYS_PCLK(sys_gpv_isp_nic, SYS_CLK_EN0_REG1, 24, 0); +static C3_SYS_PCLK(sys_gpv_cve_nic, SYS_CLK_EN0_REG1, 25, 0); +static C3_SYS_PCLK(sys_mipi_dsi_host, SYS_CLK_EN0_REG1, 26, 0); +static C3_SYS_PCLK(sys_mipi_dsi_phy, SYS_CLK_EN0_REG1, 27, 0); +static C3_SYS_PCLK(sys_eth_phy, SYS_CLK_EN0_REG1, 28, 0); +static C3_SYS_PCLK(sys_acodec, SYS_CLK_EN0_REG1, 29, 0); +static C3_SYS_PCLK(sys_dwap, SYS_CLK_EN0_REG1, 30, 0); +static C3_SYS_PCLK(sys_dos, SYS_CLK_EN0_REG1, 31, 0); +static C3_SYS_PCLK(sys_cve, SYS_CLK_EN0_REG2, 0, 0); +static C3_SYS_PCLK(sys_vout, SYS_CLK_EN0_REG2, 1, 0); +static C3_SYS_PCLK(sys_vc9000e, SYS_CLK_EN0_REG2, 2, 0); +static C3_SYS_PCLK(sys_pwm_mn, SYS_CLK_EN0_REG2, 3, 0); +static C3_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG2, 4, 0); + +#define C3_AXI_PCLK(_name, _reg, _bit, _flags) \ + C3_PCLK(_name, _reg, _bit, "axiclk", \ + &clk_regmap_gate_ops, _flags) =20 /* * NOTE: axi_sys_nic provides the clock to the AXI bus of the system NIC. = After * clock is disabled, The NIC cannot work. */ -static C3_AXI_GATE(axi_sys_nic, AXI_CLK_EN0, 2, CLK_IS_CRITICAL); -static C3_AXI_GATE(axi_isp_nic, AXI_CLK_EN0, 3, 0); -static C3_AXI_GATE(axi_cve_nic, AXI_CLK_EN0, 4, 0); -static C3_AXI_GATE(axi_ramb, AXI_CLK_EN0, 5, 0); -static C3_AXI_GATE(axi_rama, AXI_CLK_EN0, 6, 0); +static C3_AXI_PCLK(axi_sys_nic, AXI_CLK_EN0, 2, CLK_IS_CRITICAL); +static C3_AXI_PCLK(axi_isp_nic, AXI_CLK_EN0, 3, 0); +static C3_AXI_PCLK(axi_cve_nic, AXI_CLK_EN0, 4, 0); +static C3_AXI_PCLK(axi_ramb, AXI_CLK_EN0, 5, 0); +static C3_AXI_PCLK(axi_rama, AXI_CLK_EN0, 6, 0); =20 /* * NOTE: axi_cpu_dmc provides the clock to the AXI bus where the CPU acces= ses * the DDR. After clock is disabled, The CPU will not have access to the D= DR. */ -static C3_AXI_GATE(axi_cpu_dmc, AXI_CLK_EN0, 7, CLK_IS_CRITICAL); -static C3_AXI_GATE(axi_nic, AXI_CLK_EN0, 8, 0); -static C3_AXI_GATE(axi_dma, AXI_CLK_EN0, 9, 0); +static C3_AXI_PCLK(axi_cpu_dmc, AXI_CLK_EN0, 7, CLK_IS_CRITICAL); +static C3_AXI_PCLK(axi_nic, AXI_CLK_EN0, 8, 0); +static C3_AXI_PCLK(axi_dma, AXI_CLK_EN0, 9, 0); =20 /* * NOTE: axi_mux_nic provides the clock to the NIC's AXI bus for NN(Neural * Network) and other devices(CPU, EMMC, SDIO, sec_top, USB, Audio, ETH, S= PICC) * to access RAM space. */ -static C3_AXI_GATE(axi_mux_nic, AXI_CLK_EN0, 10, 0); -static C3_AXI_GATE(axi_cve, AXI_CLK_EN0, 12, 0); +static C3_AXI_PCLK(axi_mux_nic, AXI_CLK_EN0, 10, 0); +static C3_AXI_PCLK(axi_cve, AXI_CLK_EN0, 12, 0); =20 /* * NOTE: axi_dev1_dmc provides the clock for the peripherals(EMMC, SDIO, * sec_top, USB, Audio, ETH, SPICC) to access the AXI bus of the DDR. */ -static C3_AXI_GATE(axi_dev1_dmc, AXI_CLK_EN0, 13, 0); -static C3_AXI_GATE(axi_dev0_dmc, AXI_CLK_EN0, 14, 0); -static C3_AXI_GATE(axi_dsp_dmc, AXI_CLK_EN0, 15, 0); +static C3_AXI_PCLK(axi_dev1_dmc, AXI_CLK_EN0, 13, 0); +static C3_AXI_PCLK(axi_dev0_dmc, AXI_CLK_EN0, 14, 0); +static C3_AXI_PCLK(axi_dsp_dmc, AXI_CLK_EN0, 15, 0); =20 /* * clk_12_24m model @@ -335,7 +335,7 @@ static C3_AXI_GATE(axi_dsp_dmc, AXI_CLK_EN0, 15, 0); * xtal---->| gate |---->| div |------------>| pad | * |------| |-----| |-----| */ -static struct clk_regmap clk_12_24m_in =3D { +static struct clk_regmap c3_clk_12_24m_in =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLK12_24_CTRL, .bit_idx =3D 11, @@ -350,7 +350,7 @@ static struct clk_regmap clk_12_24m_in =3D { }, }; =20 -static struct clk_regmap clk_12_24m =3D { +static struct clk_regmap c3_clk_12_24m =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D CLK12_24_CTRL, .shift =3D 10, @@ -360,14 +360,14 @@ static struct clk_regmap clk_12_24m =3D { .name =3D "clk_12_24m", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &clk_12_24m_in.hw + &c3_clk_12_24m_in.hw }, .num_parents =3D 1, }, }; =20 /* Fix me: set value 0 will div by 2 like value 1 */ -static struct clk_regmap fclk_25m_div =3D { +static struct clk_regmap c3_fclk_25m_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D CLK12_24_CTRL, .shift =3D 0, @@ -383,7 +383,7 @@ static struct clk_regmap fclk_25m_div =3D { }, }; =20 -static struct clk_regmap fclk_25m =3D { +static struct clk_regmap c3_fclk_25m =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLK12_24_CTRL, .bit_idx =3D 12, @@ -392,7 +392,7 @@ static struct clk_regmap fclk_25m =3D { .name =3D "fclk_25m", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fclk_25m_div.hw + &c3_fclk_25m_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -404,11 +404,10 @@ static struct clk_regmap fclk_25m =3D { * is manged by clock measures module. Their hardware are out of clock tre= e. * Channel 4 8 9 10 11 13 14 15 16 18 are not connected. */ -static u32 gen_parent_table[] =3D { 0, 1, 2, 5, 6, 7, 17, 19, 20, 21, 22, = 23, 24}; - -static const struct clk_parent_data gen_parent_data[] =3D { +static u32 c3_gen_parents_val_table[] =3D { 0, 1, 2, 5, 6, 7, 17, 19, 20, = 21, 22, 23, 24}; +static const struct clk_parent_data c3_gen_parents[] =3D { { .fw_name =3D "oscin" }, - { .hw =3D &rtc_clk.hw }, + { .hw =3D &c3_rtc_clk.hw }, { .fw_name =3D "sysplldiv16" }, { .fw_name =3D "gp0" }, { .fw_name =3D "gp1" }, @@ -422,22 +421,22 @@ static const struct clk_parent_data gen_parent_data[]= =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap gen_sel =3D { +static struct clk_regmap c3_gen_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D GEN_CLK_CTRL, .mask =3D 0x1f, .shift =3D 12, - .table =3D gen_parent_table, + .table =3D c3_gen_parents_val_table, }, .hw.init =3D &(struct clk_init_data) { .name =3D "gen_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D gen_parent_data, - .num_parents =3D ARRAY_SIZE(gen_parent_data), + .parent_data =3D c3_gen_parents, + .num_parents =3D ARRAY_SIZE(c3_gen_parents), }, }; =20 -static struct clk_regmap gen_div =3D { +static struct clk_regmap c3_gen_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D GEN_CLK_CTRL, .shift =3D 0, @@ -447,14 +446,14 @@ static struct clk_regmap gen_div =3D { .name =3D "gen_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &gen_sel.hw + &c3_gen_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap gen =3D { +static struct clk_regmap c3_gen =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D GEN_CLK_CTRL, .bit_idx =3D 11, @@ -463,19 +462,19 @@ static struct clk_regmap gen =3D { .name =3D "gen", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &gen_div.hw + &c3_gen_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data saradc_parent_data[] =3D { +static const struct clk_parent_data c3_saradc_parents[] =3D { { .fw_name =3D "oscin" }, { .fw_name =3D "sysclk" } }; =20 -static struct clk_regmap saradc_sel =3D { +static struct clk_regmap c3_saradc_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D SAR_CLK_CTRL0, .mask =3D 0x1, @@ -484,12 +483,12 @@ static struct clk_regmap saradc_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "saradc_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D saradc_parent_data, - .num_parents =3D ARRAY_SIZE(saradc_parent_data), + .parent_data =3D c3_saradc_parents, + .num_parents =3D ARRAY_SIZE(c3_saradc_parents), }, }; =20 -static struct clk_regmap saradc_div =3D { +static struct clk_regmap c3_saradc_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D SAR_CLK_CTRL0, .shift =3D 0, @@ -499,14 +498,14 @@ static struct clk_regmap saradc_div =3D { .name =3D "saradc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &saradc_sel.hw + &c3_saradc_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap saradc =3D { +static struct clk_regmap c3_saradc =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D SAR_CLK_CTRL0, .bit_idx =3D 8, @@ -515,21 +514,21 @@ static struct clk_regmap saradc =3D { .name =3D "saradc", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &saradc_div.hw + &c3_saradc_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data pwm_parent_data[] =3D { +static const struct clk_parent_data c3_pwm_parents[] =3D { { .fw_name =3D "oscin" }, { .fw_name =3D "gp1" }, { .fw_name =3D "fdiv4" }, { .fw_name =3D "fdiv3" } }; =20 -#define AML_PWM_CLK_MUX(_name, _reg, _shift) { \ +#define C3_PWM_CLK_MUX(_name, _reg, _shift) { \ .data =3D &(struct clk_regmap_mux_data) { \ .offset =3D _reg, \ .mask =3D 0x3, \ @@ -538,12 +537,12 @@ static const struct clk_parent_data pwm_parent_data[]= =3D { .hw.init =3D &(struct clk_init_data) { \ .name =3D #_name "_sel", \ .ops =3D &clk_regmap_mux_ops, \ - .parent_data =3D pwm_parent_data, \ - .num_parents =3D ARRAY_SIZE(pwm_parent_data), \ + .parent_data =3D c3_pwm_parents, \ + .num_parents =3D ARRAY_SIZE(c3_pwm_parents), \ }, \ } =20 -#define AML_PWM_CLK_DIV(_name, _reg, _shift) { \ +#define C3_PWM_CLK_DIV(_name, _reg, _shift) { \ .data =3D &(struct clk_regmap_div_data) { \ .offset =3D _reg, \ .shift =3D _shift, \ @@ -558,7 +557,7 @@ static const struct clk_parent_data pwm_parent_data[] = =3D { }, \ } =20 -#define AML_PWM_CLK_GATE(_name, _reg, _bit) { \ +#define C3_PWM_CLK_GATE(_name, _reg, _bit) { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D _reg, \ .bit_idx =3D _bit, \ @@ -572,105 +571,105 @@ static const struct clk_parent_data pwm_parent_data= [] =3D { }, \ } =20 -static struct clk_regmap pwm_a_sel =3D - AML_PWM_CLK_MUX(pwm_a, PWM_CLK_AB_CTRL, 9); -static struct clk_regmap pwm_a_div =3D - AML_PWM_CLK_DIV(pwm_a, PWM_CLK_AB_CTRL, 0); -static struct clk_regmap pwm_a =3D - AML_PWM_CLK_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); - -static struct clk_regmap pwm_b_sel =3D - AML_PWM_CLK_MUX(pwm_b, PWM_CLK_AB_CTRL, 25); -static struct clk_regmap pwm_b_div =3D - AML_PWM_CLK_DIV(pwm_b, PWM_CLK_AB_CTRL, 16); -static struct clk_regmap pwm_b =3D - AML_PWM_CLK_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); - -static struct clk_regmap pwm_c_sel =3D - AML_PWM_CLK_MUX(pwm_c, PWM_CLK_CD_CTRL, 9); -static struct clk_regmap pwm_c_div =3D - AML_PWM_CLK_DIV(pwm_c, PWM_CLK_CD_CTRL, 0); -static struct clk_regmap pwm_c =3D - AML_PWM_CLK_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); - -static struct clk_regmap pwm_d_sel =3D - AML_PWM_CLK_MUX(pwm_d, PWM_CLK_CD_CTRL, 25); -static struct clk_regmap pwm_d_div =3D - AML_PWM_CLK_DIV(pwm_d, PWM_CLK_CD_CTRL, 16); -static struct clk_regmap pwm_d =3D - AML_PWM_CLK_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); - -static struct clk_regmap pwm_e_sel =3D - AML_PWM_CLK_MUX(pwm_e, PWM_CLK_EF_CTRL, 9); -static struct clk_regmap pwm_e_div =3D - AML_PWM_CLK_DIV(pwm_e, PWM_CLK_EF_CTRL, 0); -static struct clk_regmap pwm_e =3D - AML_PWM_CLK_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); - -static struct clk_regmap pwm_f_sel =3D - AML_PWM_CLK_MUX(pwm_f, PWM_CLK_EF_CTRL, 25); -static struct clk_regmap pwm_f_div =3D - AML_PWM_CLK_DIV(pwm_f, PWM_CLK_EF_CTRL, 16); -static struct clk_regmap pwm_f =3D - AML_PWM_CLK_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); - -static struct clk_regmap pwm_g_sel =3D - AML_PWM_CLK_MUX(pwm_g, PWM_CLK_GH_CTRL, 9); -static struct clk_regmap pwm_g_div =3D - AML_PWM_CLK_DIV(pwm_g, PWM_CLK_GH_CTRL, 0); -static struct clk_regmap pwm_g =3D - AML_PWM_CLK_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); - -static struct clk_regmap pwm_h_sel =3D - AML_PWM_CLK_MUX(pwm_h, PWM_CLK_GH_CTRL, 25); -static struct clk_regmap pwm_h_div =3D - AML_PWM_CLK_DIV(pwm_h, PWM_CLK_GH_CTRL, 16); -static struct clk_regmap pwm_h =3D - AML_PWM_CLK_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); - -static struct clk_regmap pwm_i_sel =3D - AML_PWM_CLK_MUX(pwm_i, PWM_CLK_IJ_CTRL, 9); -static struct clk_regmap pwm_i_div =3D - AML_PWM_CLK_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0); -static struct clk_regmap pwm_i =3D - AML_PWM_CLK_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8); - -static struct clk_regmap pwm_j_sel =3D - AML_PWM_CLK_MUX(pwm_j, PWM_CLK_IJ_CTRL, 25); -static struct clk_regmap pwm_j_div =3D - AML_PWM_CLK_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16); -static struct clk_regmap pwm_j =3D - AML_PWM_CLK_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24); - -static struct clk_regmap pwm_k_sel =3D - AML_PWM_CLK_MUX(pwm_k, PWM_CLK_KL_CTRL, 9); -static struct clk_regmap pwm_k_div =3D - AML_PWM_CLK_DIV(pwm_k, PWM_CLK_KL_CTRL, 0); -static struct clk_regmap pwm_k =3D - AML_PWM_CLK_GATE(pwm_k, PWM_CLK_KL_CTRL, 8); - -static struct clk_regmap pwm_l_sel =3D - AML_PWM_CLK_MUX(pwm_l, PWM_CLK_KL_CTRL, 25); -static struct clk_regmap pwm_l_div =3D - AML_PWM_CLK_DIV(pwm_l, PWM_CLK_KL_CTRL, 16); -static struct clk_regmap pwm_l =3D - AML_PWM_CLK_GATE(pwm_l, PWM_CLK_KL_CTRL, 24); - -static struct clk_regmap pwm_m_sel =3D - AML_PWM_CLK_MUX(pwm_m, PWM_CLK_MN_CTRL, 9); -static struct clk_regmap pwm_m_div =3D - AML_PWM_CLK_DIV(pwm_m, PWM_CLK_MN_CTRL, 0); -static struct clk_regmap pwm_m =3D - AML_PWM_CLK_GATE(pwm_m, PWM_CLK_MN_CTRL, 8); - -static struct clk_regmap pwm_n_sel =3D - AML_PWM_CLK_MUX(pwm_n, PWM_CLK_MN_CTRL, 25); -static struct clk_regmap pwm_n_div =3D - AML_PWM_CLK_DIV(pwm_n, PWM_CLK_MN_CTRL, 16); -static struct clk_regmap pwm_n =3D - AML_PWM_CLK_GATE(pwm_n, PWM_CLK_MN_CTRL, 24); - -static const struct clk_parent_data spicc_parent_data[] =3D { +static struct clk_regmap c3_pwm_a_sel =3D + C3_PWM_CLK_MUX(pwm_a, PWM_CLK_AB_CTRL, 9); +static struct clk_regmap c3_pwm_a_div =3D + C3_PWM_CLK_DIV(pwm_a, PWM_CLK_AB_CTRL, 0); +static struct clk_regmap c3_pwm_a =3D + C3_PWM_CLK_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); + +static struct clk_regmap c3_pwm_b_sel =3D + C3_PWM_CLK_MUX(pwm_b, PWM_CLK_AB_CTRL, 25); +static struct clk_regmap c3_pwm_b_div =3D + C3_PWM_CLK_DIV(pwm_b, PWM_CLK_AB_CTRL, 16); +static struct clk_regmap c3_pwm_b =3D + C3_PWM_CLK_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); + +static struct clk_regmap c3_pwm_c_sel =3D + C3_PWM_CLK_MUX(pwm_c, PWM_CLK_CD_CTRL, 9); +static struct clk_regmap c3_pwm_c_div =3D + C3_PWM_CLK_DIV(pwm_c, PWM_CLK_CD_CTRL, 0); +static struct clk_regmap c3_pwm_c =3D + C3_PWM_CLK_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); + +static struct clk_regmap c3_pwm_d_sel =3D + C3_PWM_CLK_MUX(pwm_d, PWM_CLK_CD_CTRL, 25); +static struct clk_regmap c3_pwm_d_div =3D + C3_PWM_CLK_DIV(pwm_d, PWM_CLK_CD_CTRL, 16); +static struct clk_regmap c3_pwm_d =3D + C3_PWM_CLK_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); + +static struct clk_regmap c3_pwm_e_sel =3D + C3_PWM_CLK_MUX(pwm_e, PWM_CLK_EF_CTRL, 9); +static struct clk_regmap c3_pwm_e_div =3D + C3_PWM_CLK_DIV(pwm_e, PWM_CLK_EF_CTRL, 0); +static struct clk_regmap c3_pwm_e =3D + C3_PWM_CLK_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); + +static struct clk_regmap c3_pwm_f_sel =3D + C3_PWM_CLK_MUX(pwm_f, PWM_CLK_EF_CTRL, 25); +static struct clk_regmap c3_pwm_f_div =3D + C3_PWM_CLK_DIV(pwm_f, PWM_CLK_EF_CTRL, 16); +static struct clk_regmap c3_pwm_f =3D + C3_PWM_CLK_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); + +static struct clk_regmap c3_pwm_g_sel =3D + C3_PWM_CLK_MUX(pwm_g, PWM_CLK_GH_CTRL, 9); +static struct clk_regmap c3_pwm_g_div =3D + C3_PWM_CLK_DIV(pwm_g, PWM_CLK_GH_CTRL, 0); +static struct clk_regmap c3_pwm_g =3D + C3_PWM_CLK_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); + +static struct clk_regmap c3_pwm_h_sel =3D + C3_PWM_CLK_MUX(pwm_h, PWM_CLK_GH_CTRL, 25); +static struct clk_regmap c3_pwm_h_div =3D + C3_PWM_CLK_DIV(pwm_h, PWM_CLK_GH_CTRL, 16); +static struct clk_regmap c3_pwm_h =3D + C3_PWM_CLK_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); + +static struct clk_regmap c3_pwm_i_sel =3D + C3_PWM_CLK_MUX(pwm_i, PWM_CLK_IJ_CTRL, 9); +static struct clk_regmap c3_pwm_i_div =3D + C3_PWM_CLK_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0); +static struct clk_regmap c3_pwm_i =3D + C3_PWM_CLK_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8); + +static struct clk_regmap c3_pwm_j_sel =3D + C3_PWM_CLK_MUX(pwm_j, PWM_CLK_IJ_CTRL, 25); +static struct clk_regmap c3_pwm_j_div =3D + C3_PWM_CLK_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16); +static struct clk_regmap c3_pwm_j =3D + C3_PWM_CLK_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24); + +static struct clk_regmap c3_pwm_k_sel =3D + C3_PWM_CLK_MUX(pwm_k, PWM_CLK_KL_CTRL, 9); +static struct clk_regmap c3_pwm_k_div =3D + C3_PWM_CLK_DIV(pwm_k, PWM_CLK_KL_CTRL, 0); +static struct clk_regmap c3_pwm_k =3D + C3_PWM_CLK_GATE(pwm_k, PWM_CLK_KL_CTRL, 8); + +static struct clk_regmap c3_pwm_l_sel =3D + C3_PWM_CLK_MUX(pwm_l, PWM_CLK_KL_CTRL, 25); +static struct clk_regmap c3_pwm_l_div =3D + C3_PWM_CLK_DIV(pwm_l, PWM_CLK_KL_CTRL, 16); +static struct clk_regmap c3_pwm_l =3D + C3_PWM_CLK_GATE(pwm_l, PWM_CLK_KL_CTRL, 24); + +static struct clk_regmap c3_pwm_m_sel =3D + C3_PWM_CLK_MUX(pwm_m, PWM_CLK_MN_CTRL, 9); +static struct clk_regmap c3_pwm_m_div =3D + C3_PWM_CLK_DIV(pwm_m, PWM_CLK_MN_CTRL, 0); +static struct clk_regmap c3_pwm_m =3D + C3_PWM_CLK_GATE(pwm_m, PWM_CLK_MN_CTRL, 8); + +static struct clk_regmap c3_pwm_n_sel =3D + C3_PWM_CLK_MUX(pwm_n, PWM_CLK_MN_CTRL, 25); +static struct clk_regmap c3_pwm_n_div =3D + C3_PWM_CLK_DIV(pwm_n, PWM_CLK_MN_CTRL, 16); +static struct clk_regmap c3_pwm_n =3D + C3_PWM_CLK_GATE(pwm_n, PWM_CLK_MN_CTRL, 24); + +static const struct clk_parent_data c3_spicc_parents[] =3D { { .fw_name =3D "oscin" }, { .fw_name =3D "sysclk" }, { .fw_name =3D "fdiv4" }, @@ -681,7 +680,7 @@ static const struct clk_parent_data spicc_parent_data[]= =3D { { .fw_name =3D "gp1" } }; =20 -static struct clk_regmap spicc_a_sel =3D { +static struct clk_regmap c3_spicc_a_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D SPICC_CLK_CTRL, .mask =3D 0x7, @@ -690,12 +689,12 @@ static struct clk_regmap spicc_a_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "spicc_a_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D spicc_parent_data, - .num_parents =3D ARRAY_SIZE(spicc_parent_data), + .parent_data =3D c3_spicc_parents, + .num_parents =3D ARRAY_SIZE(c3_spicc_parents), }, }; =20 -static struct clk_regmap spicc_a_div =3D { +static struct clk_regmap c3_spicc_a_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D SPICC_CLK_CTRL, .shift =3D 0, @@ -705,14 +704,14 @@ static struct clk_regmap spicc_a_div =3D { .name =3D "spicc_a_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &spicc_a_sel.hw + &c3_spicc_a_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap spicc_a =3D { +static struct clk_regmap c3_spicc_a =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D SPICC_CLK_CTRL, .bit_idx =3D 6, @@ -721,14 +720,14 @@ static struct clk_regmap spicc_a =3D { .name =3D "spicc_a", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &spicc_a_div.hw + &c3_spicc_a_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap spicc_b_sel =3D { +static struct clk_regmap c3_spicc_b_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D SPICC_CLK_CTRL, .mask =3D 0x7, @@ -737,12 +736,12 @@ static struct clk_regmap spicc_b_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "spicc_b_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D spicc_parent_data, - .num_parents =3D ARRAY_SIZE(spicc_parent_data), + .parent_data =3D c3_spicc_parents, + .num_parents =3D ARRAY_SIZE(c3_spicc_parents), }, }; =20 -static struct clk_regmap spicc_b_div =3D { +static struct clk_regmap c3_spicc_b_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D SPICC_CLK_CTRL, .shift =3D 16, @@ -752,14 +751,14 @@ static struct clk_regmap spicc_b_div =3D { .name =3D "spicc_b_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &spicc_b_sel.hw + &c3_spicc_b_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap spicc_b =3D { +static struct clk_regmap c3_spicc_b =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D SPICC_CLK_CTRL, .bit_idx =3D 22, @@ -768,14 +767,14 @@ static struct clk_regmap spicc_b =3D { .name =3D "spicc_b", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &spicc_b_div.hw + &c3_spicc_b_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data spifc_parent_data[] =3D { +static const struct clk_parent_data c3_spifc_parents[] =3D { { .fw_name =3D "gp0" }, { .fw_name =3D "fdiv2" }, { .fw_name =3D "fdiv3" }, @@ -786,7 +785,7 @@ static const struct clk_parent_data spifc_parent_data[]= =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap spifc_sel =3D { +static struct clk_regmap c3_spifc_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D SPIFC_CLK_CTRL, .mask =3D 0x7, @@ -795,12 +794,12 @@ static struct clk_regmap spifc_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "spifc_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D spifc_parent_data, - .num_parents =3D ARRAY_SIZE(spifc_parent_data), + .parent_data =3D c3_spifc_parents, + .num_parents =3D ARRAY_SIZE(c3_spifc_parents), }, }; =20 -static struct clk_regmap spifc_div =3D { +static struct clk_regmap c3_spifc_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D SPIFC_CLK_CTRL, .shift =3D 0, @@ -810,14 +809,14 @@ static struct clk_regmap spifc_div =3D { .name =3D "spifc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &spifc_sel.hw + &c3_spifc_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap spifc =3D { +static struct clk_regmap c3_spifc =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D SPIFC_CLK_CTRL, .bit_idx =3D 8, @@ -826,14 +825,14 @@ static struct clk_regmap spifc =3D { .name =3D "spifc", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &spifc_div.hw + &c3_spifc_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data emmc_parent_data[] =3D { +static const struct clk_parent_data c3_sd_emmc_parents[] =3D { { .fw_name =3D "oscin" }, { .fw_name =3D "fdiv2" }, { .fw_name =3D "fdiv3" }, @@ -844,7 +843,7 @@ static const struct clk_parent_data emmc_parent_data[] = =3D { { .fw_name =3D "gp0" } }; =20 -static struct clk_regmap sd_emmc_a_sel =3D { +static struct clk_regmap c3_sd_emmc_a_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D SD_EMMC_CLK_CTRL, .mask =3D 0x7, @@ -853,12 +852,12 @@ static struct clk_regmap sd_emmc_a_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_a_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D emmc_parent_data, - .num_parents =3D ARRAY_SIZE(emmc_parent_data), + .parent_data =3D c3_sd_emmc_parents, + .num_parents =3D ARRAY_SIZE(c3_sd_emmc_parents), }, }; =20 -static struct clk_regmap sd_emmc_a_div =3D { +static struct clk_regmap c3_sd_emmc_a_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D SD_EMMC_CLK_CTRL, .shift =3D 0, @@ -868,14 +867,14 @@ static struct clk_regmap sd_emmc_a_div =3D { .name =3D "sd_emmc_a_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sd_emmc_a_sel.hw + &c3_sd_emmc_a_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap sd_emmc_a =3D { +static struct clk_regmap c3_sd_emmc_a =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D SD_EMMC_CLK_CTRL, .bit_idx =3D 7, @@ -884,14 +883,14 @@ static struct clk_regmap sd_emmc_a =3D { .name =3D "sd_emmc_a", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sd_emmc_a_div.hw + &c3_sd_emmc_a_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap sd_emmc_b_sel =3D { +static struct clk_regmap c3_sd_emmc_b_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D SD_EMMC_CLK_CTRL, .mask =3D 0x7, @@ -900,12 +899,12 @@ static struct clk_regmap sd_emmc_b_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_b_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D emmc_parent_data, - .num_parents =3D ARRAY_SIZE(emmc_parent_data), + .parent_data =3D c3_sd_emmc_parents, + .num_parents =3D ARRAY_SIZE(c3_sd_emmc_parents), }, }; =20 -static struct clk_regmap sd_emmc_b_div =3D { +static struct clk_regmap c3_sd_emmc_b_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D SD_EMMC_CLK_CTRL, .shift =3D 16, @@ -915,14 +914,14 @@ static struct clk_regmap sd_emmc_b_div =3D { .name =3D "sd_emmc_b_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sd_emmc_b_sel.hw + &c3_sd_emmc_b_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap sd_emmc_b =3D { +static struct clk_regmap c3_sd_emmc_b =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D SD_EMMC_CLK_CTRL, .bit_idx =3D 23, @@ -931,14 +930,14 @@ static struct clk_regmap sd_emmc_b =3D { .name =3D "sd_emmc_b", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sd_emmc_b_div.hw + &c3_sd_emmc_b_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap sd_emmc_c_sel =3D { +static struct clk_regmap c3_sd_emmc_c_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D NAND_CLK_CTRL, .mask =3D 0x7, @@ -947,12 +946,12 @@ static struct clk_regmap sd_emmc_c_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_c_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D emmc_parent_data, - .num_parents =3D ARRAY_SIZE(emmc_parent_data), + .parent_data =3D c3_sd_emmc_parents, + .num_parents =3D ARRAY_SIZE(c3_sd_emmc_parents), }, }; =20 -static struct clk_regmap sd_emmc_c_div =3D { +static struct clk_regmap c3_sd_emmc_c_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D NAND_CLK_CTRL, .shift =3D 0, @@ -962,14 +961,14 @@ static struct clk_regmap sd_emmc_c_div =3D { .name =3D "sd_emmc_c_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sd_emmc_c_sel.hw + &c3_sd_emmc_c_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap sd_emmc_c =3D { +static struct clk_regmap c3_sd_emmc_c =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D NAND_CLK_CTRL, .bit_idx =3D 7, @@ -978,14 +977,14 @@ static struct clk_regmap sd_emmc_c =3D { .name =3D "sd_emmc_c", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sd_emmc_c_div.hw + &c3_sd_emmc_c_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap ts_div =3D { +static struct clk_regmap c3_ts_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D TS_CLK_CTRL, .shift =3D 0, @@ -1001,7 +1000,7 @@ static struct clk_regmap ts_div =3D { }, }; =20 -static struct clk_regmap ts =3D { +static struct clk_regmap c3_ts =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D TS_CLK_CTRL, .bit_idx =3D 8, @@ -1010,29 +1009,29 @@ static struct clk_regmap ts =3D { .name =3D "ts", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &ts_div.hw + &c3_ts_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data eth_parent =3D { +static const struct clk_parent_data c3_eth_parents =3D { .fw_name =3D "fdiv2", }; =20 -static struct clk_fixed_factor eth_125m_div =3D { +static struct clk_fixed_factor c3_eth_125m_div =3D { .mult =3D 1, .div =3D 8, .hw.init =3D &(struct clk_init_data) { .name =3D "eth_125m_div", .ops =3D &clk_fixed_factor_ops, - .parent_data =3D ð_parent, + .parent_data =3D &c3_eth_parents, .num_parents =3D 1, }, }; =20 -static struct clk_regmap eth_125m =3D { +static struct clk_regmap c3_eth_125m =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ETH_CLK_CTRL, .bit_idx =3D 7, @@ -1041,14 +1040,14 @@ static struct clk_regmap eth_125m =3D { .name =3D "eth_125m", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - ð_125m_div.hw + &c3_eth_125m_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap eth_rmii_div =3D { +static struct clk_regmap c3_eth_rmii_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D ETH_CLK_CTRL, .shift =3D 0, @@ -1057,12 +1056,12 @@ static struct clk_regmap eth_rmii_div =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "eth_rmii_div", .ops =3D &clk_regmap_divider_ops, - .parent_data =3D ð_parent, + .parent_data =3D &c3_eth_parents, .num_parents =3D 1, }, }; =20 -static struct clk_regmap eth_rmii =3D { +static struct clk_regmap c3_eth_rmii =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ETH_CLK_CTRL, .bit_idx =3D 8, @@ -1071,14 +1070,14 @@ static struct clk_regmap eth_rmii =3D { .name =3D "eth_rmii", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - ð_rmii_div.hw + &c3_eth_rmii_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data mipi_dsi_meas_parent_data[] =3D { +static const struct clk_parent_data c3_mipi_dsi_meas_parents[] =3D { { .fw_name =3D "oscin" }, { .fw_name =3D "fdiv4" }, { .fw_name =3D "fdiv3" }, @@ -1089,7 +1088,7 @@ static const struct clk_parent_data mipi_dsi_meas_par= ent_data[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap mipi_dsi_meas_sel =3D { +static struct clk_regmap c3_mipi_dsi_meas_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D VDIN_MEAS_CLK_CTRL, .mask =3D 0x7, @@ -1098,12 +1097,12 @@ static struct clk_regmap mipi_dsi_meas_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "mipi_dsi_meas_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D mipi_dsi_meas_parent_data, - .num_parents =3D ARRAY_SIZE(mipi_dsi_meas_parent_data), + .parent_data =3D c3_mipi_dsi_meas_parents, + .num_parents =3D ARRAY_SIZE(c3_mipi_dsi_meas_parents), }, }; =20 -static struct clk_regmap mipi_dsi_meas_div =3D { +static struct clk_regmap c3_mipi_dsi_meas_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D VDIN_MEAS_CLK_CTRL, .shift =3D 12, @@ -1113,14 +1112,14 @@ static struct clk_regmap mipi_dsi_meas_div =3D { .name =3D "mipi_dsi_meas_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &mipi_dsi_meas_sel.hw + &c3_mipi_dsi_meas_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap mipi_dsi_meas =3D { +static struct clk_regmap c3_mipi_dsi_meas =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D VDIN_MEAS_CLK_CTRL, .bit_idx =3D 20, @@ -1129,14 +1128,14 @@ static struct clk_regmap mipi_dsi_meas =3D { .name =3D "mipi_dsi_meas", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &mipi_dsi_meas_div.hw + &c3_mipi_dsi_meas_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data dsi_phy_parent_data[] =3D { +static const struct clk_parent_data c3_dsi_phy_parents[] =3D { { .fw_name =3D "gp1" }, { .fw_name =3D "gp0" }, { .fw_name =3D "hifi" }, @@ -1147,7 +1146,7 @@ static const struct clk_parent_data dsi_phy_parent_da= ta[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap dsi_phy_sel =3D { +static struct clk_regmap c3_dsi_phy_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D MIPIDSI_PHY_CLK_CTRL, .mask =3D 0x7, @@ -1156,12 +1155,12 @@ static struct clk_regmap dsi_phy_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "dsi_phy_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D dsi_phy_parent_data, - .num_parents =3D ARRAY_SIZE(dsi_phy_parent_data), + .parent_data =3D c3_dsi_phy_parents, + .num_parents =3D ARRAY_SIZE(c3_dsi_phy_parents), }, }; =20 -static struct clk_regmap dsi_phy_div =3D { +static struct clk_regmap c3_dsi_phy_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D MIPIDSI_PHY_CLK_CTRL, .shift =3D 0, @@ -1171,14 +1170,14 @@ static struct clk_regmap dsi_phy_div =3D { .name =3D "dsi_phy_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dsi_phy_sel.hw + &c3_dsi_phy_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dsi_phy =3D { +static struct clk_regmap c3_dsi_phy =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D MIPIDSI_PHY_CLK_CTRL, .bit_idx =3D 8, @@ -1187,14 +1186,14 @@ static struct clk_regmap dsi_phy =3D { .name =3D "dsi_phy", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dsi_phy_div.hw + &c3_dsi_phy_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data vout_mclk_parent_data[] =3D { +static const struct clk_parent_data c3_vout_mclk_parents[] =3D { { .fw_name =3D "fdiv2p5" }, { .fw_name =3D "fdiv3" }, { .fw_name =3D "fdiv4" }, @@ -1205,7 +1204,7 @@ static const struct clk_parent_data vout_mclk_parent_= data[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap vout_mclk_sel =3D { +static struct clk_regmap c3_vout_mclk_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D VOUTENC_CLK_CTRL, .mask =3D 0x7, @@ -1214,12 +1213,12 @@ static struct clk_regmap vout_mclk_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "vout_mclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D vout_mclk_parent_data, - .num_parents =3D ARRAY_SIZE(vout_mclk_parent_data), + .parent_data =3D c3_vout_mclk_parents, + .num_parents =3D ARRAY_SIZE(c3_vout_mclk_parents), }, }; =20 -static struct clk_regmap vout_mclk_div =3D { +static struct clk_regmap c3_vout_mclk_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D VOUTENC_CLK_CTRL, .shift =3D 0, @@ -1229,14 +1228,14 @@ static struct clk_regmap vout_mclk_div =3D { .name =3D "vout_mclk_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &vout_mclk_sel.hw + &c3_vout_mclk_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap vout_mclk =3D { +static struct clk_regmap c3_vout_mclk =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D VOUTENC_CLK_CTRL, .bit_idx =3D 8, @@ -1245,14 +1244,14 @@ static struct clk_regmap vout_mclk =3D { .name =3D "vout_mclk", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &vout_mclk_div.hw + &c3_vout_mclk_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data vout_enc_parent_data[] =3D { +static const struct clk_parent_data c3_vout_enc_parents[] =3D { { .fw_name =3D "gp1" }, { .fw_name =3D "fdiv3" }, { .fw_name =3D "fdiv4" }, @@ -1263,7 +1262,7 @@ static const struct clk_parent_data vout_enc_parent_d= ata[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap vout_enc_sel =3D { +static struct clk_regmap c3_vout_enc_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D VOUTENC_CLK_CTRL, .mask =3D 0x7, @@ -1272,12 +1271,12 @@ static struct clk_regmap vout_enc_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "vout_enc_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D vout_enc_parent_data, - .num_parents =3D ARRAY_SIZE(vout_enc_parent_data), + .parent_data =3D c3_vout_enc_parents, + .num_parents =3D ARRAY_SIZE(c3_vout_enc_parents), }, }; =20 -static struct clk_regmap vout_enc_div =3D { +static struct clk_regmap c3_vout_enc_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D VOUTENC_CLK_CTRL, .shift =3D 16, @@ -1287,14 +1286,14 @@ static struct clk_regmap vout_enc_div =3D { .name =3D "vout_enc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &vout_enc_sel.hw + &c3_vout_enc_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap vout_enc =3D { +static struct clk_regmap c3_vout_enc =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D VOUTENC_CLK_CTRL, .bit_idx =3D 24, @@ -1303,14 +1302,14 @@ static struct clk_regmap vout_enc =3D { .name =3D "vout_enc", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &vout_enc_div.hw + &c3_vout_enc_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data hcodec_pre_parent_data[] =3D { +static const struct clk_parent_data c3_hcodec_pre_parents[] =3D { { .fw_name =3D "fdiv2p5" }, { .fw_name =3D "fdiv3" }, { .fw_name =3D "fdiv4" }, @@ -1321,7 +1320,7 @@ static const struct clk_parent_data hcodec_pre_parent= _data[] =3D { { .fw_name =3D "oscin" } }; =20 -static struct clk_regmap hcodec_0_sel =3D { +static struct clk_regmap c3_hcodec_0_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D VDEC_CLK_CTRL, .mask =3D 0x7, @@ -1330,12 +1329,12 @@ static struct clk_regmap hcodec_0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "hcodec_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D hcodec_pre_parent_data, - .num_parents =3D ARRAY_SIZE(hcodec_pre_parent_data), + .parent_data =3D c3_hcodec_pre_parents, + .num_parents =3D ARRAY_SIZE(c3_hcodec_pre_parents), }, }; =20 -static struct clk_regmap hcodec_0_div =3D { +static struct clk_regmap c3_hcodec_0_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D VDEC_CLK_CTRL, .shift =3D 0, @@ -1345,14 +1344,14 @@ static struct clk_regmap hcodec_0_div =3D { .name =3D "hcodec_0_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &hcodec_0_sel.hw + &c3_hcodec_0_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap hcodec_0 =3D { +static struct clk_regmap c3_hcodec_0 =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D VDEC_CLK_CTRL, .bit_idx =3D 8, @@ -1361,14 +1360,14 @@ static struct clk_regmap hcodec_0 =3D { .name =3D "hcodec_0", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &hcodec_0_div.hw + &c3_hcodec_0_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap hcodec_1_sel =3D { +static struct clk_regmap c3_hcodec_1_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D VDEC3_CLK_CTRL, .mask =3D 0x7, @@ -1377,12 +1376,12 @@ static struct clk_regmap hcodec_1_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "hcodec_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D hcodec_pre_parent_data, - .num_parents =3D ARRAY_SIZE(hcodec_pre_parent_data), + .parent_data =3D c3_hcodec_pre_parents, + .num_parents =3D ARRAY_SIZE(c3_hcodec_pre_parents), }, }; =20 -static struct clk_regmap hcodec_1_div =3D { +static struct clk_regmap c3_hcodec_1_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D VDEC3_CLK_CTRL, .shift =3D 0, @@ -1392,14 +1391,14 @@ static struct clk_regmap hcodec_1_div =3D { .name =3D "hcodec_1_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &hcodec_1_sel.hw + &c3_hcodec_1_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap hcodec_1 =3D { +static struct clk_regmap c3_hcodec_1 =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D VDEC3_CLK_CTRL, .bit_idx =3D 8, @@ -1408,19 +1407,19 @@ static struct clk_regmap hcodec_1 =3D { .name =3D "hcodec_1", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &hcodec_1_div.hw + &c3_hcodec_1_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data hcodec_parent_data[] =3D { - { .hw =3D &hcodec_0.hw }, - { .hw =3D &hcodec_1.hw } +static const struct clk_parent_data c3_hcodec_parents[] =3D { + { .hw =3D &c3_hcodec_0.hw }, + { .hw =3D &c3_hcodec_1.hw } }; =20 -static struct clk_regmap hcodec =3D { +static struct clk_regmap c3_hcodec =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D VDEC3_CLK_CTRL, .mask =3D 0x1, @@ -1429,13 +1428,13 @@ static struct clk_regmap hcodec =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "hcodec", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D hcodec_parent_data, - .num_parents =3D ARRAY_SIZE(hcodec_parent_data), + .parent_data =3D c3_hcodec_parents, + .num_parents =3D ARRAY_SIZE(c3_hcodec_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data vc9000e_parent_data[] =3D { +static const struct clk_parent_data c3_vc9000e_parents[] =3D { { .fw_name =3D "oscin" }, { .fw_name =3D "fdiv4" }, { .fw_name =3D "fdiv3" }, @@ -1446,7 +1445,7 @@ static const struct clk_parent_data vc9000e_parent_da= ta[] =3D { { .fw_name =3D "gp0" } }; =20 -static struct clk_regmap vc9000e_aclk_sel =3D { +static struct clk_regmap c3_vc9000e_aclk_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D VC9000E_CLK_CTRL, .mask =3D 0x7, @@ -1455,12 +1454,12 @@ static struct clk_regmap vc9000e_aclk_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "vc9000e_aclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D vc9000e_parent_data, - .num_parents =3D ARRAY_SIZE(vc9000e_parent_data), + .parent_data =3D c3_vc9000e_parents, + .num_parents =3D ARRAY_SIZE(c3_vc9000e_parents), }, }; =20 -static struct clk_regmap vc9000e_aclk_div =3D { +static struct clk_regmap c3_vc9000e_aclk_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D VC9000E_CLK_CTRL, .shift =3D 0, @@ -1470,14 +1469,14 @@ static struct clk_regmap vc9000e_aclk_div =3D { .name =3D "vc9000e_aclk_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &vc9000e_aclk_sel.hw + &c3_vc9000e_aclk_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap vc9000e_aclk =3D { +static struct clk_regmap c3_vc9000e_aclk =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D VC9000E_CLK_CTRL, .bit_idx =3D 8, @@ -1486,14 +1485,14 @@ static struct clk_regmap vc9000e_aclk =3D { .name =3D "vc9000e_aclk", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &vc9000e_aclk_div.hw + &c3_vc9000e_aclk_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap vc9000e_core_sel =3D { +static struct clk_regmap c3_vc9000e_core_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D VC9000E_CLK_CTRL, .mask =3D 0x7, @@ -1502,12 +1501,12 @@ static struct clk_regmap vc9000e_core_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "vc9000e_core_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D vc9000e_parent_data, - .num_parents =3D ARRAY_SIZE(vc9000e_parent_data), + .parent_data =3D c3_vc9000e_parents, + .num_parents =3D ARRAY_SIZE(c3_vc9000e_parents), }, }; =20 -static struct clk_regmap vc9000e_core_div =3D { +static struct clk_regmap c3_vc9000e_core_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D VC9000E_CLK_CTRL, .shift =3D 16, @@ -1517,14 +1516,14 @@ static struct clk_regmap vc9000e_core_div =3D { .name =3D "vc9000e_core_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &vc9000e_core_sel.hw + &c3_vc9000e_core_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap vc9000e_core =3D { +static struct clk_regmap c3_vc9000e_core =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D VC9000E_CLK_CTRL, .bit_idx =3D 24, @@ -1533,14 +1532,14 @@ static struct clk_regmap vc9000e_core =3D { .name =3D "vc9000e_core", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &vc9000e_core_div.hw + &c3_vc9000e_core_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data csi_phy_parent_data[] =3D { +static const struct clk_parent_data c3_csi_phy_parents[] =3D { { .fw_name =3D "fdiv2p5" }, { .fw_name =3D "fdiv3" }, { .fw_name =3D "fdiv4" }, @@ -1551,7 +1550,7 @@ static const struct clk_parent_data csi_phy_parent_da= ta[] =3D { { .fw_name =3D "oscin" } }; =20 -static struct clk_regmap csi_phy0_sel =3D { +static struct clk_regmap c3_csi_phy0_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D ISP0_CLK_CTRL, .mask =3D 0x7, @@ -1560,12 +1559,12 @@ static struct clk_regmap csi_phy0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "csi_phy0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D csi_phy_parent_data, - .num_parents =3D ARRAY_SIZE(csi_phy_parent_data), + .parent_data =3D c3_csi_phy_parents, + .num_parents =3D ARRAY_SIZE(c3_csi_phy_parents), }, }; =20 -static struct clk_regmap csi_phy0_div =3D { +static struct clk_regmap c3_csi_phy0_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D ISP0_CLK_CTRL, .shift =3D 16, @@ -1575,14 +1574,14 @@ static struct clk_regmap csi_phy0_div =3D { .name =3D "csi_phy0_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &csi_phy0_sel.hw + &c3_csi_phy0_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap csi_phy0 =3D { +static struct clk_regmap c3_csi_phy0 =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ISP0_CLK_CTRL, .bit_idx =3D 24, @@ -1591,14 +1590,14 @@ static struct clk_regmap csi_phy0 =3D { .name =3D "csi_phy0", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &csi_phy0_div.hw + &c3_csi_phy0_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data dewarpa_parent_data[] =3D { +static const struct clk_parent_data c3_dewarpa_parents[] =3D { { .fw_name =3D "fdiv2p5" }, { .fw_name =3D "fdiv3" }, { .fw_name =3D "fdiv4" }, @@ -1609,7 +1608,7 @@ static const struct clk_parent_data dewarpa_parent_da= ta[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap dewarpa_sel =3D { +static struct clk_regmap c3_dewarpa_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D DEWARPA_CLK_CTRL, .mask =3D 0x7, @@ -1618,12 +1617,12 @@ static struct clk_regmap dewarpa_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "dewarpa_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D dewarpa_parent_data, - .num_parents =3D ARRAY_SIZE(dewarpa_parent_data), + .parent_data =3D c3_dewarpa_parents, + .num_parents =3D ARRAY_SIZE(c3_dewarpa_parents), }, }; =20 -static struct clk_regmap dewarpa_div =3D { +static struct clk_regmap c3_dewarpa_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D DEWARPA_CLK_CTRL, .shift =3D 0, @@ -1633,14 +1632,14 @@ static struct clk_regmap dewarpa_div =3D { .name =3D "dewarpa_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dewarpa_sel.hw + &c3_dewarpa_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap dewarpa =3D { +static struct clk_regmap c3_dewarpa =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D DEWARPA_CLK_CTRL, .bit_idx =3D 8, @@ -1649,14 +1648,14 @@ static struct clk_regmap dewarpa =3D { .name =3D "dewarpa", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &dewarpa_div.hw + &c3_dewarpa_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data isp_parent_data[] =3D { +static const struct clk_parent_data c3_isp_parents[] =3D { { .fw_name =3D "fdiv2p5" }, { .fw_name =3D "fdiv3" }, { .fw_name =3D "fdiv4" }, @@ -1667,7 +1666,7 @@ static const struct clk_parent_data isp_parent_data[]= =3D { { .fw_name =3D "oscin" } }; =20 -static struct clk_regmap isp0_sel =3D { +static struct clk_regmap c3_isp0_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D ISP0_CLK_CTRL, .mask =3D 0x7, @@ -1676,12 +1675,12 @@ static struct clk_regmap isp0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "isp0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D isp_parent_data, - .num_parents =3D ARRAY_SIZE(isp_parent_data), + .parent_data =3D c3_isp_parents, + .num_parents =3D ARRAY_SIZE(c3_isp_parents), }, }; =20 -static struct clk_regmap isp0_div =3D { +static struct clk_regmap c3_isp0_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D ISP0_CLK_CTRL, .shift =3D 0, @@ -1691,14 +1690,14 @@ static struct clk_regmap isp0_div =3D { .name =3D "isp0_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &isp0_sel.hw + &c3_isp0_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap isp0 =3D { +static struct clk_regmap c3_isp0 =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ISP0_CLK_CTRL, .bit_idx =3D 8, @@ -1707,14 +1706,14 @@ static struct clk_regmap isp0 =3D { .name =3D "isp0", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &isp0_div.hw + &c3_isp0_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data nna_core_parent_data[] =3D { +static const struct clk_parent_data c3_nna_core_parents[] =3D { { .fw_name =3D "oscin" }, { .fw_name =3D "fdiv2p5" }, { .fw_name =3D "fdiv4" }, @@ -1725,7 +1724,7 @@ static const struct clk_parent_data nna_core_parent_d= ata[] =3D { { .fw_name =3D "hifi" } }; =20 -static struct clk_regmap nna_core_sel =3D { +static struct clk_regmap c3_nna_core_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D NNA_CLK_CTRL, .mask =3D 0x7, @@ -1734,12 +1733,12 @@ static struct clk_regmap nna_core_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "nna_core_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D nna_core_parent_data, - .num_parents =3D ARRAY_SIZE(nna_core_parent_data), + .parent_data =3D c3_nna_core_parents, + .num_parents =3D ARRAY_SIZE(c3_nna_core_parents), }, }; =20 -static struct clk_regmap nna_core_div =3D { +static struct clk_regmap c3_nna_core_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D NNA_CLK_CTRL, .shift =3D 0, @@ -1749,14 +1748,14 @@ static struct clk_regmap nna_core_div =3D { .name =3D "nna_core_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &nna_core_sel.hw + &c3_nna_core_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap nna_core =3D { +static struct clk_regmap c3_nna_core =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D NNA_CLK_CTRL, .bit_idx =3D 8, @@ -1765,14 +1764,14 @@ static struct clk_regmap nna_core =3D { .name =3D "nna_core", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &nna_core_div.hw + &c3_nna_core_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data ge2d_parent_data[] =3D { +static const struct clk_parent_data c3_ge2d_parents[] =3D { { .fw_name =3D "oscin" }, { .fw_name =3D "fdiv2p5" }, { .fw_name =3D "fdiv3" }, @@ -1780,10 +1779,10 @@ static const struct clk_parent_data ge2d_parent_dat= a[] =3D { { .fw_name =3D "hifi" }, { .fw_name =3D "fdiv5" }, { .fw_name =3D "gp0" }, - { .hw =3D &rtc_clk.hw } + { .hw =3D &c3_rtc_clk.hw } }; =20 -static struct clk_regmap ge2d_sel =3D { +static struct clk_regmap c3_ge2d_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D GE2D_CLK_CTRL, .mask =3D 0x7, @@ -1792,12 +1791,12 @@ static struct clk_regmap ge2d_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "ge2d_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D ge2d_parent_data, - .num_parents =3D ARRAY_SIZE(ge2d_parent_data), + .parent_data =3D c3_ge2d_parents, + .num_parents =3D ARRAY_SIZE(c3_ge2d_parents), }, }; =20 -static struct clk_regmap ge2d_div =3D { +static struct clk_regmap c3_ge2d_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D GE2D_CLK_CTRL, .shift =3D 0, @@ -1807,14 +1806,14 @@ static struct clk_regmap ge2d_div =3D { .name =3D "ge2d_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &ge2d_sel.hw + &c3_ge2d_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap ge2d =3D { +static struct clk_regmap c3_ge2d =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D GE2D_CLK_CTRL, .bit_idx =3D 8, @@ -1823,14 +1822,14 @@ static struct clk_regmap ge2d =3D { .name =3D "ge2d", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &ge2d_div.hw + &c3_ge2d_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data vapb_parent_data[] =3D { +static const struct clk_parent_data c3_vapb_parents[] =3D { { .fw_name =3D "fdiv2p5" }, { .fw_name =3D "fdiv3" }, { .fw_name =3D "fdiv4" }, @@ -1841,7 +1840,7 @@ static const struct clk_parent_data vapb_parent_data[= ] =3D { { .fw_name =3D "oscin" }, }; =20 -static struct clk_regmap vapb_sel =3D { +static struct clk_regmap c3_vapb_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D VAPB_CLK_CTRL, .mask =3D 0x7, @@ -1850,12 +1849,12 @@ static struct clk_regmap vapb_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "vapb_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D vapb_parent_data, - .num_parents =3D ARRAY_SIZE(vapb_parent_data), + .parent_data =3D c3_vapb_parents, + .num_parents =3D ARRAY_SIZE(c3_vapb_parents), }, }; =20 -static struct clk_regmap vapb_div =3D { +static struct clk_regmap c3_vapb_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D VAPB_CLK_CTRL, .shift =3D 0, @@ -1865,14 +1864,14 @@ static struct clk_regmap vapb_div =3D { .name =3D "vapb_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &vapb_sel.hw + &c3_vapb_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap vapb =3D { +static struct clk_regmap c3_vapb =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D VAPB_CLK_CTRL, .bit_idx =3D 8, @@ -1881,230 +1880,230 @@ static struct clk_regmap vapb =3D { .name =3D "vapb", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &vapb_div.hw + &c3_vapb_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_hw *c3_periphs_hw_clks[] =3D { - [CLKID_RTC_XTAL_CLKIN] =3D &rtc_xtal_clkin.hw, - [CLKID_RTC_32K_DIV] =3D &rtc_32k_div.hw, - [CLKID_RTC_32K_MUX] =3D &rtc_32k_mux.hw, - [CLKID_RTC_32K] =3D &rtc_32k.hw, - [CLKID_RTC_CLK] =3D &rtc_clk.hw, - [CLKID_SYS_RESET_CTRL] =3D &sys_reset_ctrl.hw, - [CLKID_SYS_PWR_CTRL] =3D &sys_pwr_ctrl.hw, - [CLKID_SYS_PAD_CTRL] =3D &sys_pad_ctrl.hw, - [CLKID_SYS_CTRL] =3D &sys_ctrl.hw, - [CLKID_SYS_TS_PLL] =3D &sys_ts_pll.hw, - [CLKID_SYS_DEV_ARB] =3D &sys_dev_arb.hw, - [CLKID_SYS_MMC_PCLK] =3D &sys_mmc_pclk.hw, - [CLKID_SYS_CPU_CTRL] =3D &sys_cpu_ctrl.hw, - [CLKID_SYS_JTAG_CTRL] =3D &sys_jtag_ctrl.hw, - [CLKID_SYS_IR_CTRL] =3D &sys_ir_ctrl.hw, - [CLKID_SYS_IRQ_CTRL] =3D &sys_irq_ctrl.hw, - [CLKID_SYS_MSR_CLK] =3D &sys_msr_clk.hw, - [CLKID_SYS_ROM] =3D &sys_rom.hw, - [CLKID_SYS_UART_F] =3D &sys_uart_f.hw, - [CLKID_SYS_CPU_ARB] =3D &sys_cpu_apb.hw, - [CLKID_SYS_RSA] =3D &sys_rsa.hw, - [CLKID_SYS_SAR_ADC] =3D &sys_sar_adc.hw, - [CLKID_SYS_STARTUP] =3D &sys_startup.hw, - [CLKID_SYS_SECURE] =3D &sys_secure.hw, - [CLKID_SYS_SPIFC] =3D &sys_spifc.hw, - [CLKID_SYS_NNA] =3D &sys_nna.hw, - [CLKID_SYS_ETH_MAC] =3D &sys_eth_mac.hw, - [CLKID_SYS_GIC] =3D &sys_gic.hw, - [CLKID_SYS_RAMA] =3D &sys_rama.hw, - [CLKID_SYS_BIG_NIC] =3D &sys_big_nic.hw, - [CLKID_SYS_RAMB] =3D &sys_ramb.hw, - [CLKID_SYS_AUDIO_PCLK] =3D &sys_audio_pclk.hw, - [CLKID_SYS_PWM_KL] =3D &sys_pwm_kl.hw, - [CLKID_SYS_PWM_IJ] =3D &sys_pwm_ij.hw, - [CLKID_SYS_USB] =3D &sys_usb.hw, - [CLKID_SYS_SD_EMMC_A] =3D &sys_sd_emmc_a.hw, - [CLKID_SYS_SD_EMMC_C] =3D &sys_sd_emmc_c.hw, - [CLKID_SYS_PWM_AB] =3D &sys_pwm_ab.hw, - [CLKID_SYS_PWM_CD] =3D &sys_pwm_cd.hw, - [CLKID_SYS_PWM_EF] =3D &sys_pwm_ef.hw, - [CLKID_SYS_PWM_GH] =3D &sys_pwm_gh.hw, - [CLKID_SYS_SPICC_1] =3D &sys_spicc_1.hw, - [CLKID_SYS_SPICC_0] =3D &sys_spicc_0.hw, - [CLKID_SYS_UART_A] =3D &sys_uart_a.hw, - [CLKID_SYS_UART_B] =3D &sys_uart_b.hw, - [CLKID_SYS_UART_C] =3D &sys_uart_c.hw, - [CLKID_SYS_UART_D] =3D &sys_uart_d.hw, - [CLKID_SYS_UART_E] =3D &sys_uart_e.hw, - [CLKID_SYS_I2C_M_A] =3D &sys_i2c_m_a.hw, - [CLKID_SYS_I2C_M_B] =3D &sys_i2c_m_b.hw, - [CLKID_SYS_I2C_M_C] =3D &sys_i2c_m_c.hw, - [CLKID_SYS_I2C_M_D] =3D &sys_i2c_m_d.hw, - [CLKID_SYS_I2S_S_A] =3D &sys_i2c_s_a.hw, - [CLKID_SYS_RTC] =3D &sys_rtc.hw, - [CLKID_SYS_GE2D] =3D &sys_ge2d.hw, - [CLKID_SYS_ISP] =3D &sys_isp.hw, - [CLKID_SYS_GPV_ISP_NIC] =3D &sys_gpv_isp_nic.hw, - [CLKID_SYS_GPV_CVE_NIC] =3D &sys_gpv_cve_nic.hw, - [CLKID_SYS_MIPI_DSI_HOST] =3D &sys_mipi_dsi_host.hw, - [CLKID_SYS_MIPI_DSI_PHY] =3D &sys_mipi_dsi_phy.hw, - [CLKID_SYS_ETH_PHY] =3D &sys_eth_phy.hw, - [CLKID_SYS_ACODEC] =3D &sys_acodec.hw, - [CLKID_SYS_DWAP] =3D &sys_dwap.hw, - [CLKID_SYS_DOS] =3D &sys_dos.hw, - [CLKID_SYS_CVE] =3D &sys_cve.hw, - [CLKID_SYS_VOUT] =3D &sys_vout.hw, - [CLKID_SYS_VC9000E] =3D &sys_vc9000e.hw, - [CLKID_SYS_PWM_MN] =3D &sys_pwm_mn.hw, - [CLKID_SYS_SD_EMMC_B] =3D &sys_sd_emmc_b.hw, - [CLKID_AXI_SYS_NIC] =3D &axi_sys_nic.hw, - [CLKID_AXI_ISP_NIC] =3D &axi_isp_nic.hw, - [CLKID_AXI_CVE_NIC] =3D &axi_cve_nic.hw, - [CLKID_AXI_RAMB] =3D &axi_ramb.hw, - [CLKID_AXI_RAMA] =3D &axi_rama.hw, - [CLKID_AXI_CPU_DMC] =3D &axi_cpu_dmc.hw, - [CLKID_AXI_NIC] =3D &axi_nic.hw, - [CLKID_AXI_DMA] =3D &axi_dma.hw, - [CLKID_AXI_MUX_NIC] =3D &axi_mux_nic.hw, - [CLKID_AXI_CVE] =3D &axi_cve.hw, - [CLKID_AXI_DEV1_DMC] =3D &axi_dev1_dmc.hw, - [CLKID_AXI_DEV0_DMC] =3D &axi_dev0_dmc.hw, - [CLKID_AXI_DSP_DMC] =3D &axi_dsp_dmc.hw, - [CLKID_12_24M_IN] =3D &clk_12_24m_in.hw, - [CLKID_12M_24M] =3D &clk_12_24m.hw, - [CLKID_FCLK_25M_DIV] =3D &fclk_25m_div.hw, - [CLKID_FCLK_25M] =3D &fclk_25m.hw, - [CLKID_GEN_SEL] =3D &gen_sel.hw, - [CLKID_GEN_DIV] =3D &gen_div.hw, - [CLKID_GEN] =3D &gen.hw, - [CLKID_SARADC_SEL] =3D &saradc_sel.hw, - [CLKID_SARADC_DIV] =3D &saradc_div.hw, - [CLKID_SARADC] =3D &saradc.hw, - [CLKID_PWM_A_SEL] =3D &pwm_a_sel.hw, - [CLKID_PWM_A_DIV] =3D &pwm_a_div.hw, - [CLKID_PWM_A] =3D &pwm_a.hw, - [CLKID_PWM_B_SEL] =3D &pwm_b_sel.hw, - [CLKID_PWM_B_DIV] =3D &pwm_b_div.hw, - [CLKID_PWM_B] =3D &pwm_b.hw, - [CLKID_PWM_C_SEL] =3D &pwm_c_sel.hw, - [CLKID_PWM_C_DIV] =3D &pwm_c_div.hw, - [CLKID_PWM_C] =3D &pwm_c.hw, - [CLKID_PWM_D_SEL] =3D &pwm_d_sel.hw, - [CLKID_PWM_D_DIV] =3D &pwm_d_div.hw, - [CLKID_PWM_D] =3D &pwm_d.hw, - [CLKID_PWM_E_SEL] =3D &pwm_e_sel.hw, - [CLKID_PWM_E_DIV] =3D &pwm_e_div.hw, - [CLKID_PWM_E] =3D &pwm_e.hw, - [CLKID_PWM_F_SEL] =3D &pwm_f_sel.hw, - [CLKID_PWM_F_DIV] =3D &pwm_f_div.hw, - [CLKID_PWM_F] =3D &pwm_f.hw, - [CLKID_PWM_G_SEL] =3D &pwm_g_sel.hw, - [CLKID_PWM_G_DIV] =3D &pwm_g_div.hw, - [CLKID_PWM_G] =3D &pwm_g.hw, - [CLKID_PWM_H_SEL] =3D &pwm_h_sel.hw, - [CLKID_PWM_H_DIV] =3D &pwm_h_div.hw, - [CLKID_PWM_H] =3D &pwm_h.hw, - [CLKID_PWM_I_SEL] =3D &pwm_i_sel.hw, - [CLKID_PWM_I_DIV] =3D &pwm_i_div.hw, - [CLKID_PWM_I] =3D &pwm_i.hw, - [CLKID_PWM_J_SEL] =3D &pwm_j_sel.hw, - [CLKID_PWM_J_DIV] =3D &pwm_j_div.hw, - [CLKID_PWM_J] =3D &pwm_j.hw, - [CLKID_PWM_K_SEL] =3D &pwm_k_sel.hw, - [CLKID_PWM_K_DIV] =3D &pwm_k_div.hw, - [CLKID_PWM_K] =3D &pwm_k.hw, - [CLKID_PWM_L_SEL] =3D &pwm_l_sel.hw, - [CLKID_PWM_L_DIV] =3D &pwm_l_div.hw, - [CLKID_PWM_L] =3D &pwm_l.hw, - [CLKID_PWM_M_SEL] =3D &pwm_m_sel.hw, - [CLKID_PWM_M_DIV] =3D &pwm_m_div.hw, - [CLKID_PWM_M] =3D &pwm_m.hw, - [CLKID_PWM_N_SEL] =3D &pwm_n_sel.hw, - [CLKID_PWM_N_DIV] =3D &pwm_n_div.hw, - [CLKID_PWM_N] =3D &pwm_n.hw, - [CLKID_SPICC_A_SEL] =3D &spicc_a_sel.hw, - [CLKID_SPICC_A_DIV] =3D &spicc_a_div.hw, - [CLKID_SPICC_A] =3D &spicc_a.hw, - [CLKID_SPICC_B_SEL] =3D &spicc_b_sel.hw, - [CLKID_SPICC_B_DIV] =3D &spicc_b_div.hw, - [CLKID_SPICC_B] =3D &spicc_b.hw, - [CLKID_SPIFC_SEL] =3D &spifc_sel.hw, - [CLKID_SPIFC_DIV] =3D &spifc_div.hw, - [CLKID_SPIFC] =3D &spifc.hw, - [CLKID_SD_EMMC_A_SEL] =3D &sd_emmc_a_sel.hw, - [CLKID_SD_EMMC_A_DIV] =3D &sd_emmc_a_div.hw, - [CLKID_SD_EMMC_A] =3D &sd_emmc_a.hw, - [CLKID_SD_EMMC_B_SEL] =3D &sd_emmc_b_sel.hw, - [CLKID_SD_EMMC_B_DIV] =3D &sd_emmc_b_div.hw, - [CLKID_SD_EMMC_B] =3D &sd_emmc_b.hw, - [CLKID_SD_EMMC_C_SEL] =3D &sd_emmc_c_sel.hw, - [CLKID_SD_EMMC_C_DIV] =3D &sd_emmc_c_div.hw, - [CLKID_SD_EMMC_C] =3D &sd_emmc_c.hw, - [CLKID_TS_DIV] =3D &ts_div.hw, - [CLKID_TS] =3D &ts.hw, - [CLKID_ETH_125M_DIV] =3D ð_125m_div.hw, - [CLKID_ETH_125M] =3D ð_125m.hw, - [CLKID_ETH_RMII_DIV] =3D ð_rmii_div.hw, - [CLKID_ETH_RMII] =3D ð_rmii.hw, - [CLKID_MIPI_DSI_MEAS_SEL] =3D &mipi_dsi_meas_sel.hw, - [CLKID_MIPI_DSI_MEAS_DIV] =3D &mipi_dsi_meas_div.hw, - [CLKID_MIPI_DSI_MEAS] =3D &mipi_dsi_meas.hw, - [CLKID_DSI_PHY_SEL] =3D &dsi_phy_sel.hw, - [CLKID_DSI_PHY_DIV] =3D &dsi_phy_div.hw, - [CLKID_DSI_PHY] =3D &dsi_phy.hw, - [CLKID_VOUT_MCLK_SEL] =3D &vout_mclk_sel.hw, - [CLKID_VOUT_MCLK_DIV] =3D &vout_mclk_div.hw, - [CLKID_VOUT_MCLK] =3D &vout_mclk.hw, - [CLKID_VOUT_ENC_SEL] =3D &vout_enc_sel.hw, - [CLKID_VOUT_ENC_DIV] =3D &vout_enc_div.hw, - [CLKID_VOUT_ENC] =3D &vout_enc.hw, - [CLKID_HCODEC_0_SEL] =3D &hcodec_0_sel.hw, - [CLKID_HCODEC_0_DIV] =3D &hcodec_0_div.hw, - [CLKID_HCODEC_0] =3D &hcodec_0.hw, - [CLKID_HCODEC_1_SEL] =3D &hcodec_1_sel.hw, - [CLKID_HCODEC_1_DIV] =3D &hcodec_1_div.hw, - [CLKID_HCODEC_1] =3D &hcodec_1.hw, - [CLKID_HCODEC] =3D &hcodec.hw, - [CLKID_VC9000E_ACLK_SEL] =3D &vc9000e_aclk_sel.hw, - [CLKID_VC9000E_ACLK_DIV] =3D &vc9000e_aclk_div.hw, - [CLKID_VC9000E_ACLK] =3D &vc9000e_aclk.hw, - [CLKID_VC9000E_CORE_SEL] =3D &vc9000e_core_sel.hw, - [CLKID_VC9000E_CORE_DIV] =3D &vc9000e_core_div.hw, - [CLKID_VC9000E_CORE] =3D &vc9000e_core.hw, - [CLKID_CSI_PHY0_SEL] =3D &csi_phy0_sel.hw, - [CLKID_CSI_PHY0_DIV] =3D &csi_phy0_div.hw, - [CLKID_CSI_PHY0] =3D &csi_phy0.hw, - [CLKID_DEWARPA_SEL] =3D &dewarpa_sel.hw, - [CLKID_DEWARPA_DIV] =3D &dewarpa_div.hw, - [CLKID_DEWARPA] =3D &dewarpa.hw, - [CLKID_ISP0_SEL] =3D &isp0_sel.hw, - [CLKID_ISP0_DIV] =3D &isp0_div.hw, - [CLKID_ISP0] =3D &isp0.hw, - [CLKID_NNA_CORE_SEL] =3D &nna_core_sel.hw, - [CLKID_NNA_CORE_DIV] =3D &nna_core_div.hw, - [CLKID_NNA_CORE] =3D &nna_core.hw, - [CLKID_GE2D_SEL] =3D &ge2d_sel.hw, - [CLKID_GE2D_DIV] =3D &ge2d_div.hw, - [CLKID_GE2D] =3D &ge2d.hw, - [CLKID_VAPB_SEL] =3D &vapb_sel.hw, - [CLKID_VAPB_DIV] =3D &vapb_div.hw, - [CLKID_VAPB] =3D &vapb.hw, -}; - -static const struct regmap_config clkc_regmap_config =3D { +static struct clk_hw *c3_peripherals_hw_clks[] =3D { + [CLKID_RTC_XTAL_CLKIN] =3D &c3_rtc_xtal_clkin.hw, + [CLKID_RTC_32K_DIV] =3D &c3_rtc_32k_div.hw, + [CLKID_RTC_32K_MUX] =3D &c3_rtc_32k_sel.hw, + [CLKID_RTC_32K] =3D &c3_rtc_32k.hw, + [CLKID_RTC_CLK] =3D &c3_rtc_clk.hw, + [CLKID_SYS_RESET_CTRL] =3D &c3_sys_reset_ctrl.hw, + [CLKID_SYS_PWR_CTRL] =3D &c3_sys_pwr_ctrl.hw, + [CLKID_SYS_PAD_CTRL] =3D &c3_sys_pad_ctrl.hw, + [CLKID_SYS_CTRL] =3D &c3_sys_ctrl.hw, + [CLKID_SYS_TS_PLL] =3D &c3_sys_ts_pll.hw, + [CLKID_SYS_DEV_ARB] =3D &c3_sys_dev_arb.hw, + [CLKID_SYS_MMC_PCLK] =3D &c3_sys_mmc_pclk.hw, + [CLKID_SYS_CPU_CTRL] =3D &c3_sys_cpu_ctrl.hw, + [CLKID_SYS_JTAG_CTRL] =3D &c3_sys_jtag_ctrl.hw, + [CLKID_SYS_IR_CTRL] =3D &c3_sys_ir_ctrl.hw, + [CLKID_SYS_IRQ_CTRL] =3D &c3_sys_irq_ctrl.hw, + [CLKID_SYS_MSR_CLK] =3D &c3_sys_msr_clk.hw, + [CLKID_SYS_ROM] =3D &c3_sys_rom.hw, + [CLKID_SYS_UART_F] =3D &c3_sys_uart_f.hw, + [CLKID_SYS_CPU_ARB] =3D &c3_sys_cpu_apb.hw, + [CLKID_SYS_RSA] =3D &c3_sys_rsa.hw, + [CLKID_SYS_SAR_ADC] =3D &c3_sys_sar_adc.hw, + [CLKID_SYS_STARTUP] =3D &c3_sys_startup.hw, + [CLKID_SYS_SECURE] =3D &c3_sys_secure.hw, + [CLKID_SYS_SPIFC] =3D &c3_sys_spifc.hw, + [CLKID_SYS_NNA] =3D &c3_sys_nna.hw, + [CLKID_SYS_ETH_MAC] =3D &c3_sys_eth_mac.hw, + [CLKID_SYS_GIC] =3D &c3_sys_gic.hw, + [CLKID_SYS_RAMA] =3D &c3_sys_rama.hw, + [CLKID_SYS_BIG_NIC] =3D &c3_sys_big_nic.hw, + [CLKID_SYS_RAMB] =3D &c3_sys_ramb.hw, + [CLKID_SYS_AUDIO_PCLK] =3D &c3_sys_audio_pclk.hw, + [CLKID_SYS_PWM_KL] =3D &c3_sys_pwm_kl.hw, + [CLKID_SYS_PWM_IJ] =3D &c3_sys_pwm_ij.hw, + [CLKID_SYS_USB] =3D &c3_sys_usb.hw, + [CLKID_SYS_SD_EMMC_A] =3D &c3_sys_sd_emmc_a.hw, + [CLKID_SYS_SD_EMMC_C] =3D &c3_sys_sd_emmc_c.hw, + [CLKID_SYS_PWM_AB] =3D &c3_sys_pwm_ab.hw, + [CLKID_SYS_PWM_CD] =3D &c3_sys_pwm_cd.hw, + [CLKID_SYS_PWM_EF] =3D &c3_sys_pwm_ef.hw, + [CLKID_SYS_PWM_GH] =3D &c3_sys_pwm_gh.hw, + [CLKID_SYS_SPICC_1] =3D &c3_sys_spicc_1.hw, + [CLKID_SYS_SPICC_0] =3D &c3_sys_spicc_0.hw, + [CLKID_SYS_UART_A] =3D &c3_sys_uart_a.hw, + [CLKID_SYS_UART_B] =3D &c3_sys_uart_b.hw, + [CLKID_SYS_UART_C] =3D &c3_sys_uart_c.hw, + [CLKID_SYS_UART_D] =3D &c3_sys_uart_d.hw, + [CLKID_SYS_UART_E] =3D &c3_sys_uart_e.hw, + [CLKID_SYS_I2C_M_A] =3D &c3_sys_i2c_m_a.hw, + [CLKID_SYS_I2C_M_B] =3D &c3_sys_i2c_m_b.hw, + [CLKID_SYS_I2C_M_C] =3D &c3_sys_i2c_m_c.hw, + [CLKID_SYS_I2C_M_D] =3D &c3_sys_i2c_m_d.hw, + [CLKID_SYS_I2S_S_A] =3D &c3_sys_i2c_s_a.hw, + [CLKID_SYS_RTC] =3D &c3_sys_rtc.hw, + [CLKID_SYS_GE2D] =3D &c3_sys_ge2d.hw, + [CLKID_SYS_ISP] =3D &c3_sys_isp.hw, + [CLKID_SYS_GPV_ISP_NIC] =3D &c3_sys_gpv_isp_nic.hw, + [CLKID_SYS_GPV_CVE_NIC] =3D &c3_sys_gpv_cve_nic.hw, + [CLKID_SYS_MIPI_DSI_HOST] =3D &c3_sys_mipi_dsi_host.hw, + [CLKID_SYS_MIPI_DSI_PHY] =3D &c3_sys_mipi_dsi_phy.hw, + [CLKID_SYS_ETH_PHY] =3D &c3_sys_eth_phy.hw, + [CLKID_SYS_ACODEC] =3D &c3_sys_acodec.hw, + [CLKID_SYS_DWAP] =3D &c3_sys_dwap.hw, + [CLKID_SYS_DOS] =3D &c3_sys_dos.hw, + [CLKID_SYS_CVE] =3D &c3_sys_cve.hw, + [CLKID_SYS_VOUT] =3D &c3_sys_vout.hw, + [CLKID_SYS_VC9000E] =3D &c3_sys_vc9000e.hw, + [CLKID_SYS_PWM_MN] =3D &c3_sys_pwm_mn.hw, + [CLKID_SYS_SD_EMMC_B] =3D &c3_sys_sd_emmc_b.hw, + [CLKID_AXI_SYS_NIC] =3D &c3_axi_sys_nic.hw, + [CLKID_AXI_ISP_NIC] =3D &c3_axi_isp_nic.hw, + [CLKID_AXI_CVE_NIC] =3D &c3_axi_cve_nic.hw, + [CLKID_AXI_RAMB] =3D &c3_axi_ramb.hw, + [CLKID_AXI_RAMA] =3D &c3_axi_rama.hw, + [CLKID_AXI_CPU_DMC] =3D &c3_axi_cpu_dmc.hw, + [CLKID_AXI_NIC] =3D &c3_axi_nic.hw, + [CLKID_AXI_DMA] =3D &c3_axi_dma.hw, + [CLKID_AXI_MUX_NIC] =3D &c3_axi_mux_nic.hw, + [CLKID_AXI_CVE] =3D &c3_axi_cve.hw, + [CLKID_AXI_DEV1_DMC] =3D &c3_axi_dev1_dmc.hw, + [CLKID_AXI_DEV0_DMC] =3D &c3_axi_dev0_dmc.hw, + [CLKID_AXI_DSP_DMC] =3D &c3_axi_dsp_dmc.hw, + [CLKID_12_24M_IN] =3D &c3_clk_12_24m_in.hw, + [CLKID_12M_24M] =3D &c3_clk_12_24m.hw, + [CLKID_FCLK_25M_DIV] =3D &c3_fclk_25m_div.hw, + [CLKID_FCLK_25M] =3D &c3_fclk_25m.hw, + [CLKID_GEN_SEL] =3D &c3_gen_sel.hw, + [CLKID_GEN_DIV] =3D &c3_gen_div.hw, + [CLKID_GEN] =3D &c3_gen.hw, + [CLKID_SARADC_SEL] =3D &c3_saradc_sel.hw, + [CLKID_SARADC_DIV] =3D &c3_saradc_div.hw, + [CLKID_SARADC] =3D &c3_saradc.hw, + [CLKID_PWM_A_SEL] =3D &c3_pwm_a_sel.hw, + [CLKID_PWM_A_DIV] =3D &c3_pwm_a_div.hw, + [CLKID_PWM_A] =3D &c3_pwm_a.hw, + [CLKID_PWM_B_SEL] =3D &c3_pwm_b_sel.hw, + [CLKID_PWM_B_DIV] =3D &c3_pwm_b_div.hw, + [CLKID_PWM_B] =3D &c3_pwm_b.hw, + [CLKID_PWM_C_SEL] =3D &c3_pwm_c_sel.hw, + [CLKID_PWM_C_DIV] =3D &c3_pwm_c_div.hw, + [CLKID_PWM_C] =3D &c3_pwm_c.hw, + [CLKID_PWM_D_SEL] =3D &c3_pwm_d_sel.hw, + [CLKID_PWM_D_DIV] =3D &c3_pwm_d_div.hw, + [CLKID_PWM_D] =3D &c3_pwm_d.hw, + [CLKID_PWM_E_SEL] =3D &c3_pwm_e_sel.hw, + [CLKID_PWM_E_DIV] =3D &c3_pwm_e_div.hw, + [CLKID_PWM_E] =3D &c3_pwm_e.hw, + [CLKID_PWM_F_SEL] =3D &c3_pwm_f_sel.hw, + [CLKID_PWM_F_DIV] =3D &c3_pwm_f_div.hw, + [CLKID_PWM_F] =3D &c3_pwm_f.hw, + [CLKID_PWM_G_SEL] =3D &c3_pwm_g_sel.hw, + [CLKID_PWM_G_DIV] =3D &c3_pwm_g_div.hw, + [CLKID_PWM_G] =3D &c3_pwm_g.hw, + [CLKID_PWM_H_SEL] =3D &c3_pwm_h_sel.hw, + [CLKID_PWM_H_DIV] =3D &c3_pwm_h_div.hw, + [CLKID_PWM_H] =3D &c3_pwm_h.hw, + [CLKID_PWM_I_SEL] =3D &c3_pwm_i_sel.hw, + [CLKID_PWM_I_DIV] =3D &c3_pwm_i_div.hw, + [CLKID_PWM_I] =3D &c3_pwm_i.hw, + [CLKID_PWM_J_SEL] =3D &c3_pwm_j_sel.hw, + [CLKID_PWM_J_DIV] =3D &c3_pwm_j_div.hw, + [CLKID_PWM_J] =3D &c3_pwm_j.hw, + [CLKID_PWM_K_SEL] =3D &c3_pwm_k_sel.hw, + [CLKID_PWM_K_DIV] =3D &c3_pwm_k_div.hw, + [CLKID_PWM_K] =3D &c3_pwm_k.hw, + [CLKID_PWM_L_SEL] =3D &c3_pwm_l_sel.hw, + [CLKID_PWM_L_DIV] =3D &c3_pwm_l_div.hw, + [CLKID_PWM_L] =3D &c3_pwm_l.hw, + [CLKID_PWM_M_SEL] =3D &c3_pwm_m_sel.hw, + [CLKID_PWM_M_DIV] =3D &c3_pwm_m_div.hw, + [CLKID_PWM_M] =3D &c3_pwm_m.hw, + [CLKID_PWM_N_SEL] =3D &c3_pwm_n_sel.hw, + [CLKID_PWM_N_DIV] =3D &c3_pwm_n_div.hw, + [CLKID_PWM_N] =3D &c3_pwm_n.hw, + [CLKID_SPICC_A_SEL] =3D &c3_spicc_a_sel.hw, + [CLKID_SPICC_A_DIV] =3D &c3_spicc_a_div.hw, + [CLKID_SPICC_A] =3D &c3_spicc_a.hw, + [CLKID_SPICC_B_SEL] =3D &c3_spicc_b_sel.hw, + [CLKID_SPICC_B_DIV] =3D &c3_spicc_b_div.hw, + [CLKID_SPICC_B] =3D &c3_spicc_b.hw, + [CLKID_SPIFC_SEL] =3D &c3_spifc_sel.hw, + [CLKID_SPIFC_DIV] =3D &c3_spifc_div.hw, + [CLKID_SPIFC] =3D &c3_spifc.hw, + [CLKID_SD_EMMC_A_SEL] =3D &c3_sd_emmc_a_sel.hw, + [CLKID_SD_EMMC_A_DIV] =3D &c3_sd_emmc_a_div.hw, + [CLKID_SD_EMMC_A] =3D &c3_sd_emmc_a.hw, + [CLKID_SD_EMMC_B_SEL] =3D &c3_sd_emmc_b_sel.hw, + [CLKID_SD_EMMC_B_DIV] =3D &c3_sd_emmc_b_div.hw, + [CLKID_SD_EMMC_B] =3D &c3_sd_emmc_b.hw, + [CLKID_SD_EMMC_C_SEL] =3D &c3_sd_emmc_c_sel.hw, + [CLKID_SD_EMMC_C_DIV] =3D &c3_sd_emmc_c_div.hw, + [CLKID_SD_EMMC_C] =3D &c3_sd_emmc_c.hw, + [CLKID_TS_DIV] =3D &c3_ts_div.hw, + [CLKID_TS] =3D &c3_ts.hw, + [CLKID_ETH_125M_DIV] =3D &c3_eth_125m_div.hw, + [CLKID_ETH_125M] =3D &c3_eth_125m.hw, + [CLKID_ETH_RMII_DIV] =3D &c3_eth_rmii_div.hw, + [CLKID_ETH_RMII] =3D &c3_eth_rmii.hw, + [CLKID_MIPI_DSI_MEAS_SEL] =3D &c3_mipi_dsi_meas_sel.hw, + [CLKID_MIPI_DSI_MEAS_DIV] =3D &c3_mipi_dsi_meas_div.hw, + [CLKID_MIPI_DSI_MEAS] =3D &c3_mipi_dsi_meas.hw, + [CLKID_DSI_PHY_SEL] =3D &c3_dsi_phy_sel.hw, + [CLKID_DSI_PHY_DIV] =3D &c3_dsi_phy_div.hw, + [CLKID_DSI_PHY] =3D &c3_dsi_phy.hw, + [CLKID_VOUT_MCLK_SEL] =3D &c3_vout_mclk_sel.hw, + [CLKID_VOUT_MCLK_DIV] =3D &c3_vout_mclk_div.hw, + [CLKID_VOUT_MCLK] =3D &c3_vout_mclk.hw, + [CLKID_VOUT_ENC_SEL] =3D &c3_vout_enc_sel.hw, + [CLKID_VOUT_ENC_DIV] =3D &c3_vout_enc_div.hw, + [CLKID_VOUT_ENC] =3D &c3_vout_enc.hw, + [CLKID_HCODEC_0_SEL] =3D &c3_hcodec_0_sel.hw, + [CLKID_HCODEC_0_DIV] =3D &c3_hcodec_0_div.hw, + [CLKID_HCODEC_0] =3D &c3_hcodec_0.hw, + [CLKID_HCODEC_1_SEL] =3D &c3_hcodec_1_sel.hw, + [CLKID_HCODEC_1_DIV] =3D &c3_hcodec_1_div.hw, + [CLKID_HCODEC_1] =3D &c3_hcodec_1.hw, + [CLKID_HCODEC] =3D &c3_hcodec.hw, + [CLKID_VC9000E_ACLK_SEL] =3D &c3_vc9000e_aclk_sel.hw, + [CLKID_VC9000E_ACLK_DIV] =3D &c3_vc9000e_aclk_div.hw, + [CLKID_VC9000E_ACLK] =3D &c3_vc9000e_aclk.hw, + [CLKID_VC9000E_CORE_SEL] =3D &c3_vc9000e_core_sel.hw, + [CLKID_VC9000E_CORE_DIV] =3D &c3_vc9000e_core_div.hw, + [CLKID_VC9000E_CORE] =3D &c3_vc9000e_core.hw, + [CLKID_CSI_PHY0_SEL] =3D &c3_csi_phy0_sel.hw, + [CLKID_CSI_PHY0_DIV] =3D &c3_csi_phy0_div.hw, + [CLKID_CSI_PHY0] =3D &c3_csi_phy0.hw, + [CLKID_DEWARPA_SEL] =3D &c3_dewarpa_sel.hw, + [CLKID_DEWARPA_DIV] =3D &c3_dewarpa_div.hw, + [CLKID_DEWARPA] =3D &c3_dewarpa.hw, + [CLKID_ISP0_SEL] =3D &c3_isp0_sel.hw, + [CLKID_ISP0_DIV] =3D &c3_isp0_div.hw, + [CLKID_ISP0] =3D &c3_isp0.hw, + [CLKID_NNA_CORE_SEL] =3D &c3_nna_core_sel.hw, + [CLKID_NNA_CORE_DIV] =3D &c3_nna_core_div.hw, + [CLKID_NNA_CORE] =3D &c3_nna_core.hw, + [CLKID_GE2D_SEL] =3D &c3_ge2d_sel.hw, + [CLKID_GE2D_DIV] =3D &c3_ge2d_div.hw, + [CLKID_GE2D] =3D &c3_ge2d.hw, + [CLKID_VAPB_SEL] =3D &c3_vapb_sel.hw, + [CLKID_VAPB_DIV] =3D &c3_vapb_div.hw, + [CLKID_VAPB] =3D &c3_vapb.hw, +}; + +static const struct regmap_config c3_peripherals_regmap_cfg =3D { .reg_bits =3D 32, .val_bits =3D 32, .reg_stride =3D 4, .max_register =3D NNA_CLK_CTRL, }; =20 -static struct meson_clk_hw_data c3_periphs_clks =3D { - .hws =3D c3_periphs_hw_clks, - .num =3D ARRAY_SIZE(c3_periphs_hw_clks), +static struct meson_clk_hw_data c3_peripherals_clks =3D { + .hws =3D c3_peripherals_hw_clks, + .num =3D ARRAY_SIZE(c3_peripherals_hw_clks), }; =20 -static int c3_peripherals_probe(struct platform_device *pdev) +static int c3_peripherals_clkc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct regmap *regmap; @@ -2115,16 +2114,16 @@ static int c3_peripherals_probe(struct platform_dev= ice *pdev) if (IS_ERR(base)) return PTR_ERR(base); =20 - regmap =3D devm_regmap_init_mmio(dev, base, &clkc_regmap_config); + regmap =3D devm_regmap_init_mmio(dev, base, &c3_peripherals_regmap_cfg); if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 - for (clkid =3D 0; clkid < c3_periphs_clks.num; clkid++) { + for (clkid =3D 0; clkid < c3_peripherals_clks.num; clkid++) { /* array might be sparse */ - if (!c3_periphs_clks.hws[clkid]) + if (!c3_peripherals_clks.hws[clkid]) continue; =20 - ret =3D devm_clk_hw_register(dev, c3_periphs_clks.hws[clkid]); + ret =3D devm_clk_hw_register(dev, c3_peripherals_clks.hws[clkid]); if (ret) { dev_err(dev, "Clock registration failed\n"); return ret; @@ -2132,7 +2131,7 @@ static int c3_peripherals_probe(struct platform_devic= e *pdev) } =20 return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, - &c3_periphs_clks); + &c3_peripherals_clks); } =20 static const struct of_device_id c3_peripherals_clkc_match_table[] =3D { @@ -2144,14 +2143,14 @@ static const struct of_device_id c3_peripherals_clk= c_match_table[] =3D { =20 MODULE_DEVICE_TABLE(of, c3_peripherals_clkc_match_table); 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i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet Reviewed-by: Chuan Liu --- drivers/clk/meson/c3-pll.c | 202 ++++++++++++++++++++++-------------------= ---- 1 file changed, 101 insertions(+), 101 deletions(-) diff --git a/drivers/clk/meson/c3-pll.c b/drivers/clk/meson/c3-pll.c index 2c5594b8e49a24ae8067117465ee4c0e29d7420d..ccfcd4b5be8996592c27df31fa6= 2d4871c826926 100644 --- a/drivers/clk/meson/c3-pll.c +++ b/drivers/clk/meson/c3-pll.c @@ -34,7 +34,7 @@ #define ANACTRL_MPLL_CTRL3 0x18c #define ANACTRL_MPLL_CTRL4 0x190 =20 -static struct clk_regmap fclk_50m_en =3D { +static struct clk_regmap c3_fclk_50m_en =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ANACTRL_FIXPLL_CTRL4, .bit_idx =3D 0, @@ -49,20 +49,20 @@ static struct clk_regmap fclk_50m_en =3D { }, }; =20 -static struct clk_fixed_factor fclk_50m =3D { +static struct clk_fixed_factor c3_fclk_50m =3D { .mult =3D 1, .div =3D 40, .hw.init =3D &(struct clk_init_data) { .name =3D "fclk_50m", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fclk_50m_en.hw + &c3_fclk_50m_en.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_fixed_factor fclk_div2_div =3D { +static struct clk_fixed_factor c3_fclk_div2_div =3D { .mult =3D 1, .div =3D 2, .hw.init =3D &(struct clk_init_data) { @@ -75,7 +75,7 @@ static struct clk_fixed_factor fclk_div2_div =3D { }, }; =20 -static struct clk_regmap fclk_div2 =3D { +static struct clk_regmap c3_fclk_div2 =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ANACTRL_FIXPLL_CTRL4, .bit_idx =3D 24, @@ -84,13 +84,13 @@ static struct clk_regmap fclk_div2 =3D { .name =3D "fclk_div2", .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fclk_div2_div.hw + &c3_fclk_div2_div.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_fixed_factor fclk_div2p5_div =3D { +static struct clk_fixed_factor c3_fclk_div2p5_div =3D { .mult =3D 2, .div =3D 5, .hw.init =3D &(struct clk_init_data) { @@ -103,7 +103,7 @@ static struct clk_fixed_factor fclk_div2p5_div =3D { }, }; =20 -static struct clk_regmap fclk_div2p5 =3D { +static struct clk_regmap c3_fclk_div2p5 =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ANACTRL_FIXPLL_CTRL4, .bit_idx =3D 4, @@ -112,13 +112,13 @@ static struct clk_regmap fclk_div2p5 =3D { .name =3D "fclk_div2p5", .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fclk_div2p5_div.hw + &c3_fclk_div2p5_div.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_fixed_factor fclk_div3_div =3D { +static struct clk_fixed_factor c3_fclk_div3_div =3D { .mult =3D 1, .div =3D 3, .hw.init =3D &(struct clk_init_data) { @@ -131,7 +131,7 @@ static struct clk_fixed_factor fclk_div3_div =3D { }, }; =20 -static struct clk_regmap fclk_div3 =3D { +static struct clk_regmap c3_fclk_div3 =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ANACTRL_FIXPLL_CTRL4, .bit_idx =3D 20, @@ -140,13 +140,13 @@ static struct clk_regmap fclk_div3 =3D { .name =3D "fclk_div3", .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fclk_div3_div.hw + &c3_fclk_div3_div.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_fixed_factor fclk_div4_div =3D { +static struct clk_fixed_factor c3_fclk_div4_div =3D { .mult =3D 1, .div =3D 4, .hw.init =3D &(struct clk_init_data) { @@ -159,7 +159,7 @@ static struct clk_fixed_factor fclk_div4_div =3D { }, }; =20 -static struct clk_regmap fclk_div4 =3D { +static struct clk_regmap c3_fclk_div4 =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ANACTRL_FIXPLL_CTRL4, .bit_idx =3D 21, @@ -168,13 +168,13 @@ static struct clk_regmap fclk_div4 =3D { .name =3D "fclk_div4", .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fclk_div4_div.hw + &c3_fclk_div4_div.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_fixed_factor fclk_div5_div =3D { +static struct clk_fixed_factor c3_fclk_div5_div =3D { .mult =3D 1, .div =3D 5, .hw.init =3D &(struct clk_init_data) { @@ -187,7 +187,7 @@ static struct clk_fixed_factor fclk_div5_div =3D { }, }; =20 -static struct clk_regmap fclk_div5 =3D { +static struct clk_regmap c3_fclk_div5 =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ANACTRL_FIXPLL_CTRL4, .bit_idx =3D 22, @@ -196,13 +196,13 @@ static struct clk_regmap fclk_div5 =3D { .name =3D "fclk_div5", .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fclk_div5_div.hw + &c3_fclk_div5_div.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_fixed_factor fclk_div7_div =3D { +static struct clk_fixed_factor c3_fclk_div7_div =3D { .mult =3D 1, .div =3D 7, .hw.init =3D &(struct clk_init_data) { @@ -215,7 +215,7 @@ static struct clk_fixed_factor fclk_div7_div =3D { }, }; =20 -static struct clk_regmap fclk_div7 =3D { +static struct clk_regmap c3_fclk_div7 =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ANACTRL_FIXPLL_CTRL4, .bit_idx =3D 23, @@ -224,13 +224,13 @@ static struct clk_regmap fclk_div7 =3D { .name =3D "fclk_div7", .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &fclk_div7_div.hw + &c3_fclk_div7_div.hw }, .num_parents =3D 1, }, }; =20 -static const struct reg_sequence c3_gp0_init_regs[] =3D { +static const struct reg_sequence c3_gp0_pll_init_regs[] =3D { { .reg =3D ANACTRL_GP0PLL_CTRL2, .def =3D 0x0 }, { .reg =3D ANACTRL_GP0PLL_CTRL3, .def =3D 0x48681c00 }, { .reg =3D ANACTRL_GP0PLL_CTRL4, .def =3D 0x88770290 }, @@ -243,7 +243,7 @@ static const struct pll_mult_range c3_gp0_pll_mult_rang= e =3D { .max =3D 250, }; =20 -static struct clk_regmap gp0_pll_dco =3D { +static struct clk_regmap c3_gp0_pll_dco =3D { .data =3D &(struct meson_clk_pll_data) { .en =3D { .reg_off =3D ANACTRL_GP0PLL_CTRL0, @@ -276,8 +276,8 @@ static struct clk_regmap gp0_pll_dco =3D { .width =3D 1, }, .range =3D &c3_gp0_pll_mult_range, - .init_regs =3D c3_gp0_init_regs, - .init_count =3D ARRAY_SIZE(c3_gp0_init_regs), + .init_regs =3D c3_gp0_pll_init_regs, + .init_count =3D ARRAY_SIZE(c3_gp0_pll_init_regs), }, .hw.init =3D &(struct clk_init_data) { .name =3D "gp0_pll_dco", @@ -300,7 +300,7 @@ static const struct clk_div_table c3_gp0_pll_od_table[]= =3D { { /* sentinel */ } }; =20 -static struct clk_regmap gp0_pll =3D { +static struct clk_regmap c3_gp0_pll =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D ANACTRL_GP0PLL_CTRL0, .shift =3D 16, @@ -311,14 +311,14 @@ static struct clk_regmap gp0_pll =3D { .name =3D "gp0_pll", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &gp0_pll_dco.hw + &c3_gp0_pll_dco.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct reg_sequence c3_hifi_init_regs[] =3D { +static const struct reg_sequence c3_hifi_pll_init_regs[] =3D { { .reg =3D ANACTRL_HIFIPLL_CTRL2, .def =3D 0x0 }, { .reg =3D ANACTRL_HIFIPLL_CTRL3, .def =3D 0x6a285c00 }, { .reg =3D ANACTRL_HIFIPLL_CTRL4, .def =3D 0x65771290 }, @@ -326,7 +326,7 @@ static const struct reg_sequence c3_hifi_init_regs[] = =3D { { .reg =3D ANACTRL_HIFIPLL_CTRL6, .def =3D 0x56540000 }, }; =20 -static struct clk_regmap hifi_pll_dco =3D { +static struct clk_regmap c3_hifi_pll_dco =3D { .data =3D &(struct meson_clk_pll_data) { .en =3D { .reg_off =3D ANACTRL_HIFIPLL_CTRL0, @@ -359,8 +359,8 @@ static struct clk_regmap hifi_pll_dco =3D { .width =3D 1, }, .range =3D &c3_gp0_pll_mult_range, - .init_regs =3D c3_hifi_init_regs, - .init_count =3D ARRAY_SIZE(c3_hifi_init_regs), + .init_regs =3D c3_hifi_pll_init_regs, + .init_count =3D ARRAY_SIZE(c3_hifi_pll_init_regs), .frac_max =3D 100000, }, .hw.init =3D &(struct clk_init_data) { @@ -373,7 +373,7 @@ static struct clk_regmap hifi_pll_dco =3D { }, }; =20 -static struct clk_regmap hifi_pll =3D { +static struct clk_regmap c3_hifi_pll =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D ANACTRL_HIFIPLL_CTRL0, .shift =3D 16, @@ -384,14 +384,14 @@ static struct clk_regmap hifi_pll =3D { .name =3D "hifi_pll", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &hifi_pll_dco.hw + &c3_hifi_pll_dco.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct reg_sequence c3_mclk_init_regs[] =3D { +static const struct reg_sequence c3_mclk_pll_init_regs[] =3D { { .reg =3D ANACTRL_MPLL_CTRL1, .def =3D 0x1420500f }, { .reg =3D ANACTRL_MPLL_CTRL2, .def =3D 0x00023041 }, { .reg =3D ANACTRL_MPLL_CTRL3, .def =3D 0x18180000 }, @@ -403,7 +403,7 @@ static const struct pll_mult_range c3_mclk_pll_mult_ran= ge =3D { .max =3D 133, }; =20 -static struct clk_regmap mclk_pll_dco =3D { +static struct clk_regmap c3_mclk_pll_dco =3D { .data =3D &(struct meson_clk_pll_data) { .en =3D { .reg_off =3D ANACTRL_MPLL_CTRL0, @@ -431,8 +431,8 @@ static struct clk_regmap mclk_pll_dco =3D { .width =3D 1, }, .range =3D &c3_mclk_pll_mult_range, - .init_regs =3D c3_mclk_init_regs, - .init_count =3D ARRAY_SIZE(c3_mclk_init_regs), + .init_regs =3D c3_mclk_pll_init_regs, + .init_count =3D ARRAY_SIZE(c3_mclk_pll_init_regs), }, .hw.init =3D &(struct clk_init_data) { .name =3D "mclk_pll_dco", @@ -444,7 +444,7 @@ static struct clk_regmap mclk_pll_dco =3D { }, }; =20 -static const struct clk_div_table c3_mpll_od_table[] =3D { +static const struct clk_div_table c3_mpll_pll_od_table[] =3D { { 0, 1 }, { 1, 2 }, { 2, 4 }, @@ -453,25 +453,25 @@ static const struct clk_div_table c3_mpll_od_table[] = =3D { { /* sentinel */ } }; =20 -static struct clk_regmap mclk_pll_od =3D { +static struct clk_regmap c3_mclk_pll_od =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D ANACTRL_MPLL_CTRL0, .shift =3D 12, .width =3D 3, - .table =3D c3_mpll_od_table, + .table =3D c3_mpll_pll_od_table, }, .hw.init =3D &(struct clk_init_data) { .name =3D "mclk_pll_od", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &mclk_pll_dco.hw }, + &c3_mclk_pll_dco.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 /* both value 0 and 1 gives divide the input rate by one */ -static struct clk_regmap mclk_pll =3D { +static struct clk_regmap c3_mclk_pll =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D ANACTRL_MPLL_CTRL4, .shift =3D 16, @@ -482,20 +482,20 @@ static struct clk_regmap mclk_pll =3D { .name =3D "mclk_pll", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &mclk_pll_od.hw + &c3_mclk_pll_od.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const struct clk_parent_data mclk_parent[] =3D { - { .hw =3D &mclk_pll.hw }, +static const struct clk_parent_data c3_mclk_parents[] =3D { + { .hw =3D &c3_mclk_pll.hw }, { .fw_name =3D "mclk" }, - { .hw =3D &fclk_50m.hw } + { .hw =3D &c3_fclk_50m.hw } }; =20 -static struct clk_regmap mclk0_sel =3D { +static struct clk_regmap c3_mclk0_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D ANACTRL_MPLL_CTRL4, .mask =3D 0x3, @@ -504,12 +504,12 @@ static struct clk_regmap mclk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "mclk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D mclk_parent, - .num_parents =3D ARRAY_SIZE(mclk_parent), + .parent_data =3D c3_mclk_parents, + .num_parents =3D ARRAY_SIZE(c3_mclk_parents), }, }; =20 -static struct clk_regmap mclk0_div_en =3D { +static struct clk_regmap c3_mclk0_div_en =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ANACTRL_MPLL_CTRL4, .bit_idx =3D 1, @@ -518,14 +518,14 @@ static struct clk_regmap mclk0_div_en =3D { .name =3D "mclk0_div_en", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &mclk0_sel.hw + &c3_mclk0_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap mclk0_div =3D { +static struct clk_regmap c3_mclk0_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D ANACTRL_MPLL_CTRL4, .shift =3D 2, @@ -535,14 +535,14 @@ static struct clk_regmap mclk0_div =3D { .name =3D "mclk0_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &mclk0_div_en.hw + &c3_mclk0_div_en.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap mclk0 =3D { +static struct clk_regmap c3_mclk0 =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ANACTRL_MPLL_CTRL4, .bit_idx =3D 0, @@ -551,14 +551,14 @@ static struct clk_regmap mclk0 =3D { .name =3D "mclk0", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &mclk0_div.hw + &c3_mclk0_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap mclk1_sel =3D { +static struct clk_regmap c3_mclk1_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D ANACTRL_MPLL_CTRL4, .mask =3D 0x3, @@ -567,12 +567,12 @@ static struct clk_regmap mclk1_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "mclk1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D mclk_parent, - .num_parents =3D ARRAY_SIZE(mclk_parent), + .parent_data =3D c3_mclk_parents, + .num_parents =3D ARRAY_SIZE(c3_mclk_parents), }, }; =20 -static struct clk_regmap mclk1_div_en =3D { +static struct clk_regmap c3_mclk1_div_en =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ANACTRL_MPLL_CTRL4, .bit_idx =3D 9, @@ -581,14 +581,14 @@ static struct clk_regmap mclk1_div_en =3D { .name =3D "mclk1_div_en", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &mclk1_sel.hw + &c3_mclk1_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap mclk1_div =3D { +static struct clk_regmap c3_mclk1_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D ANACTRL_MPLL_CTRL4, .shift =3D 10, @@ -598,14 +598,14 @@ static struct clk_regmap mclk1_div =3D { .name =3D "mclk1_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &mclk1_div_en.hw + &c3_mclk1_div_en.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap mclk1 =3D { +static struct clk_regmap c3_mclk1 =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D ANACTRL_MPLL_CTRL4, .bit_idx =3D 8, @@ -614,7 +614,7 @@ static struct clk_regmap mclk1 =3D { .name =3D "mclk1", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &mclk1_div.hw + &c3_mclk1_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -622,38 +622,38 @@ static struct clk_regmap mclk1 =3D { }; =20 static struct clk_hw *c3_pll_hw_clks[] =3D { - [CLKID_FCLK_50M_EN] =3D &fclk_50m_en.hw, - [CLKID_FCLK_50M] =3D &fclk_50m.hw, - [CLKID_FCLK_DIV2_DIV] =3D &fclk_div2_div.hw, - [CLKID_FCLK_DIV2] =3D &fclk_div2.hw, - [CLKID_FCLK_DIV2P5_DIV] =3D &fclk_div2p5_div.hw, - [CLKID_FCLK_DIV2P5] =3D &fclk_div2p5.hw, - [CLKID_FCLK_DIV3_DIV] =3D &fclk_div3_div.hw, - [CLKID_FCLK_DIV3] =3D &fclk_div3.hw, - [CLKID_FCLK_DIV4_DIV] =3D &fclk_div4_div.hw, - [CLKID_FCLK_DIV4] =3D &fclk_div4.hw, - [CLKID_FCLK_DIV5_DIV] =3D &fclk_div5_div.hw, - [CLKID_FCLK_DIV5] =3D &fclk_div5.hw, - [CLKID_FCLK_DIV7_DIV] =3D &fclk_div7_div.hw, - [CLKID_FCLK_DIV7] =3D &fclk_div7.hw, - [CLKID_GP0_PLL_DCO] =3D &gp0_pll_dco.hw, - [CLKID_GP0_PLL] =3D &gp0_pll.hw, - [CLKID_HIFI_PLL_DCO] =3D &hifi_pll_dco.hw, - [CLKID_HIFI_PLL] =3D &hifi_pll.hw, - [CLKID_MCLK_PLL_DCO] =3D &mclk_pll_dco.hw, - [CLKID_MCLK_PLL_OD] =3D &mclk_pll_od.hw, - [CLKID_MCLK_PLL] =3D &mclk_pll.hw, - [CLKID_MCLK0_SEL] =3D &mclk0_sel.hw, - [CLKID_MCLK0_SEL_EN] =3D &mclk0_div_en.hw, - [CLKID_MCLK0_DIV] =3D &mclk0_div.hw, - [CLKID_MCLK0] =3D &mclk0.hw, - [CLKID_MCLK1_SEL] =3D &mclk1_sel.hw, - [CLKID_MCLK1_SEL_EN] =3D &mclk1_div_en.hw, - [CLKID_MCLK1_DIV] =3D &mclk1_div.hw, - [CLKID_MCLK1] =3D &mclk1.hw -}; - -static const struct regmap_config clkc_regmap_config =3D { + [CLKID_FCLK_50M_EN] =3D &c3_fclk_50m_en.hw, + [CLKID_FCLK_50M] =3D &c3_fclk_50m.hw, + [CLKID_FCLK_DIV2_DIV] =3D &c3_fclk_div2_div.hw, + [CLKID_FCLK_DIV2] =3D &c3_fclk_div2.hw, + [CLKID_FCLK_DIV2P5_DIV] =3D &c3_fclk_div2p5_div.hw, + [CLKID_FCLK_DIV2P5] =3D &c3_fclk_div2p5.hw, + [CLKID_FCLK_DIV3_DIV] =3D &c3_fclk_div3_div.hw, + [CLKID_FCLK_DIV3] =3D &c3_fclk_div3.hw, + [CLKID_FCLK_DIV4_DIV] =3D &c3_fclk_div4_div.hw, + [CLKID_FCLK_DIV4] =3D &c3_fclk_div4.hw, + [CLKID_FCLK_DIV5_DIV] =3D &c3_fclk_div5_div.hw, + [CLKID_FCLK_DIV5] =3D &c3_fclk_div5.hw, + [CLKID_FCLK_DIV7_DIV] =3D &c3_fclk_div7_div.hw, + [CLKID_FCLK_DIV7] =3D &c3_fclk_div7.hw, + [CLKID_GP0_PLL_DCO] =3D &c3_gp0_pll_dco.hw, + [CLKID_GP0_PLL] =3D &c3_gp0_pll.hw, + [CLKID_HIFI_PLL_DCO] =3D &c3_hifi_pll_dco.hw, + [CLKID_HIFI_PLL] =3D &c3_hifi_pll.hw, + [CLKID_MCLK_PLL_DCO] =3D &c3_mclk_pll_dco.hw, + [CLKID_MCLK_PLL_OD] =3D &c3_mclk_pll_od.hw, + [CLKID_MCLK_PLL] =3D &c3_mclk_pll.hw, + [CLKID_MCLK0_SEL] =3D &c3_mclk0_sel.hw, + [CLKID_MCLK0_SEL_EN] =3D &c3_mclk0_div_en.hw, + [CLKID_MCLK0_DIV] =3D &c3_mclk0_div.hw, + [CLKID_MCLK0] =3D &c3_mclk0.hw, + [CLKID_MCLK1_SEL] =3D &c3_mclk1_sel.hw, + [CLKID_MCLK1_SEL_EN] =3D &c3_mclk1_div_en.hw, + [CLKID_MCLK1_DIV] =3D &c3_mclk1_div.hw, + [CLKID_MCLK1] =3D &c3_mclk1.hw +}; + +static const struct regmap_config c3_pll_regmap_cfg =3D { .reg_bits =3D 32, .val_bits =3D 32, .reg_stride =3D 4, @@ -665,7 +665,7 @@ static struct meson_clk_hw_data c3_pll_clks =3D { .num =3D ARRAY_SIZE(c3_pll_hw_clks), }; =20 -static int c3_pll_probe(struct platform_device *pdev) +static int c3_pll_clkc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct regmap *regmap; @@ -676,7 +676,7 @@ static int c3_pll_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); =20 - regmap =3D devm_regmap_init_mmio(dev, base, &clkc_regmap_config); + regmap =3D devm_regmap_init_mmio(dev, base, &c3_pll_regmap_cfg); if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 @@ -704,14 +704,14 @@ static const struct of_device_id c3_pll_clkc_match_ta= ble[] =3D { }; MODULE_DEVICE_TABLE(of, c3_pll_clkc_match_table); =20 -static struct platform_driver c3_pll_driver =3D { - .probe =3D c3_pll_probe, +static struct platform_driver c3_pll_clkc_driver =3D { + .probe =3D c3_pll_clkc_probe, .driver =3D { .name =3D "c3-pll-clkc", .of_match_table =3D c3_pll_clkc_match_table, }, }; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet --- drivers/clk/meson/g12a-aoclk.c | 207 +++++++++++++++++++++----------------= ---- 1 file changed, 107 insertions(+), 100 deletions(-) diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c index 4095a1b2bb80ee430f8aeb56cbcf5ed549188781..3eaf1db16f45a0adf0acd901ed7= ae1f51a9c8dc1 100644 --- a/drivers/clk/meson/g12a-aoclk.c +++ b/drivers/clk/meson/g12a-aoclk.c @@ -43,8 +43,8 @@ * bootloader. The goal is to remove this flag at some point. * Actually removing it will require some extensive test to be done safely. */ -#define AXG_AO_GATE(_name, _reg, _bit) \ -static struct clk_regmap g12a_aoclk_##_name =3D { \ +#define G12A_AO_PCLK(_name, _reg, _bit) \ +static struct clk_regmap g12a_ao_##_name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D (_reg), \ .bit_idx =3D (_bit), \ @@ -60,23 +60,24 @@ static struct clk_regmap g12a_aoclk_##_name =3D { \ }, \ } =20 -AXG_AO_GATE(ahb, AO_CLK_GATE0, 0); -AXG_AO_GATE(ir_in, AO_CLK_GATE0, 1); -AXG_AO_GATE(i2c_m0, AO_CLK_GATE0, 2); -AXG_AO_GATE(i2c_s0, AO_CLK_GATE0, 3); -AXG_AO_GATE(uart, AO_CLK_GATE0, 4); -AXG_AO_GATE(prod_i2c, AO_CLK_GATE0, 5); -AXG_AO_GATE(uart2, AO_CLK_GATE0, 6); -AXG_AO_GATE(ir_out, AO_CLK_GATE0, 7); -AXG_AO_GATE(saradc, AO_CLK_GATE0, 8); -AXG_AO_GATE(mailbox, AO_CLK_GATE0_SP, 0); -AXG_AO_GATE(m3, AO_CLK_GATE0_SP, 1); -AXG_AO_GATE(ahb_sram, AO_CLK_GATE0_SP, 2); -AXG_AO_GATE(rti, AO_CLK_GATE0_SP, 3); -AXG_AO_GATE(m4_fclk, AO_CLK_GATE0_SP, 4); -AXG_AO_GATE(m4_hclk, AO_CLK_GATE0_SP, 5); +G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0); +G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1); +G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2); +G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3); +G12A_AO_PCLK(uart, AO_CLK_GATE0, 4); +G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5); +G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6); +G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7); +G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8); =20 -static struct clk_regmap g12a_aoclk_cts_oscin =3D { +G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0); +G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1); +G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2); +G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3); +G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4); +G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5); + +static struct clk_regmap g12a_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTI_PWR_CNTL_REG0, .bit_idx =3D 14, @@ -103,22 +104,22 @@ static const struct meson_clk_dualdiv_param g12a_32k_= div_table[] =3D { =20 /* 32k_by_oscin clock */ =20 -static struct clk_regmap g12a_aoclk_32k_by_oscin_pre =3D { +static struct clk_regmap g12a_ao_32k_by_oscin_pre =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTC_ALT_CLK_CNTL0, .bit_idx =3D 31, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_32k_by_oscin_pre", + .name =3D "ao_32k_by_oscin_pre", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_cts_oscin.hw + &g12a_ao_cts_oscin.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap g12a_aoclk_32k_by_oscin_div =3D { +static struct clk_regmap g12a_ao_32k_by_oscin_div =3D { .data =3D &(struct meson_clk_dualdiv_data){ .n1 =3D { .reg_off =3D AO_RTC_ALT_CLK_CNTL0, @@ -148,16 +149,16 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_div = =3D { .table =3D g12a_32k_div_table, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_32k_by_oscin_div", + .name =3D "ao_32k_by_oscin_div", .ops =3D &meson_clk_dualdiv_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_32k_by_oscin_pre.hw + &g12a_ao_32k_by_oscin_pre.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap g12a_aoclk_32k_by_oscin_sel =3D { +static struct clk_regmap g12a_ao_32k_by_oscin_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTC_ALT_CLK_CNTL1, .mask =3D 0x1, @@ -165,27 +166,27 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_32k_by_oscin_sel", + .name =3D "ao_32k_by_oscin_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_32k_by_oscin_div.hw, - &g12a_aoclk_32k_by_oscin_pre.hw, + &g12a_ao_32k_by_oscin_div.hw, + &g12a_ao_32k_by_oscin_pre.hw, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap g12a_aoclk_32k_by_oscin =3D { +static struct clk_regmap g12a_ao_32k_by_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTC_ALT_CLK_CNTL0, .bit_idx =3D 30, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_32k_by_oscin", + .name =3D "ao_32k_by_oscin", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_32k_by_oscin_sel.hw + &g12a_ao_32k_by_oscin_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -194,22 +195,22 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin =3D { =20 /* cec clock */ =20 -static struct clk_regmap g12a_aoclk_cec_pre =3D { +static struct clk_regmap g12a_ao_cec_pre =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_CEC_CLK_CNTL_REG0, .bit_idx =3D 31, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_cec_pre", + .name =3D "ao_cec_pre", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_cts_oscin.hw + &g12a_ao_cts_oscin.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap g12a_aoclk_cec_div =3D { +static struct clk_regmap g12a_ao_cec_div =3D { .data =3D &(struct meson_clk_dualdiv_data){ .n1 =3D { .reg_off =3D AO_CEC_CLK_CNTL_REG0, @@ -239,16 +240,16 @@ static struct clk_regmap g12a_aoclk_cec_div =3D { .table =3D g12a_32k_div_table, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_cec_div", + .name =3D "ao_cec_div", .ops =3D &meson_clk_dualdiv_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_cec_pre.hw + &g12a_ao_cec_pre.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap g12a_aoclk_cec_sel =3D { +static struct clk_regmap g12a_ao_cec_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_CEC_CLK_CNTL_REG1, .mask =3D 0x1, @@ -256,34 +257,34 @@ static struct clk_regmap g12a_aoclk_cec_sel =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_cec_sel", + .name =3D "ao_cec_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_cec_div.hw, - &g12a_aoclk_cec_pre.hw, + &g12a_ao_cec_div.hw, + &g12a_ao_cec_pre.hw, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap g12a_aoclk_cec =3D { +static struct clk_regmap g12a_ao_cec =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_CEC_CLK_CNTL_REG0, .bit_idx =3D 30, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_cec", + .name =3D "ao_cec", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_cec_sel.hw + &g12a_ao_cec_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap g12a_aoclk_cts_rtc_oscin =3D { +static struct clk_regmap g12a_ao_cts_rtc_oscin =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTI_PWR_CNTL_REG0, .mask =3D 0x1, @@ -291,10 +292,10 @@ static struct clk_regmap g12a_aoclk_cts_rtc_oscin =3D= { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_cts_rtc_oscin", + .name =3D "ao_cts_rtc_oscin", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { - { .hw =3D &g12a_aoclk_32k_by_oscin.hw }, + { .hw =3D &g12a_ao_32k_by_oscin.hw }, { .fw_name =3D "ext-32k-0", }, }, .num_parents =3D 2, @@ -302,7 +303,7 @@ static struct clk_regmap g12a_aoclk_cts_rtc_oscin =3D { }, }; =20 -static struct clk_regmap g12a_aoclk_clk81 =3D { +static struct clk_regmap g12a_ao_clk81 =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTI_PWR_CNTL_REG0, .mask =3D 0x1, @@ -310,68 +311,74 @@ static struct clk_regmap g12a_aoclk_clk81 =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ + /* + * NOTE: this is one of the infamous clock the pwm driver + * can request directly by its global name. It's wrong but + * there is not much we can do about it until the support + * for the old pwm bindings is dropped + */ .name =3D "g12a_ao_clk81", .ops =3D &clk_regmap_mux_ro_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "mpeg-clk", }, - { .hw =3D &g12a_aoclk_cts_rtc_oscin.hw }, + { .hw =3D &g12a_ao_cts_rtc_oscin.hw }, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap g12a_aoclk_saradc_mux =3D { +static struct clk_regmap g12a_ao_saradc_mux =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_SAR_CLK, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_saradc_mux", + .name =3D "ao_saradc_mux", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "xtal", }, - { .hw =3D &g12a_aoclk_clk81.hw }, + { .hw =3D &g12a_ao_clk81.hw }, }, .num_parents =3D 2, }, }; =20 -static struct clk_regmap g12a_aoclk_saradc_div =3D { +static struct clk_regmap g12a_ao_saradc_div =3D { .data =3D &(struct clk_regmap_div_data) { .offset =3D AO_SAR_CLK, .shift =3D 0, .width =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_saradc_div", + .name =3D "ao_saradc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_saradc_mux.hw + &g12a_ao_saradc_mux.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap g12a_aoclk_saradc_gate =3D { +static struct clk_regmap g12a_ao_saradc_gate =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D AO_SAR_CLK, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "g12a_ao_saradc_gate", + .name =3D "ao_saradc_gate", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_aoclk_saradc_div.hw + &g12a_ao_saradc_div.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const unsigned int g12a_aoclk_reset[] =3D { +static const unsigned int g12a_ao_reset[] =3D { [RESET_AO_IR_IN] =3D 16, [RESET_AO_UART] =3D 17, [RESET_AO_I2C_M] =3D 18, @@ -381,65 +388,65 @@ static const unsigned int g12a_aoclk_reset[] =3D { [RESET_AO_IR_OUT] =3D 23, }; =20 -static struct clk_hw *g12a_aoclk_hw_clks[] =3D { - [CLKID_AO_AHB] =3D &g12a_aoclk_ahb.hw, - [CLKID_AO_IR_IN] =3D &g12a_aoclk_ir_in.hw, - [CLKID_AO_I2C_M0] =3D &g12a_aoclk_i2c_m0.hw, - [CLKID_AO_I2C_S0] =3D &g12a_aoclk_i2c_s0.hw, - [CLKID_AO_UART] =3D &g12a_aoclk_uart.hw, - [CLKID_AO_PROD_I2C] =3D &g12a_aoclk_prod_i2c.hw, - [CLKID_AO_UART2] =3D &g12a_aoclk_uart2.hw, - [CLKID_AO_IR_OUT] =3D &g12a_aoclk_ir_out.hw, - [CLKID_AO_SAR_ADC] =3D &g12a_aoclk_saradc.hw, - [CLKID_AO_MAILBOX] =3D &g12a_aoclk_mailbox.hw, - [CLKID_AO_M3] =3D &g12a_aoclk_m3.hw, - [CLKID_AO_AHB_SRAM] =3D &g12a_aoclk_ahb_sram.hw, - [CLKID_AO_RTI] =3D &g12a_aoclk_rti.hw, - [CLKID_AO_M4_FCLK] =3D &g12a_aoclk_m4_fclk.hw, - [CLKID_AO_M4_HCLK] =3D &g12a_aoclk_m4_hclk.hw, - [CLKID_AO_CLK81] =3D &g12a_aoclk_clk81.hw, - [CLKID_AO_SAR_ADC_SEL] =3D &g12a_aoclk_saradc_mux.hw, - [CLKID_AO_SAR_ADC_DIV] =3D &g12a_aoclk_saradc_div.hw, - [CLKID_AO_SAR_ADC_CLK] =3D &g12a_aoclk_saradc_gate.hw, - [CLKID_AO_CTS_OSCIN] =3D &g12a_aoclk_cts_oscin.hw, - [CLKID_AO_32K_PRE] =3D &g12a_aoclk_32k_by_oscin_pre.hw, - [CLKID_AO_32K_DIV] =3D &g12a_aoclk_32k_by_oscin_div.hw, - [CLKID_AO_32K_SEL] =3D &g12a_aoclk_32k_by_oscin_sel.hw, - [CLKID_AO_32K] =3D &g12a_aoclk_32k_by_oscin.hw, - [CLKID_AO_CEC_PRE] =3D &g12a_aoclk_cec_pre.hw, - [CLKID_AO_CEC_DIV] =3D &g12a_aoclk_cec_div.hw, - [CLKID_AO_CEC_SEL] =3D &g12a_aoclk_cec_sel.hw, - [CLKID_AO_CEC] =3D &g12a_aoclk_cec.hw, - [CLKID_AO_CTS_RTC_OSCIN] =3D &g12a_aoclk_cts_rtc_oscin.hw, +static struct clk_hw *g12a_ao_hw_clks[] =3D { + [CLKID_AO_AHB] =3D &g12a_ao_ahb.hw, + [CLKID_AO_IR_IN] =3D &g12a_ao_ir_in.hw, + [CLKID_AO_I2C_M0] =3D &g12a_ao_i2c_m0.hw, + [CLKID_AO_I2C_S0] =3D &g12a_ao_i2c_s0.hw, + [CLKID_AO_UART] =3D &g12a_ao_uart.hw, + [CLKID_AO_PROD_I2C] =3D &g12a_ao_prod_i2c.hw, + [CLKID_AO_UART2] =3D &g12a_ao_uart2.hw, + [CLKID_AO_IR_OUT] =3D &g12a_ao_ir_out.hw, + [CLKID_AO_SAR_ADC] =3D &g12a_ao_saradc.hw, + [CLKID_AO_MAILBOX] =3D &g12a_ao_mailbox.hw, + [CLKID_AO_M3] =3D &g12a_ao_m3.hw, + [CLKID_AO_AHB_SRAM] =3D &g12a_ao_ahb_sram.hw, + [CLKID_AO_RTI] =3D &g12a_ao_rti.hw, + [CLKID_AO_M4_FCLK] =3D &g12a_ao_m4_fclk.hw, + [CLKID_AO_M4_HCLK] =3D &g12a_ao_m4_hclk.hw, + [CLKID_AO_CLK81] =3D &g12a_ao_clk81.hw, + [CLKID_AO_SAR_ADC_SEL] =3D &g12a_ao_saradc_mux.hw, + [CLKID_AO_SAR_ADC_DIV] =3D &g12a_ao_saradc_div.hw, + [CLKID_AO_SAR_ADC_CLK] =3D &g12a_ao_saradc_gate.hw, + [CLKID_AO_CTS_OSCIN] =3D &g12a_ao_cts_oscin.hw, + [CLKID_AO_32K_PRE] =3D &g12a_ao_32k_by_oscin_pre.hw, + [CLKID_AO_32K_DIV] =3D &g12a_ao_32k_by_oscin_div.hw, + [CLKID_AO_32K_SEL] =3D &g12a_ao_32k_by_oscin_sel.hw, + [CLKID_AO_32K] =3D &g12a_ao_32k_by_oscin.hw, + [CLKID_AO_CEC_PRE] =3D &g12a_ao_cec_pre.hw, + [CLKID_AO_CEC_DIV] =3D &g12a_ao_cec_div.hw, + [CLKID_AO_CEC_SEL] =3D &g12a_ao_cec_sel.hw, + [CLKID_AO_CEC] =3D &g12a_ao_cec.hw, + [CLKID_AO_CTS_RTC_OSCIN] =3D &g12a_ao_cts_rtc_oscin.hw, }; =20 -static const struct meson_aoclk_data g12a_aoclkc_data =3D { +static const struct meson_aoclk_data g12a_ao_clkc_data =3D { .reset_reg =3D AO_RTI_GEN_CNTL_REG0, - .num_reset =3D ARRAY_SIZE(g12a_aoclk_reset), - .reset =3D g12a_aoclk_reset, + .num_reset =3D ARRAY_SIZE(g12a_ao_reset), + .reset =3D g12a_ao_reset, .hw_clks =3D { - .hws =3D g12a_aoclk_hw_clks, - .num =3D ARRAY_SIZE(g12a_aoclk_hw_clks), + .hws =3D g12a_ao_hw_clks, + .num =3D ARRAY_SIZE(g12a_ao_hw_clks), }, }; =20 -static const struct of_device_id g12a_aoclkc_match_table[] =3D { +static const struct of_device_id g12a_ao_clkc_match_table[] =3D { { .compatible =3D "amlogic,meson-g12a-aoclkc", - .data =3D &g12a_aoclkc_data, + .data =3D &g12a_ao_clkc_data, }, { } }; -MODULE_DEVICE_TABLE(of, g12a_aoclkc_match_table); +MODULE_DEVICE_TABLE(of, g12a_ao_clkc_match_table); =20 -static struct platform_driver g12a_aoclkc_driver =3D { +static struct platform_driver g12a_ao_clkc_driver =3D { .probe =3D meson_aoclkc_probe, .driver =3D { .name =3D "g12a-aoclkc", - .of_match_table =3D g12a_aoclkc_match_table, + .of_match_table =3D g12a_ao_clkc_match_table, }, }; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet --- drivers/clk/meson/g12a.c | 3240 +++++++++++++++++++++++-------------------= ---- 1 file changed, 1608 insertions(+), 1632 deletions(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 1b30f1bcca5535cabbfeca16338f6d9f7e79198d..9de0531821a8f0297273189b44a= 81024d8bf9093 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -386,1935 +386,1912 @@ static struct clk_fixed_factor g12b_sys1_pll_div1= 6 =3D { }, }; =20 -static struct clk_fixed_factor g12a_fclk_div2_div =3D { - .mult =3D 1, - .div =3D 2, - .hw.init =3D &(struct clk_init_data){ - .name =3D "fclk_div2_div", - .ops =3D &clk_fixed_factor_ops, - .parent_hws =3D (const struct clk_hw *[]) { &g12a_fixed_pll.hw }, - .num_parents =3D 1, - }, +static const struct pll_mult_range g12a_gp0_pll_mult_range =3D { + .min =3D 125, + .max =3D 255, }; =20 -static struct clk_regmap g12a_fclk_div2 =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_FIX_PLL_CNTL1, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "fclk_div2", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12a_fclk_div2_div.hw - }, - .num_parents =3D 1, - /* - * Similar to fclk_div3, it seems that this clock is used by - * the resident firmware and is required by the platform to - * operate correctly. - * Until the following condition are met, we need this clock to - * be marked as critical: - * a) Mark the clock used by a firmware resource, if possible - * b) CCF has a clock hand-off mechanism to make the sure the - * clock stays on until the proper driver comes along - */ - .flags =3D CLK_IS_CRITICAL, - }, +/* + * Internal gp0 pll emulation configuration parameters + */ +static const struct reg_sequence g12a_gp0_pll_init_regs[] =3D { + { .reg =3D HHI_GP0_PLL_CNTL1, .def =3D 0x00000000 }, + { .reg =3D HHI_GP0_PLL_CNTL2, .def =3D 0x00000000 }, + { .reg =3D HHI_GP0_PLL_CNTL3, .def =3D 0x48681c00 }, + { .reg =3D HHI_GP0_PLL_CNTL4, .def =3D 0x33771290 }, + { .reg =3D HHI_GP0_PLL_CNTL5, .def =3D 0x39272000 }, + { .reg =3D HHI_GP0_PLL_CNTL6, .def =3D 0x56540000 }, }; =20 -static struct clk_fixed_factor g12a_fclk_div3_div =3D { - .mult =3D 1, - .div =3D 3, +static struct clk_regmap g12a_gp0_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D HHI_GP0_PLL_CNTL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D HHI_GP0_PLL_CNTL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D HHI_GP0_PLL_CNTL0, + .shift =3D 10, + .width =3D 5, + }, + .frac =3D { + .reg_off =3D HHI_GP0_PLL_CNTL1, + .shift =3D 0, + .width =3D 17, + }, + .l =3D { + .reg_off =3D HHI_GP0_PLL_CNTL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D HHI_GP0_PLL_CNTL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &g12a_gp0_pll_mult_range, + .init_regs =3D g12a_gp0_pll_init_regs, + .init_count =3D ARRAY_SIZE(g12a_gp0_pll_init_regs), + }, .hw.init =3D &(struct clk_init_data){ - .name =3D "fclk_div3_div", - .ops =3D &clk_fixed_factor_ops, - .parent_hws =3D (const struct clk_hw *[]) { &g12a_fixed_pll.hw }, + .name =3D "gp0_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap g12a_fclk_div3 =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_FIX_PLL_CNTL1, - .bit_idx =3D 20, +static struct clk_regmap g12a_gp0_pll =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HHI_GP0_PLL_CNTL0, + .shift =3D 16, + .width =3D 3, + .flags =3D (CLK_DIVIDER_POWER_OF_TWO | + CLK_DIVIDER_ROUND_CLOSEST), }, .hw.init =3D &(struct clk_init_data){ - .name =3D "fclk_div3", - .ops =3D &clk_regmap_gate_ops, + .name =3D "gp0_pll", + .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_fclk_div3_div.hw + &g12a_gp0_pll_dco.hw }, .num_parents =3D 1, - /* - * This clock is used by the resident firmware and is required - * by the platform to operate correctly. - * Until the following condition are met, we need this clock to - * be marked as critical: - * a) Mark the clock used by a firmware resource, if possible - * b) CCF has a clock hand-off mechanism to make the sure the - * clock stays on until the proper driver comes along - */ - .flags =3D CLK_IS_CRITICAL, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -/* Datasheet names this field as "premux0" */ -static struct clk_regmap g12a_cpu_clk_premux0 =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL0, - .mask =3D 0x3, - .shift =3D 0, - .flags =3D CLK_MUX_ROUND_CLOSEST, +static struct clk_regmap sm1_gp1_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D HHI_GP1_PLL_CNTL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D HHI_GP1_PLL_CNTL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D HHI_GP1_PLL_CNTL0, + .shift =3D 10, + .width =3D 5, + }, + .frac =3D { + .reg_off =3D HHI_GP1_PLL_CNTL1, + .shift =3D 0, + .width =3D 17, + }, + .l =3D { + .reg_off =3D HHI_GP1_PLL_CNTL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D HHI_GP1_PLL_CNTL0, + .shift =3D 29, + .width =3D 1, + }, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk_dyn0_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D (const struct clk_parent_data []) { - { .fw_name =3D "xtal", }, - { .hw =3D &g12a_fclk_div2.hw }, - { .hw =3D &g12a_fclk_div3.hw }, + .name =3D "gp1_pll_dco", + .ops =3D &meson_clk_pll_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", }, - .num_parents =3D 3, - .flags =3D CLK_SET_RATE_PARENT, + .num_parents =3D 1, + /* This clock feeds the DSU, avoid disabling it */ + .flags =3D CLK_IS_CRITICAL, }, }; =20 -/* Datasheet names this field as "premux1" */ -static struct clk_regmap g12a_cpu_clk_premux1 =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL0, - .mask =3D 0x3, +static struct clk_regmap sm1_gp1_pll =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HHI_GP1_PLL_CNTL0, .shift =3D 16, + .width =3D 3, + .flags =3D (CLK_DIVIDER_POWER_OF_TWO | + CLK_DIVIDER_ROUND_CLOSEST), }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk_dyn1_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D (const struct clk_parent_data []) { - { .fw_name =3D "xtal", }, - { .hw =3D &g12a_fclk_div2.hw }, - { .hw =3D &g12a_fclk_div3.hw }, + .name =3D "gp1_pll", + .ops =3D &clk_regmap_divider_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sm1_gp1_pll_dco.hw }, - .num_parents =3D 3, - /* This sub-tree is used a parking clock */ - .flags =3D CLK_SET_RATE_NO_REPARENT + .num_parents =3D 1, }, }; =20 -/* Datasheet names this field as "mux0_divn_tcnt" */ -static struct clk_regmap g12a_cpu_clk_mux0_div =3D { - .data =3D &(struct meson_clk_cpu_dyndiv_data){ - .div =3D { - .reg_off =3D HHI_SYS_CPU_CLK_CNTL0, - .shift =3D 4, - .width =3D 6, +/* + * Internal hifi pll emulation configuration parameters + */ +static const struct reg_sequence g12a_hifi_pll_init_regs[] =3D { + { .reg =3D HHI_HIFI_PLL_CNTL1, .def =3D 0x00000000 }, + { .reg =3D HHI_HIFI_PLL_CNTL2, .def =3D 0x00000000 }, + { .reg =3D HHI_HIFI_PLL_CNTL3, .def =3D 0x6a285c00 }, + { .reg =3D HHI_HIFI_PLL_CNTL4, .def =3D 0x65771290 }, + { .reg =3D HHI_HIFI_PLL_CNTL5, .def =3D 0x39272000 }, + { .reg =3D HHI_HIFI_PLL_CNTL6, .def =3D 0x56540000 }, +}; + +static struct clk_regmap g12a_hifi_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D HHI_HIFI_PLL_CNTL0, + .shift =3D 28, + .width =3D 1, }, - .dyn =3D { - .reg_off =3D HHI_SYS_CPU_CLK_CNTL0, - .shift =3D 26, - .width =3D 1, + .m =3D { + .reg_off =3D HHI_HIFI_PLL_CNTL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D HHI_HIFI_PLL_CNTL0, + .shift =3D 10, + .width =3D 5, + }, + .frac =3D { + .reg_off =3D HHI_HIFI_PLL_CNTL1, + .shift =3D 0, + .width =3D 17, + }, + .l =3D { + .reg_off =3D HHI_HIFI_PLL_CNTL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D HHI_HIFI_PLL_CNTL0, + .shift =3D 29, + .width =3D 1, }, + .range =3D &g12a_gp0_pll_mult_range, + .init_regs =3D g12a_hifi_pll_init_regs, + .init_count =3D ARRAY_SIZE(g12a_hifi_pll_init_regs), + .flags =3D CLK_MESON_PLL_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk_dyn0_div", - .ops =3D &meson_clk_cpu_dyndiv_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk_premux0.hw + .name =3D "hifi_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -/* Datasheet names this field as "postmux0" */ -static struct clk_regmap g12a_cpu_clk_postmux0 =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL0, - .mask =3D 0x1, - .shift =3D 2, - .flags =3D CLK_MUX_ROUND_CLOSEST, +static struct clk_regmap g12a_hifi_pll =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HHI_HIFI_PLL_CNTL0, + .shift =3D 16, + .width =3D 2, + .flags =3D (CLK_DIVIDER_POWER_OF_TWO | + CLK_DIVIDER_ROUND_CLOSEST), }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk_dyn0", - .ops =3D &clk_regmap_mux_ops, + .name =3D "hifi_pll", + .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk_premux0.hw, - &g12a_cpu_clk_mux0_div.hw, + &g12a_hifi_pll_dco.hw }, - .num_parents =3D 2, + .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -/* Datasheet names this field as "Mux1_divn_tcnt" */ -static struct clk_regmap g12a_cpu_clk_mux1_div =3D { - .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL0, - .shift =3D 20, - .width =3D 6, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk_dyn1_div", - .ops =3D &clk_regmap_divider_ro_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk_premux1.hw - }, - .num_parents =3D 1, - }, +/* + * The Meson G12A PCIE PLL is fined tuned to deliver a very precise + * 100MHz reference clock for the PCIe Analog PHY, and thus requires + * a strict register sequence to enable the PLL. + */ +static const struct reg_sequence g12a_pcie_pll_init_regs[] =3D { + { .reg =3D HHI_PCIE_PLL_CNTL0, .def =3D 0x20090496 }, + { .reg =3D HHI_PCIE_PLL_CNTL0, .def =3D 0x30090496 }, + { .reg =3D HHI_PCIE_PLL_CNTL1, .def =3D 0x00000000 }, + { .reg =3D HHI_PCIE_PLL_CNTL2, .def =3D 0x00001100 }, + { .reg =3D HHI_PCIE_PLL_CNTL3, .def =3D 0x10058e00 }, + { .reg =3D HHI_PCIE_PLL_CNTL4, .def =3D 0x000100c0 }, + { .reg =3D HHI_PCIE_PLL_CNTL5, .def =3D 0x68000048 }, + { .reg =3D HHI_PCIE_PLL_CNTL5, .def =3D 0x68000068, .delay_us =3D 20 }, + { .reg =3D HHI_PCIE_PLL_CNTL4, .def =3D 0x008100c0, .delay_us =3D 10 }, + { .reg =3D HHI_PCIE_PLL_CNTL0, .def =3D 0x34090496 }, + { .reg =3D HHI_PCIE_PLL_CNTL0, .def =3D 0x14090496, .delay_us =3D 10 }, + { .reg =3D HHI_PCIE_PLL_CNTL2, .def =3D 0x00001000 }, }; =20 -/* Datasheet names this field as "postmux1" */ -static struct clk_regmap g12a_cpu_clk_postmux1 =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL0, - .mask =3D 0x1, - .shift =3D 18, +/* Keep a single entry table for recalc/round_rate() ops */ +static const struct pll_params_table g12a_pcie_pll_table[] =3D { + PLL_PARAMS(150, 1), + {0, 0}, +}; + +static struct clk_regmap g12a_pcie_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D HHI_PCIE_PLL_CNTL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D HHI_PCIE_PLL_CNTL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D HHI_PCIE_PLL_CNTL0, + .shift =3D 10, + .width =3D 5, + }, + .frac =3D { + .reg_off =3D HHI_PCIE_PLL_CNTL1, + .shift =3D 0, + .width =3D 12, + }, + .l =3D { + .reg_off =3D HHI_PCIE_PLL_CNTL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D HHI_PCIE_PLL_CNTL0, + .shift =3D 29, + .width =3D 1, + }, + .table =3D g12a_pcie_pll_table, + .init_regs =3D g12a_pcie_pll_init_regs, + .init_count =3D ARRAY_SIZE(g12a_pcie_pll_init_regs), }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk_dyn1", - .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk_premux1.hw, - &g12a_cpu_clk_mux1_div.hw, + .name =3D "pcie_pll_dco", + .ops =3D &meson_clk_pcie_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", }, - .num_parents =3D 2, - /* This sub-tree is used a parking clock */ - .flags =3D CLK_SET_RATE_NO_REPARENT, + .num_parents =3D 1, }, }; =20 -/* Datasheet names this field as "Final_dyn_mux_sel" */ -static struct clk_regmap g12a_cpu_clk_dyn =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL0, - .mask =3D 0x1, - .shift =3D 10, - .flags =3D CLK_MUX_ROUND_CLOSEST, - }, +static struct clk_fixed_factor g12a_pcie_pll_dco_div2 =3D { + .mult =3D 1, + .div =3D 2, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk_dyn", - .ops =3D &clk_regmap_mux_ops, + .name =3D "pcie_pll_dco_div2", + .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk_postmux0.hw, - &g12a_cpu_clk_postmux1.hw, + &g12a_pcie_pll_dco.hw }, - .num_parents =3D 2, + .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -/* Datasheet names this field as "Final_mux_sel" */ -static struct clk_regmap g12a_cpu_clk =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL0, - .mask =3D 0x1, - .shift =3D 11, - .flags =3D CLK_MUX_ROUND_CLOSEST, +static struct clk_regmap g12a_pcie_pll_od =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HHI_PCIE_PLL_CNTL0, + .shift =3D 16, + .width =3D 5, + .flags =3D CLK_DIVIDER_ROUND_CLOSEST | + CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk", - .ops =3D &clk_regmap_mux_ops, + .name =3D "pcie_pll_od", + .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk_dyn.hw, - &g12a_sys_pll.hw, + &g12a_pcie_pll_dco_div2.hw }, - .num_parents =3D 2, + .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -/* Datasheet names this field as "Final_mux_sel" */ -static struct clk_regmap g12b_cpu_clk =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL0, - .mask =3D 0x1, - .shift =3D 11, - .flags =3D CLK_MUX_ROUND_CLOSEST, - }, +static struct clk_fixed_factor g12a_pcie_pll =3D { + .mult =3D 1, + .div =3D 2, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk", - .ops =3D &clk_regmap_mux_ops, + .name =3D "pcie_pll_pll", + .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk_dyn.hw, - &g12b_sys1_pll.hw + &g12a_pcie_pll_od.hw }, - .num_parents =3D 2, + .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -/* Datasheet names this field as "premux0" */ -static struct clk_regmap g12b_cpub_clk_premux0 =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL, - .mask =3D 0x3, - .shift =3D 0, - .flags =3D CLK_MUX_ROUND_CLOSEST, +static struct clk_regmap g12a_hdmi_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D HHI_HDMI_PLL_CNTL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D HHI_HDMI_PLL_CNTL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D HHI_HDMI_PLL_CNTL0, + .shift =3D 10, + .width =3D 5, + }, + .frac =3D { + .reg_off =3D HHI_HDMI_PLL_CNTL1, + .shift =3D 0, + .width =3D 16, + }, + .l =3D { + .reg_off =3D HHI_HDMI_PLL_CNTL0, + .shift =3D 30, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D HHI_HDMI_PLL_CNTL0, + .shift =3D 29, + .width =3D 1, + }, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_dyn0_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D (const struct clk_parent_data []) { - { .fw_name =3D "xtal", }, - { .hw =3D &g12a_fclk_div2.hw }, - { .hw =3D &g12a_fclk_div3.hw }, + .name =3D "hdmi_pll_dco", + .ops =3D &meson_clk_pll_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", }, - .num_parents =3D 3, - .flags =3D CLK_SET_RATE_PARENT, + .num_parents =3D 1, + /* + * Display directly handle hdmi pll registers ATM, we need + * NOCACHE to keep our view of the clock as accurate as possible + */ + .flags =3D CLK_GET_RATE_NOCACHE, }, }; =20 -/* Datasheet names this field as "mux0_divn_tcnt" */ -static struct clk_regmap g12b_cpub_clk_mux0_div =3D { - .data =3D &(struct meson_clk_cpu_dyndiv_data){ - .div =3D { - .reg_off =3D HHI_SYS_CPUB_CLK_CNTL, - .shift =3D 4, - .width =3D 6, - }, - .dyn =3D { - .reg_off =3D HHI_SYS_CPUB_CLK_CNTL, - .shift =3D 26, - .width =3D 1, - }, +static struct clk_regmap g12a_hdmi_pll_od =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HHI_HDMI_PLL_CNTL0, + .shift =3D 16, + .width =3D 2, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_dyn0_div", - .ops =3D &meson_clk_cpu_dyndiv_ops, + .name =3D "hdmi_pll_od", + .ops =3D &clk_regmap_divider_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_premux0.hw + &g12a_hdmi_pll_dco.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, + .flags =3D CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, }, }; =20 -/* Datasheet names this field as "postmux0" */ -static struct clk_regmap g12b_cpub_clk_postmux0 =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL, - .mask =3D 0x1, - .shift =3D 2, - .flags =3D CLK_MUX_ROUND_CLOSEST, +static struct clk_regmap g12a_hdmi_pll_od2 =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HHI_HDMI_PLL_CNTL0, + .shift =3D 18, + .width =3D 2, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_dyn0", - .ops =3D &clk_regmap_mux_ops, + .name =3D "hdmi_pll_od2", + .ops =3D &clk_regmap_divider_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_premux0.hw, - &g12b_cpub_clk_mux0_div.hw - }, - .num_parents =3D 2, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -/* Datasheet names this field as "premux1" */ -static struct clk_regmap g12b_cpub_clk_premux1 =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL, - .mask =3D 0x3, - .shift =3D 16, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_dyn1_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D (const struct clk_parent_data []) { - { .fw_name =3D "xtal", }, - { .hw =3D &g12a_fclk_div2.hw }, - { .hw =3D &g12a_fclk_div3.hw }, + &g12a_hdmi_pll_od.hw }, - .num_parents =3D 3, - /* This sub-tree is used a parking clock */ - .flags =3D CLK_SET_RATE_NO_REPARENT, + .num_parents =3D 1, + .flags =3D CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, }, }; =20 -/* Datasheet names this field as "Mux1_divn_tcnt" */ -static struct clk_regmap g12b_cpub_clk_mux1_div =3D { +static struct clk_regmap g12a_hdmi_pll =3D { .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL, + .offset =3D HHI_HDMI_PLL_CNTL0, .shift =3D 20, - .width =3D 6, + .width =3D 2, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_dyn1_div", + .name =3D "hdmi_pll", .ops =3D &clk_regmap_divider_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_premux1.hw + &g12a_hdmi_pll_od2.hw }, .num_parents =3D 1, + .flags =3D CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, }, }; =20 -/* Datasheet names this field as "postmux1" */ -static struct clk_regmap g12b_cpub_clk_postmux1 =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL, - .mask =3D 0x1, - .shift =3D 18, - }, +static struct clk_fixed_factor g12a_fclk_div2_div =3D { + .mult =3D 1, + .div =3D 2, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_dyn1", - .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_premux1.hw, - &g12b_cpub_clk_mux1_div.hw - }, - .num_parents =3D 2, - /* This sub-tree is used a parking clock */ - .flags =3D CLK_SET_RATE_NO_REPARENT, + .name =3D "fclk_div2_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { &g12a_fixed_pll.hw }, + .num_parents =3D 1, }, }; =20 -/* Datasheet names this field as "Final_dyn_mux_sel" */ -static struct clk_regmap g12b_cpub_clk_dyn =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL, - .mask =3D 0x1, - .shift =3D 10, - .flags =3D CLK_MUX_ROUND_CLOSEST, +static struct clk_regmap g12a_fclk_div2 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_FIX_PLL_CNTL1, + .bit_idx =3D 24, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_dyn", - .ops =3D &clk_regmap_mux_ops, + .name =3D "fclk_div2", + .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_postmux0.hw, - &g12b_cpub_clk_postmux1.hw + &g12a_fclk_div2_div.hw }, - .num_parents =3D 2, - .flags =3D CLK_SET_RATE_PARENT, + .num_parents =3D 1, + /* + * Similar to fclk_div3, it seems that this clock is used by + * the resident firmware and is required by the platform to + * operate correctly. + * Until the following condition are met, we need this clock to + * be marked as critical: + * a) Mark the clock used by a firmware resource, if possible + * b) CCF has a clock hand-off mechanism to make the sure the + * clock stays on until the proper driver comes along + */ + .flags =3D CLK_IS_CRITICAL, }, }; =20 -/* Datasheet names this field as "Final_mux_sel" */ -static struct clk_regmap g12b_cpub_clk =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL, - .mask =3D 0x1, - .shift =3D 11, - .flags =3D CLK_MUX_ROUND_CLOSEST, +static struct clk_fixed_factor g12a_fclk_div3_div =3D { + .mult =3D 1, + .div =3D 3, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fclk_div3_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { &g12a_fixed_pll.hw }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap g12a_fclk_div3 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_FIX_PLL_CNTL1, + .bit_idx =3D 20, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk", - .ops =3D &clk_regmap_mux_ops, + .name =3D "fclk_div3", + .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_dyn.hw, - &g12a_sys_pll.hw + &g12a_fclk_div3_div.hw }, - .num_parents =3D 2, - .flags =3D CLK_SET_RATE_PARENT, + .num_parents =3D 1, + /* + * This clock is used by the resident firmware and is required + * by the platform to operate correctly. + * Until the following condition are met, we need this clock to + * be marked as critical: + * a) Mark the clock used by a firmware resource, if possible + * b) CCF has a clock hand-off mechanism to make the sure the + * clock stays on until the proper driver comes along + */ + .flags =3D CLK_IS_CRITICAL, }, }; =20 -static struct clk_regmap sm1_gp1_pll; =20 -/* Datasheet names this field as "premux0" */ -static struct clk_regmap sm1_dsu_clk_premux0 =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL5, - .mask =3D 0x3, - .shift =3D 0, - }, +static struct clk_fixed_factor g12a_fclk_div4_div =3D { + .mult =3D 1, + .div =3D 4, .hw.init =3D &(struct clk_init_data){ - .name =3D "dsu_clk_dyn0_sel", - .ops =3D &clk_regmap_mux_ro_ops, - .parent_data =3D (const struct clk_parent_data []) { - { .fw_name =3D "xtal", }, - { .hw =3D &g12a_fclk_div2.hw }, - { .hw =3D &g12a_fclk_div3.hw }, - { .hw =3D &sm1_gp1_pll.hw }, - }, - .num_parents =3D 4, + .name =3D "fclk_div4_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { &g12a_fixed_pll.hw }, + .num_parents =3D 1, }, }; =20 -/* Datasheet names this field as "premux1" */ -static struct clk_regmap sm1_dsu_clk_premux1 =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL5, - .mask =3D 0x3, - .shift =3D 16, +static struct clk_regmap g12a_fclk_div4 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_FIX_PLL_CNTL1, + .bit_idx =3D 21, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "dsu_clk_dyn1_sel", - .ops =3D &clk_regmap_mux_ro_ops, - .parent_data =3D (const struct clk_parent_data []) { - { .fw_name =3D "xtal", }, - { .hw =3D &g12a_fclk_div2.hw }, - { .hw =3D &g12a_fclk_div3.hw }, - { .hw =3D &sm1_gp1_pll.hw }, + .name =3D "fclk_div4", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12a_fclk_div4_div.hw }, - .num_parents =3D 4, + .num_parents =3D 1, }, }; =20 -/* Datasheet names this field as "Mux0_divn_tcnt" */ -static struct clk_regmap sm1_dsu_clk_mux0_div =3D { - .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL5, - .shift =3D 4, - .width =3D 6, - }, +static struct clk_fixed_factor g12a_fclk_div5_div =3D { + .mult =3D 1, + .div =3D 5, .hw.init =3D &(struct clk_init_data){ - .name =3D "dsu_clk_dyn0_div", - .ops =3D &clk_regmap_divider_ro_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &sm1_dsu_clk_premux0.hw - }, + .name =3D "fclk_div5_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { &g12a_fixed_pll.hw }, .num_parents =3D 1, }, }; =20 -/* Datasheet names this field as "postmux0" */ -static struct clk_regmap sm1_dsu_clk_postmux0 =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL5, - .mask =3D 0x1, - .shift =3D 2, +static struct clk_regmap g12a_fclk_div5 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_FIX_PLL_CNTL1, + .bit_idx =3D 22, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "dsu_clk_dyn0", - .ops =3D &clk_regmap_mux_ro_ops, + .name =3D "fclk_div5", + .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sm1_dsu_clk_premux0.hw, - &sm1_dsu_clk_mux0_div.hw, + &g12a_fclk_div5_div.hw }, - .num_parents =3D 2, + .num_parents =3D 1, }, }; =20 -/* Datasheet names this field as "Mux1_divn_tcnt" */ -static struct clk_regmap sm1_dsu_clk_mux1_div =3D { - .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL5, - .shift =3D 20, - .width =3D 6, +static struct clk_fixed_factor g12a_fclk_div7_div =3D { + .mult =3D 1, + .div =3D 7, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fclk_div7_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { &g12a_fixed_pll.hw }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap g12a_fclk_div7 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_FIX_PLL_CNTL1, + .bit_idx =3D 23, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "dsu_clk_dyn1_div", - .ops =3D &clk_regmap_divider_ro_ops, + .name =3D "fclk_div7", + .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sm1_dsu_clk_premux1.hw + &g12a_fclk_div7_div.hw }, .num_parents =3D 1, }, }; =20 -/* Datasheet names this field as "postmux1" */ -static struct clk_regmap sm1_dsu_clk_postmux1 =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL5, - .mask =3D 0x1, - .shift =3D 18, - }, +static struct clk_fixed_factor g12a_fclk_div2p5_div =3D { + .mult =3D 1, + .div =3D 5, .hw.init =3D &(struct clk_init_data){ - .name =3D "dsu_clk_dyn1", - .ops =3D &clk_regmap_mux_ro_ops, + .name =3D "fclk_div2p5_div", + .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sm1_dsu_clk_premux1.hw, - &sm1_dsu_clk_mux1_div.hw, + &g12a_fixed_pll_dco.hw }, - .num_parents =3D 2, + .num_parents =3D 1, }, }; =20 -/* Datasheet names this field as "Final_dyn_mux_sel" */ -static struct clk_regmap sm1_dsu_clk_dyn =3D { +static struct clk_regmap g12a_fclk_div2p5 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_FIX_PLL_CNTL1, + .bit_idx =3D 25, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fclk_div2p5", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12a_fclk_div2p5_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor g12a_mpll_50m_div =3D { + .mult =3D 1, + .div =3D 80, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll_50m_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12a_fixed_pll_dco.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap g12a_mpll_50m =3D { .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL5, + .offset =3D HHI_FIX_PLL_CNTL3, .mask =3D 0x1, - .shift =3D 10, + .shift =3D 5, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "dsu_clk_dyn", + .name =3D "mpll_50m", .ops =3D &clk_regmap_mux_ro_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &sm1_dsu_clk_postmux0.hw, - &sm1_dsu_clk_postmux1.hw, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .hw =3D &g12a_mpll_50m_div.hw }, }, .num_parents =3D 2, }, }; =20 -/* Datasheet names this field as "Final_mux_sel" */ -static struct clk_regmap sm1_dsu_final_clk =3D { +static struct clk_fixed_factor g12a_mpll_prediv =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll_prediv", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12a_fixed_pll_dco.hw + }, + .num_parents =3D 1, + }, +}; + +/* Datasheet names this field as "premux0" */ +static struct clk_regmap g12a_cpu_clk_dyn0_sel =3D { .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL5, + .offset =3D HHI_SYS_CPU_CLK_CNTL0, + .mask =3D 0x3, + .shift =3D 0, + .flags =3D CLK_MUX_ROUND_CLOSEST, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cpu_clk_dyn0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .hw =3D &g12a_fclk_div2.hw }, + { .hw =3D &g12a_fclk_div3.hw }, + }, + .num_parents =3D 3, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* Datasheet names this field as "mux0_divn_tcnt" */ +static struct clk_regmap g12a_cpu_clk_dyn0_div =3D { + .data =3D &(struct meson_clk_cpu_dyndiv_data){ + .div =3D { + .reg_off =3D HHI_SYS_CPU_CLK_CNTL0, + .shift =3D 4, + .width =3D 6, + }, + .dyn =3D { + .reg_off =3D HHI_SYS_CPU_CLK_CNTL0, + .shift =3D 26, + .width =3D 1, + }, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cpu_clk_dyn0_div", + .ops =3D &meson_clk_cpu_dyndiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12a_cpu_clk_dyn0_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* Datasheet names this field as "postmux0" */ +static struct clk_regmap g12a_cpu_clk_dyn0 =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL0, .mask =3D 0x1, - .shift =3D 11, + .shift =3D 2, + .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "dsu_clk_final", - .ops =3D &clk_regmap_mux_ro_ops, + .name =3D "cpu_clk_dyn0", + .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &sm1_dsu_clk_dyn.hw, - &g12a_sys_pll.hw, + &g12a_cpu_clk_dyn0_sel.hw, + &g12a_cpu_clk_dyn0_div.hw, }, .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */ -static struct clk_regmap sm1_cpu1_clk =3D { +/* Datasheet names this field as "premux1" */ +static struct clk_regmap g12a_cpu_clk_dyn1_sel =3D { .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL6, - .mask =3D 0x1, - .shift =3D 24, + .offset =3D HHI_SYS_CPU_CLK_CNTL0, + .mask =3D 0x3, + .shift =3D 16, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu1_clk", - .ops =3D &clk_regmap_mux_ro_ops, + .name =3D "cpu_clk_dyn1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .hw =3D &g12a_fclk_div2.hw }, + { .hw =3D &g12a_fclk_div3.hw }, + }, + .num_parents =3D 3, + /* This sub-tree is used a parking clock */ + .flags =3D CLK_SET_RATE_NO_REPARENT + }, +}; + +/* Datasheet names this field as "Mux1_divn_tcnt" */ +static struct clk_regmap g12a_cpu_clk_dyn1_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL0, + .shift =3D 20, + .width =3D 6, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cpu_clk_dyn1_div", + .ops =3D &clk_regmap_divider_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk.hw, - /* This CPU also have a dedicated clock tree */ + &g12a_cpu_clk_dyn1_sel.hw }, .num_parents =3D 1, }, }; =20 -/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */ -static struct clk_regmap sm1_cpu2_clk =3D { +/* Datasheet names this field as "postmux1" */ +static struct clk_regmap g12a_cpu_clk_dyn1 =3D { .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL6, + .offset =3D HHI_SYS_CPU_CLK_CNTL0, .mask =3D 0x1, - .shift =3D 25, + .shift =3D 18, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu2_clk", - .ops =3D &clk_regmap_mux_ro_ops, + .name =3D "cpu_clk_dyn1", + .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk.hw, - /* This CPU also have a dedicated clock tree */ + &g12a_cpu_clk_dyn1_sel.hw, + &g12a_cpu_clk_dyn1_div.hw, }, - .num_parents =3D 1, + .num_parents =3D 2, + /* This sub-tree is used a parking clock */ + .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; =20 -/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */ -static struct clk_regmap sm1_cpu3_clk =3D { +/* Datasheet names this field as "Final_dyn_mux_sel" */ +static struct clk_regmap g12a_cpu_clk_dyn =3D { .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL6, + .offset =3D HHI_SYS_CPU_CLK_CNTL0, .mask =3D 0x1, - .shift =3D 26, + .shift =3D 10, + .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu3_clk", - .ops =3D &clk_regmap_mux_ro_ops, + .name =3D "cpu_clk_dyn", + .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk.hw, - /* This CPU also have a dedicated clock tree */ + &g12a_cpu_clk_dyn0.hw, + &g12a_cpu_clk_dyn1.hw, }, - .num_parents =3D 1, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */ -static struct clk_regmap sm1_dsu_clk =3D { +/* Datasheet names this field as "Final_mux_sel" */ +static struct clk_regmap g12a_cpu_clk =3D { .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL6, + .offset =3D HHI_SYS_CPU_CLK_CNTL0, .mask =3D 0x1, - .shift =3D 27, + .shift =3D 11, + .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "dsu_clk", - .ops =3D &clk_regmap_mux_ro_ops, + .name =3D "cpu_clk", + .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk.hw, - &sm1_dsu_final_clk.hw, + &g12a_cpu_clk_dyn.hw, + &g12a_sys_pll.hw, }, .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb, - unsigned long event, void *data) -{ - if (event =3D=3D POST_RATE_CHANGE || event =3D=3D PRE_RATE_CHANGE) { - /* Wait for clock propagation before/after changing the mux */ - udelay(100); - return NOTIFY_OK; - } - - return NOTIFY_DONE; -} - -static struct notifier_block g12a_cpu_clk_mux_nb =3D { - .notifier_call =3D g12a_cpu_clk_mux_notifier_cb, +/* Datasheet names this field as "Final_mux_sel" */ +static struct clk_regmap g12b_cpu_clk =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL0, + .mask =3D 0x1, + .shift =3D 11, + .flags =3D CLK_MUX_ROUND_CLOSEST, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cpu_clk", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12a_cpu_clk_dyn.hw, + &g12b_sys1_pll.hw + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, }; =20 -struct g12a_cpu_clk_postmux_nb_data { - struct notifier_block nb; - struct clk_hw *xtal; - struct clk_hw *cpu_clk_dyn; - struct clk_hw *cpu_clk_postmux0; - struct clk_hw *cpu_clk_postmux1; - struct clk_hw *cpu_clk_premux1; +/* Datasheet names this field as "premux0" */ +static struct clk_regmap g12b_cpub_clk_dyn0_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL, + .mask =3D 0x3, + .shift =3D 0, + .flags =3D CLK_MUX_ROUND_CLOSEST, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cpub_clk_dyn0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .hw =3D &g12a_fclk_div2.hw }, + { .hw =3D &g12a_fclk_div3.hw }, + }, + .num_parents =3D 3, + .flags =3D CLK_SET_RATE_PARENT, + }, }; =20 -static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb, - unsigned long event, void *data) -{ - struct g12a_cpu_clk_postmux_nb_data *nb_data =3D - container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb); - - switch (event) { - case PRE_RATE_CHANGE: - /* - * This notifier means cpu_clk_postmux0 clock will be changed - * to feed cpu_clk, this is the current path : - * cpu_clk - * \- cpu_clk_dyn - * \- cpu_clk_postmux0 - * \- cpu_clk_muxX_div - * \- cpu_clk_premux0 - * \- fclk_div3 or fclk_div2 - * OR - * \- cpu_clk_premux0 - * \- fclk_div3 or fclk_div2 - */ - - /* Setup cpu_clk_premux1 to xtal */ - clk_hw_set_parent(nb_data->cpu_clk_premux1, - nb_data->xtal); - - /* Setup cpu_clk_postmux1 to bypass divider */ - clk_hw_set_parent(nb_data->cpu_clk_postmux1, - nb_data->cpu_clk_premux1); - - /* Switch to parking clk on cpu_clk_postmux1 */ - clk_hw_set_parent(nb_data->cpu_clk_dyn, - nb_data->cpu_clk_postmux1); - - /* - * Now, cpu_clk is 24MHz in the current path : - * cpu_clk - * \- cpu_clk_dyn - * \- cpu_clk_postmux1 - * \- cpu_clk_premux1 - * \- xtal - */ - - udelay(100); - - return NOTIFY_OK; - - case POST_RATE_CHANGE: - /* - * The cpu_clk_postmux0 has ben updated, now switch back - * cpu_clk_dyn to cpu_clk_postmux0 and take the changes - * in account. - */ - - /* Configure cpu_clk_dyn back to cpu_clk_postmux0 */ - clk_hw_set_parent(nb_data->cpu_clk_dyn, - nb_data->cpu_clk_postmux0); - - /* - * new path : - * cpu_clk - * \- cpu_clk_dyn - * \- cpu_clk_postmux0 - * \- cpu_clk_muxX_div - * \- cpu_clk_premux0 - * \- fclk_div3 or fclk_div2 - * OR - * \- cpu_clk_premux0 - * \- fclk_div3 or fclk_div2 - */ - - udelay(100); - - return NOTIFY_OK; - - default: - return NOTIFY_DONE; - } -} - -static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = =3D { - .cpu_clk_dyn =3D &g12a_cpu_clk_dyn.hw, - .cpu_clk_postmux0 =3D &g12a_cpu_clk_postmux0.hw, - .cpu_clk_postmux1 =3D &g12a_cpu_clk_postmux1.hw, - .cpu_clk_premux1 =3D &g12a_cpu_clk_premux1.hw, - .nb.notifier_call =3D g12a_cpu_clk_postmux_notifier_cb, -}; - -static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = =3D { - .cpu_clk_dyn =3D &g12b_cpub_clk_dyn.hw, - .cpu_clk_postmux0 =3D &g12b_cpub_clk_postmux0.hw, - .cpu_clk_postmux1 =3D &g12b_cpub_clk_postmux1.hw, - .cpu_clk_premux1 =3D &g12b_cpub_clk_premux1.hw, - .nb.notifier_call =3D g12a_cpu_clk_postmux_notifier_cb, -}; - -struct g12a_sys_pll_nb_data { - struct notifier_block nb; - struct clk_hw *sys_pll; - struct clk_hw *cpu_clk; - struct clk_hw *cpu_clk_dyn; -}; - -static int g12a_sys_pll_notifier_cb(struct notifier_block *nb, - unsigned long event, void *data) -{ - struct g12a_sys_pll_nb_data *nb_data =3D - container_of(nb, struct g12a_sys_pll_nb_data, nb); - - switch (event) { - case PRE_RATE_CHANGE: - /* - * This notifier means sys_pll clock will be changed - * to feed cpu_clk, this the current path : - * cpu_clk - * \- sys_pll - * \- sys_pll_dco - */ - - /* Configure cpu_clk to use cpu_clk_dyn */ - clk_hw_set_parent(nb_data->cpu_clk, - nb_data->cpu_clk_dyn); - - /* - * Now, cpu_clk uses the dyn path - * cpu_clk - * \- cpu_clk_dyn - * \- cpu_clk_dynX - * \- cpu_clk_dynX_sel - * \- cpu_clk_dynX_div - * \- xtal/fclk_div2/fclk_div3 - * \- xtal/fclk_div2/fclk_div3 - */ - - udelay(100); - - return NOTIFY_OK; - - case POST_RATE_CHANGE: - /* - * The sys_pll has ben updated, now switch back cpu_clk to - * sys_pll - */ - - /* Configure cpu_clk to use sys_pll */ - clk_hw_set_parent(nb_data->cpu_clk, - nb_data->sys_pll); - - udelay(100); - - /* new path : - * cpu_clk - * \- sys_pll - * \- sys_pll_dco - */ - - return NOTIFY_OK; - - default: - return NOTIFY_DONE; - } -} - -static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data =3D { - .sys_pll =3D &g12a_sys_pll.hw, - .cpu_clk =3D &g12a_cpu_clk.hw, - .cpu_clk_dyn =3D &g12a_cpu_clk_dyn.hw, - .nb.notifier_call =3D g12a_sys_pll_notifier_cb, -}; - -/* G12B first CPU cluster uses sys1_pll */ -static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data =3D { - .sys_pll =3D &g12b_sys1_pll.hw, - .cpu_clk =3D &g12b_cpu_clk.hw, - .cpu_clk_dyn =3D &g12a_cpu_clk_dyn.hw, - .nb.notifier_call =3D g12a_sys_pll_notifier_cb, -}; - -/* G12B second CPU cluster uses sys_pll */ -static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data =3D { - .sys_pll =3D &g12a_sys_pll.hw, - .cpu_clk =3D &g12b_cpub_clk.hw, - .cpu_clk_dyn =3D &g12b_cpub_clk_dyn.hw, - .nb.notifier_call =3D g12a_sys_pll_notifier_cb, -}; - -static struct clk_regmap g12a_cpu_clk_div16_en =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL1, - .bit_idx =3D 1, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "cpu_clk_div16_en", - .ops =3D &clk_regmap_gate_ro_ops, - .parent_data =3D &(const struct clk_parent_data) { - /* - * Note: - * G12A and G12B have different cpu clocks (with - * different struct clk_hw). We fallback to the global - * naming string mechanism so this clock picks - * up the appropriate one. Same goes for the other - * clock using cpu cluster A clock output and present - * on both G12 variant. - */ - .name =3D "cpu_clk", - .index =3D -1, +/* Datasheet names this field as "mux0_divn_tcnt" */ +static struct clk_regmap g12b_cpub_clk_dyn0_div =3D { + .data =3D &(struct meson_clk_cpu_dyndiv_data){ + .div =3D { + .reg_off =3D HHI_SYS_CPUB_CLK_CNTL, + .shift =3D 4, + .width =3D 6, + }, + .dyn =3D { + .reg_off =3D HHI_SYS_CPUB_CLK_CNTL, + .shift =3D 26, + .width =3D 1, }, - .num_parents =3D 1, - /* - * This clock is used to debug the cpu_clk range - * Linux should not change it at runtime - */ - }, -}; - -static struct clk_regmap g12b_cpub_clk_div16_en =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL1, - .bit_idx =3D 1, }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "cpub_clk_div16_en", - .ops =3D &clk_regmap_gate_ro_ops, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cpub_clk_dyn0_div", + .ops =3D &meson_clk_cpu_dyndiv_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk.hw + &g12b_cpub_clk_dyn0_sel.hw }, .num_parents =3D 1, - /* - * This clock is used to debug the cpu_clk range - * Linux should not change it at runtime - */ + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_fixed_factor g12a_cpu_clk_div16 =3D { - .mult =3D 1, - .div =3D 16, +/* Datasheet names this field as "postmux0" */ +static struct clk_regmap g12b_cpub_clk_dyn0 =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL, + .mask =3D 0x1, + .shift =3D 2, + .flags =3D CLK_MUX_ROUND_CLOSEST, + }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk_div16", - .ops =3D &clk_fixed_factor_ops, + .name =3D "cpub_clk_dyn0", + .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk_div16_en.hw + &g12b_cpub_clk_dyn0_sel.hw, + &g12b_cpub_clk_dyn0_div.hw }, - .num_parents =3D 1, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_fixed_factor g12b_cpub_clk_div16 =3D { - .mult =3D 1, - .div =3D 16, +/* Datasheet names this field as "premux1" */ +static struct clk_regmap g12b_cpub_clk_dyn1_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL, + .mask =3D 0x3, + .shift =3D 16, + }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_div16", - .ops =3D &clk_fixed_factor_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_div16_en.hw + .name =3D "cpub_clk_dyn1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .hw =3D &g12a_fclk_div2.hw }, + { .hw =3D &g12a_fclk_div3.hw }, }, - .num_parents =3D 1, + .num_parents =3D 3, + /* This sub-tree is used a parking clock */ + .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; =20 -static struct clk_regmap g12a_cpu_clk_apb_div =3D { +/* Datasheet names this field as "Mux1_divn_tcnt" */ +static struct clk_regmap g12b_cpub_clk_dyn1_div =3D { .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL1, - .shift =3D 3, - .width =3D 3, - .flags =3D CLK_DIVIDER_POWER_OF_TWO, + .offset =3D HHI_SYS_CPUB_CLK_CNTL, + .shift =3D 20, + .width =3D 6, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk_apb_div", + .name =3D "cpub_clk_dyn1_div", .ops =3D &clk_regmap_divider_ro_ops, - .parent_data =3D &(const struct clk_parent_data) { - .name =3D "cpu_clk", - .index =3D -1, - }, - .num_parents =3D 1, - }, -}; - -static struct clk_regmap g12a_cpu_clk_apb =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL1, - .bit_idx =3D 1, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "cpu_clk_apb", - .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk_apb_div.hw + &g12b_cpub_clk_dyn1_sel.hw }, .num_parents =3D 1, - /* - * This clock is set by the ROM monitor code, - * Linux should not change it at runtime - */ }, }; =20 -static struct clk_regmap g12a_cpu_clk_atb_div =3D { - .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL1, - .shift =3D 6, - .width =3D 3, - .flags =3D CLK_DIVIDER_POWER_OF_TWO, +/* Datasheet names this field as "postmux1" */ +static struct clk_regmap g12b_cpub_clk_dyn1 =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL, + .mask =3D 0x1, + .shift =3D 18, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk_atb_div", - .ops =3D &clk_regmap_divider_ro_ops, - .parent_data =3D &(const struct clk_parent_data) { - .name =3D "cpu_clk", - .index =3D -1, + .name =3D "cpub_clk_dyn1", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12b_cpub_clk_dyn1_sel.hw, + &g12b_cpub_clk_dyn1_div.hw }, - .num_parents =3D 1, + .num_parents =3D 2, + /* This sub-tree is used a parking clock */ + .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; =20 -static struct clk_regmap g12a_cpu_clk_atb =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL1, - .bit_idx =3D 17, +/* Datasheet names this field as "Final_dyn_mux_sel" */ +static struct clk_regmap g12b_cpub_clk_dyn =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL, + .mask =3D 0x1, + .shift =3D 10, + .flags =3D CLK_MUX_ROUND_CLOSEST, }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "cpu_clk_atb", - .ops =3D &clk_regmap_gate_ro_ops, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cpub_clk_dyn", + .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk_atb_div.hw + &g12b_cpub_clk_dyn0.hw, + &g12b_cpub_clk_dyn1.hw }, - .num_parents =3D 1, - /* - * This clock is set by the ROM monitor code, - * Linux should not change it at runtime - */ + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap g12a_cpu_clk_axi_div =3D { - .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL1, - .shift =3D 9, - .width =3D 3, - .flags =3D CLK_DIVIDER_POWER_OF_TWO, +/* Datasheet names this field as "Final_mux_sel" */ +static struct clk_regmap g12b_cpub_clk =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL, + .mask =3D 0x1, + .shift =3D 11, + .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk_axi_div", - .ops =3D &clk_regmap_divider_ro_ops, - .parent_data =3D &(const struct clk_parent_data) { - .name =3D "cpu_clk", - .index =3D -1, + .name =3D "cpub_clk", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12b_cpub_clk_dyn.hw, + &g12a_sys_pll.hw }, - .num_parents =3D 1, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap g12a_cpu_clk_axi =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL1, - .bit_idx =3D 18, +/* Datasheet names this field as "premux0" */ +static struct clk_regmap sm1_dsu_clk_dyn0_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL5, + .mask =3D 0x3, + .shift =3D 0, }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "cpu_clk_axi", - .ops =3D &clk_regmap_gate_ro_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk_axi_div.hw + .hw.init =3D &(struct clk_init_data){ + .name =3D "dsu_clk_dyn0_sel", + .ops =3D &clk_regmap_mux_ro_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .hw =3D &g12a_fclk_div2.hw }, + { .hw =3D &g12a_fclk_div3.hw }, + { .hw =3D &sm1_gp1_pll.hw }, }, - .num_parents =3D 1, - /* - * This clock is set by the ROM monitor code, - * Linux should not change it at runtime - */ + .num_parents =3D 4, }, }; =20 -static struct clk_regmap g12a_cpu_clk_trace_div =3D { +/* Datasheet names this field as "Mux0_divn_tcnt" */ +static struct clk_regmap sm1_dsu_clk_dyn0_div =3D { .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL1, - .shift =3D 20, - .width =3D 3, - .flags =3D CLK_DIVIDER_POWER_OF_TWO, + .offset =3D HHI_SYS_CPU_CLK_CNTL5, + .shift =3D 4, + .width =3D 6, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpu_clk_trace_div", + .name =3D "dsu_clk_dyn0_div", .ops =3D &clk_regmap_divider_ro_ops, - .parent_data =3D &(const struct clk_parent_data) { - .name =3D "cpu_clk", - .index =3D -1, + .parent_hws =3D (const struct clk_hw *[]) { + &sm1_dsu_clk_dyn0_sel.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap g12a_cpu_clk_trace =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_SYS_CPU_CLK_CNTL1, - .bit_idx =3D 23, +/* Datasheet names this field as "postmux0" */ +static struct clk_regmap sm1_dsu_clk_dyn0 =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL5, + .mask =3D 0x1, + .shift =3D 2, }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "cpu_clk_trace", - .ops =3D &clk_regmap_gate_ro_ops, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dsu_clk_dyn0", + .ops =3D &clk_regmap_mux_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_cpu_clk_trace_div.hw + &sm1_dsu_clk_dyn0_sel.hw, + &sm1_dsu_clk_dyn0_div.hw, }, - .num_parents =3D 1, - /* - * This clock is set by the ROM monitor code, - * Linux should not change it at runtime - */ + .num_parents =3D 2, }, }; =20 -static struct clk_fixed_factor g12b_cpub_clk_div2 =3D { - .mult =3D 1, - .div =3D 2, +/* Datasheet names this field as "premux1" */ +static struct clk_regmap sm1_dsu_clk_dyn1_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL5, + .mask =3D 0x3, + .shift =3D 16, + }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_div2", - .ops =3D &clk_fixed_factor_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk.hw + .name =3D "dsu_clk_dyn1_sel", + .ops =3D &clk_regmap_mux_ro_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .hw =3D &g12a_fclk_div2.hw }, + { .hw =3D &g12a_fclk_div3.hw }, + { .hw =3D &sm1_gp1_pll.hw }, }, - .num_parents =3D 1, + .num_parents =3D 4, }, }; =20 -static struct clk_fixed_factor g12b_cpub_clk_div3 =3D { - .mult =3D 1, - .div =3D 3, +/* Datasheet names this field as "Mux1_divn_tcnt" */ +static struct clk_regmap sm1_dsu_clk_dyn1_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL5, + .shift =3D 20, + .width =3D 6, + }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_div3", - .ops =3D &clk_fixed_factor_ops, + .name =3D "dsu_clk_dyn1_div", + .ops =3D &clk_regmap_divider_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk.hw + &sm1_dsu_clk_dyn1_sel.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_fixed_factor g12b_cpub_clk_div4 =3D { - .mult =3D 1, - .div =3D 4, +/* Datasheet names this field as "postmux1" */ +static struct clk_regmap sm1_dsu_clk_dyn1 =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL5, + .mask =3D 0x1, + .shift =3D 18, + }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_div4", - .ops =3D &clk_fixed_factor_ops, + .name =3D "dsu_clk_dyn1", + .ops =3D &clk_regmap_mux_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk.hw + &sm1_dsu_clk_dyn1_sel.hw, + &sm1_dsu_clk_dyn1_div.hw, }, - .num_parents =3D 1, + .num_parents =3D 2, }, }; =20 -static struct clk_fixed_factor g12b_cpub_clk_div5 =3D { - .mult =3D 1, - .div =3D 5, +/* Datasheet names this field as "Final_dyn_mux_sel" */ +static struct clk_regmap sm1_dsu_clk_dyn =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL5, + .mask =3D 0x1, + .shift =3D 10, + }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_div5", - .ops =3D &clk_fixed_factor_ops, + .name =3D "dsu_clk_dyn", + .ops =3D &clk_regmap_mux_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk.hw + &sm1_dsu_clk_dyn0.hw, + &sm1_dsu_clk_dyn1.hw, }, - .num_parents =3D 1, + .num_parents =3D 2, }, }; =20 -static struct clk_fixed_factor g12b_cpub_clk_div6 =3D { - .mult =3D 1, - .div =3D 6, +/* Datasheet names this field as "Final_mux_sel" */ +static struct clk_regmap sm1_dsu_final_clk =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL5, + .mask =3D 0x1, + .shift =3D 11, + }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_div6", - .ops =3D &clk_fixed_factor_ops, + .name =3D "dsu_clk_final", + .ops =3D &clk_regmap_mux_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk.hw + &sm1_dsu_clk_dyn.hw, + &g12a_sys_pll.hw, }, - .num_parents =3D 1, + .num_parents =3D 2, }, }; =20 -static struct clk_fixed_factor g12b_cpub_clk_div7 =3D { - .mult =3D 1, - .div =3D 7, - .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_div7", - .ops =3D &clk_fixed_factor_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk.hw - }, - .num_parents =3D 1, +/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */ +static struct clk_regmap sm1_cpu1_clk =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL6, + .mask =3D 0x1, + .shift =3D 24, }, -}; - -static struct clk_fixed_factor g12b_cpub_clk_div8 =3D { - .mult =3D 1, - .div =3D 8, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_div8", - .ops =3D &clk_fixed_factor_ops, + .name =3D "cpu1_clk", + .ops =3D &clk_regmap_mux_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk.hw + &g12a_cpu_clk.hw, + /* This CPU also have a dedicated clock tree */ }, .num_parents =3D 1, }, }; =20 -static u32 mux_table_cpub[] =3D { 1, 2, 3, 4, 5, 6, 7 }; -static struct clk_regmap g12b_cpub_clk_apb_sel =3D { +/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */ +static struct clk_regmap sm1_cpu2_clk =3D { .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL1, - .mask =3D 7, - .shift =3D 3, - .table =3D mux_table_cpub, + .offset =3D HHI_SYS_CPU_CLK_CNTL6, + .mask =3D 0x1, + .shift =3D 25, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_apb_sel", + .name =3D "cpu2_clk", .ops =3D &clk_regmap_mux_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_div2.hw, - &g12b_cpub_clk_div3.hw, - &g12b_cpub_clk_div4.hw, - &g12b_cpub_clk_div5.hw, - &g12b_cpub_clk_div6.hw, - &g12b_cpub_clk_div7.hw, - &g12b_cpub_clk_div8.hw - }, - .num_parents =3D 7, - }, -}; - -static struct clk_regmap g12b_cpub_clk_apb =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL1, - .bit_idx =3D 16, - .flags =3D CLK_GATE_SET_TO_DISABLE, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "cpub_clk_apb", - .ops =3D &clk_regmap_gate_ro_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_apb_sel.hw + &g12a_cpu_clk.hw, + /* This CPU also have a dedicated clock tree */ }, .num_parents =3D 1, - /* - * This clock is set by the ROM monitor code, - * Linux should not change it at runtime - */ }, }; =20 -static struct clk_regmap g12b_cpub_clk_atb_sel =3D { +/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */ +static struct clk_regmap sm1_cpu3_clk =3D { .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL1, - .mask =3D 7, - .shift =3D 6, - .table =3D mux_table_cpub, + .offset =3D HHI_SYS_CPU_CLK_CNTL6, + .mask =3D 0x1, + .shift =3D 26, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_atb_sel", + .name =3D "cpu3_clk", .ops =3D &clk_regmap_mux_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_div2.hw, - &g12b_cpub_clk_div3.hw, - &g12b_cpub_clk_div4.hw, - &g12b_cpub_clk_div5.hw, - &g12b_cpub_clk_div6.hw, - &g12b_cpub_clk_div7.hw, - &g12b_cpub_clk_div8.hw - }, - .num_parents =3D 7, - }, -}; - -static struct clk_regmap g12b_cpub_clk_atb =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL1, - .bit_idx =3D 17, - .flags =3D CLK_GATE_SET_TO_DISABLE, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "cpub_clk_atb", - .ops =3D &clk_regmap_gate_ro_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_atb_sel.hw + &g12a_cpu_clk.hw, + /* This CPU also have a dedicated clock tree */ }, .num_parents =3D 1, - /* - * This clock is set by the ROM monitor code, - * Linux should not change it at runtime - */ }, }; =20 -static struct clk_regmap g12b_cpub_clk_axi_sel =3D { +/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */ +static struct clk_regmap sm1_dsu_clk =3D { .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL1, - .mask =3D 7, - .shift =3D 9, - .table =3D mux_table_cpub, + .offset =3D HHI_SYS_CPU_CLK_CNTL6, + .mask =3D 0x1, + .shift =3D 27, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_axi_sel", + .name =3D "dsu_clk", .ops =3D &clk_regmap_mux_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_div2.hw, - &g12b_cpub_clk_div3.hw, - &g12b_cpub_clk_div4.hw, - &g12b_cpub_clk_div5.hw, - &g12b_cpub_clk_div6.hw, - &g12b_cpub_clk_div7.hw, - &g12b_cpub_clk_div8.hw + &g12a_cpu_clk.hw, + &sm1_dsu_final_clk.hw, }, - .num_parents =3D 7, + .num_parents =3D 2, }, }; =20 -static struct clk_regmap g12b_cpub_clk_axi =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL1, - .bit_idx =3D 18, - .flags =3D CLK_GATE_SET_TO_DISABLE, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "cpub_clk_axi", - .ops =3D &clk_regmap_gate_ro_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_axi_sel.hw - }, - .num_parents =3D 1, - /* - * This clock is set by the ROM monitor code, - * Linux should not change it at runtime - */ - }, +static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + if (event =3D=3D POST_RATE_CHANGE || event =3D=3D PRE_RATE_CHANGE) { + /* Wait for clock propagation before/after changing the mux */ + udelay(100); + return NOTIFY_OK; + } + + return NOTIFY_DONE; +} + +static struct notifier_block g12a_cpu_clk_mux_nb =3D { + .notifier_call =3D g12a_cpu_clk_mux_notifier_cb, }; =20 -static struct clk_regmap g12b_cpub_clk_trace_sel =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL1, - .mask =3D 7, - .shift =3D 20, - .table =3D mux_table_cpub, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "cpub_clk_trace_sel", - .ops =3D &clk_regmap_mux_ro_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_div2.hw, - &g12b_cpub_clk_div3.hw, - &g12b_cpub_clk_div4.hw, - &g12b_cpub_clk_div5.hw, - &g12b_cpub_clk_div6.hw, - &g12b_cpub_clk_div7.hw, - &g12b_cpub_clk_div8.hw - }, - .num_parents =3D 7, - }, +struct g12a_cpu_clk_dyn_nb_data { + struct notifier_block nb; + struct clk_hw *xtal; + struct clk_hw *cpu_clk_dyn; + struct clk_hw *cpu_clk_postmux0; + struct clk_hw *cpu_clk_postmux1; + struct clk_hw *cpu_clk_premux1; }; =20 -static struct clk_regmap g12b_cpub_clk_trace =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_SYS_CPUB_CLK_CNTL1, - .bit_idx =3D 23, - .flags =3D CLK_GATE_SET_TO_DISABLE, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "cpub_clk_trace", - .ops =3D &clk_regmap_gate_ro_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12b_cpub_clk_trace_sel.hw - }, - .num_parents =3D 1, +static int g12a_cpu_clk_dyn_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct g12a_cpu_clk_dyn_nb_data *nb_data =3D + container_of(nb, struct g12a_cpu_clk_dyn_nb_data, nb); + + switch (event) { + case PRE_RATE_CHANGE: /* - * This clock is set by the ROM monitor code, - * Linux should not change it at runtime + * This notifier means cpu_clk_dyn0 clock will be changed + * to feed cpu_clk, this is the current path : + * cpu_clk + * \- cpu_clk_dyn + * \- cpu_clk_dyn0 + * \- cpu_clk_dyn0_div + * \- cpu_clk_dyn0_sel + * \- fclk_div3 or fclk_div2 + * OR + * \- cpu_clk_dyn0_sel + * \- fclk_div3 or fclk_div2 */ - }, -}; =20 -static const struct pll_mult_range g12a_gp0_pll_mult_range =3D { - .min =3D 125, - .max =3D 255, -}; + /* Setup cpu_clk_dyn1_sel to xtal */ + clk_hw_set_parent(nb_data->cpu_clk_premux1, + nb_data->xtal); =20 -/* - * Internal gp0 pll emulation configuration parameters - */ -static const struct reg_sequence g12a_gp0_init_regs[] =3D { - { .reg =3D HHI_GP0_PLL_CNTL1, .def =3D 0x00000000 }, - { .reg =3D HHI_GP0_PLL_CNTL2, .def =3D 0x00000000 }, - { .reg =3D HHI_GP0_PLL_CNTL3, .def =3D 0x48681c00 }, - { .reg =3D HHI_GP0_PLL_CNTL4, .def =3D 0x33771290 }, - { .reg =3D HHI_GP0_PLL_CNTL5, .def =3D 0x39272000 }, - { .reg =3D HHI_GP0_PLL_CNTL6, .def =3D 0x56540000 }, + /* Setup cpu_clk_dyn1 to bypass divider */ + clk_hw_set_parent(nb_data->cpu_clk_postmux1, + nb_data->cpu_clk_premux1); + + /* Switch to parking clk on cpu_clk_postmux1 */ + clk_hw_set_parent(nb_data->cpu_clk_dyn, + nb_data->cpu_clk_postmux1); + + /* + * Now, cpu_clk is 24MHz in the current path : + * cpu_clk + * \- cpu_clk_dyn + * \- cpu_clk_dyn1 + * \- cpu_clk_dyn1_sel + * \- xtal + */ + + udelay(100); + + return NOTIFY_OK; + + case POST_RATE_CHANGE: + /* + * The cpu_clk_dyn0 has ben updated, now switch back + * cpu_clk_dyn to cpu_clk_dyn0 and take the changes + * in account. + */ + + /* Configure cpu_clk_dyn back to cpu_clk_postmux0 */ + clk_hw_set_parent(nb_data->cpu_clk_dyn, + nb_data->cpu_clk_postmux0); + + /* + * new path : + * cpu_clk + * \- cpu_clk_dyn + * \- cpu_clk_dyn0 + * \- cpu_clk_dyn0_div + * \- cpu_clk_dyn0_sel + * \- fclk_div3 or fclk_div2 + * OR + * \- cpu_clk_dyn0_sel + * \- fclk_div3 or fclk_div2 + */ + + udelay(100); + + return NOTIFY_OK; + + default: + return NOTIFY_DONE; + } +} + +static struct g12a_cpu_clk_dyn_nb_data g12a_cpu_clk_dyn0_nb_data =3D { + .cpu_clk_dyn =3D &g12a_cpu_clk_dyn.hw, + .cpu_clk_postmux0 =3D &g12a_cpu_clk_dyn0.hw, + .cpu_clk_postmux1 =3D &g12a_cpu_clk_dyn1.hw, + .cpu_clk_premux1 =3D &g12a_cpu_clk_dyn1_sel.hw, + .nb.notifier_call =3D g12a_cpu_clk_dyn_notifier_cb, }; =20 -static struct clk_regmap g12a_gp0_pll_dco =3D { - .data =3D &(struct meson_clk_pll_data){ - .en =3D { - .reg_off =3D HHI_GP0_PLL_CNTL0, - .shift =3D 28, - .width =3D 1, - }, - .m =3D { - .reg_off =3D HHI_GP0_PLL_CNTL0, - .shift =3D 0, - .width =3D 8, - }, - .n =3D { - .reg_off =3D HHI_GP0_PLL_CNTL0, - .shift =3D 10, - .width =3D 5, - }, - .frac =3D { - .reg_off =3D HHI_GP0_PLL_CNTL1, - .shift =3D 0, - .width =3D 17, - }, - .l =3D { - .reg_off =3D HHI_GP0_PLL_CNTL0, - .shift =3D 31, - .width =3D 1, - }, - .rst =3D { - .reg_off =3D HHI_GP0_PLL_CNTL0, - .shift =3D 29, - .width =3D 1, - }, - .range =3D &g12a_gp0_pll_mult_range, - .init_regs =3D g12a_gp0_init_regs, - .init_count =3D ARRAY_SIZE(g12a_gp0_init_regs), - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "gp0_pll_dco", - .ops =3D &meson_clk_pll_ops, - .parent_data =3D &(const struct clk_parent_data) { - .fw_name =3D "xtal", - }, - .num_parents =3D 1, - }, +static struct g12a_cpu_clk_dyn_nb_data g12b_cpub_clk_dyn0_nb_data =3D { + .cpu_clk_dyn =3D &g12b_cpub_clk_dyn.hw, + .cpu_clk_postmux0 =3D &g12b_cpub_clk_dyn0.hw, + .cpu_clk_postmux1 =3D &g12b_cpub_clk_dyn1.hw, + .cpu_clk_premux1 =3D &g12b_cpub_clk_dyn1_sel.hw, + .nb.notifier_call =3D g12a_cpu_clk_dyn_notifier_cb, }; =20 -static struct clk_regmap g12a_gp0_pll =3D { - .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_GP0_PLL_CNTL0, - .shift =3D 16, - .width =3D 3, - .flags =3D (CLK_DIVIDER_POWER_OF_TWO | - CLK_DIVIDER_ROUND_CLOSEST), - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "gp0_pll", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12a_gp0_pll_dco.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, +struct g12a_sys_pll_nb_data { + struct notifier_block nb; + struct clk_hw *sys_pll; + struct clk_hw *cpu_clk; + struct clk_hw *cpu_clk_dyn; }; =20 -static struct clk_regmap sm1_gp1_pll_dco =3D { - .data =3D &(struct meson_clk_pll_data){ - .en =3D { - .reg_off =3D HHI_GP1_PLL_CNTL0, - .shift =3D 28, - .width =3D 1, - }, - .m =3D { - .reg_off =3D HHI_GP1_PLL_CNTL0, - .shift =3D 0, - .width =3D 8, - }, - .n =3D { - .reg_off =3D HHI_GP1_PLL_CNTL0, - .shift =3D 10, - .width =3D 5, - }, - .frac =3D { - .reg_off =3D HHI_GP1_PLL_CNTL1, - .shift =3D 0, - .width =3D 17, - }, - .l =3D { - .reg_off =3D HHI_GP1_PLL_CNTL0, - .shift =3D 31, - .width =3D 1, - }, - .rst =3D { - .reg_off =3D HHI_GP1_PLL_CNTL0, - .shift =3D 29, - .width =3D 1, - }, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "gp1_pll_dco", - .ops =3D &meson_clk_pll_ro_ops, - .parent_data =3D &(const struct clk_parent_data) { - .fw_name =3D "xtal", - }, - .num_parents =3D 1, - /* This clock feeds the DSU, avoid disabling it */ - .flags =3D CLK_IS_CRITICAL, - }, +static int g12a_sys_pll_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct g12a_sys_pll_nb_data *nb_data =3D + container_of(nb, struct g12a_sys_pll_nb_data, nb); + + switch (event) { + case PRE_RATE_CHANGE: + /* + * This notifier means sys_pll clock will be changed + * to feed cpu_clk, this the current path : + * cpu_clk + * \- sys_pll + * \- sys_pll_dco + */ + + /* Configure cpu_clk to use cpu_clk_dyn */ + clk_hw_set_parent(nb_data->cpu_clk, + nb_data->cpu_clk_dyn); + + /* + * Now, cpu_clk uses the dyn path + * cpu_clk + * \- cpu_clk_dyn + * \- cpu_clk_dynX + * \- cpu_clk_dynX_sel + * \- cpu_clk_dynX_div + * \- xtal/fclk_div2/fclk_div3 + * \- xtal/fclk_div2/fclk_div3 + */ + + udelay(100); + + return NOTIFY_OK; + + case POST_RATE_CHANGE: + /* + * The sys_pll has ben updated, now switch back cpu_clk to + * sys_pll + */ + + /* Configure cpu_clk to use sys_pll */ + clk_hw_set_parent(nb_data->cpu_clk, + nb_data->sys_pll); + + udelay(100); + + /* new path : + * cpu_clk + * \- sys_pll + * \- sys_pll_dco + */ + + return NOTIFY_OK; + + default: + return NOTIFY_DONE; + } +} + +static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data =3D { + .sys_pll =3D &g12a_sys_pll.hw, + .cpu_clk =3D &g12a_cpu_clk.hw, + .cpu_clk_dyn =3D &g12a_cpu_clk_dyn.hw, + .nb.notifier_call =3D g12a_sys_pll_notifier_cb, }; =20 -static struct clk_regmap sm1_gp1_pll =3D { - .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_GP1_PLL_CNTL0, - .shift =3D 16, - .width =3D 3, - .flags =3D (CLK_DIVIDER_POWER_OF_TWO | - CLK_DIVIDER_ROUND_CLOSEST), - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "gp1_pll", - .ops =3D &clk_regmap_divider_ro_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &sm1_gp1_pll_dco.hw - }, - .num_parents =3D 1, - }, +/* G12B first CPU cluster uses sys1_pll */ +static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data =3D { + .sys_pll =3D &g12b_sys1_pll.hw, + .cpu_clk =3D &g12b_cpu_clk.hw, + .cpu_clk_dyn =3D &g12a_cpu_clk_dyn.hw, + .nb.notifier_call =3D g12a_sys_pll_notifier_cb, }; =20 -/* - * Internal hifi pll emulation configuration parameters - */ -static const struct reg_sequence g12a_hifi_init_regs[] =3D { - { .reg =3D HHI_HIFI_PLL_CNTL1, .def =3D 0x00000000 }, - { .reg =3D HHI_HIFI_PLL_CNTL2, .def =3D 0x00000000 }, - { .reg =3D HHI_HIFI_PLL_CNTL3, .def =3D 0x6a285c00 }, - { .reg =3D HHI_HIFI_PLL_CNTL4, .def =3D 0x65771290 }, - { .reg =3D HHI_HIFI_PLL_CNTL5, .def =3D 0x39272000 }, - { .reg =3D HHI_HIFI_PLL_CNTL6, .def =3D 0x56540000 }, +/* G12B second CPU cluster uses sys_pll */ +static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data =3D { + .sys_pll =3D &g12a_sys_pll.hw, + .cpu_clk =3D &g12b_cpub_clk.hw, + .cpu_clk_dyn =3D &g12b_cpub_clk_dyn.hw, + .nb.notifier_call =3D g12a_sys_pll_notifier_cb, }; =20 -static struct clk_regmap g12a_hifi_pll_dco =3D { - .data =3D &(struct meson_clk_pll_data){ - .en =3D { - .reg_off =3D HHI_HIFI_PLL_CNTL0, - .shift =3D 28, - .width =3D 1, - }, - .m =3D { - .reg_off =3D HHI_HIFI_PLL_CNTL0, - .shift =3D 0, - .width =3D 8, - }, - .n =3D { - .reg_off =3D HHI_HIFI_PLL_CNTL0, - .shift =3D 10, - .width =3D 5, - }, - .frac =3D { - .reg_off =3D HHI_HIFI_PLL_CNTL1, - .shift =3D 0, - .width =3D 17, - }, - .l =3D { - .reg_off =3D HHI_HIFI_PLL_CNTL0, - .shift =3D 31, - .width =3D 1, - }, - .rst =3D { - .reg_off =3D HHI_HIFI_PLL_CNTL0, - .shift =3D 29, - .width =3D 1, - }, - .range =3D &g12a_gp0_pll_mult_range, - .init_regs =3D g12a_hifi_init_regs, - .init_count =3D ARRAY_SIZE(g12a_hifi_init_regs), - .flags =3D CLK_MESON_PLL_ROUND_CLOSEST, +static struct clk_regmap g12a_cpu_clk_div16_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL1, + .bit_idx =3D 1, }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "hifi_pll_dco", - .ops =3D &meson_clk_pll_ops, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cpu_clk_div16_en", + .ops =3D &clk_regmap_gate_ro_ops, .parent_data =3D &(const struct clk_parent_data) { - .fw_name =3D "xtal", + /* + * Note: + * G12A and G12B have different cpu clocks (with + * different struct clk_hw). We fallback to the global + * naming string mechanism so this clock picks + * up the appropriate one. Same goes for the other + * clock using cpu cluster A clock output and present + * on both G12 variant. + */ + .name =3D "cpu_clk", + .index =3D -1, }, .num_parents =3D 1, + /* + * This clock is used to debug the cpu_clk range + * Linux should not change it at runtime + */ }, }; =20 -static struct clk_regmap g12a_hifi_pll =3D { - .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_HIFI_PLL_CNTL0, - .shift =3D 16, - .width =3D 2, - .flags =3D (CLK_DIVIDER_POWER_OF_TWO | - CLK_DIVIDER_ROUND_CLOSEST), +static struct clk_regmap g12b_cpub_clk_div16_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL1, + .bit_idx =3D 1, }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "hifi_pll", - .ops =3D &clk_regmap_divider_ops, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cpub_clk_div16_en", + .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_hifi_pll_dco.hw + &g12b_cpub_clk.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, + /* + * This clock is used to debug the cpu_clk range + * Linux should not change it at runtime + */ }, }; =20 -/* - * The Meson G12A PCIE PLL is fined tuned to deliver a very precise - * 100MHz reference clock for the PCIe Analog PHY, and thus requires - * a strict register sequence to enable the PLL. - */ -static const struct reg_sequence g12a_pcie_pll_init_regs[] =3D { - { .reg =3D HHI_PCIE_PLL_CNTL0, .def =3D 0x20090496 }, - { .reg =3D HHI_PCIE_PLL_CNTL0, .def =3D 0x30090496 }, - { .reg =3D HHI_PCIE_PLL_CNTL1, .def =3D 0x00000000 }, - { .reg =3D HHI_PCIE_PLL_CNTL2, .def =3D 0x00001100 }, - { .reg =3D HHI_PCIE_PLL_CNTL3, .def =3D 0x10058e00 }, - { .reg =3D HHI_PCIE_PLL_CNTL4, .def =3D 0x000100c0 }, - { .reg =3D HHI_PCIE_PLL_CNTL5, .def =3D 0x68000048 }, - { .reg =3D HHI_PCIE_PLL_CNTL5, .def =3D 0x68000068, .delay_us =3D 20 }, - { .reg =3D HHI_PCIE_PLL_CNTL4, .def =3D 0x008100c0, .delay_us =3D 10 }, - { .reg =3D HHI_PCIE_PLL_CNTL0, .def =3D 0x34090496 }, - { .reg =3D HHI_PCIE_PLL_CNTL0, .def =3D 0x14090496, .delay_us =3D 10 }, - { .reg =3D HHI_PCIE_PLL_CNTL2, .def =3D 0x00001000 }, +static struct clk_fixed_factor g12a_cpu_clk_div16 =3D { + .mult =3D 1, + .div =3D 16, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cpu_clk_div16", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12a_cpu_clk_div16_en.hw + }, + .num_parents =3D 1, + }, }; =20 -/* Keep a single entry table for recalc/round_rate() ops */ -static const struct pll_params_table g12a_pcie_pll_table[] =3D { - PLL_PARAMS(150, 1), - {0, 0}, +static struct clk_fixed_factor g12b_cpub_clk_div16 =3D { + .mult =3D 1, + .div =3D 16, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cpub_clk_div16", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12b_cpub_clk_div16_en.hw + }, + .num_parents =3D 1, + }, }; =20 -static struct clk_regmap g12a_pcie_pll_dco =3D { - .data =3D &(struct meson_clk_pll_data){ - .en =3D { - .reg_off =3D HHI_PCIE_PLL_CNTL0, - .shift =3D 28, - .width =3D 1, - }, - .m =3D { - .reg_off =3D HHI_PCIE_PLL_CNTL0, - .shift =3D 0, - .width =3D 8, - }, - .n =3D { - .reg_off =3D HHI_PCIE_PLL_CNTL0, - .shift =3D 10, - .width =3D 5, - }, - .frac =3D { - .reg_off =3D HHI_PCIE_PLL_CNTL1, - .shift =3D 0, - .width =3D 12, - }, - .l =3D { - .reg_off =3D HHI_PCIE_PLL_CNTL0, - .shift =3D 31, - .width =3D 1, - }, - .rst =3D { - .reg_off =3D HHI_PCIE_PLL_CNTL0, - .shift =3D 29, - .width =3D 1, - }, - .table =3D g12a_pcie_pll_table, - .init_regs =3D g12a_pcie_pll_init_regs, - .init_count =3D ARRAY_SIZE(g12a_pcie_pll_init_regs), +static struct clk_regmap g12a_cpu_clk_apb_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL1, + .shift =3D 3, + .width =3D 3, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pcie_pll_dco", - .ops =3D &meson_clk_pcie_pll_ops, + .name =3D "cpu_clk_apb_div", + .ops =3D &clk_regmap_divider_ro_ops, .parent_data =3D &(const struct clk_parent_data) { - .fw_name =3D "xtal", + .name =3D "cpu_clk", + .index =3D -1, }, .num_parents =3D 1, }, }; =20 -static struct clk_fixed_factor g12a_pcie_pll_dco_div2 =3D { - .mult =3D 1, - .div =3D 2, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pcie_pll_dco_div2", - .ops =3D &clk_fixed_factor_ops, +static struct clk_regmap g12a_cpu_clk_apb =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL1, + .bit_idx =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cpu_clk_apb", + .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_pcie_pll_dco.hw + &g12a_cpu_clk_apb_div.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, + /* + * This clock is set by the ROM monitor code, + * Linux should not change it at runtime + */ }, }; =20 -static struct clk_regmap g12a_pcie_pll_od =3D { +static struct clk_regmap g12a_cpu_clk_atb_div =3D { .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_PCIE_PLL_CNTL0, - .shift =3D 16, - .width =3D 5, - .flags =3D CLK_DIVIDER_ROUND_CLOSEST | - CLK_DIVIDER_ONE_BASED | - CLK_DIVIDER_ALLOW_ZERO, + .offset =3D HHI_SYS_CPU_CLK_CNTL1, + .shift =3D 6, + .width =3D 3, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pcie_pll_od", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12a_pcie_pll_dco_div2.hw + .name =3D "cpu_clk_atb_div", + .ops =3D &clk_regmap_divider_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .name =3D "cpu_clk", + .index =3D -1, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_fixed_factor g12a_pcie_pll =3D { - .mult =3D 1, - .div =3D 2, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pcie_pll_pll", - .ops =3D &clk_fixed_factor_ops, +static struct clk_regmap g12a_cpu_clk_atb =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL1, + .bit_idx =3D 17, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cpu_clk_atb", + .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_pcie_pll_od.hw + &g12a_cpu_clk_atb_div.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, + /* + * This clock is set by the ROM monitor code, + * Linux should not change it at runtime + */ }, }; =20 -static struct clk_regmap g12a_hdmi_pll_dco =3D { - .data =3D &(struct meson_clk_pll_data){ - .en =3D { - .reg_off =3D HHI_HDMI_PLL_CNTL0, - .shift =3D 28, - .width =3D 1, - }, - .m =3D { - .reg_off =3D HHI_HDMI_PLL_CNTL0, - .shift =3D 0, - .width =3D 8, - }, - .n =3D { - .reg_off =3D HHI_HDMI_PLL_CNTL0, - .shift =3D 10, - .width =3D 5, - }, - .frac =3D { - .reg_off =3D HHI_HDMI_PLL_CNTL1, - .shift =3D 0, - .width =3D 16, - }, - .l =3D { - .reg_off =3D HHI_HDMI_PLL_CNTL0, - .shift =3D 30, - .width =3D 1, - }, - .rst =3D { - .reg_off =3D HHI_HDMI_PLL_CNTL0, - .shift =3D 29, - .width =3D 1, - }, +static struct clk_regmap g12a_cpu_clk_axi_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL1, + .shift =3D 9, + .width =3D 3, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "hdmi_pll_dco", - .ops =3D &meson_clk_pll_ro_ops, + .name =3D "cpu_clk_axi_div", + .ops =3D &clk_regmap_divider_ro_ops, .parent_data =3D &(const struct clk_parent_data) { - .fw_name =3D "xtal", + .name =3D "cpu_clk", + .index =3D -1, + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap g12a_cpu_clk_axi =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL1, + .bit_idx =3D 18, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cpu_clk_axi", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12a_cpu_clk_axi_div.hw }, .num_parents =3D 1, /* - * Display directly handle hdmi pll registers ATM, we need - * NOCACHE to keep our view of the clock as accurate as possible + * This clock is set by the ROM monitor code, + * Linux should not change it at runtime */ - .flags =3D CLK_GET_RATE_NOCACHE, }, }; =20 -static struct clk_regmap g12a_hdmi_pll_od =3D { - .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_HDMI_PLL_CNTL0, - .shift =3D 16, - .width =3D 2, +static struct clk_regmap g12a_cpu_clk_trace_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL1, + .shift =3D 20, + .width =3D 3, .flags =3D CLK_DIVIDER_POWER_OF_TWO, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "hdmi_pll_od", + .name =3D "cpu_clk_trace_div", .ops =3D &clk_regmap_divider_ro_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &g12a_hdmi_pll_dco.hw + .parent_data =3D &(const struct clk_parent_data) { + .name =3D "cpu_clk", + .index =3D -1, }, .num_parents =3D 1, - .flags =3D CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap g12a_hdmi_pll_od2 =3D { - .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_HDMI_PLL_CNTL0, - .shift =3D 18, - .width =3D 2, - .flags =3D CLK_DIVIDER_POWER_OF_TWO, +static struct clk_regmap g12a_cpu_clk_trace =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_SYS_CPU_CLK_CNTL1, + .bit_idx =3D 23, }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "hdmi_pll_od2", - .ops =3D &clk_regmap_divider_ro_ops, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cpu_clk_trace", + .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_hdmi_pll_od.hw + &g12a_cpu_clk_trace_div.hw }, .num_parents =3D 1, - .flags =3D CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, + /* + * This clock is set by the ROM monitor code, + * Linux should not change it at runtime + */ }, }; =20 -static struct clk_regmap g12a_hdmi_pll =3D { - .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_HDMI_PLL_CNTL0, - .shift =3D 20, - .width =3D 2, - .flags =3D CLK_DIVIDER_POWER_OF_TWO, - }, +static struct clk_fixed_factor g12b_cpub_clk_div2 =3D { + .mult =3D 1, + .div =3D 2, .hw.init =3D &(struct clk_init_data){ - .name =3D "hdmi_pll", - .ops =3D &clk_regmap_divider_ro_ops, + .name =3D "cpub_clk_div2", + .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_hdmi_pll_od2.hw + &g12b_cpub_clk.hw }, .num_parents =3D 1, - .flags =3D CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_fixed_factor g12a_fclk_div4_div =3D { +static struct clk_fixed_factor g12b_cpub_clk_div3 =3D { .mult =3D 1, - .div =3D 4, + .div =3D 3, .hw.init =3D &(struct clk_init_data){ - .name =3D "fclk_div4_div", + .name =3D "cpub_clk_div3", .ops =3D &clk_fixed_factor_ops, - .parent_hws =3D (const struct clk_hw *[]) { &g12a_fixed_pll.hw }, + .parent_hws =3D (const struct clk_hw *[]) { + &g12b_cpub_clk.hw + }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap g12a_fclk_div4 =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_FIX_PLL_CNTL1, - .bit_idx =3D 21, - }, +static struct clk_fixed_factor g12b_cpub_clk_div4 =3D { + .mult =3D 1, + .div =3D 4, .hw.init =3D &(struct clk_init_data){ - .name =3D "fclk_div4", - .ops =3D &clk_regmap_gate_ops, + .name =3D "cpub_clk_div4", + .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_fclk_div4_div.hw + &g12b_cpub_clk.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_fixed_factor g12a_fclk_div5_div =3D { +static struct clk_fixed_factor g12b_cpub_clk_div5 =3D { .mult =3D 1, .div =3D 5, .hw.init =3D &(struct clk_init_data){ - .name =3D "fclk_div5_div", + .name =3D "cpub_clk_div5", .ops =3D &clk_fixed_factor_ops, - .parent_hws =3D (const struct clk_hw *[]) { &g12a_fixed_pll.hw }, + .parent_hws =3D (const struct clk_hw *[]) { + &g12b_cpub_clk.hw + }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap g12a_fclk_div5 =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_FIX_PLL_CNTL1, - .bit_idx =3D 22, - }, +static struct clk_fixed_factor g12b_cpub_clk_div6 =3D { + .mult =3D 1, + .div =3D 6, .hw.init =3D &(struct clk_init_data){ - .name =3D "fclk_div5", - .ops =3D &clk_regmap_gate_ops, + .name =3D "cpub_clk_div6", + .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_fclk_div5_div.hw + &g12b_cpub_clk.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_fixed_factor g12a_fclk_div7_div =3D { +static struct clk_fixed_factor g12b_cpub_clk_div7 =3D { .mult =3D 1, .div =3D 7, .hw.init =3D &(struct clk_init_data){ - .name =3D "fclk_div7_div", + .name =3D "cpub_clk_div7", .ops =3D &clk_fixed_factor_ops, - .parent_hws =3D (const struct clk_hw *[]) { &g12a_fixed_pll.hw }, + .parent_hws =3D (const struct clk_hw *[]) { + &g12b_cpub_clk.hw + }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap g12a_fclk_div7 =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_FIX_PLL_CNTL1, - .bit_idx =3D 23, - }, +static struct clk_fixed_factor g12b_cpub_clk_div8 =3D { + .mult =3D 1, + .div =3D 8, .hw.init =3D &(struct clk_init_data){ - .name =3D "fclk_div7", - .ops =3D &clk_regmap_gate_ops, + .name =3D "cpub_clk_div8", + .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_fclk_div7_div.hw + &g12b_cpub_clk.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_fixed_factor g12a_fclk_div2p5_div =3D { - .mult =3D 1, - .div =3D 5, +static u32 g12b_cpub_clk_if_parents_val_table[] =3D { 1, 2, 3, 4, 5, 6, 7 = }; +static const struct clk_hw *g12b_cpub_clk_if_parents[] =3D { + &g12b_cpub_clk_div2.hw, + &g12b_cpub_clk_div3.hw, + &g12b_cpub_clk_div4.hw, + &g12b_cpub_clk_div5.hw, + &g12b_cpub_clk_div6.hw, + &g12b_cpub_clk_div7.hw, + &g12b_cpub_clk_div8.hw, +}; + +static struct clk_regmap g12b_cpub_clk_apb_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL1, + .mask =3D 7, + .shift =3D 3, + .table =3D g12b_cpub_clk_if_parents_val_table, + }, .hw.init =3D &(struct clk_init_data){ - .name =3D "fclk_div2p5_div", - .ops =3D &clk_fixed_factor_ops, + .name =3D "cpub_clk_apb_sel", + .ops =3D &clk_regmap_mux_ro_ops, + .parent_hws =3D g12b_cpub_clk_if_parents, + .num_parents =3D ARRAY_SIZE(g12b_cpub_clk_if_parents), + }, +}; + +static struct clk_regmap g12b_cpub_clk_apb =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL1, + .bit_idx =3D 16, + .flags =3D CLK_GATE_SET_TO_DISABLE, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cpub_clk_apb", + .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_fixed_pll_dco.hw + &g12b_cpub_clk_apb_sel.hw }, .num_parents =3D 1, + /* + * This clock is set by the ROM monitor code, + * Linux should not change it at runtime + */ }, }; =20 -static struct clk_regmap g12a_fclk_div2p5 =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_FIX_PLL_CNTL1, - .bit_idx =3D 25, +static struct clk_regmap g12b_cpub_clk_atb_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL1, + .mask =3D 7, + .shift =3D 6, + .table =3D g12b_cpub_clk_if_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "fclk_div2p5", - .ops =3D &clk_regmap_gate_ops, + .name =3D "cpub_clk_atb_sel", + .ops =3D &clk_regmap_mux_ro_ops, + .parent_hws =3D g12b_cpub_clk_if_parents, + .num_parents =3D ARRAY_SIZE(g12b_cpub_clk_if_parents), + }, +}; + +static struct clk_regmap g12b_cpub_clk_atb =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL1, + .bit_idx =3D 17, + .flags =3D CLK_GATE_SET_TO_DISABLE, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cpub_clk_atb", + .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_fclk_div2p5_div.hw + &g12b_cpub_clk_atb_sel.hw }, .num_parents =3D 1, + /* + * This clock is set by the ROM monitor code, + * Linux should not change it at runtime + */ }, }; =20 -static struct clk_fixed_factor g12a_mpll_50m_div =3D { - .mult =3D 1, - .div =3D 80, +static struct clk_regmap g12b_cpub_clk_axi_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL1, + .mask =3D 7, + .shift =3D 9, + .table =3D g12b_cpub_clk_if_parents_val_table, + }, .hw.init =3D &(struct clk_init_data){ - .name =3D "mpll_50m_div", - .ops =3D &clk_fixed_factor_ops, + .name =3D "cpub_clk_axi_sel", + .ops =3D &clk_regmap_mux_ro_ops, + .parent_hws =3D g12b_cpub_clk_if_parents, + .num_parents =3D ARRAY_SIZE(g12b_cpub_clk_if_parents), + }, +}; + +static struct clk_regmap g12b_cpub_clk_axi =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL1, + .bit_idx =3D 18, + .flags =3D CLK_GATE_SET_TO_DISABLE, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cpub_clk_axi", + .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_fixed_pll_dco.hw + &g12b_cpub_clk_axi_sel.hw }, .num_parents =3D 1, + /* + * This clock is set by the ROM monitor code, + * Linux should not change it at runtime + */ }, }; =20 -static struct clk_regmap g12a_mpll_50m =3D { +static struct clk_regmap g12b_cpub_clk_trace_sel =3D { .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_FIX_PLL_CNTL3, - .mask =3D 0x1, - .shift =3D 5, + .offset =3D HHI_SYS_CPUB_CLK_CNTL1, + .mask =3D 7, + .shift =3D 20, + .table =3D g12b_cpub_clk_if_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "mpll_50m", + .name =3D "cpub_clk_trace_sel", .ops =3D &clk_regmap_mux_ro_ops, - .parent_data =3D (const struct clk_parent_data []) { - { .fw_name =3D "xtal", }, - { .hw =3D &g12a_mpll_50m_div.hw }, - }, - .num_parents =3D 2, + .parent_hws =3D g12b_cpub_clk_if_parents, + .num_parents =3D ARRAY_SIZE(g12b_cpub_clk_if_parents), }, }; =20 -static struct clk_fixed_factor g12a_mpll_prediv =3D { - .mult =3D 1, - .div =3D 2, - .hw.init =3D &(struct clk_init_data){ - .name =3D "mpll_prediv", - .ops =3D &clk_fixed_factor_ops, +static struct clk_regmap g12b_cpub_clk_trace =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_SYS_CPUB_CLK_CNTL1, + .bit_idx =3D 23, + .flags =3D CLK_GATE_SET_TO_DISABLE, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cpub_clk_trace", + .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_fixed_pll_dco.hw + &g12b_cpub_clk_trace_sel.hw }, .num_parents =3D 1, + /* + * This clock is set by the ROM monitor code, + * Linux should not change it at runtime + */ }, }; =20 @@ -2530,8 +2507,9 @@ static struct clk_regmap g12a_mpll3 =3D { }, }; =20 -static u32 mux_table_clk81[] =3D { 0, 2, 3, 4, 5, 6, 7 }; -static const struct clk_parent_data clk81_parent_data[] =3D { +/* clk81 is often referred as "mpeg_clk" */ +static u32 g12a_clk81_parents_val_table[] =3D { 0, 2, 3, 4, 5, 6, 7 }; +static const struct clk_parent_data g12a_clk81_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &g12a_fclk_div7.hw }, { .hw =3D &g12a_mpll1.hw }, @@ -2541,32 +2519,32 @@ static const struct clk_parent_data clk81_parent_da= ta[] =3D { { .hw =3D &g12a_fclk_div5.hw }, }; =20 -static struct clk_regmap g12a_mpeg_clk_sel =3D { +static struct clk_regmap g12a_clk81_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_MPEG_CLK_CNTL, .mask =3D 0x7, .shift =3D 12, - .table =3D mux_table_clk81, + .table =3D g12a_clk81_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "mpeg_clk_sel", + .name =3D "clk81_sel", .ops =3D &clk_regmap_mux_ro_ops, - .parent_data =3D clk81_parent_data, - .num_parents =3D ARRAY_SIZE(clk81_parent_data), + .parent_data =3D g12a_clk81_parents, + .num_parents =3D ARRAY_SIZE(g12a_clk81_parents), }, }; =20 -static struct clk_regmap g12a_mpeg_clk_div =3D { +static struct clk_regmap g12a_clk81_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D HHI_MPEG_CLK_CNTL, .shift =3D 0, .width =3D 7, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "mpeg_clk_div", + .name =3D "clk81_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_mpeg_clk_sel.hw + &g12a_clk81_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2582,14 +2560,14 @@ static struct clk_regmap g12a_clk81 =3D { .name =3D "clk81", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &g12a_mpeg_clk_div.hw + &g12a_clk81_div.hw }, .num_parents =3D 1, .flags =3D (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), }, }; =20 -static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] =3D { +static const struct clk_parent_data g12a_sd_emmc_clk0_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &g12a_fclk_div2.hw }, { .hw =3D &g12a_fclk_div3.hw }, @@ -2613,8 +2591,8 @@ static struct clk_regmap g12a_sd_emmc_a_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_a_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D g12a_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data), + .parent_data =3D g12a_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(g12a_sd_emmc_clk0_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2662,8 +2640,8 @@ static struct clk_regmap g12a_sd_emmc_b_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_b_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D g12a_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data), + .parent_data =3D g12a_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(g12a_sd_emmc_clk0_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2711,8 +2689,8 @@ static struct clk_regmap g12a_sd_emmc_c_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_c_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D g12a_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data), + .parent_data =3D g12a_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(g12a_sd_emmc_clk0_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2774,7 +2752,7 @@ static struct clk_regmap g12a_vid_pll_div =3D { }, }; =20 -static const struct clk_hw *g12a_vid_pll_parent_hws[] =3D { +static const struct clk_hw *g12a_vid_pll_parents[] =3D { &g12a_vid_pll_div.hw, &g12a_hdmi_pll.hw, }; @@ -2792,8 +2770,8 @@ static struct clk_regmap g12a_vid_pll_sel =3D { * bit 18 selects from 2 possible parents: * vid_pll_div or hdmi_pll */ - .parent_hws =3D g12a_vid_pll_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_vid_pll_parent_hws), + .parent_hws =3D g12a_vid_pll_parents, + .num_parents =3D ARRAY_SIZE(g12a_vid_pll_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -2816,7 +2794,7 @@ static struct clk_regmap g12a_vid_pll =3D { =20 /* VPU Clock */ =20 -static const struct clk_hw *g12a_vpu_parent_hws[] =3D { +static const struct clk_hw *g12a_vpu_parents[] =3D { &g12a_fclk_div3.hw, &g12a_fclk_div4.hw, &g12a_fclk_div5.hw, @@ -2836,8 +2814,8 @@ static struct clk_regmap g12a_vpu_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vpu_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_vpu_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_vpu_parent_hws), + .parent_hws =3D g12a_vpu_parents, + .num_parents =3D ARRAY_SIZE(g12a_vpu_parents), .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; @@ -2880,8 +2858,8 @@ static struct clk_regmap g12a_vpu_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vpu_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_vpu_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_vpu_parent_hws), + .parent_hws =3D g12a_vpu_parents, + .num_parents =3D ARRAY_SIZE(g12a_vpu_parents), .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; @@ -2939,7 +2917,7 @@ static struct clk_regmap g12a_vpu =3D { =20 /* VDEC clocks */ =20 -static const struct clk_hw *g12a_vdec_parent_hws[] =3D { +static const struct clk_hw *g12a_vdec_parents[] =3D { &g12a_fclk_div2p5.hw, &g12a_fclk_div3.hw, &g12a_fclk_div4.hw, @@ -2959,8 +2937,8 @@ static struct clk_regmap g12a_vdec_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vdec_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_vdec_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_vdec_parent_hws), + .parent_hws =3D g12a_vdec_parents, + .num_parents =3D ARRAY_SIZE(g12a_vdec_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -3009,8 +2987,8 @@ static struct clk_regmap g12a_vdec_hevcf_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vdec_hevcf_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_vdec_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_vdec_parent_hws), + .parent_hws =3D g12a_vdec_parents, + .num_parents =3D ARRAY_SIZE(g12a_vdec_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -3059,8 +3037,8 @@ static struct clk_regmap g12a_vdec_hevc_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vdec_hevc_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_vdec_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_vdec_parent_hws), + .parent_hws =3D g12a_vdec_parents, + .num_parents =3D ARRAY_SIZE(g12a_vdec_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -3101,7 +3079,7 @@ static struct clk_regmap g12a_vdec_hevc =3D { =20 /* VAPB Clock */ =20 -static const struct clk_hw *g12a_vapb_parent_hws[] =3D { +static const struct clk_hw *g12a_vapb_parents[] =3D { &g12a_fclk_div4.hw, &g12a_fclk_div3.hw, &g12a_fclk_div5.hw, @@ -3121,8 +3099,8 @@ static struct clk_regmap g12a_vapb_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vapb_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_vapb_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_vapb_parent_hws), + .parent_hws =3D g12a_vapb_parents, + .num_parents =3D ARRAY_SIZE(g12a_vapb_parents), .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; @@ -3169,8 +3147,8 @@ static struct clk_regmap g12a_vapb_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vapb_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_vapb_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_vapb_parent_hws), + .parent_hws =3D g12a_vapb_parents, + .num_parents =3D ARRAY_SIZE(g12a_vapb_parents), .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; @@ -3244,7 +3222,7 @@ static struct clk_regmap g12a_vapb =3D { }, }; =20 -static const struct clk_hw *g12a_vclk_parent_hws[] =3D { +static const struct clk_hw *g12a_vclk_parents[] =3D { &g12a_vid_pll.hw, &g12a_gp0_pll.hw, &g12a_hifi_pll.hw, @@ -3264,8 +3242,8 @@ static struct clk_regmap g12a_vclk_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_vclk_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_vclk_parent_hws), + .parent_hws =3D g12a_vclk_parents, + .num_parents =3D ARRAY_SIZE(g12a_vclk_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -3279,8 +3257,8 @@ static struct clk_regmap g12a_vclk2_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vclk2_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_vclk_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_vclk_parent_hws), + .parent_hws =3D g12a_vclk_parents, + .num_parents =3D ARRAY_SIZE(g12a_vclk_parents), .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; @@ -3643,8 +3621,8 @@ static struct clk_fixed_factor g12a_vclk2_div12 =3D { }, }; =20 -static u32 mux_table_cts_sel[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; -static const struct clk_hw *g12a_cts_parent_hws[] =3D { +static u32 g12a_cts_parents_val_table[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11,= 12 }; +static const struct clk_hw *g12a_cts_parents[] =3D { &g12a_vclk_div1.hw, &g12a_vclk_div2.hw, &g12a_vclk_div4.hw, @@ -3662,13 +3640,13 @@ static struct clk_regmap g12a_cts_enci_sel =3D { .offset =3D HHI_VID_CLK_DIV, .mask =3D 0xf, .shift =3D 28, - .table =3D mux_table_cts_sel, + .table =3D g12a_cts_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_enci_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_cts_parent_hws), + .parent_hws =3D g12a_cts_parents, + .num_parents =3D ARRAY_SIZE(g12a_cts_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -3678,13 +3656,13 @@ static struct clk_regmap g12a_cts_encp_sel =3D { .offset =3D HHI_VID_CLK_DIV, .mask =3D 0xf, .shift =3D 20, - .table =3D mux_table_cts_sel, + .table =3D g12a_cts_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_encp_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_cts_parent_hws), + .parent_hws =3D g12a_cts_parents, + .num_parents =3D ARRAY_SIZE(g12a_cts_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -3694,13 +3672,13 @@ static struct clk_regmap g12a_cts_encl_sel =3D { .offset =3D HHI_VIID_CLK_DIV, .mask =3D 0xf, .shift =3D 12, - .table =3D mux_table_cts_sel, + .table =3D g12a_cts_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_encl_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_cts_parent_hws), + .parent_hws =3D g12a_cts_parents, + .num_parents =3D ARRAY_SIZE(g12a_cts_parents), .flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, }, }; @@ -3710,20 +3688,20 @@ static struct clk_regmap g12a_cts_vdac_sel =3D { .offset =3D HHI_VIID_CLK_DIV, .mask =3D 0xf, .shift =3D 28, - .table =3D mux_table_cts_sel, + .table =3D g12a_cts_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_vdac_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_cts_parent_hws), + .parent_hws =3D g12a_cts_parents, + .num_parents =3D ARRAY_SIZE(g12a_cts_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; =20 /* TOFIX: add support for cts_tcon */ -static u32 mux_table_hdmi_tx_sel[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; -static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] =3D { +static u32 g12a_hdmi_tx_parents_val_table[] =3D { 0, 1, 2, 3, 4, 8, 9, 10,= 11, 12 }; +static const struct clk_hw *g12a_hdmi_tx_parents[] =3D { &g12a_vclk_div1.hw, &g12a_vclk_div2.hw, &g12a_vclk_div4.hw, @@ -3741,13 +3719,13 @@ static struct clk_regmap g12a_hdmi_tx_sel =3D { .offset =3D HHI_HDMI_CLK_CNTL, .mask =3D 0xf, .shift =3D 16, - .table =3D mux_table_hdmi_tx_sel, + .table =3D g12a_hdmi_tx_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "hdmi_tx_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_cts_hdmi_tx_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws), + .parent_hws =3D g12a_hdmi_tx_parents, + .num_parents =3D ARRAY_SIZE(g12a_hdmi_tx_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -3834,7 +3812,7 @@ static struct clk_regmap g12a_hdmi_tx =3D { =20 /* MIPI DSI Host Clocks */ =20 -static const struct clk_hw *g12a_mipi_dsi_pxclk_parent_hws[] =3D { +static const struct clk_hw *g12a_mipi_dsi_pxclk_parents[] =3D { &g12a_vid_pll.hw, &g12a_gp0_pll.hw, &g12a_hifi_pll.hw, @@ -3855,8 +3833,8 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "mipi_dsi_pxclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_mipi_dsi_pxclk_parent_hws, - .num_parents =3D ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws), + .parent_hws =3D g12a_mipi_dsi_pxclk_parents, + .num_parents =3D ARRAY_SIZE(g12a_mipi_dsi_pxclk_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, }, }; @@ -3907,7 +3885,7 @@ static struct clk_regmap g12a_mipi_dsi_pxclk =3D { =20 /* MIPI ISP Clocks */ =20 -static const struct clk_parent_data g12b_mipi_isp_parent_data[] =3D { +static const struct clk_parent_data g12b_mipi_isp_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &g12a_gp0_pll.hw }, { .hw =3D &g12a_hifi_pll.hw }, @@ -3927,8 +3905,8 @@ static struct clk_regmap g12b_mipi_isp_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "mipi_isp_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D g12b_mipi_isp_parent_data, - .num_parents =3D ARRAY_SIZE(g12b_mipi_isp_parent_data), + .parent_data =3D g12b_mipi_isp_parents, + .num_parents =3D ARRAY_SIZE(g12b_mipi_isp_parents), }, }; =20 @@ -3967,7 +3945,7 @@ static struct clk_regmap g12b_mipi_isp =3D { =20 /* HDMI Clocks */ =20 -static const struct clk_parent_data g12a_hdmi_parent_data[] =3D { +static const struct clk_parent_data g12a_hdmi_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &g12a_fclk_div4.hw }, { .hw =3D &g12a_fclk_div3.hw }, @@ -3984,8 +3962,8 @@ static struct clk_regmap g12a_hdmi_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "hdmi_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D g12a_hdmi_parent_data, - .num_parents =3D ARRAY_SIZE(g12a_hdmi_parent_data), + .parent_data =3D g12a_hdmi_parents, + .num_parents =3D ARRAY_SIZE(g12a_hdmi_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -4025,7 +4003,7 @@ static struct clk_regmap g12a_hdmi =3D { * mux because it does top-to-bottom updates the each clock tree and * switches to the "inactive" one when CLK_SET_RATE_GATE is set. */ -static const struct clk_parent_data g12a_mali_0_1_parent_data[] =3D { +static const struct clk_parent_data g12a_mali_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &g12a_gp0_pll.hw }, { .hw =3D &g12a_hifi_pll.hw }, @@ -4045,8 +4023,8 @@ static struct clk_regmap g12a_mali_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "mali_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D g12a_mali_0_1_parent_data, - .num_parents =3D 8, + .parent_data =3D g12a_mali_parents, + .num_parents =3D ARRAY_SIZE(g12a_mali_parents), /* * Don't request the parent to change the rate because * all GPU frequencies can be derived from the fclk_* @@ -4099,8 +4077,8 @@ static struct clk_regmap g12a_mali_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "mali_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D g12a_mali_0_1_parent_data, - .num_parents =3D 8, + .parent_data =3D g12a_mali_parents, + .num_parents =3D ARRAY_SIZE(g12a_mali_parents), /* * Don't request the parent to change the rate because * all GPU frequencies can be derived from the fclk_* @@ -4144,11 +4122,6 @@ static struct clk_regmap g12a_mali_1 =3D { }, }; =20 -static const struct clk_hw *g12a_mali_parent_hws[] =3D { - &g12a_mali_0.hw, - &g12a_mali_1.hw, -}; - static struct clk_regmap g12a_mali =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_MALI_CLK_CNTL, @@ -4158,7 +4131,10 @@ static struct clk_regmap g12a_mali =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "mali", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D g12a_mali_parent_hws, + .parent_hws =3D (const struct clk_hw *[]) { + &g12a_mali_0.hw, + &g12a_mali_1.hw, + }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, @@ -4197,7 +4173,7 @@ static struct clk_regmap g12a_ts =3D { =20 /* SPICC SCLK source clock */ =20 -static const struct clk_parent_data spicc_sclk_parent_data[] =3D { +static const struct clk_parent_data g12a_spicc_sclk_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &g12a_clk81.hw }, { .hw =3D &g12a_fclk_div4.hw }, @@ -4216,8 +4192,8 @@ static struct clk_regmap g12a_spicc0_sclk_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "spicc0_sclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D spicc_sclk_parent_data, - .num_parents =3D ARRAY_SIZE(spicc_sclk_parent_data), + .parent_data =3D g12a_spicc_sclk_parents, + .num_parents =3D ARRAY_SIZE(g12a_spicc_sclk_parents), }, }; =20 @@ -4263,8 +4239,8 @@ static struct clk_regmap g12a_spicc1_sclk_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "spicc1_sclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D spicc_sclk_parent_data, - .num_parents =3D ARRAY_SIZE(spicc_sclk_parent_data), + .parent_data =3D g12a_spicc_sclk_parents, + .num_parents =3D ARRAY_SIZE(g12a_spicc_sclk_parents), }, }; =20 @@ -4303,7 +4279,7 @@ static struct clk_regmap g12a_spicc1_sclk =3D { =20 /* Neural Network Accelerator source clock */ =20 -static const struct clk_parent_data nna_clk_parent_data[] =3D { +static const struct clk_parent_data sm1_nna_clk_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &g12a_gp0_pll.hw, }, { .hw =3D &g12a_hifi_pll.hw, }, @@ -4323,8 +4299,8 @@ static struct clk_regmap sm1_nna_axi_clk_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "nna_axi_clk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D nna_clk_parent_data, - .num_parents =3D ARRAY_SIZE(nna_clk_parent_data), + .parent_data =3D sm1_nna_clk_parents, + .num_parents =3D ARRAY_SIZE(sm1_nna_clk_parents), }, }; =20 @@ -4370,8 +4346,8 @@ static struct clk_regmap sm1_nna_core_clk_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "nna_core_clk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D nna_clk_parent_data, - .num_parents =3D ARRAY_SIZE(nna_clk_parent_data), + .parent_data =3D sm1_nna_clk_parents, + .num_parents =3D ARRAY_SIZE(sm1_nna_clk_parents), }, }; =20 @@ -4408,89 +4384,89 @@ static struct clk_regmap sm1_nna_core_clk =3D { }, }; =20 -#define MESON_GATE(_name, _reg, _bit) \ +#define G12A_PCLK(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw) =20 -#define MESON_GATE_RO(_name, _reg, _bit) \ +#define G12A_PCLK_RO(_name, _reg, _bit) \ MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw) =20 /* Everything Else (EE) domain gates */ -static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0); -static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1); -static MESON_GATE(g12a_audio_locker, HHI_GCLK_MPEG0, 2); -static MESON_GATE(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3); -static MESON_GATE(g12a_eth_phy, HHI_GCLK_MPEG0, 4); -static MESON_GATE(g12a_isa, HHI_GCLK_MPEG0, 5); -static MESON_GATE(g12a_pl301, HHI_GCLK_MPEG0, 6); -static MESON_GATE(g12a_periphs, HHI_GCLK_MPEG0, 7); -static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8); -static MESON_GATE(g12a_i2c, HHI_GCLK_MPEG0, 9); -static MESON_GATE(g12a_sana, HHI_GCLK_MPEG0, 10); -static MESON_GATE(g12a_sd, HHI_GCLK_MPEG0, 11); -static MESON_GATE(g12a_rng0, HHI_GCLK_MPEG0, 12); -static MESON_GATE(g12a_uart0, HHI_GCLK_MPEG0, 13); -static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14); -static MESON_GATE(g12a_hiu_reg, HHI_GCLK_MPEG0, 19); -static MESON_GATE(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20); -static MESON_GATE(g12a_assist_misc, HHI_GCLK_MPEG0, 23); -static MESON_GATE(g12a_emmc_a, HHI_GCLK_MPEG0, 24); -static MESON_GATE(g12a_emmc_b, HHI_GCLK_MPEG0, 25); -static MESON_GATE(g12a_emmc_c, HHI_GCLK_MPEG0, 26); -static MESON_GATE(g12a_audio_codec, HHI_GCLK_MPEG0, 28); - -static MESON_GATE(g12a_audio, HHI_GCLK_MPEG1, 0); -static MESON_GATE(g12a_eth_core, HHI_GCLK_MPEG1, 3); -static MESON_GATE(g12a_demux, HHI_GCLK_MPEG1, 4); -static MESON_GATE(g12a_audio_ififo, HHI_GCLK_MPEG1, 11); -static MESON_GATE(g12a_adc, HHI_GCLK_MPEG1, 13); -static MESON_GATE(g12a_uart1, HHI_GCLK_MPEG1, 16); -static MESON_GATE(g12a_g2d, HHI_GCLK_MPEG1, 20); -static MESON_GATE(g12a_reset, HHI_GCLK_MPEG1, 23); -static MESON_GATE(g12a_pcie_comb, HHI_GCLK_MPEG1, 24); -static MESON_GATE(g12a_parser, HHI_GCLK_MPEG1, 25); -static MESON_GATE(g12a_usb_general, HHI_GCLK_MPEG1, 26); -static MESON_GATE(g12a_pcie_phy, HHI_GCLK_MPEG1, 27); -static MESON_GATE(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29); - -static MESON_GATE(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1); -static MESON_GATE(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3); -static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4); -static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6); -static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8); -static MESON_GATE(g12b_mipi_isp_gate, HHI_GCLK_MPEG2, 17); -static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11); -static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15); -static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25); -static MESON_GATE(g12b_csi_phy1, HHI_GCLK_MPEG2, 28); -static MESON_GATE(g12b_csi_phy0, HHI_GCLK_MPEG2, 29); -static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30); - -static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1); -static MESON_GATE(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2); -static MESON_GATE(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3); -static MESON_GATE(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4); -static MESON_GATE(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5); -static MESON_GATE(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6); -static MESON_GATE(g12a_vclk2_other, HHI_GCLK_OTHER, 7); -static MESON_GATE(g12a_vclk2_enci, HHI_GCLK_OTHER, 8); -static MESON_GATE(g12a_vclk2_encp, HHI_GCLK_OTHER, 9); -static MESON_GATE(g12a_dac_clk, HHI_GCLK_OTHER, 10); -static MESON_GATE(g12a_aoclk_gate, HHI_GCLK_OTHER, 14); -static MESON_GATE(g12a_iec958_gate, HHI_GCLK_OTHER, 16); -static MESON_GATE(g12a_enc480p, HHI_GCLK_OTHER, 20); -static MESON_GATE(g12a_rng1, HHI_GCLK_OTHER, 21); -static MESON_GATE(g12a_vclk2_enct, HHI_GCLK_OTHER, 22); -static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23); -static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24); -static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25); -static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26); - -static MESON_GATE_RO(g12a_dma, HHI_GCLK_OTHER2, 0); -static MESON_GATE_RO(g12a_efuse, HHI_GCLK_OTHER2, 1); -static MESON_GATE_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2); -static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3); -static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4); +static G12A_PCLK(g12a_ddr, HHI_GCLK_MPEG0, 0); +static G12A_PCLK(g12a_dos, HHI_GCLK_MPEG0, 1); +static G12A_PCLK(g12a_audio_locker, HHI_GCLK_MPEG0, 2); +static G12A_PCLK(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3); +static G12A_PCLK(g12a_eth_phy, HHI_GCLK_MPEG0, 4); +static G12A_PCLK(g12a_isa, HHI_GCLK_MPEG0, 5); +static G12A_PCLK(g12a_pl301, HHI_GCLK_MPEG0, 6); +static G12A_PCLK(g12a_periphs, HHI_GCLK_MPEG0, 7); +static G12A_PCLK(g12a_spicc_0, HHI_GCLK_MPEG0, 8); +static G12A_PCLK(g12a_i2c, HHI_GCLK_MPEG0, 9); +static G12A_PCLK(g12a_sana, HHI_GCLK_MPEG0, 10); +static G12A_PCLK(g12a_sd, HHI_GCLK_MPEG0, 11); +static G12A_PCLK(g12a_rng0, HHI_GCLK_MPEG0, 12); +static G12A_PCLK(g12a_uart0, HHI_GCLK_MPEG0, 13); +static G12A_PCLK(g12a_spicc_1, HHI_GCLK_MPEG0, 14); +static G12A_PCLK(g12a_hiu_reg, HHI_GCLK_MPEG0, 19); +static G12A_PCLK(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20); +static G12A_PCLK(g12a_assist_misc, HHI_GCLK_MPEG0, 23); +static G12A_PCLK(g12a_emmc_a, HHI_GCLK_MPEG0, 24); +static G12A_PCLK(g12a_emmc_b, HHI_GCLK_MPEG0, 25); +static G12A_PCLK(g12a_emmc_c, HHI_GCLK_MPEG0, 26); +static G12A_PCLK(g12a_audio_codec, HHI_GCLK_MPEG0, 28); + +static G12A_PCLK(g12a_audio, HHI_GCLK_MPEG1, 0); +static G12A_PCLK(g12a_eth_core, HHI_GCLK_MPEG1, 3); +static G12A_PCLK(g12a_demux, HHI_GCLK_MPEG1, 4); +static G12A_PCLK(g12a_audio_ififo, HHI_GCLK_MPEG1, 11); +static G12A_PCLK(g12a_adc, HHI_GCLK_MPEG1, 13); +static G12A_PCLK(g12a_uart1, HHI_GCLK_MPEG1, 16); +static G12A_PCLK(g12a_g2d, HHI_GCLK_MPEG1, 20); +static G12A_PCLK(g12a_reset, HHI_GCLK_MPEG1, 23); +static G12A_PCLK(g12a_pcie_comb, HHI_GCLK_MPEG1, 24); +static G12A_PCLK(g12a_parser, HHI_GCLK_MPEG1, 25); +static G12A_PCLK(g12a_usb_general, HHI_GCLK_MPEG1, 26); +static G12A_PCLK(g12a_pcie_phy, HHI_GCLK_MPEG1, 27); +static G12A_PCLK(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29); + +static G12A_PCLK(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1); +static G12A_PCLK(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); +static G12A_PCLK(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3); +static G12A_PCLK(g12a_htx_pclk, HHI_GCLK_MPEG2, 4); +static G12A_PCLK(g12a_bt656, HHI_GCLK_MPEG2, 6); +static G12A_PCLK(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8); +static G12A_PCLK(g12b_mipi_isp_gate, HHI_GCLK_MPEG2, 17); +static G12A_PCLK(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11); +static G12A_PCLK(g12a_uart2, HHI_GCLK_MPEG2, 15); +static G12A_PCLK(g12a_vpu_intr, HHI_GCLK_MPEG2, 25); +static G12A_PCLK(g12b_csi_phy1, HHI_GCLK_MPEG2, 28); +static G12A_PCLK(g12b_csi_phy0, HHI_GCLK_MPEG2, 29); +static G12A_PCLK(g12a_gic, HHI_GCLK_MPEG2, 30); + +static G12A_PCLK(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1); +static G12A_PCLK(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2); +static G12A_PCLK(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3); +static G12A_PCLK(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4); +static G12A_PCLK(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5); +static G12A_PCLK(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6); +static G12A_PCLK(g12a_vclk2_other, HHI_GCLK_OTHER, 7); +static G12A_PCLK(g12a_vclk2_enci, HHI_GCLK_OTHER, 8); +static G12A_PCLK(g12a_vclk2_encp, HHI_GCLK_OTHER, 9); +static G12A_PCLK(g12a_dac_clk, HHI_GCLK_OTHER, 10); +static G12A_PCLK(g12a_aoclk_gate, HHI_GCLK_OTHER, 14); +static G12A_PCLK(g12a_iec958_gate, HHI_GCLK_OTHER, 16); +static G12A_PCLK(g12a_enc480p, HHI_GCLK_OTHER, 20); +static G12A_PCLK(g12a_rng1, HHI_GCLK_OTHER, 21); +static G12A_PCLK(g12a_vclk2_enct, HHI_GCLK_OTHER, 22); +static G12A_PCLK(g12a_vclk2_encl, HHI_GCLK_OTHER, 23); +static G12A_PCLK(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24); +static G12A_PCLK(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25); +static G12A_PCLK(g12a_vclk2_other1, HHI_GCLK_OTHER, 26); + +static G12A_PCLK_RO(g12a_dma, HHI_GCLK_OTHER2, 0); +static G12A_PCLK_RO(g12a_efuse, HHI_GCLK_OTHER2, 1); +static G12A_PCLK_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2); +static G12A_PCLK_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3); +static G12A_PCLK_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4); =20 /* Array of all clocks provided by this provider */ static struct clk_hw *g12a_hw_clks[] =3D { @@ -4503,8 +4479,8 @@ static struct clk_hw *g12a_hw_clks[] =3D { [CLKID_FCLK_DIV7] =3D &g12a_fclk_div7.hw, [CLKID_FCLK_DIV2P5] =3D &g12a_fclk_div2p5.hw, [CLKID_GP0_PLL] =3D &g12a_gp0_pll.hw, - [CLKID_MPEG_SEL] =3D &g12a_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &g12a_mpeg_clk_div.hw, + [CLKID_MPEG_SEL] =3D &g12a_clk81_sel.hw, + [CLKID_MPEG_DIV] =3D &g12a_clk81_div.hw, [CLKID_CLK81] =3D &g12a_clk81.hw, [CLKID_MPLL0] =3D &g12a_mpll0.hw, [CLKID_MPLL1] =3D &g12a_mpll1.hw, @@ -4676,12 +4652,12 @@ static struct clk_hw *g12a_hw_clks[] =3D { [CLKID_MPLL_50M] =3D &g12a_mpll_50m.hw, [CLKID_SYS_PLL_DIV16_EN] =3D &g12a_sys_pll_div16_en.hw, [CLKID_SYS_PLL_DIV16] =3D &g12a_sys_pll_div16.hw, - [CLKID_CPU_CLK_DYN0_SEL] =3D &g12a_cpu_clk_premux0.hw, - [CLKID_CPU_CLK_DYN0_DIV] =3D &g12a_cpu_clk_mux0_div.hw, - [CLKID_CPU_CLK_DYN0] =3D &g12a_cpu_clk_postmux0.hw, - [CLKID_CPU_CLK_DYN1_SEL] =3D &g12a_cpu_clk_premux1.hw, - [CLKID_CPU_CLK_DYN1_DIV] =3D &g12a_cpu_clk_mux1_div.hw, - [CLKID_CPU_CLK_DYN1] =3D &g12a_cpu_clk_postmux1.hw, + [CLKID_CPU_CLK_DYN0_SEL] =3D &g12a_cpu_clk_dyn0_sel.hw, + [CLKID_CPU_CLK_DYN0_DIV] =3D &g12a_cpu_clk_dyn0_div.hw, + [CLKID_CPU_CLK_DYN0] =3D &g12a_cpu_clk_dyn0.hw, + [CLKID_CPU_CLK_DYN1_SEL] =3D &g12a_cpu_clk_dyn1_sel.hw, + [CLKID_CPU_CLK_DYN1_DIV] =3D &g12a_cpu_clk_dyn1_div.hw, + [CLKID_CPU_CLK_DYN1] =3D &g12a_cpu_clk_dyn1.hw, [CLKID_CPU_CLK_DYN] =3D &g12a_cpu_clk_dyn.hw, [CLKID_CPU_CLK] =3D &g12a_cpu_clk.hw, [CLKID_CPU_CLK_DIV16_EN] =3D &g12a_cpu_clk_div16_en.hw, @@ -4730,8 +4706,8 @@ static struct clk_hw *g12b_hw_clks[] =3D { [CLKID_FCLK_DIV7] =3D &g12a_fclk_div7.hw, [CLKID_FCLK_DIV2P5] =3D &g12a_fclk_div2p5.hw, [CLKID_GP0_PLL] =3D &g12a_gp0_pll.hw, - [CLKID_MPEG_SEL] =3D &g12a_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &g12a_mpeg_clk_div.hw, + [CLKID_MPEG_SEL] =3D &g12a_clk81_sel.hw, + [CLKID_MPEG_DIV] =3D &g12a_clk81_div.hw, [CLKID_CLK81] =3D &g12a_clk81.hw, [CLKID_MPLL0] =3D &g12a_mpll0.hw, [CLKID_MPLL1] =3D &g12a_mpll1.hw, @@ -4903,12 +4879,12 @@ static struct clk_hw *g12b_hw_clks[] =3D { [CLKID_MPLL_50M] =3D &g12a_mpll_50m.hw, [CLKID_SYS_PLL_DIV16_EN] =3D &g12a_sys_pll_div16_en.hw, [CLKID_SYS_PLL_DIV16] =3D &g12a_sys_pll_div16.hw, - [CLKID_CPU_CLK_DYN0_SEL] =3D &g12a_cpu_clk_premux0.hw, - [CLKID_CPU_CLK_DYN0_DIV] =3D &g12a_cpu_clk_mux0_div.hw, - [CLKID_CPU_CLK_DYN0] =3D &g12a_cpu_clk_postmux0.hw, - [CLKID_CPU_CLK_DYN1_SEL] =3D &g12a_cpu_clk_premux1.hw, - [CLKID_CPU_CLK_DYN1_DIV] =3D &g12a_cpu_clk_mux1_div.hw, - [CLKID_CPU_CLK_DYN1] =3D &g12a_cpu_clk_postmux1.hw, + [CLKID_CPU_CLK_DYN0_SEL] =3D &g12a_cpu_clk_dyn0_sel.hw, + [CLKID_CPU_CLK_DYN0_DIV] =3D &g12a_cpu_clk_dyn0_div.hw, + [CLKID_CPU_CLK_DYN0] =3D &g12a_cpu_clk_dyn0.hw, + [CLKID_CPU_CLK_DYN1_SEL] =3D &g12a_cpu_clk_dyn1_sel.hw, + [CLKID_CPU_CLK_DYN1_DIV] =3D &g12a_cpu_clk_dyn1_div.hw, + [CLKID_CPU_CLK_DYN1] =3D &g12a_cpu_clk_dyn1.hw, [CLKID_CPU_CLK_DYN] =3D &g12a_cpu_clk_dyn.hw, [CLKID_CPU_CLK] =3D &g12b_cpu_clk.hw, [CLKID_CPU_CLK_DIV16_EN] =3D &g12a_cpu_clk_div16_en.hw, @@ -4940,12 +4916,12 @@ static struct clk_hw *g12b_hw_clks[] =3D { [CLKID_SYS1_PLL] =3D &g12b_sys1_pll.hw, [CLKID_SYS1_PLL_DIV16_EN] =3D &g12b_sys1_pll_div16_en.hw, [CLKID_SYS1_PLL_DIV16] =3D &g12b_sys1_pll_div16.hw, - [CLKID_CPUB_CLK_DYN0_SEL] =3D &g12b_cpub_clk_premux0.hw, - [CLKID_CPUB_CLK_DYN0_DIV] =3D &g12b_cpub_clk_mux0_div.hw, - [CLKID_CPUB_CLK_DYN0] =3D &g12b_cpub_clk_postmux0.hw, - [CLKID_CPUB_CLK_DYN1_SEL] =3D &g12b_cpub_clk_premux1.hw, - [CLKID_CPUB_CLK_DYN1_DIV] =3D &g12b_cpub_clk_mux1_div.hw, - [CLKID_CPUB_CLK_DYN1] =3D &g12b_cpub_clk_postmux1.hw, + [CLKID_CPUB_CLK_DYN0_SEL] =3D &g12b_cpub_clk_dyn0_sel.hw, + [CLKID_CPUB_CLK_DYN0_DIV] =3D &g12b_cpub_clk_dyn0_div.hw, + [CLKID_CPUB_CLK_DYN0] =3D &g12b_cpub_clk_dyn0.hw, + [CLKID_CPUB_CLK_DYN1_SEL] =3D &g12b_cpub_clk_dyn1.hw, + [CLKID_CPUB_CLK_DYN1_DIV] =3D &g12b_cpub_clk_dyn1_div.hw, + [CLKID_CPUB_CLK_DYN1] =3D &g12b_cpub_clk_dyn1.hw, [CLKID_CPUB_CLK_DYN] =3D &g12b_cpub_clk_dyn.hw, [CLKID_CPUB_CLK] =3D &g12b_cpub_clk.hw, [CLKID_CPUB_CLK_DIV16_EN] =3D &g12b_cpub_clk_div16_en.hw, @@ -4998,8 +4974,8 @@ static struct clk_hw *sm1_hw_clks[] =3D { [CLKID_FCLK_DIV7] =3D &g12a_fclk_div7.hw, [CLKID_FCLK_DIV2P5] =3D &g12a_fclk_div2p5.hw, [CLKID_GP0_PLL] =3D &g12a_gp0_pll.hw, - [CLKID_MPEG_SEL] =3D &g12a_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &g12a_mpeg_clk_div.hw, + [CLKID_MPEG_SEL] =3D &g12a_clk81_sel.hw, + [CLKID_MPEG_DIV] =3D &g12a_clk81_div.hw, [CLKID_CLK81] =3D &g12a_clk81.hw, [CLKID_MPLL0] =3D &g12a_mpll0.hw, [CLKID_MPLL1] =3D &g12a_mpll1.hw, @@ -5171,12 +5147,12 @@ static struct clk_hw *sm1_hw_clks[] =3D { [CLKID_MPLL_50M] =3D &g12a_mpll_50m.hw, [CLKID_SYS_PLL_DIV16_EN] =3D &g12a_sys_pll_div16_en.hw, [CLKID_SYS_PLL_DIV16] =3D &g12a_sys_pll_div16.hw, - [CLKID_CPU_CLK_DYN0_SEL] =3D &g12a_cpu_clk_premux0.hw, - [CLKID_CPU_CLK_DYN0_DIV] =3D &g12a_cpu_clk_mux0_div.hw, - [CLKID_CPU_CLK_DYN0] =3D &g12a_cpu_clk_postmux0.hw, - [CLKID_CPU_CLK_DYN1_SEL] =3D &g12a_cpu_clk_premux1.hw, - [CLKID_CPU_CLK_DYN1_DIV] =3D &g12a_cpu_clk_mux1_div.hw, - [CLKID_CPU_CLK_DYN1] =3D &g12a_cpu_clk_postmux1.hw, + [CLKID_CPU_CLK_DYN0_SEL] =3D &g12a_cpu_clk_dyn0_sel.hw, + [CLKID_CPU_CLK_DYN0_DIV] =3D &g12a_cpu_clk_dyn0_div.hw, + [CLKID_CPU_CLK_DYN0] =3D &g12a_cpu_clk_dyn0.hw, + [CLKID_CPU_CLK_DYN1_SEL] =3D &g12a_cpu_clk_dyn1_sel.hw, + [CLKID_CPU_CLK_DYN1_DIV] =3D &g12a_cpu_clk_dyn1_div.hw, + [CLKID_CPU_CLK_DYN1] =3D &g12a_cpu_clk_dyn1.hw, [CLKID_CPU_CLK_DYN] =3D &g12a_cpu_clk_dyn.hw, [CLKID_CPU_CLK] =3D &g12a_cpu_clk.hw, [CLKID_CPU_CLK_DIV16_EN] =3D &g12a_cpu_clk_div16_en.hw, @@ -5206,12 +5182,12 @@ static struct clk_hw *sm1_hw_clks[] =3D { [CLKID_TS] =3D &g12a_ts.hw, [CLKID_GP1_PLL_DCO] =3D &sm1_gp1_pll_dco.hw, [CLKID_GP1_PLL] =3D &sm1_gp1_pll.hw, - [CLKID_DSU_CLK_DYN0_SEL] =3D &sm1_dsu_clk_premux0.hw, - [CLKID_DSU_CLK_DYN0_DIV] =3D &sm1_dsu_clk_premux1.hw, - [CLKID_DSU_CLK_DYN0] =3D &sm1_dsu_clk_mux0_div.hw, - [CLKID_DSU_CLK_DYN1_SEL] =3D &sm1_dsu_clk_postmux0.hw, - [CLKID_DSU_CLK_DYN1_DIV] =3D &sm1_dsu_clk_mux1_div.hw, - [CLKID_DSU_CLK_DYN1] =3D &sm1_dsu_clk_postmux1.hw, + [CLKID_DSU_CLK_DYN0_SEL] =3D &sm1_dsu_clk_dyn0_sel.hw, + [CLKID_DSU_CLK_DYN0_DIV] =3D &sm1_dsu_clk_dyn0_div.hw, + [CLKID_DSU_CLK_DYN0] =3D &sm1_dsu_clk_dyn0.hw, + [CLKID_DSU_CLK_DYN1_SEL] =3D &sm1_dsu_clk_dyn1_sel.hw, + [CLKID_DSU_CLK_DYN1_DIV] =3D &sm1_dsu_clk_dyn1_div.hw, + [CLKID_DSU_CLK_DYN1] =3D &sm1_dsu_clk_dyn1.hw, [CLKID_DSU_CLK_DYN] =3D &sm1_dsu_clk_dyn.hw, [CLKID_DSU_CLK_FINAL] =3D &sm1_dsu_final_clk.hw, [CLKID_DSU_CLK] =3D &sm1_dsu_clk.hw, @@ -5241,8 +5217,7 @@ static const struct reg_sequence g12a_init_regs[] =3D= { =20 #define DVFS_CON_ID "dvfs" =20 -static int meson_g12a_dvfs_setup_common(struct device *dev, - struct clk_hw **hws) +static int g12a_dvfs_setup_common(struct device *dev, struct clk_hw **hws) { struct clk *notifier_clk; struct clk_hw *xtal; @@ -5251,13 +5226,13 @@ static int meson_g12a_dvfs_setup_common(struct devi= ce *dev, xtal =3D clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0); =20 /* Setup clock notifier for cpu_clk_postmux0 */ - g12a_cpu_clk_postmux0_nb_data.xtal =3D xtal; - notifier_clk =3D devm_clk_hw_get_clk(dev, &g12a_cpu_clk_postmux0.hw, + g12a_cpu_clk_dyn0_nb_data.xtal =3D xtal; + notifier_clk =3D devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn0.hw, DVFS_CON_ID); ret =3D devm_clk_notifier_register(dev, notifier_clk, - &g12a_cpu_clk_postmux0_nb_data.nb); + &g12a_cpu_clk_dyn0_nb_data.nb); if (ret) { - dev_err(dev, "failed to register the cpu_clk_postmux0 notifier\n"); + dev_err(dev, "failed to register the cpu_clk_dyn0 notifier\n"); return ret; } =20 @@ -5274,7 +5249,7 @@ static int meson_g12a_dvfs_setup_common(struct device= *dev, return 0; } =20 -static int meson_g12b_dvfs_setup(struct platform_device *pdev) +static int g12b_dvfs_setup(struct platform_device *pdev) { struct clk_hw **hws =3D g12b_hw_clks; struct device *dev =3D &pdev->dev; @@ -5282,7 +5257,7 @@ static int meson_g12b_dvfs_setup(struct platform_devi= ce *pdev) struct clk_hw *xtal; int ret; =20 - ret =3D meson_g12a_dvfs_setup_common(dev, hws); + ret =3D g12a_dvfs_setup_common(dev, hws); if (ret) return ret; =20 @@ -5311,18 +5286,19 @@ static int meson_g12b_dvfs_setup(struct platform_de= vice *pdev) /* Add notifiers for the second CPU cluster */ =20 /* Setup clock notifier for cpub_clk_postmux0 */ - g12b_cpub_clk_postmux0_nb_data.xtal =3D xtal; - notifier_clk =3D devm_clk_hw_get_clk(dev, &g12b_cpub_clk_postmux0.hw, + g12b_cpub_clk_dyn0_nb_data.xtal =3D xtal; + notifier_clk =3D devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn0.hw, DVFS_CON_ID); ret =3D devm_clk_notifier_register(dev, notifier_clk, - &g12b_cpub_clk_postmux0_nb_data.nb); + &g12b_cpub_clk_dyn0_nb_data.nb); if (ret) { - dev_err(dev, "failed to register the cpub_clk_postmux0 notifier\n"); + dev_err(dev, "failed to register the cpub_clk_dyn0 notifier\n"); return ret; } =20 /* Setup clock notifier for cpub_clk_dyn mux */ - notifier_clk =3D devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, "dvfs"); + notifier_clk =3D devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, + DVFS_CON_ID); ret =3D devm_clk_notifier_register(dev, notifier_clk, &g12a_cpu_clk_mux_nb); if (ret) { @@ -5351,14 +5327,14 @@ static int meson_g12b_dvfs_setup(struct platform_de= vice *pdev) return 0; } =20 -static int meson_g12a_dvfs_setup(struct platform_device *pdev) +static int g12a_dvfs_setup(struct platform_device *pdev) { struct clk_hw **hws =3D g12a_hw_clks; struct device *dev =3D &pdev->dev; struct clk *notifier_clk; int ret; =20 - ret =3D meson_g12a_dvfs_setup_common(dev, hws); + ret =3D g12a_dvfs_setup_common(dev, hws); if (ret) return ret; =20 @@ -5383,15 +5359,15 @@ static int meson_g12a_dvfs_setup(struct platform_de= vice *pdev) return 0; } =20 -struct meson_g12a_data { +struct g12a_clkc_data { const struct meson_eeclkc_data eeclkc_data; int (*dvfs_setup)(struct platform_device *pdev); }; =20 -static int meson_g12a_probe(struct platform_device *pdev) +static int g12a_clkc_probe(struct platform_device *pdev) { const struct meson_eeclkc_data *eeclkc_data; - const struct meson_g12a_data *g12a_data; + const struct g12a_clkc_data *g12a_data; int ret; =20 eeclkc_data =3D of_device_get_match_data(&pdev->dev); @@ -5402,7 +5378,7 @@ static int meson_g12a_probe(struct platform_device *p= dev) if (ret) return ret; =20 - g12a_data =3D container_of(eeclkc_data, struct meson_g12a_data, + g12a_data =3D container_of(eeclkc_data, struct g12a_clkc_data, eeclkc_data); =20 if (g12a_data->dvfs_setup) @@ -5411,7 +5387,7 @@ static int meson_g12a_probe(struct platform_device *p= dev) return 0; } =20 -static const struct meson_g12a_data g12a_clkc_data =3D { +static const struct g12a_clkc_data g12a_clkc_data =3D { .eeclkc_data =3D { .hw_clks =3D { .hws =3D g12a_hw_clks, @@ -5420,30 +5396,30 @@ static const struct meson_g12a_data g12a_clkc_data = =3D { .init_regs =3D g12a_init_regs, .init_count =3D ARRAY_SIZE(g12a_init_regs), }, - .dvfs_setup =3D meson_g12a_dvfs_setup, + .dvfs_setup =3D g12a_dvfs_setup, }; =20 -static const struct meson_g12a_data g12b_clkc_data =3D { +static const struct g12a_clkc_data g12b_clkc_data =3D { .eeclkc_data =3D { .hw_clks =3D { .hws =3D g12b_hw_clks, .num =3D ARRAY_SIZE(g12b_hw_clks), }, }, - .dvfs_setup =3D meson_g12b_dvfs_setup, + .dvfs_setup =3D g12b_dvfs_setup, }; =20 -static const struct meson_g12a_data sm1_clkc_data =3D { +static const struct g12a_clkc_data sm1_clkc_data =3D { .eeclkc_data =3D { .hw_clks =3D { .hws =3D sm1_hw_clks, .num =3D ARRAY_SIZE(sm1_hw_clks), }, }, - .dvfs_setup =3D meson_g12a_dvfs_setup, + .dvfs_setup =3D g12a_dvfs_setup, }; =20 -static const struct of_device_id clkc_match_table[] =3D { +static const struct of_device_id g12a_clkc_match_table[] =3D { { .compatible =3D "amlogic,g12a-clkc", .data =3D &g12a_clkc_data.eeclkc_data @@ -5458,16 +5434,16 @@ static const struct of_device_id clkc_match_table[]= =3D { }, {} }; -MODULE_DEVICE_TABLE(of, clkc_match_table); +MODULE_DEVICE_TABLE(of, g12a_clkc_match_table); =20 -static struct platform_driver g12a_driver =3D { - .probe =3D meson_g12a_probe, +static struct platform_driver g12a_clkc_driver =3D { + .probe =3D g12a_clkc_probe, .driver =3D { .name =3D "g12a-clkc", - .of_match_table =3D clkc_match_table, + .of_match_table =3D g12a_clkc_match_table, }, }; -module_platform_driver(g12a_driver); +module_platform_driver(g12a_clkc_driver); =20 MODULE_DESCRIPTION("Amlogic G12/SM1 Main Clock Controller driver"); MODULE_LICENSE("GPL"); --=20 2.47.2 From nobody Wed Oct 8 03:53:54 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher 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<20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9775; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=zCYXCSSXQjziG+h/5aIsAP+nLV6vpqnZUuUAtdeaR3M=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoZU++XefazoyZ/Qm0mWo5gHhVpfZQgxU3CWjPs sOcC3TCm+qJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaGVPvgAKCRDm/A8cN/La hUV4D/9SH6Ryl59OqhIOhiV3bYl47W+94El4y+cQsB9GojDP1aT53b7aI+mOfHFcm/Erjnp2PIw RfviCT+FB6dbxSXlVkGT23zNLtlepabH3z6vkCgREZ1qk2y3oy5SYEgiN2DugFEf72iOPKXoN3n 6aLcW4/UBmV4oQ7SJ8hcL4PQtpAY+OEnJLu5etoxKe2apmu7qi+VIQNxv09zsu3nbhJzHiIV8CD S4HtxpZ73+IYH1zysDPEz7wqeTqGPwvJzobmeQIOUn1RHLCkALRE3ZwPNlLNYLq4t2sFr928Wvq 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Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet --- drivers/clk/meson/gxbb-aoclk.c | 104 ++++++++++++++++++++-----------------= ---- 1 file changed, 52 insertions(+), 52 deletions(-) diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index f075fbd450f34bac9b2f9f969930337d3831a893..11b11fa7791eb1903938c0d3ee4= 6121a23b94a46 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c @@ -23,14 +23,14 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define GXBB_AO_GATE(_name, _bit) \ -static struct clk_regmap _name##_ao =3D { \ +#define GXBB_AO_PCLK(_name, _bit) \ +static struct clk_regmap gxbb_ao_##_name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D AO_RTI_GEN_CNTL_REG0, \ .bit_idx =3D (_bit), \ }, \ .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name "_ao", \ + .name =3D "gxbb_ao_" #_name, \ .ops =3D &clk_regmap_gate_ops, \ .parent_data =3D &(const struct clk_parent_data) { \ .fw_name =3D "mpeg-clk", \ @@ -40,14 +40,14 @@ static struct clk_regmap _name##_ao =3D { \ }, \ } =20 -GXBB_AO_GATE(remote, 0); -GXBB_AO_GATE(i2c_master, 1); -GXBB_AO_GATE(i2c_slave, 2); -GXBB_AO_GATE(uart1, 3); -GXBB_AO_GATE(uart2, 5); -GXBB_AO_GATE(ir_blaster, 6); +GXBB_AO_PCLK(remote, 0); +GXBB_AO_PCLK(i2c_master, 1); +GXBB_AO_PCLK(i2c_slave, 2); +GXBB_AO_PCLK(uart1, 3); +GXBB_AO_PCLK(uart2, 5); +GXBB_AO_PCLK(ir_blaster, 6); =20 -static struct clk_regmap ao_cts_oscin =3D { +static struct clk_regmap gxbb_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTI_PWR_CNTL_REG0, .bit_idx =3D 6, @@ -62,7 +62,7 @@ static struct clk_regmap ao_cts_oscin =3D { }, }; =20 -static struct clk_regmap ao_32k_pre =3D { +static struct clk_regmap gxbb_ao_32k_pre =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTC_ALT_CLK_CNTL0, .bit_idx =3D 31, @@ -70,7 +70,7 @@ static struct clk_regmap ao_32k_pre =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "ao_32k_pre", .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { &ao_cts_oscin.hw }, + .parent_hws =3D (const struct clk_hw *[]) { &gxbb_ao_cts_oscin.hw }, .num_parents =3D 1, }, }; @@ -85,7 +85,7 @@ static const struct meson_clk_dualdiv_param gxbb_32k_div_= table[] =3D { }, {} }; =20 -static struct clk_regmap ao_32k_div =3D { +static struct clk_regmap gxbb_ao_32k_div =3D { .data =3D &(struct meson_clk_dualdiv_data){ .n1 =3D { .reg_off =3D AO_RTC_ALT_CLK_CNTL0, @@ -117,12 +117,12 @@ static struct clk_regmap ao_32k_div =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "ao_32k_div", .ops =3D &meson_clk_dualdiv_ops, - .parent_hws =3D (const struct clk_hw *[]) { &ao_32k_pre.hw }, + .parent_hws =3D (const struct clk_hw *[]) { &gxbb_ao_32k_pre.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap ao_32k_sel =3D { +static struct clk_regmap gxbb_ao_32k_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTC_ALT_CLK_CNTL1, .mask =3D 0x1, @@ -133,15 +133,15 @@ static struct clk_regmap ao_32k_sel =3D { .name =3D "ao_32k_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &ao_32k_div.hw, - &ao_32k_pre.hw + &gxbb_ao_32k_div.hw, + &gxbb_ao_32k_pre.hw }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap ao_32k =3D { +static struct clk_regmap gxbb_ao_32k =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D AO_RTC_ALT_CLK_CNTL0, .bit_idx =3D 30, @@ -149,13 +149,13 @@ static struct clk_regmap ao_32k =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "ao_32k", .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { &ao_32k_sel.hw }, + .parent_hws =3D (const struct clk_hw *[]) { &gxbb_ao_32k_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap ao_cts_rtc_oscin =3D { +static struct clk_regmap gxbb_ao_cts_rtc_oscin =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTI_PWR_CNTL_REG0, .mask =3D 0x7, @@ -170,14 +170,14 @@ static struct clk_regmap ao_cts_rtc_oscin =3D { { .fw_name =3D "ext-32k-0", }, { .fw_name =3D "ext-32k-1", }, { .fw_name =3D "ext-32k-2", }, - { .hw =3D &ao_32k.hw }, + { .hw =3D &gxbb_ao_32k.hw }, }, .num_parents =3D 4, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap ao_clk81 =3D { +static struct clk_regmap gxbb_ao_clk81 =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_RTI_PWR_CNTL_REG0, .mask =3D 0x1, @@ -189,14 +189,14 @@ static struct clk_regmap ao_clk81 =3D { .ops =3D &clk_regmap_mux_ro_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "mpeg-clk", }, - { .hw =3D &ao_cts_rtc_oscin.hw }, + { .hw =3D &gxbb_ao_cts_rtc_oscin.hw }, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap ao_cts_cec =3D { +static struct clk_regmap gxbb_ao_cts_cec =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D AO_CRT_CLK_CNTL1, .mask =3D 0x1, @@ -221,14 +221,14 @@ static struct clk_regmap ao_cts_cec =3D { */ .parent_data =3D (const struct clk_parent_data []) { { .name =3D "fixme", .index =3D -1, }, - { .hw =3D &ao_cts_rtc_oscin.hw }, + { .hw =3D &gxbb_ao_cts_rtc_oscin.hw }, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static const unsigned int gxbb_aoclk_reset[] =3D { +static const unsigned int gxbb_ao_reset[] =3D { [RESET_AO_REMOTE] =3D 16, [RESET_AO_I2C_MASTER] =3D 18, [RESET_AO_I2C_SLAVE] =3D 19, @@ -237,50 +237,50 @@ static const unsigned int gxbb_aoclk_reset[] =3D { [RESET_AO_IR_BLASTER] =3D 23, }; =20 -static struct clk_hw *gxbb_aoclk_hw_clks[] =3D { - [CLKID_AO_REMOTE] =3D &remote_ao.hw, - [CLKID_AO_I2C_MASTER] =3D &i2c_master_ao.hw, - [CLKID_AO_I2C_SLAVE] =3D &i2c_slave_ao.hw, - [CLKID_AO_UART1] =3D &uart1_ao.hw, - [CLKID_AO_UART2] =3D &uart2_ao.hw, - [CLKID_AO_IR_BLASTER] =3D &ir_blaster_ao.hw, - [CLKID_AO_CEC_32K] =3D &ao_cts_cec.hw, - [CLKID_AO_CTS_OSCIN] =3D &ao_cts_oscin.hw, - [CLKID_AO_32K_PRE] =3D &ao_32k_pre.hw, - [CLKID_AO_32K_DIV] =3D &ao_32k_div.hw, - [CLKID_AO_32K_SEL] =3D &ao_32k_sel.hw, - [CLKID_AO_32K] =3D &ao_32k.hw, - [CLKID_AO_CTS_RTC_OSCIN] =3D &ao_cts_rtc_oscin.hw, - [CLKID_AO_CLK81] =3D &ao_clk81.hw, +static struct clk_hw *gxbb_ao_hw_clks[] =3D { + [CLKID_AO_REMOTE] =3D &gxbb_ao_remote.hw, + [CLKID_AO_I2C_MASTER] =3D &gxbb_ao_i2c_master.hw, + [CLKID_AO_I2C_SLAVE] =3D &gxbb_ao_i2c_slave.hw, + [CLKID_AO_UART1] =3D &gxbb_ao_uart1.hw, + [CLKID_AO_UART2] =3D &gxbb_ao_uart2.hw, + [CLKID_AO_IR_BLASTER] =3D &gxbb_ao_ir_blaster.hw, + [CLKID_AO_CEC_32K] =3D &gxbb_ao_cts_cec.hw, + [CLKID_AO_CTS_OSCIN] =3D &gxbb_ao_cts_oscin.hw, + [CLKID_AO_32K_PRE] =3D &gxbb_ao_32k_pre.hw, + [CLKID_AO_32K_DIV] =3D &gxbb_ao_32k_div.hw, + [CLKID_AO_32K_SEL] =3D &gxbb_ao_32k_sel.hw, + [CLKID_AO_32K] =3D &gxbb_ao_32k.hw, + [CLKID_AO_CTS_RTC_OSCIN] =3D &gxbb_ao_cts_rtc_oscin.hw, + [CLKID_AO_CLK81] =3D &gxbb_ao_clk81.hw, }; =20 -static const struct meson_aoclk_data gxbb_aoclkc_data =3D { +static const struct meson_aoclk_data gxbb_ao_clkc_data =3D { .reset_reg =3D AO_RTI_GEN_CNTL_REG0, - .num_reset =3D ARRAY_SIZE(gxbb_aoclk_reset), - .reset =3D gxbb_aoclk_reset, + .num_reset =3D ARRAY_SIZE(gxbb_ao_reset), + .reset =3D gxbb_ao_reset, .hw_clks =3D { - .hws =3D gxbb_aoclk_hw_clks, - .num =3D ARRAY_SIZE(gxbb_aoclk_hw_clks), + .hws =3D gxbb_ao_hw_clks, + .num =3D ARRAY_SIZE(gxbb_ao_hw_clks), }, }; =20 -static const struct of_device_id gxbb_aoclkc_match_table[] =3D { +static const struct of_device_id gxbb_ao_clkc_match_table[] =3D { { .compatible =3D "amlogic,meson-gx-aoclkc", - .data =3D &gxbb_aoclkc_data, + .data =3D &gxbb_ao_clkc_data, }, { } }; -MODULE_DEVICE_TABLE(of, gxbb_aoclkc_match_table); +MODULE_DEVICE_TABLE(of, gxbb_ao_clkc_match_table); =20 -static struct platform_driver gxbb_aoclkc_driver =3D { +static struct platform_driver gxbb_ao_clkc_driver =3D { .probe =3D meson_aoclkc_probe, .driver =3D { .name =3D "gxbb-aoclkc", - .of_match_table =3D gxbb_aoclkc_match_table, + .of_match_table =3D gxbb_ao_clkc_match_table, }, }; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet --- drivers/clk/meson/gxbb.c | 579 +++++++++++++++++++++++--------------------= ---- 1 file changed, 288 insertions(+), 291 deletions(-) diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 3b8731ec20168eaee01cc55cf805e24431afaffe..f969e3cf9566de5dff615d59360= 729d963507b36 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -116,70 +116,6 @@ #define HHI_BT656_CLK_CNTL 0x3d4 #define HHI_SAR_CLK_CNTL 0x3d8 =20 -static const struct pll_params_table gxbb_gp0_pll_params_table[] =3D { - PLL_PARAMS(32, 1), - PLL_PARAMS(33, 1), - PLL_PARAMS(34, 1), - PLL_PARAMS(35, 1), - PLL_PARAMS(36, 1), - PLL_PARAMS(37, 1), - PLL_PARAMS(38, 1), - PLL_PARAMS(39, 1), - PLL_PARAMS(40, 1), - PLL_PARAMS(41, 1), - PLL_PARAMS(42, 1), - PLL_PARAMS(43, 1), - PLL_PARAMS(44, 1), - PLL_PARAMS(45, 1), - PLL_PARAMS(46, 1), - PLL_PARAMS(47, 1), - PLL_PARAMS(48, 1), - PLL_PARAMS(49, 1), - PLL_PARAMS(50, 1), - PLL_PARAMS(51, 1), - PLL_PARAMS(52, 1), - PLL_PARAMS(53, 1), - PLL_PARAMS(54, 1), - PLL_PARAMS(55, 1), - PLL_PARAMS(56, 1), - PLL_PARAMS(57, 1), - PLL_PARAMS(58, 1), - PLL_PARAMS(59, 1), - PLL_PARAMS(60, 1), - PLL_PARAMS(61, 1), - PLL_PARAMS(62, 1), - { /* sentinel */ }, -}; - -static const struct pll_params_table gxl_gp0_pll_params_table[] =3D { - PLL_PARAMS(42, 1), - PLL_PARAMS(43, 1), - PLL_PARAMS(44, 1), - PLL_PARAMS(45, 1), - PLL_PARAMS(46, 1), - PLL_PARAMS(47, 1), - PLL_PARAMS(48, 1), - PLL_PARAMS(49, 1), - PLL_PARAMS(50, 1), - PLL_PARAMS(51, 1), - PLL_PARAMS(52, 1), - PLL_PARAMS(53, 1), - PLL_PARAMS(54, 1), - PLL_PARAMS(55, 1), - PLL_PARAMS(56, 1), - PLL_PARAMS(57, 1), - PLL_PARAMS(58, 1), - PLL_PARAMS(59, 1), - PLL_PARAMS(60, 1), - PLL_PARAMS(61, 1), - PLL_PARAMS(62, 1), - PLL_PARAMS(63, 1), - PLL_PARAMS(64, 1), - PLL_PARAMS(65, 1), - PLL_PARAMS(66, 1), - { /* sentinel */ }, -}; - static struct clk_regmap gxbb_fixed_pll_dco =3D { .data =3D &(struct meson_clk_pll_data){ .en =3D { @@ -523,7 +459,42 @@ static struct clk_regmap gxbb_sys_pll =3D { }, }; =20 -static const struct reg_sequence gxbb_gp0_init_regs[] =3D { +static const struct pll_params_table gxbb_gp0_pll_params_table[] =3D { + PLL_PARAMS(32, 1), + PLL_PARAMS(33, 1), + PLL_PARAMS(34, 1), + PLL_PARAMS(35, 1), + PLL_PARAMS(36, 1), + PLL_PARAMS(37, 1), + PLL_PARAMS(38, 1), + PLL_PARAMS(39, 1), + PLL_PARAMS(40, 1), + PLL_PARAMS(41, 1), + PLL_PARAMS(42, 1), + PLL_PARAMS(43, 1), + PLL_PARAMS(44, 1), + PLL_PARAMS(45, 1), + PLL_PARAMS(46, 1), + PLL_PARAMS(47, 1), + PLL_PARAMS(48, 1), + PLL_PARAMS(49, 1), + PLL_PARAMS(50, 1), + PLL_PARAMS(51, 1), + PLL_PARAMS(52, 1), + PLL_PARAMS(53, 1), + PLL_PARAMS(54, 1), + PLL_PARAMS(55, 1), + PLL_PARAMS(56, 1), + PLL_PARAMS(57, 1), + PLL_PARAMS(58, 1), + PLL_PARAMS(59, 1), + PLL_PARAMS(60, 1), + PLL_PARAMS(61, 1), + PLL_PARAMS(62, 1), + { /* sentinel */ }, +}; + +static const struct reg_sequence gxbb_gp0_pll_init_regs[] =3D { { .reg =3D HHI_GP0_PLL_CNTL2, .def =3D 0x69c80000 }, { .reg =3D HHI_GP0_PLL_CNTL3, .def =3D 0x0a5590c4 }, { .reg =3D HHI_GP0_PLL_CNTL4, .def =3D 0x0000500d }, @@ -557,8 +528,8 @@ static struct clk_regmap gxbb_gp0_pll_dco =3D { .width =3D 1, }, .table =3D gxbb_gp0_pll_params_table, - .init_regs =3D gxbb_gp0_init_regs, - .init_count =3D ARRAY_SIZE(gxbb_gp0_init_regs), + .init_regs =3D gxbb_gp0_pll_init_regs, + .init_count =3D ARRAY_SIZE(gxbb_gp0_pll_init_regs), }, .hw.init =3D &(struct clk_init_data){ .name =3D "gp0_pll_dco", @@ -570,7 +541,36 @@ static struct clk_regmap gxbb_gp0_pll_dco =3D { }, }; =20 -static const struct reg_sequence gxl_gp0_init_regs[] =3D { +static const struct pll_params_table gxl_gp0_pll_params_table[] =3D { + PLL_PARAMS(42, 1), + PLL_PARAMS(43, 1), + PLL_PARAMS(44, 1), + PLL_PARAMS(45, 1), + PLL_PARAMS(46, 1), + PLL_PARAMS(47, 1), + PLL_PARAMS(48, 1), + PLL_PARAMS(49, 1), + PLL_PARAMS(50, 1), + PLL_PARAMS(51, 1), + PLL_PARAMS(52, 1), + PLL_PARAMS(53, 1), + PLL_PARAMS(54, 1), + PLL_PARAMS(55, 1), + PLL_PARAMS(56, 1), + PLL_PARAMS(57, 1), + PLL_PARAMS(58, 1), + PLL_PARAMS(59, 1), + PLL_PARAMS(60, 1), + PLL_PARAMS(61, 1), + PLL_PARAMS(62, 1), + PLL_PARAMS(63, 1), + PLL_PARAMS(64, 1), + PLL_PARAMS(65, 1), + PLL_PARAMS(66, 1), + { /* sentinel */ }, +}; + +static const struct reg_sequence gxl_gp0_pll_init_regs[] =3D { { .reg =3D HHI_GP0_PLL_CNTL1, .def =3D 0xc084b000 }, { .reg =3D HHI_GP0_PLL_CNTL2, .def =3D 0xb75020be }, { .reg =3D HHI_GP0_PLL_CNTL3, .def =3D 0x0a59a288 }, @@ -611,8 +611,8 @@ static struct clk_regmap gxl_gp0_pll_dco =3D { .width =3D 1, }, .table =3D gxl_gp0_pll_params_table, - .init_regs =3D gxl_gp0_init_regs, - .init_count =3D ARRAY_SIZE(gxl_gp0_init_regs), + .init_regs =3D gxl_gp0_pll_init_regs, + .init_count =3D ARRAY_SIZE(gxl_gp0_pll_init_regs), }, .hw.init =3D &(struct clk_init_data){ .name =3D "gp0_pll_dco", @@ -972,8 +972,9 @@ static struct clk_regmap gxbb_mpll2 =3D { }, }; =20 -static u32 mux_table_clk81[] =3D { 0, 2, 3, 4, 5, 6, 7 }; -static const struct clk_parent_data clk81_parent_data[] =3D { +/* clk81 is often referred as "mpeg_clk" */ +static u32 clk81_parents_val_table[] =3D { 0, 2, 3, 4, 5, 6, 7 }; +static const struct clk_parent_data clk81_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &gxbb_fclk_div7.hw }, { .hw =3D &gxbb_mpll1.hw }, @@ -983,37 +984,37 @@ static const struct clk_parent_data clk81_parent_data= [] =3D { { .hw =3D &gxbb_fclk_div5.hw }, }; =20 -static struct clk_regmap gxbb_mpeg_clk_sel =3D { +static struct clk_regmap gxbb_clk81_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_MPEG_CLK_CNTL, .mask =3D 0x7, .shift =3D 12, - .table =3D mux_table_clk81, + .table =3D clk81_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "mpeg_clk_sel", + .name =3D "clk81_sel", .ops =3D &clk_regmap_mux_ro_ops, /* * bits 14:12 selects from 8 possible parents: * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, * fclk_div4, fclk_div3, fclk_div5 */ - .parent_data =3D clk81_parent_data, - .num_parents =3D ARRAY_SIZE(clk81_parent_data), + .parent_data =3D clk81_parents, + .num_parents =3D ARRAY_SIZE(clk81_parents), }, }; =20 -static struct clk_regmap gxbb_mpeg_clk_div =3D { +static struct clk_regmap gxbb_clk81_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D HHI_MPEG_CLK_CNTL, .shift =3D 0, .width =3D 7, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "mpeg_clk_div", + .name =3D "clk81_div", .ops =3D &clk_regmap_divider_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &gxbb_mpeg_clk_sel.hw + &gxbb_clk81_sel.hw }, .num_parents =3D 1, }, @@ -1029,7 +1030,7 @@ static struct clk_regmap gxbb_clk81 =3D { .name =3D "clk81", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &gxbb_mpeg_clk_div.hw + &gxbb_clk81_div.hw }, .num_parents =3D 1, .flags =3D CLK_IS_CRITICAL, @@ -1094,7 +1095,7 @@ static struct clk_regmap gxbb_sar_adc_clk =3D { * switches to the "inactive" one when CLK_SET_RATE_GATE is set. */ =20 -static const struct clk_parent_data gxbb_mali_0_1_parent_data[] =3D { +static const struct clk_parent_data gxbb_mali_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &gxbb_gp0_pll.hw }, { .hw =3D &gxbb_mpll2.hw }, @@ -1114,8 +1115,8 @@ static struct clk_regmap gxbb_mali_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "mali_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D gxbb_mali_0_1_parent_data, - .num_parents =3D 8, + .parent_data =3D gxbb_mali_parents, + .num_parents =3D ARRAY_SIZE(gxbb_mali_parents), /* * Don't request the parent to change the rate because * all GPU frequencies can be derived from the fclk_* @@ -1168,8 +1169,8 @@ static struct clk_regmap gxbb_mali_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "mali_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D gxbb_mali_0_1_parent_data, - .num_parents =3D 8, + .parent_data =3D gxbb_mali_parents, + .num_parents =3D ARRAY_SIZE(gxbb_mali_parents), /* * Don't request the parent to change the rate because * all GPU frequencies can be derived from the fclk_* @@ -1213,11 +1214,6 @@ static struct clk_regmap gxbb_mali_1 =3D { }, }; =20 -static const struct clk_hw *gxbb_mali_parent_hws[] =3D { - &gxbb_mali_0.hw, - &gxbb_mali_1.hw, -}; - static struct clk_regmap gxbb_mali =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_MALI_CLK_CNTL, @@ -1227,29 +1223,35 @@ static struct clk_regmap gxbb_mali =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "mali", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D gxbb_mali_parent_hws, + .parent_hws =3D (const struct clk_hw *[]) { + &gxbb_mali_0.hw, + &gxbb_mali_1.hw, + }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 +static u32 gxbb_cts_mclk_parents_val_table[] =3D { 1, 2, 3 }; +static const struct clk_hw *gxbb_cts_mclk_parents[] =3D { + &gxbb_mpll0.hw, + &gxbb_mpll1.hw, + &gxbb_mpll2.hw, +}; + static struct clk_regmap gxbb_cts_amclk_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_AUD_CLK_CNTL, .mask =3D 0x3, .shift =3D 9, - .table =3D (u32[]){ 1, 2, 3 }, + .table =3D gxbb_cts_mclk_parents_val_table, .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_amclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &gxbb_mpll0.hw, - &gxbb_mpll1.hw, - &gxbb_mpll2.hw, - }, - .num_parents =3D 3, + .parent_hws =3D gxbb_cts_mclk_parents, + .num_parents =3D ARRAY_SIZE(gxbb_cts_mclk_parents), }, }; =20 @@ -1292,18 +1294,14 @@ static struct clk_regmap gxbb_cts_mclk_i958_sel =3D= { .offset =3D HHI_AUD_CLK_CNTL2, .mask =3D 0x3, .shift =3D 25, - .table =3D (u32[]){ 1, 2, 3 }, + .table =3D gxbb_cts_mclk_parents_val_table, .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data) { .name =3D "cts_mclk_i958_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &gxbb_mpll0.hw, - &gxbb_mpll1.hw, - &gxbb_mpll2.hw, - }, - .num_parents =3D 3, + .parent_hws =3D gxbb_cts_mclk_parents, + .num_parents =3D ARRAY_SIZE(gxbb_cts_mclk_parents), }, }; =20 @@ -1368,7 +1366,7 @@ static struct clk_regmap gxbb_cts_i958 =3D { * This clock does not exist yet in this controller or the AO one */ static u32 gxbb_32k_clk_parents_val_table[] =3D { 0, 2, 3 }; -static const struct clk_parent_data gxbb_32k_clk_parent_data[] =3D { +static const struct clk_parent_data gxbb_32k_clk_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &gxbb_fclk_div3.hw }, { .hw =3D &gxbb_fclk_div5.hw }, @@ -1380,11 +1378,11 @@ static struct clk_regmap gxbb_32k_clk_sel =3D { .mask =3D 0x3, .shift =3D 16, .table =3D gxbb_32k_clk_parents_val_table, - }, + }, .hw.init =3D &(struct clk_init_data){ .name =3D "32k_clk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D gxbb_32k_clk_parent_data, + .parent_data =3D gxbb_32k_clk_parents, .num_parents =3D 4, .flags =3D CLK_SET_RATE_PARENT, }, @@ -1423,7 +1421,7 @@ static struct clk_regmap gxbb_32k_clk =3D { }, }; =20 -static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] =3D { +static const struct clk_parent_data gxbb_sd_emmc_clk0_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &gxbb_fclk_div2.hw }, { .hw =3D &gxbb_fclk_div3.hw }, @@ -1447,8 +1445,8 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_a_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D gxbb_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), + .parent_data =3D gxbb_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(gxbb_sd_emmc_clk0_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1497,8 +1495,8 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_b_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D gxbb_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), + .parent_data =3D gxbb_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(gxbb_sd_emmc_clk0_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1547,8 +1545,8 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_c_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D gxbb_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), + .parent_data =3D gxbb_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(gxbb_sd_emmc_clk0_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1589,7 +1587,7 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0 =3D { =20 /* VPU Clock */ =20 -static const struct clk_hw *gxbb_vpu_parent_hws[] =3D { +static const struct clk_hw *gxbb_vpu_parents[] =3D { &gxbb_fclk_div4.hw, &gxbb_fclk_div3.hw, &gxbb_fclk_div5.hw, @@ -1609,8 +1607,8 @@ static struct clk_regmap gxbb_vpu_0_sel =3D { * bits 9:10 selects from 4 possible parents: * fclk_div4, fclk_div3, fclk_div5, fclk_div7, */ - .parent_hws =3D gxbb_vpu_parent_hws, - .num_parents =3D ARRAY_SIZE(gxbb_vpu_parent_hws), + .parent_hws =3D gxbb_vpu_parents, + .num_parents =3D ARRAY_SIZE(gxbb_vpu_parents), .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; @@ -1657,8 +1655,8 @@ static struct clk_regmap gxbb_vpu_1_sel =3D { * bits 25:26 selects from 4 possible parents: * fclk_div4, fclk_div3, fclk_div5, fclk_div7, */ - .parent_hws =3D gxbb_vpu_parent_hws, - .num_parents =3D ARRAY_SIZE(gxbb_vpu_parent_hws), + .parent_hws =3D gxbb_vpu_parents, + .num_parents =3D ARRAY_SIZE(gxbb_vpu_parents), .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; @@ -1716,7 +1714,7 @@ static struct clk_regmap gxbb_vpu =3D { =20 /* VAPB Clock */ =20 -static const struct clk_hw *gxbb_vapb_parent_hws[] =3D { +static const struct clk_hw *gxbb_vapb_parents[] =3D { &gxbb_fclk_div4.hw, &gxbb_fclk_div3.hw, &gxbb_fclk_div5.hw, @@ -1736,8 +1734,8 @@ static struct clk_regmap gxbb_vapb_0_sel =3D { * bits 9:10 selects from 4 possible parents: * fclk_div4, fclk_div3, fclk_div5, fclk_div7, */ - .parent_hws =3D gxbb_vapb_parent_hws, - .num_parents =3D ARRAY_SIZE(gxbb_vapb_parent_hws), + .parent_hws =3D gxbb_vapb_parents, + .num_parents =3D ARRAY_SIZE(gxbb_vapb_parents), .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; @@ -1788,8 +1786,8 @@ static struct clk_regmap gxbb_vapb_1_sel =3D { * bits 25:26 selects from 4 possible parents: * fclk_div4, fclk_div3, fclk_div5, fclk_div7, */ - .parent_hws =3D gxbb_vapb_parent_hws, - .num_parents =3D ARRAY_SIZE(gxbb_vapb_parent_hws), + .parent_hws =3D gxbb_vapb_parents, + .num_parents =3D ARRAY_SIZE(gxbb_vapb_parents), .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; @@ -1897,7 +1895,7 @@ static struct clk_regmap gxbb_vid_pll_div =3D { }, }; =20 -static const struct clk_parent_data gxbb_vid_pll_parent_data[] =3D { +static const struct clk_parent_data gxbb_vid_pll_parents[] =3D { { .hw =3D &gxbb_vid_pll_div.hw }, /* * Note: @@ -1922,8 +1920,8 @@ static struct clk_regmap gxbb_vid_pll_sel =3D { * bit 18 selects from 2 possible parents: * vid_pll_div or hdmi_pll */ - .parent_data =3D gxbb_vid_pll_parent_data, - .num_parents =3D ARRAY_SIZE(gxbb_vid_pll_parent_data), + .parent_data =3D gxbb_vid_pll_parents, + .num_parents =3D ARRAY_SIZE(gxbb_vid_pll_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -1944,7 +1942,7 @@ static struct clk_regmap gxbb_vid_pll =3D { }, }; =20 -static const struct clk_hw *gxbb_vclk_parent_hws[] =3D { +static const struct clk_hw *gxbb_vclk_parents[] =3D { &gxbb_vid_pll.hw, &gxbb_fclk_div4.hw, &gxbb_fclk_div3.hw, @@ -1968,8 +1966,8 @@ static struct clk_regmap gxbb_vclk_sel =3D { * vid_pll, fclk_div4, fclk_div3, fclk_div5, * vid_pll, fclk_div7, mp1 */ - .parent_hws =3D gxbb_vclk_parent_hws, - .num_parents =3D ARRAY_SIZE(gxbb_vclk_parent_hws), + .parent_hws =3D gxbb_vclk_parents, + .num_parents =3D ARRAY_SIZE(gxbb_vclk_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -1988,8 +1986,8 @@ static struct clk_regmap gxbb_vclk2_sel =3D { * vid_pll, fclk_div4, fclk_div3, fclk_div5, * vid_pll, fclk_div7, mp1 */ - .parent_hws =3D gxbb_vclk_parent_hws, - .num_parents =3D ARRAY_SIZE(gxbb_vclk_parent_hws), + .parent_hws =3D gxbb_vclk_parents, + .num_parents =3D ARRAY_SIZE(gxbb_vclk_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -2328,8 +2326,8 @@ static struct clk_fixed_factor gxbb_vclk2_div12 =3D { }, }; =20 -static u32 mux_table_cts_sel[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; -static const struct clk_hw *gxbb_cts_parent_hws[] =3D { +static u32 gxbb_cts_parents_val_table[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11,= 12 }; +static const struct clk_hw *gxbb_cts_parents[] =3D { &gxbb_vclk_div1.hw, &gxbb_vclk_div2.hw, &gxbb_vclk_div4.hw, @@ -2347,13 +2345,13 @@ static struct clk_regmap gxbb_cts_enci_sel =3D { .offset =3D HHI_VID_CLK_DIV, .mask =3D 0xf, .shift =3D 28, - .table =3D mux_table_cts_sel, + .table =3D gxbb_cts_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_enci_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D gxbb_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(gxbb_cts_parent_hws), + .parent_hws =3D gxbb_cts_parents, + .num_parents =3D ARRAY_SIZE(gxbb_cts_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -2363,13 +2361,13 @@ static struct clk_regmap gxbb_cts_encp_sel =3D { .offset =3D HHI_VID_CLK_DIV, .mask =3D 0xf, .shift =3D 20, - .table =3D mux_table_cts_sel, + .table =3D gxbb_cts_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_encp_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D gxbb_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(gxbb_cts_parent_hws), + .parent_hws =3D gxbb_cts_parents, + .num_parents =3D ARRAY_SIZE(gxbb_cts_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -2379,50 +2377,13 @@ static struct clk_regmap gxbb_cts_vdac_sel =3D { .offset =3D HHI_VIID_CLK_DIV, .mask =3D 0xf, .shift =3D 28, - .table =3D mux_table_cts_sel, + .table =3D gxbb_cts_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_vdac_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D gxbb_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(gxbb_cts_parent_hws), - .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, - }, -}; - -/* TOFIX: add support for cts_tcon */ -static u32 mux_table_hdmi_tx_sel[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; -static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] =3D { - &gxbb_vclk_div1.hw, - &gxbb_vclk_div2.hw, - &gxbb_vclk_div4.hw, - &gxbb_vclk_div6.hw, - &gxbb_vclk_div12.hw, - &gxbb_vclk2_div1.hw, - &gxbb_vclk2_div2.hw, - &gxbb_vclk2_div4.hw, - &gxbb_vclk2_div6.hw, - &gxbb_vclk2_div12.hw, -}; - -static struct clk_regmap gxbb_hdmi_tx_sel =3D { - .data =3D &(struct clk_regmap_mux_data){ - .offset =3D HHI_HDMI_CLK_CNTL, - .mask =3D 0xf, - .shift =3D 16, - .table =3D mux_table_hdmi_tx_sel, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "hdmi_tx_sel", - .ops =3D &clk_regmap_mux_ops, - /* - * bits 31:28 selects from 12 possible parents: - * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12 - * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12, - * cts_tcon - */ - .parent_hws =3D gxbb_cts_hdmi_tx_parent_hws, - .num_parents =3D ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws), + .parent_hws =3D gxbb_cts_parents, + .num_parents =3D ARRAY_SIZE(gxbb_cts_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -2475,6 +2436,43 @@ static struct clk_regmap gxbb_cts_vdac =3D { }, }; =20 +/* TOFIX: add support for cts_tcon */ +static u32 gxbb_hdmi_tx_parents_val_table[] =3D { 0, 1, 2, 3, 4, 8, 9, 10,= 11, 12 }; +static const struct clk_hw *gxbb_hdmi_tx_parents[] =3D { + &gxbb_vclk_div1.hw, + &gxbb_vclk_div2.hw, + &gxbb_vclk_div4.hw, + &gxbb_vclk_div6.hw, + &gxbb_vclk_div12.hw, + &gxbb_vclk2_div1.hw, + &gxbb_vclk2_div2.hw, + &gxbb_vclk2_div4.hw, + &gxbb_vclk2_div6.hw, + &gxbb_vclk2_div12.hw, +}; + +static struct clk_regmap gxbb_hdmi_tx_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_HDMI_CLK_CNTL, + .mask =3D 0xf, + .shift =3D 16, + .table =3D gxbb_hdmi_tx_parents_val_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "hdmi_tx_sel", + .ops =3D &clk_regmap_mux_ops, + /* + * bits 31:28 selects from 12 possible parents: + * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12 + * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12, + * cts_tcon + */ + .parent_hws =3D gxbb_hdmi_tx_parents, + .num_parents =3D ARRAY_SIZE(gxbb_hdmi_tx_parents), + .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, + }, +}; + static struct clk_regmap gxbb_hdmi_tx =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VID_CLK_CNTL2, @@ -2493,7 +2491,7 @@ static struct clk_regmap gxbb_hdmi_tx =3D { =20 /* HDMI Clocks */ =20 -static const struct clk_parent_data gxbb_hdmi_parent_data[] =3D { +static const struct clk_parent_data gxbb_hdmi_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &gxbb_fclk_div4.hw }, { .hw =3D &gxbb_fclk_div3.hw }, @@ -2510,8 +2508,8 @@ static struct clk_regmap gxbb_hdmi_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "hdmi_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D gxbb_hdmi_parent_data, - .num_parents =3D ARRAY_SIZE(gxbb_hdmi_parent_data), + .parent_data =3D gxbb_hdmi_parents, + .num_parents =3D ARRAY_SIZE(gxbb_hdmi_parents), .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -2547,7 +2545,7 @@ static struct clk_regmap gxbb_hdmi =3D { =20 /* VDEC clocks */ =20 -static const struct clk_hw *gxbb_vdec_parent_hws[] =3D { +static const struct clk_hw *gxbb_vdec_parents[] =3D { &gxbb_fclk_div4.hw, &gxbb_fclk_div3.hw, &gxbb_fclk_div5.hw, @@ -2564,8 +2562,8 @@ static struct clk_regmap gxbb_vdec_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vdec_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D gxbb_vdec_parent_hws, - .num_parents =3D ARRAY_SIZE(gxbb_vdec_parent_hws), + .parent_hws =3D gxbb_vdec_parents, + .num_parents =3D ARRAY_SIZE(gxbb_vdec_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2614,8 +2612,8 @@ static struct clk_regmap gxbb_vdec_hevc_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vdec_hevc_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D gxbb_vdec_parent_hws, - .num_parents =3D ARRAY_SIZE(gxbb_vdec_parent_hws), + .parent_hws =3D gxbb_vdec_parents, + .num_parents =3D ARRAY_SIZE(gxbb_vdec_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2654,9 +2652,8 @@ static struct clk_regmap gxbb_vdec_hevc =3D { }, }; =20 -static u32 mux_table_gen_clk[] =3D { 0, 4, 5, 6, 7, 8, - 9, 10, 11, 13, 14, }; -static const struct clk_parent_data gen_clk_parent_data[] =3D { +static u32 gxbb_gen_clk_parents_val_table[] =3D { 0, 4, 5, 6, 7, 8, 9, 10,= 11, 13, 14, }; +static const struct clk_parent_data gxbb_gen_clk_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &gxbb_vdec_1.hw }, { .hw =3D &gxbb_vdec_hevc.hw }, @@ -2675,7 +2672,7 @@ static struct clk_regmap gxbb_gen_clk_sel =3D { .offset =3D HHI_GEN_CLK_CNTL, .mask =3D 0xf, .shift =3D 12, - .table =3D mux_table_gen_clk, + .table =3D gxbb_gen_clk_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "gen_clk_sel", @@ -2686,8 +2683,8 @@ static struct clk_regmap gxbb_gen_clk_sel =3D { * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4, * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll */ - .parent_data =3D gen_clk_parent_data, - .num_parents =3D ARRAY_SIZE(gen_clk_parent_data), + .parent_data =3D gxbb_gen_clk_parents, + .num_parents =3D ARRAY_SIZE(gxbb_gen_clk_parents), }, }; =20 @@ -2724,100 +2721,100 @@ static struct clk_regmap gxbb_gen_clk =3D { }, }; =20 -#define MESON_GATE(_name, _reg, _bit) \ +#define GXBB_PCLK(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw) =20 /* Everything Else (EE) domain gates */ -static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); -static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); -static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5); -static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); -static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); -static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); -static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); -static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10); -static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); -static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); -static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); -static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14); -static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15); -static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); -static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); -static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); -static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); -static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); -static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); -static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); -static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); -static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28); -static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30); - -static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); -static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3); -static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4); -static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14); -static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15); -static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16); -static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20); -static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21); -static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22); -static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23); -static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24); -static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); -static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26); -static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28); -static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); -static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30); -static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); - -static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); -static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); -static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); -static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); -static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); -static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); -static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); -static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); -static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); -static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); -static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); -static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); - -static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); -static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); -static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); -static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); -static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); -static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); -static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10); -static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); -static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); -static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20); -static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21); -static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); -static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); -static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); -static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26); -static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31); +static GXBB_PCLK(gxbb_ddr, HHI_GCLK_MPEG0, 0); +static GXBB_PCLK(gxbb_dos, HHI_GCLK_MPEG0, 1); +static GXBB_PCLK(gxbb_isa, HHI_GCLK_MPEG0, 5); +static GXBB_PCLK(gxbb_pl301, HHI_GCLK_MPEG0, 6); +static GXBB_PCLK(gxbb_periphs, HHI_GCLK_MPEG0, 7); +static GXBB_PCLK(gxbb_spicc, HHI_GCLK_MPEG0, 8); +static GXBB_PCLK(gxbb_i2c, HHI_GCLK_MPEG0, 9); +static GXBB_PCLK(gxbb_sana, HHI_GCLK_MPEG0, 10); +static GXBB_PCLK(gxbb_smart_card, HHI_GCLK_MPEG0, 11); +static GXBB_PCLK(gxbb_rng0, HHI_GCLK_MPEG0, 12); +static GXBB_PCLK(gxbb_uart0, HHI_GCLK_MPEG0, 13); +static GXBB_PCLK(gxbb_sdhc, HHI_GCLK_MPEG0, 14); +static GXBB_PCLK(gxbb_stream, HHI_GCLK_MPEG0, 15); +static GXBB_PCLK(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); +static GXBB_PCLK(gxbb_sdio, HHI_GCLK_MPEG0, 17); +static GXBB_PCLK(gxbb_abuf, HHI_GCLK_MPEG0, 18); +static GXBB_PCLK(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); +static GXBB_PCLK(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); +static GXBB_PCLK(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); +static GXBB_PCLK(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); +static GXBB_PCLK(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); +static GXBB_PCLK(gxl_acodec, HHI_GCLK_MPEG0, 28); +static GXBB_PCLK(gxbb_spi, HHI_GCLK_MPEG0, 30); + +static GXBB_PCLK(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); +static GXBB_PCLK(gxbb_eth, HHI_GCLK_MPEG1, 3); +static GXBB_PCLK(gxbb_demux, HHI_GCLK_MPEG1, 4); +static GXBB_PCLK(gxbb_blkmv, HHI_GCLK_MPEG1, 14); +static GXBB_PCLK(gxbb_aiu, HHI_GCLK_MPEG1, 15); +static GXBB_PCLK(gxbb_uart1, HHI_GCLK_MPEG1, 16); +static GXBB_PCLK(gxbb_g2d, HHI_GCLK_MPEG1, 20); +static GXBB_PCLK(gxbb_usb0, HHI_GCLK_MPEG1, 21); +static GXBB_PCLK(gxbb_usb1, HHI_GCLK_MPEG1, 22); +static GXBB_PCLK(gxbb_reset, HHI_GCLK_MPEG1, 23); +static GXBB_PCLK(gxbb_nand, HHI_GCLK_MPEG1, 24); +static GXBB_PCLK(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); +static GXBB_PCLK(gxbb_usb, HHI_GCLK_MPEG1, 26); +static GXBB_PCLK(gxbb_vdin1, HHI_GCLK_MPEG1, 28); +static GXBB_PCLK(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); +static GXBB_PCLK(gxbb_efuse, HHI_GCLK_MPEG1, 30); +static GXBB_PCLK(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); + +static GXBB_PCLK(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); +static GXBB_PCLK(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); +static GXBB_PCLK(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); +static GXBB_PCLK(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); +static GXBB_PCLK(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); +static GXBB_PCLK(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); +static GXBB_PCLK(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); +static GXBB_PCLK(gxbb_dvin, HHI_GCLK_MPEG2, 12); +static GXBB_PCLK(gxbb_uart2, HHI_GCLK_MPEG2, 15); +static GXBB_PCLK(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); +static GXBB_PCLK(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); +static GXBB_PCLK(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); +static GXBB_PCLK(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); + +static GXBB_PCLK(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); +static GXBB_PCLK(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); +static GXBB_PCLK(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); +static GXBB_PCLK(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); +static GXBB_PCLK(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); +static GXBB_PCLK(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); +static GXBB_PCLK(gxbb_dac_clk, HHI_GCLK_OTHER, 10); +static GXBB_PCLK(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); +static GXBB_PCLK(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); +static GXBB_PCLK(gxbb_enc480p, HHI_GCLK_OTHER, 20); +static GXBB_PCLK(gxbb_rng1, HHI_GCLK_OTHER, 21); +static GXBB_PCLK(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); +static GXBB_PCLK(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); +static GXBB_PCLK(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); +static GXBB_PCLK(gxbb_vclk_other, HHI_GCLK_OTHER, 26); +static GXBB_PCLK(gxbb_edp, HHI_GCLK_OTHER, 31); =20 /* Always On (AO) domain gates */ =20 -static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); -static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); -static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); -static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3); -static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); +static GXBB_PCLK(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); +static GXBB_PCLK(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); +static GXBB_PCLK(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); +static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3); +static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4); =20 /* AIU gates */ -static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw); -static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw); +static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw); +static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw); +static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw); +static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw); +static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw); +static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw); +static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw); +static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw); =20 /* Array of all clocks provided by this provider */ =20 @@ -2831,8 +2828,8 @@ static struct clk_hw *gxbb_hw_clks[] =3D { [CLKID_FCLK_DIV5] =3D &gxbb_fclk_div5.hw, [CLKID_FCLK_DIV7] =3D &gxbb_fclk_div7.hw, [CLKID_GP0_PLL] =3D &gxbb_gp0_pll.hw, - [CLKID_MPEG_SEL] =3D &gxbb_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &gxbb_mpeg_clk_div.hw, + [CLKID_MPEG_SEL] =3D &gxbb_clk81_sel.hw, + [CLKID_MPEG_DIV] =3D &gxbb_clk81_div.hw, [CLKID_CLK81] =3D &gxbb_clk81.hw, [CLKID_MPLL0] =3D &gxbb_mpll0.hw, [CLKID_MPLL1] =3D &gxbb_mpll1.hw, @@ -3039,8 +3036,8 @@ static struct clk_hw *gxl_hw_clks[] =3D { [CLKID_FCLK_DIV5] =3D &gxbb_fclk_div5.hw, [CLKID_FCLK_DIV7] =3D &gxbb_fclk_div7.hw, [CLKID_GP0_PLL] =3D &gxbb_gp0_pll.hw, - [CLKID_MPEG_SEL] =3D &gxbb_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &gxbb_mpeg_clk_div.hw, + [CLKID_MPEG_SEL] =3D &gxbb_clk81_sel.hw, + [CLKID_MPEG_DIV] =3D &gxbb_clk81_div.hw, [CLKID_CLK81] =3D &gxbb_clk81.hw, [CLKID_MPLL0] =3D &gxbb_mpll0.hw, [CLKID_MPLL1] =3D &gxbb_mpll1.hw, @@ -3251,21 +3248,21 @@ static const struct meson_eeclkc_data gxl_clkc_data= =3D { }, }; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson8b.c | 720 +++++++++++++++++++++-------------------= ---- 1 file changed, 340 insertions(+), 380 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 2065383266145b76f86e7f945cbf552a24ae881e..446e57d45d8deeab9516a923ddd= dcba7fa274203 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -214,7 +214,7 @@ static const struct reg_sequence meson8b_hdmi_pll_init_= regs[] =3D { { .reg =3D HHI_VID2_PLL_CNTL2, .def =3D 0x0430a800 }, }; =20 -static const struct pll_params_table hdmi_pll_params_table[] =3D { +static const struct pll_params_table meson8b_hdmi_pll_params_table[] =3D { PLL_PARAMS(40, 1), PLL_PARAMS(42, 1), PLL_PARAMS(44, 1), @@ -267,7 +267,7 @@ static struct clk_regmap meson8b_hdmi_pll_dco =3D { .shift =3D 29, .width =3D 1, }, - .table =3D hdmi_pll_params_table, + .table =3D meson8b_hdmi_pll_params_table, .init_regs =3D meson8b_hdmi_pll_init_regs, .init_count =3D ARRAY_SIZE(meson8b_hdmi_pll_init_regs), }, @@ -670,16 +670,17 @@ static struct clk_regmap meson8b_mpll2 =3D { }, }; =20 -static u32 mux_table_clk81[] =3D { 6, 5, 7 }; -static struct clk_regmap meson8b_mpeg_clk_sel =3D { +/* clk81 is often referred as "mpeg_clk" */ +static u32 meson8b_clk81_parents_val_table[] =3D { 6, 5, 7 }; +static struct clk_regmap meson8b_clk81_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_MPEG_CLK_CNTL, .mask =3D 0x7, .shift =3D 12, - .table =3D mux_table_clk81, + .table =3D meson8b_clk81_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "mpeg_clk_sel", + .name =3D "clk81_sel", .ops =3D &clk_regmap_mux_ro_ops, /* * FIXME bits 14:12 selects from 8 possible parents: @@ -695,17 +696,17 @@ static struct clk_regmap meson8b_mpeg_clk_sel =3D { }, }; =20 -static struct clk_regmap meson8b_mpeg_clk_div =3D { +static struct clk_regmap meson8b_clk81_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D HHI_MPEG_CLK_CNTL, .shift =3D 0, .width =3D 7, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "mpeg_clk_div", + .name =3D "clk81_div", .ops =3D &clk_regmap_divider_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_mpeg_clk_sel.hw + &meson8b_clk81_sel.hw }, .num_parents =3D 1, }, @@ -720,7 +721,7 @@ static struct clk_regmap meson8b_clk81 =3D { .name =3D "clk81", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_mpeg_clk_div.hw + &meson8b_clk81_div.hw }, .num_parents =3D 1, .flags =3D CLK_IS_CRITICAL, @@ -774,7 +775,7 @@ static struct clk_fixed_factor meson8b_cpu_in_div3 =3D { }, }; =20 -static const struct clk_div_table cpu_scale_table[] =3D { +static const struct clk_div_table meson8b_cpu_scale_div_table[] =3D { { .val =3D 1, .div =3D 4 }, { .val =3D 2, .div =3D 6 }, { .val =3D 3, .div =3D 8 }, @@ -791,7 +792,7 @@ static struct clk_regmap meson8b_cpu_scale_div =3D { .offset =3D HHI_SYS_CPU_CLK_CNTL1, .shift =3D 20, .width =3D 10, - .table =3D cpu_scale_table, + .table =3D meson8b_cpu_scale_div_table, .flags =3D CLK_DIVIDER_ALLOW_ZERO, }, .hw.init =3D &(struct clk_init_data){ @@ -805,13 +806,13 @@ static struct clk_regmap meson8b_cpu_scale_div =3D { }, }; =20 -static u32 mux_table_cpu_scale_out_sel[] =3D { 0, 1, 3 }; +static u32 meson8b_cpu_scale_out_parents_val_table[] =3D { 0, 1, 3 }; static struct clk_regmap meson8b_cpu_scale_out_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_SYS_CPU_CLK_CNTL0, .mask =3D 0x3, .shift =3D 2, - .table =3D mux_table_cpu_scale_out_sel, + .table =3D meson8b_cpu_scale_out_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cpu_scale_out_sel", @@ -893,13 +894,13 @@ static struct clk_regmap meson8b_nand_clk_div =3D { }, }; =20 -static struct clk_regmap meson8b_nand_clk_gate =3D { +static struct clk_regmap meson8b_nand_clk =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_NAND_CLK_CNTL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "nand_clk_gate", + .name =3D "nand_clk", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_nand_clk_div.hw @@ -1000,160 +1001,137 @@ static struct clk_fixed_factor meson8b_cpu_clk_di= v8 =3D { }, }; =20 -static u32 mux_table_apb[] =3D { 1, 2, 3, 4, 5, 6, 7 }; -static struct clk_regmap meson8b_apb_clk_sel =3D { +static u32 meson8b_cpu_if_parents_val_table[] =3D { 1, 2, 3, 4, 5, 6, 7 }; +static const struct clk_hw *meson8b_cpu_if_parents[] =3D { + &meson8b_cpu_clk_div2.hw, + &meson8b_cpu_clk_div3.hw, + &meson8b_cpu_clk_div4.hw, + &meson8b_cpu_clk_div5.hw, + &meson8b_cpu_clk_div6.hw, + &meson8b_cpu_clk_div7.hw, + &meson8b_cpu_clk_div8.hw, +}; + +static struct clk_regmap meson8b_apb_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_SYS_CPU_CLK_CNTL1, .mask =3D 0x7, .shift =3D 3, - .table =3D mux_table_apb, + .table =3D meson8b_cpu_if_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "apb_clk_sel", + .name =3D "apb_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_cpu_clk_div2.hw, - &meson8b_cpu_clk_div3.hw, - &meson8b_cpu_clk_div4.hw, - &meson8b_cpu_clk_div5.hw, - &meson8b_cpu_clk_div6.hw, - &meson8b_cpu_clk_div7.hw, - &meson8b_cpu_clk_div8.hw, - }, - .num_parents =3D 7, + .parent_hws =3D meson8b_cpu_if_parents, + .num_parents =3D ARRAY_SIZE(meson8b_cpu_if_parents), }, }; =20 -static struct clk_regmap meson8b_apb_clk_gate =3D { +static struct clk_regmap meson8b_apb =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_SYS_CPU_CLK_CNTL1, .bit_idx =3D 16, .flags =3D CLK_GATE_SET_TO_DISABLE, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "apb_clk_dis", + .name =3D "apb", .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_apb_clk_sel.hw + &meson8b_apb_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap meson8b_periph_clk_sel =3D { +static struct clk_regmap meson8b_periph_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_SYS_CPU_CLK_CNTL1, .mask =3D 0x7, .shift =3D 6, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "periph_clk_sel", + .name =3D "periph_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_cpu_clk_div2.hw, - &meson8b_cpu_clk_div3.hw, - &meson8b_cpu_clk_div4.hw, - &meson8b_cpu_clk_div5.hw, - &meson8b_cpu_clk_div6.hw, - &meson8b_cpu_clk_div7.hw, - &meson8b_cpu_clk_div8.hw, - }, - .num_parents =3D 7, + .parent_hws =3D meson8b_cpu_if_parents, + .num_parents =3D ARRAY_SIZE(meson8b_cpu_if_parents), }, }; =20 -static struct clk_regmap meson8b_periph_clk_gate =3D { +static struct clk_regmap meson8b_periph =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_SYS_CPU_CLK_CNTL1, .bit_idx =3D 17, .flags =3D CLK_GATE_SET_TO_DISABLE, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "periph_clk_dis", + .name =3D "periph", .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_periph_clk_sel.hw + &meson8b_periph_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static u32 mux_table_axi[] =3D { 1, 2, 3, 4, 5, 6, 7 }; -static struct clk_regmap meson8b_axi_clk_sel =3D { +static struct clk_regmap meson8b_axi_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_SYS_CPU_CLK_CNTL1, .mask =3D 0x7, .shift =3D 9, - .table =3D mux_table_axi, + .table =3D meson8b_cpu_if_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "axi_clk_sel", + .name =3D "axi_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_cpu_clk_div2.hw, - &meson8b_cpu_clk_div3.hw, - &meson8b_cpu_clk_div4.hw, - &meson8b_cpu_clk_div5.hw, - &meson8b_cpu_clk_div6.hw, - &meson8b_cpu_clk_div7.hw, - &meson8b_cpu_clk_div8.hw, - }, - .num_parents =3D 7, + .parent_hws =3D meson8b_cpu_if_parents, + .num_parents =3D ARRAY_SIZE(meson8b_cpu_if_parents), }, }; =20 -static struct clk_regmap meson8b_axi_clk_gate =3D { +static struct clk_regmap meson8b_axi =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_SYS_CPU_CLK_CNTL1, .bit_idx =3D 18, .flags =3D CLK_GATE_SET_TO_DISABLE, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "axi_clk_dis", + .name =3D "axi", .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_axi_clk_sel.hw + &meson8b_axi_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap meson8b_l2_dram_clk_sel =3D { +static struct clk_regmap meson8b_l2_dram_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_SYS_CPU_CLK_CNTL1, .mask =3D 0x7, .shift =3D 12, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "l2_dram_clk_sel", + .name =3D "l2_dram_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_cpu_clk_div2.hw, - &meson8b_cpu_clk_div3.hw, - &meson8b_cpu_clk_div4.hw, - &meson8b_cpu_clk_div5.hw, - &meson8b_cpu_clk_div6.hw, - &meson8b_cpu_clk_div7.hw, - &meson8b_cpu_clk_div8.hw, - }, - .num_parents =3D 7, + .parent_hws =3D meson8b_cpu_if_parents, + .num_parents =3D ARRAY_SIZE(meson8b_cpu_if_parents), }, }; =20 -static struct clk_regmap meson8b_l2_dram_clk_gate =3D { +static struct clk_regmap meson8b_l2_dram =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_SYS_CPU_CLK_CNTL1, .bit_idx =3D 19, .flags =3D CLK_GATE_SET_TO_DISABLE, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "l2_dram_clk_dis", + .name =3D "l2_dram", .ops =3D &clk_regmap_gate_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_l2_dram_clk_sel.hw + &meson8b_l2_dram_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1286,7 +1264,7 @@ static struct clk_regmap meson8b_vid_pll_final_div = =3D { }, }; =20 -static const struct clk_hw *meson8b_vclk_mux_parent_hws[] =3D { +static const struct clk_hw *meson8b_vclk_parents[] =3D { &meson8b_vid_pll_final_div.hw, &meson8b_fclk_div4.hw, &meson8b_fclk_div3.hw, @@ -1305,8 +1283,8 @@ static struct clk_regmap meson8b_vclk_in_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vclk_in_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vclk_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vclk_mux_parent_hws), + .parent_hws =3D meson8b_vclk_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vclk_parents), .flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, }, }; @@ -1343,13 +1321,13 @@ static struct clk_regmap meson8b_vclk_en =3D { }, }; =20 -static struct clk_regmap meson8b_vclk_div1_gate =3D { +static struct clk_regmap meson8b_vclk_div1 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VID_CLK_CNTL, .bit_idx =3D 0, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk_div1_en", + .name =3D "vclk_div1", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_vclk_en.hw @@ -1363,7 +1341,7 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = =3D { .mult =3D 1, .div =3D 2, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk_div2", + .name =3D "vclk_div2_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_vclk_en.hw @@ -1373,13 +1351,13 @@ static struct clk_fixed_factor meson8b_vclk_div2_di= v =3D { } }; =20 -static struct clk_regmap meson8b_vclk_div2_div_gate =3D { +static struct clk_regmap meson8b_vclk_div2 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VID_CLK_CNTL, .bit_idx =3D 1, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk_div2_en", + .name =3D "vclk_div2", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_vclk_div2_div.hw @@ -1393,7 +1371,7 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = =3D { .mult =3D 1, .div =3D 4, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk_div4", + .name =3D "vclk_div4_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_vclk_en.hw @@ -1403,13 +1381,13 @@ static struct clk_fixed_factor meson8b_vclk_div4_di= v =3D { } }; =20 -static struct clk_regmap meson8b_vclk_div4_div_gate =3D { +static struct clk_regmap meson8b_vclk_div4 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VID_CLK_CNTL, .bit_idx =3D 2, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk_div4_en", + .name =3D "vclk_div4", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_vclk_div4_div.hw @@ -1423,7 +1401,7 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = =3D { .mult =3D 1, .div =3D 6, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk_div6", + .name =3D "vclk_div6_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_vclk_en.hw @@ -1433,13 +1411,13 @@ static struct clk_fixed_factor meson8b_vclk_div6_di= v =3D { } }; =20 -static struct clk_regmap meson8b_vclk_div6_div_gate =3D { +static struct clk_regmap meson8b_vclk_div6 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VID_CLK_CNTL, .bit_idx =3D 3, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk_div6_en", + .name =3D "vclk_div6", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_vclk_div6_div.hw @@ -1453,7 +1431,7 @@ static struct clk_fixed_factor meson8b_vclk_div12_div= =3D { .mult =3D 1, .div =3D 12, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk_div12", + .name =3D "vclk_div12_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_vclk_en.hw @@ -1463,13 +1441,13 @@ static struct clk_fixed_factor meson8b_vclk_div12_d= iv =3D { } }; =20 -static struct clk_regmap meson8b_vclk_div12_div_gate =3D { +static struct clk_regmap meson8b_vclk_div12 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VID_CLK_CNTL, .bit_idx =3D 4, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk_div12_en", + .name =3D "vclk_div12", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_vclk_div12_div.hw @@ -1488,13 +1466,13 @@ static struct clk_regmap meson8b_vclk2_in_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vclk2_in_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vclk_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vclk_mux_parent_hws), + .parent_hws =3D meson8b_vclk_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vclk_parents), .flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, }, }; =20 -static struct clk_regmap meson8b_vclk2_clk_in_en =3D { +static struct clk_regmap meson8b_vclk2_in_en =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VIID_CLK_DIV, .bit_idx =3D 16, @@ -1510,7 +1488,7 @@ static struct clk_regmap meson8b_vclk2_clk_in_en =3D { }, }; =20 -static struct clk_regmap meson8b_vclk2_clk_en =3D { +static struct clk_regmap meson8b_vclk2_en =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VIID_CLK_DIV, .bit_idx =3D 19, @@ -1519,23 +1497,23 @@ static struct clk_regmap meson8b_vclk2_clk_en =3D { .name =3D "vclk2_en", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_vclk2_clk_in_en.hw + &meson8b_vclk2_in_en.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap meson8b_vclk2_div1_gate =3D { +static struct clk_regmap meson8b_vclk2_div1 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VIID_CLK_DIV, .bit_idx =3D 0, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk2_div1_en", + .name =3D "vclk2_div1", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_vclk2_clk_en.hw + &meson8b_vclk2_en.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1546,23 +1524,23 @@ static struct clk_fixed_factor meson8b_vclk2_div2_d= iv =3D { .mult =3D 1, .div =3D 2, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk2_div2", + .name =3D "vclk2_div2_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_vclk2_clk_en.hw + &meson8b_vclk2_en.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, } }; =20 -static struct clk_regmap meson8b_vclk2_div2_div_gate =3D { +static struct clk_regmap meson8b_vclk2_div2 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VIID_CLK_DIV, .bit_idx =3D 1, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk2_div2_en", + .name =3D "vclk2_div2", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_vclk2_div2_div.hw @@ -1576,23 +1554,23 @@ static struct clk_fixed_factor meson8b_vclk2_div4_d= iv =3D { .mult =3D 1, .div =3D 4, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk2_div4", + .name =3D "vclk2_div4_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_vclk2_clk_en.hw + &meson8b_vclk2_en.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, } }; =20 -static struct clk_regmap meson8b_vclk2_div4_div_gate =3D { +static struct clk_regmap meson8b_vclk2_div4 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VIID_CLK_DIV, .bit_idx =3D 2, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk2_div4_en", + .name =3D "vclk2_div4", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_vclk2_div4_div.hw @@ -1606,23 +1584,23 @@ static struct clk_fixed_factor meson8b_vclk2_div6_d= iv =3D { .mult =3D 1, .div =3D 6, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk2_div6", + .name =3D "vclk2_div6_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_vclk2_clk_en.hw + &meson8b_vclk2_en.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, } }; =20 -static struct clk_regmap meson8b_vclk2_div6_div_gate =3D { +static struct clk_regmap meson8b_vclk2_div6 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VIID_CLK_DIV, .bit_idx =3D 3, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk2_div6_en", + .name =3D "vclk2_div6", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_vclk2_div6_div.hw @@ -1636,23 +1614,23 @@ static struct clk_fixed_factor meson8b_vclk2_div12_= div =3D { .mult =3D 1, .div =3D 12, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk2_div12", + .name =3D "vclk2_div12_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &meson8b_vclk2_clk_en.hw + &meson8b_vclk2_en.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, } }; =20 -static struct clk_regmap meson8b_vclk2_div12_div_gate =3D { +static struct clk_regmap meson8b_vclk2_div12 =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VIID_CLK_DIV, .bit_idx =3D 4, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "vclk2_div12_en", + .name =3D "vclk2_div12", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &meson8b_vclk2_div12_div.hw @@ -1662,12 +1640,12 @@ static struct clk_regmap meson8b_vclk2_div12_div_ga= te =3D { }, }; =20 -static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] =3D { - &meson8b_vclk_div1_gate.hw, - &meson8b_vclk_div2_div_gate.hw, - &meson8b_vclk_div4_div_gate.hw, - &meson8b_vclk_div6_div_gate.hw, - &meson8b_vclk_div12_div_gate.hw, +static const struct clk_hw *meson8b_vclk_enc_parents[] =3D { + &meson8b_vclk_div1.hw, + &meson8b_vclk_div2.hw, + &meson8b_vclk_div4.hw, + &meson8b_vclk_div6.hw, + &meson8b_vclk_div12.hw, }; =20 static struct clk_regmap meson8b_cts_enct_sel =3D { @@ -1679,8 +1657,8 @@ static struct clk_regmap meson8b_cts_enct_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "cts_enct_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vclk_enc_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), + .parent_hws =3D meson8b_vclk_enc_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vclk_enc_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1710,8 +1688,8 @@ static struct clk_regmap meson8b_cts_encp_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "cts_encp_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vclk_enc_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), + .parent_hws =3D meson8b_vclk_enc_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vclk_enc_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1741,8 +1719,8 @@ static struct clk_regmap meson8b_cts_enci_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "cts_enci_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vclk_enc_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), + .parent_hws =3D meson8b_vclk_enc_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vclk_enc_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1772,8 +1750,8 @@ static struct clk_regmap meson8b_hdmi_tx_pixel_sel = =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "hdmi_tx_pixel_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vclk_enc_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), + .parent_hws =3D meson8b_vclk_enc_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vclk_enc_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1794,14 +1772,6 @@ static struct clk_regmap meson8b_hdmi_tx_pixel =3D { }, }; =20 -static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] =3D { - &meson8b_vclk2_div1_gate.hw, - &meson8b_vclk2_div2_div_gate.hw, - &meson8b_vclk2_div4_div_gate.hw, - &meson8b_vclk2_div6_div_gate.hw, - &meson8b_vclk2_div12_div_gate.hw, -}; - static struct clk_regmap meson8b_cts_encl_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_VIID_CLK_DIV, @@ -1811,8 +1781,8 @@ static struct clk_regmap meson8b_cts_encl_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "cts_encl_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vclk2_enc_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws), + .parent_hws =3D meson8b_vclk_enc_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vclk_enc_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1842,8 +1812,8 @@ static struct clk_regmap meson8b_cts_vdac0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "cts_vdac0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vclk2_enc_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws), + .parent_hws =3D meson8b_vclk_enc_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vclk_enc_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1926,7 +1896,8 @@ static struct clk_regmap meson8b_hdmi_sys =3D { * CLK_SET_RATE_GATE is set. * Meson8 only has mali_0 and no glitch-free mux. */ -static const struct clk_parent_data meson8b_mali_0_1_parent_data[] =3D { +static u32 meson8b_mali_parents_val_table[] =3D { 0, 2, 3, 4, 5, 6, 7 }; +static const struct clk_parent_data meson8b_mali_parents[] =3D { { .fw_name =3D "xtal", .name =3D "xtal", .index =3D -1, }, { .hw =3D &meson8b_mpll2.hw, }, { .hw =3D &meson8b_mpll1.hw, }, @@ -1936,20 +1907,18 @@ static const struct clk_parent_data meson8b_mali_0_= 1_parent_data[] =3D { { .hw =3D &meson8b_fclk_div5.hw, }, }; =20 -static u32 meson8b_mali_0_1_mux_table[] =3D { 0, 2, 3, 4, 5, 6, 7 }; - static struct clk_regmap meson8b_mali_0_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_MALI_CLK_CNTL, .mask =3D 0x7, .shift =3D 9, - .table =3D meson8b_mali_0_1_mux_table, + .table =3D meson8b_mali_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "mali_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D meson8b_mali_0_1_parent_data, - .num_parents =3D ARRAY_SIZE(meson8b_mali_0_1_parent_data), + .parent_data =3D meson8b_mali_parents, + .num_parents =3D ARRAY_SIZE(meson8b_mali_parents), /* * Don't propagate rate changes up because the only changeable * parents are mpll1 and mpll2 but we need those for audio and @@ -1998,13 +1967,13 @@ static struct clk_regmap meson8b_mali_1_sel =3D { .offset =3D HHI_MALI_CLK_CNTL, .mask =3D 0x7, .shift =3D 25, - .table =3D meson8b_mali_0_1_mux_table, + .table =3D meson8b_mali_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "mali_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D meson8b_mali_0_1_parent_data, - .num_parents =3D ARRAY_SIZE(meson8b_mali_0_1_parent_data), + .parent_data =3D meson8b_mali_parents, + .num_parents =3D ARRAY_SIZE(meson8b_mali_parents), /* * Don't propagate rate changes up because the only changeable * parents are mpll1 and mpll2 but we need those for audio and @@ -2139,20 +2108,13 @@ static struct clk_regmap meson8m2_gp_pll =3D { }, }; =20 -static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] =3D { +static const struct clk_hw *meson8b_vpu_parents[] =3D { &meson8b_fclk_div4.hw, &meson8b_fclk_div3.hw, &meson8b_fclk_div5.hw, &meson8b_fclk_div7.hw, }; =20 -static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] =3D { - &meson8b_fclk_div4.hw, - &meson8b_fclk_div3.hw, - &meson8b_fclk_div5.hw, - &meson8m2_gp_pll.hw, -}; - static struct clk_regmap meson8b_vpu_0_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_VPU_CLK_CNTL, @@ -2162,12 +2124,19 @@ static struct clk_regmap meson8b_vpu_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vpu_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vpu_0_1_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vpu_0_1_parent_hws), + .parent_hws =3D meson8b_vpu_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vpu_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; =20 +static const struct clk_hw *mmeson8m2_vpu_parents[] =3D { + &meson8b_fclk_div4.hw, + &meson8b_fclk_div3.hw, + &meson8b_fclk_div5.hw, + &meson8m2_gp_pll.hw, +}; + static struct clk_regmap meson8m2_vpu_0_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_VPU_CLK_CNTL, @@ -2177,8 +2146,8 @@ static struct clk_regmap meson8m2_vpu_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vpu_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D mmeson8m2_vpu_0_1_parent_hws, - .num_parents =3D ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws), + .parent_hws =3D mmeson8m2_vpu_parents, + .num_parents =3D ARRAY_SIZE(mmeson8m2_vpu_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2233,8 +2202,8 @@ static struct clk_regmap meson8b_vpu_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vpu_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vpu_0_1_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vpu_0_1_parent_hws), + .parent_hws =3D meson8b_vpu_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vpu_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2248,8 +2217,8 @@ static struct clk_regmap meson8m2_vpu_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vpu_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D mmeson8m2_vpu_0_1_parent_hws, - .num_parents =3D ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws), + .parent_hws =3D mmeson8m2_vpu_parents, + .num_parents =3D ARRAY_SIZE(mmeson8m2_vpu_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2321,7 +2290,7 @@ static struct clk_regmap meson8b_vpu =3D { }, }; =20 -static const struct clk_hw *meson8b_vdec_parent_hws[] =3D { +static const struct clk_hw *meson8b_vdec_parents[] =3D { &meson8b_fclk_div4.hw, &meson8b_fclk_div3.hw, &meson8b_fclk_div5.hw, @@ -2340,8 +2309,8 @@ static struct clk_regmap meson8b_vdec_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vdec_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vdec_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vdec_parent_hws), + .parent_hws =3D meson8b_vdec_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vdec_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2443,8 +2412,8 @@ static struct clk_regmap meson8b_vdec_hcodec_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vdec_hcodec_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vdec_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vdec_parent_hws), + .parent_hws =3D meson8b_vdec_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vdec_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2493,8 +2462,8 @@ static struct clk_regmap meson8b_vdec_2_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vdec_2_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vdec_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vdec_parent_hws), + .parent_hws =3D meson8b_vdec_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vdec_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2543,8 +2512,8 @@ static struct clk_regmap meson8b_vdec_hevc_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vdec_hevc_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_vdec_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_vdec_parent_hws), + .parent_hws =3D meson8b_vdec_parents, + .num_parents =3D ARRAY_SIZE(meson8b_vdec_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2603,27 +2572,26 @@ static struct clk_regmap meson8b_vdec_hevc =3D { }; =20 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */ -static const struct clk_hw *meson8b_cts_amclk_parent_hws[] =3D { +static u32 meson8b_cts_mclk_parents_val_table[] =3D { 1, 2, 3 }; +static const struct clk_hw *meson8b_cts_mclk_parents[] =3D { &meson8b_mpll0.hw, &meson8b_mpll1.hw, &meson8b_mpll2.hw }; =20 -static u32 meson8b_cts_amclk_mux_table[] =3D { 1, 2, 3 }; - static struct clk_regmap meson8b_cts_amclk_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_AUD_CLK_CNTL, .mask =3D 0x3, .shift =3D 9, - .table =3D meson8b_cts_amclk_mux_table, + .table =3D meson8b_cts_mclk_parents_val_table, .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_amclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_cts_amclk_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_cts_amclk_parent_hws), + .parent_hws =3D meson8b_cts_mclk_parents, + .num_parents =3D ARRAY_SIZE(meson8b_cts_mclk_parents), }, }; =20 @@ -2661,28 +2629,19 @@ static struct clk_regmap meson8b_cts_amclk =3D { }, }; =20 -/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */ -static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] =3D { - &meson8b_mpll0.hw, - &meson8b_mpll1.hw, - &meson8b_mpll2.hw -}; - -static u32 meson8b_cts_mclk_i958_mux_table[] =3D { 1, 2, 3 }; - static struct clk_regmap meson8b_cts_mclk_i958_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_AUD_CLK_CNTL2, .mask =3D 0x3, .shift =3D 25, - .table =3D meson8b_cts_mclk_i958_mux_table, + .table =3D meson8b_cts_mclk_parents_val_table, .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data) { .name =3D "cts_mclk_i958_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D meson8b_cts_mclk_i958_parent_hws, - .num_parents =3D ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws), + .parent_hws =3D meson8b_cts_mclk_parents, + .num_parents =3D ARRAY_SIZE(meson8b_cts_mclk_parents), }, }; =20 @@ -2742,113 +2701,114 @@ static struct clk_regmap meson8b_cts_i958 =3D { }, }; =20 -#define MESON_GATE(_name, _reg, _bit) \ +#define MESON8B_PCLK(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw) =20 /* Everything Else (EE) domain gates */ =20 -static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); -static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1); -static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5); -static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6); -static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7); -static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8); -static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9); -static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10); -static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11); -static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12); -static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13); -static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14); -static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15); -static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16); -static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17); -static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18); -static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19); -static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23); -static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30); - -static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2); -static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3); -static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4); -static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14); -static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15); -static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16); -static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20); -static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21); -static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22); -static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23); -static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24); -static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25); -static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26); -static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28); -static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29); -static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30); -static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31); - -static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1); -static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); -static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4); -static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); -static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); -static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11); -static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12); -static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15); -static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22); -static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25); -static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); -static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29); - -static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1); -static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2); -static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3); -static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4); -static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8); -static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9); -static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10); -static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14); -static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16); -static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20); -static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21); -static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22); -static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24); -static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25); -static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26); -static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31); +static MESON8B_PCLK(meson8b_ddr, HHI_GCLK_MPEG0, 0); +static MESON8B_PCLK(meson8b_dos, HHI_GCLK_MPEG0, 1); +static MESON8B_PCLK(meson8b_isa, HHI_GCLK_MPEG0, 5); +static MESON8B_PCLK(meson8b_pl301, HHI_GCLK_MPEG0, 6); +static MESON8B_PCLK(meson8b_periphs, HHI_GCLK_MPEG0, 7); +static MESON8B_PCLK(meson8b_spicc, HHI_GCLK_MPEG0, 8); +static MESON8B_PCLK(meson8b_i2c, HHI_GCLK_MPEG0, 9); +static MESON8B_PCLK(meson8b_sar_adc, HHI_GCLK_MPEG0, 10); +static MESON8B_PCLK(meson8b_smart_card, HHI_GCLK_MPEG0, 11); +static MESON8B_PCLK(meson8b_rng0, HHI_GCLK_MPEG0, 12); +static MESON8B_PCLK(meson8b_uart0, HHI_GCLK_MPEG0, 13); +static MESON8B_PCLK(meson8b_sdhc, HHI_GCLK_MPEG0, 14); +static MESON8B_PCLK(meson8b_stream, HHI_GCLK_MPEG0, 15); +static MESON8B_PCLK(meson8b_async_fifo, HHI_GCLK_MPEG0, 16); +static MESON8B_PCLK(meson8b_sdio, HHI_GCLK_MPEG0, 17); +static MESON8B_PCLK(meson8b_abuf, HHI_GCLK_MPEG0, 18); +static MESON8B_PCLK(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19); +static MESON8B_PCLK(meson8b_assist_misc, HHI_GCLK_MPEG0, 23); +static MESON8B_PCLK(meson8b_spi, HHI_GCLK_MPEG0, 30); + +static MESON8B_PCLK(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2); +static MESON8B_PCLK(meson8b_eth, HHI_GCLK_MPEG1, 3); +static MESON8B_PCLK(meson8b_demux, HHI_GCLK_MPEG1, 4); +static MESON8B_PCLK(meson8b_blkmv, HHI_GCLK_MPEG1, 14); +static MESON8B_PCLK(meson8b_aiu, HHI_GCLK_MPEG1, 15); +static MESON8B_PCLK(meson8b_uart1, HHI_GCLK_MPEG1, 16); +static MESON8B_PCLK(meson8b_g2d, HHI_GCLK_MPEG1, 20); +static MESON8B_PCLK(meson8b_usb0, HHI_GCLK_MPEG1, 21); +static MESON8B_PCLK(meson8b_usb1, HHI_GCLK_MPEG1, 22); +static MESON8B_PCLK(meson8b_reset, HHI_GCLK_MPEG1, 23); +static MESON8B_PCLK(meson8b_nand, HHI_GCLK_MPEG1, 24); +static MESON8B_PCLK(meson8b_dos_parser, HHI_GCLK_MPEG1, 25); +static MESON8B_PCLK(meson8b_usb, HHI_GCLK_MPEG1, 26); +static MESON8B_PCLK(meson8b_vdin1, HHI_GCLK_MPEG1, 28); +static MESON8B_PCLK(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29); +static MESON8B_PCLK(meson8b_efuse, HHI_GCLK_MPEG1, 30); +static MESON8B_PCLK(meson8b_boot_rom, HHI_GCLK_MPEG1, 31); + +static MESON8B_PCLK(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1); +static MESON8B_PCLK(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); +static MESON8B_PCLK(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); +static MESON8B_PCLK(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4); +static MESON8B_PCLK(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); +static MESON8B_PCLK(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); +static MESON8B_PCLK(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11); +static MESON8B_PCLK(meson8b_dvin, HHI_GCLK_MPEG2, 12); +static MESON8B_PCLK(meson8b_uart2, HHI_GCLK_MPEG2, 15); +static MESON8B_PCLK(meson8b_sana, HHI_GCLK_MPEG2, 22); +static MESON8B_PCLK(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25); +static MESON8B_PCLK(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); +static MESON8B_PCLK(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29); + +static MESON8B_PCLK(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1); +static MESON8B_PCLK(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2); +static MESON8B_PCLK(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3); +static MESON8B_PCLK(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4); +static MESON8B_PCLK(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8); +static MESON8B_PCLK(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9); +static MESON8B_PCLK(meson8b_dac_clk, HHI_GCLK_OTHER, 10); +static MESON8B_PCLK(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14); +static MESON8B_PCLK(meson8b_iec958_gate, HHI_GCLK_OTHER, 16); +static MESON8B_PCLK(meson8b_enc480p, HHI_GCLK_OTHER, 20); +static MESON8B_PCLK(meson8b_rng1, HHI_GCLK_OTHER, 21); +static MESON8B_PCLK(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22); +static MESON8B_PCLK(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24); +static MESON8B_PCLK(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25); +static MESON8B_PCLK(meson8b_vclk2_other, HHI_GCLK_OTHER, 26); +static MESON8B_PCLK(meson8b_edp, HHI_GCLK_OTHER, 31); =20 /* AIU gates */ -#define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \ +static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw); + +#define MESON_AIU_PCLK(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw) =20 -static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw); -static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7); -static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8); -static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9); -static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10); -static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11); -static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12); -static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13); +static MESON_AIU_PCLK(meson8b_iec958, HHI_GCLK_MPEG1, 7); +static MESON_AIU_PCLK(meson8b_i2s_out, HHI_GCLK_MPEG1, 8); +static MESON_AIU_PCLK(meson8b_amclk, HHI_GCLK_MPEG1, 9); +static MESON_AIU_PCLK(meson8b_aififo2, HHI_GCLK_MPEG1, 10); +static MESON_AIU_PCLK(meson8b_mixer, HHI_GCLK_MPEG1, 11); +static MESON_AIU_PCLK(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12); +static MESON_AIU_PCLK(meson8b_adc, HHI_GCLK_MPEG1, 13); =20 /* Always On (AO) domain gates */ =20 -static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0); -static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1); -static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2); -static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3); +static MESON8B_PCLK(meson8b_ao_media_cpu, HHI_GCLK_AO, 0); +static MESON8B_PCLK(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1); +static MESON8B_PCLK(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2); +static MESON8B_PCLK(meson8b_ao_iface, HHI_GCLK_AO, 3); =20 static struct clk_hw *meson8_hw_clks[] =3D { - [CLKID_PLL_FIXED] =3D &meson8b_fixed_pll.hw, - [CLKID_PLL_VID] =3D &meson8b_vid_pll.hw, - [CLKID_PLL_SYS] =3D &meson8b_sys_pll.hw, - [CLKID_FCLK_DIV2] =3D &meson8b_fclk_div2.hw, - [CLKID_FCLK_DIV3] =3D &meson8b_fclk_div3.hw, - [CLKID_FCLK_DIV4] =3D &meson8b_fclk_div4.hw, - [CLKID_FCLK_DIV5] =3D &meson8b_fclk_div5.hw, - [CLKID_FCLK_DIV7] =3D &meson8b_fclk_div7.hw, - [CLKID_CPUCLK] =3D &meson8b_cpu_clk.hw, - [CLKID_MPEG_SEL] =3D &meson8b_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &meson8b_mpeg_clk_div.hw, - [CLKID_CLK81] =3D &meson8b_clk81.hw, + [CLKID_PLL_FIXED] =3D &meson8b_fixed_pll.hw, + [CLKID_PLL_VID] =3D &meson8b_vid_pll.hw, + [CLKID_PLL_SYS] =3D &meson8b_sys_pll.hw, + [CLKID_FCLK_DIV2] =3D &meson8b_fclk_div2.hw, + [CLKID_FCLK_DIV3] =3D &meson8b_fclk_div3.hw, + [CLKID_FCLK_DIV4] =3D &meson8b_fclk_div4.hw, + [CLKID_FCLK_DIV5] =3D &meson8b_fclk_div5.hw, + [CLKID_FCLK_DIV7] =3D &meson8b_fclk_div7.hw, + [CLKID_CPUCLK] =3D &meson8b_cpu_clk.hw, + [CLKID_MPEG_SEL] =3D &meson8b_clk81_sel.hw, + [CLKID_MPEG_DIV] =3D &meson8b_clk81_div.hw, + [CLKID_CLK81] =3D &meson8b_clk81.hw, [CLKID_DDR] =3D &meson8b_ddr.hw, [CLKID_DOS] =3D &meson8b_dos.hw, [CLKID_ISA] =3D &meson8b_isa.hw, @@ -2945,7 +2905,7 @@ static struct clk_hw *meson8_hw_clks[] =3D { [CLKID_FCLK_DIV7_DIV] =3D &meson8b_fclk_div7_div.hw, [CLKID_NAND_SEL] =3D &meson8b_nand_clk_sel.hw, [CLKID_NAND_DIV] =3D &meson8b_nand_clk_div.hw, - [CLKID_NAND_CLK] =3D &meson8b_nand_clk_gate.hw, + [CLKID_NAND_CLK] =3D &meson8b_nand_clk.hw, [CLKID_PLL_FIXED_DCO] =3D &meson8b_fixed_pll_dco.hw, [CLKID_HDMI_PLL_DCO] =3D &meson8b_hdmi_pll_dco.hw, [CLKID_PLL_SYS_DCO] =3D &meson8b_sys_pll_dco.hw, @@ -2956,14 +2916,14 @@ static struct clk_hw *meson8_hw_clks[] =3D { [CLKID_CPU_CLK_DIV6] =3D &meson8b_cpu_clk_div6.hw, [CLKID_CPU_CLK_DIV7] =3D &meson8b_cpu_clk_div7.hw, [CLKID_CPU_CLK_DIV8] =3D &meson8b_cpu_clk_div8.hw, - [CLKID_APB_SEL] =3D &meson8b_apb_clk_sel.hw, - [CLKID_APB] =3D &meson8b_apb_clk_gate.hw, - [CLKID_PERIPH_SEL] =3D &meson8b_periph_clk_sel.hw, - [CLKID_PERIPH] =3D &meson8b_periph_clk_gate.hw, - [CLKID_AXI_SEL] =3D &meson8b_axi_clk_sel.hw, - [CLKID_AXI] =3D &meson8b_axi_clk_gate.hw, - [CLKID_L2_DRAM_SEL] =3D &meson8b_l2_dram_clk_sel.hw, - [CLKID_L2_DRAM] =3D &meson8b_l2_dram_clk_gate.hw, + [CLKID_APB_SEL] =3D &meson8b_apb_sel.hw, + [CLKID_APB] =3D &meson8b_apb.hw, + [CLKID_PERIPH_SEL] =3D &meson8b_periph_sel.hw, + [CLKID_PERIPH] =3D &meson8b_periph.hw, + [CLKID_AXI_SEL] =3D &meson8b_axi_sel.hw, + [CLKID_AXI] =3D &meson8b_axi.hw, + [CLKID_L2_DRAM_SEL] =3D &meson8b_l2_dram_sel.hw, + [CLKID_L2_DRAM] =3D &meson8b_l2_dram.hw, [CLKID_HDMI_PLL_LVDS_OUT] =3D &meson8b_hdmi_pll_lvds_out.hw, [CLKID_HDMI_PLL_HDMI_OUT] =3D &meson8b_hdmi_pll_hdmi_out.hw, [CLKID_VID_PLL_IN_SEL] =3D &meson8b_vid_pll_in_sel.hw, @@ -2974,27 +2934,27 @@ static struct clk_hw *meson8_hw_clks[] =3D { [CLKID_VCLK_IN_SEL] =3D &meson8b_vclk_in_sel.hw, [CLKID_VCLK_IN_EN] =3D &meson8b_vclk_in_en.hw, [CLKID_VCLK_EN] =3D &meson8b_vclk_en.hw, - [CLKID_VCLK_DIV1] =3D &meson8b_vclk_div1_gate.hw, + [CLKID_VCLK_DIV1] =3D &meson8b_vclk_div1.hw, [CLKID_VCLK_DIV2_DIV] =3D &meson8b_vclk_div2_div.hw, - [CLKID_VCLK_DIV2] =3D &meson8b_vclk_div2_div_gate.hw, + [CLKID_VCLK_DIV2] =3D &meson8b_vclk_div2.hw, [CLKID_VCLK_DIV4_DIV] =3D &meson8b_vclk_div4_div.hw, - [CLKID_VCLK_DIV4] =3D &meson8b_vclk_div4_div_gate.hw, + [CLKID_VCLK_DIV4] =3D &meson8b_vclk_div4.hw, [CLKID_VCLK_DIV6_DIV] =3D &meson8b_vclk_div6_div.hw, - [CLKID_VCLK_DIV6] =3D &meson8b_vclk_div6_div_gate.hw, + [CLKID_VCLK_DIV6] =3D &meson8b_vclk_div6.hw, [CLKID_VCLK_DIV12_DIV] =3D &meson8b_vclk_div12_div.hw, - [CLKID_VCLK_DIV12] =3D &meson8b_vclk_div12_div_gate.hw, + [CLKID_VCLK_DIV12] =3D &meson8b_vclk_div12.hw, [CLKID_VCLK2_IN_SEL] =3D &meson8b_vclk2_in_sel.hw, - [CLKID_VCLK2_IN_EN] =3D &meson8b_vclk2_clk_in_en.hw, - [CLKID_VCLK2_EN] =3D &meson8b_vclk2_clk_en.hw, - [CLKID_VCLK2_DIV1] =3D &meson8b_vclk2_div1_gate.hw, + [CLKID_VCLK2_IN_EN] =3D &meson8b_vclk2_in_en.hw, + [CLKID_VCLK2_EN] =3D &meson8b_vclk2_en.hw, + [CLKID_VCLK2_DIV1] =3D &meson8b_vclk2_div1.hw, [CLKID_VCLK2_DIV2_DIV] =3D &meson8b_vclk2_div2_div.hw, - [CLKID_VCLK2_DIV2] =3D &meson8b_vclk2_div2_div_gate.hw, + [CLKID_VCLK2_DIV2] =3D &meson8b_vclk2_div2.hw, [CLKID_VCLK2_DIV4_DIV] =3D &meson8b_vclk2_div4_div.hw, - [CLKID_VCLK2_DIV4] =3D &meson8b_vclk2_div4_div_gate.hw, + [CLKID_VCLK2_DIV4] =3D &meson8b_vclk2_div4.hw, [CLKID_VCLK2_DIV6_DIV] =3D &meson8b_vclk2_div6_div.hw, - [CLKID_VCLK2_DIV6] =3D &meson8b_vclk2_div6_div_gate.hw, + [CLKID_VCLK2_DIV6] =3D &meson8b_vclk2_div6.hw, [CLKID_VCLK2_DIV12_DIV] =3D &meson8b_vclk2_div12_div.hw, - [CLKID_VCLK2_DIV12] =3D &meson8b_vclk2_div12_div_gate.hw, + [CLKID_VCLK2_DIV12] =3D &meson8b_vclk2_div12.hw, [CLKID_CTS_ENCT_SEL] =3D &meson8b_cts_enct_sel.hw, [CLKID_CTS_ENCT] =3D &meson8b_cts_enct.hw, [CLKID_CTS_ENCP_SEL] =3D &meson8b_cts_encp_sel.hw, @@ -3041,18 +3001,18 @@ static struct clk_hw *meson8_hw_clks[] =3D { }; =20 static struct clk_hw *meson8b_hw_clks[] =3D { - [CLKID_PLL_FIXED] =3D &meson8b_fixed_pll.hw, - [CLKID_PLL_VID] =3D &meson8b_vid_pll.hw, - [CLKID_PLL_SYS] =3D &meson8b_sys_pll.hw, - [CLKID_FCLK_DIV2] =3D &meson8b_fclk_div2.hw, - [CLKID_FCLK_DIV3] =3D &meson8b_fclk_div3.hw, - [CLKID_FCLK_DIV4] =3D &meson8b_fclk_div4.hw, - [CLKID_FCLK_DIV5] =3D &meson8b_fclk_div5.hw, - [CLKID_FCLK_DIV7] =3D &meson8b_fclk_div7.hw, - [CLKID_CPUCLK] =3D &meson8b_cpu_clk.hw, - [CLKID_MPEG_SEL] =3D &meson8b_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &meson8b_mpeg_clk_div.hw, - [CLKID_CLK81] =3D &meson8b_clk81.hw, + [CLKID_PLL_FIXED] =3D &meson8b_fixed_pll.hw, + [CLKID_PLL_VID] =3D &meson8b_vid_pll.hw, + [CLKID_PLL_SYS] =3D &meson8b_sys_pll.hw, + [CLKID_FCLK_DIV2] =3D &meson8b_fclk_div2.hw, + [CLKID_FCLK_DIV3] =3D &meson8b_fclk_div3.hw, + [CLKID_FCLK_DIV4] =3D &meson8b_fclk_div4.hw, + [CLKID_FCLK_DIV5] =3D &meson8b_fclk_div5.hw, + [CLKID_FCLK_DIV7] =3D &meson8b_fclk_div7.hw, + [CLKID_CPUCLK] =3D &meson8b_cpu_clk.hw, + [CLKID_MPEG_SEL] =3D &meson8b_clk81_sel.hw, + [CLKID_MPEG_DIV] =3D &meson8b_clk81_div.hw, + [CLKID_CLK81] =3D &meson8b_clk81.hw, [CLKID_DDR] =3D &meson8b_ddr.hw, [CLKID_DOS] =3D &meson8b_dos.hw, [CLKID_ISA] =3D &meson8b_isa.hw, @@ -3149,7 +3109,7 @@ static struct clk_hw *meson8b_hw_clks[] =3D { [CLKID_FCLK_DIV7_DIV] =3D &meson8b_fclk_div7_div.hw, [CLKID_NAND_SEL] =3D &meson8b_nand_clk_sel.hw, [CLKID_NAND_DIV] =3D &meson8b_nand_clk_div.hw, - [CLKID_NAND_CLK] =3D &meson8b_nand_clk_gate.hw, + [CLKID_NAND_CLK] =3D &meson8b_nand_clk.hw, [CLKID_PLL_FIXED_DCO] =3D &meson8b_fixed_pll_dco.hw, [CLKID_HDMI_PLL_DCO] =3D &meson8b_hdmi_pll_dco.hw, [CLKID_PLL_SYS_DCO] =3D &meson8b_sys_pll_dco.hw, @@ -3160,14 +3120,14 @@ static struct clk_hw *meson8b_hw_clks[] =3D { [CLKID_CPU_CLK_DIV6] =3D &meson8b_cpu_clk_div6.hw, [CLKID_CPU_CLK_DIV7] =3D &meson8b_cpu_clk_div7.hw, [CLKID_CPU_CLK_DIV8] =3D &meson8b_cpu_clk_div8.hw, - [CLKID_APB_SEL] =3D &meson8b_apb_clk_sel.hw, - [CLKID_APB] =3D &meson8b_apb_clk_gate.hw, - [CLKID_PERIPH_SEL] =3D &meson8b_periph_clk_sel.hw, - [CLKID_PERIPH] =3D &meson8b_periph_clk_gate.hw, - [CLKID_AXI_SEL] =3D &meson8b_axi_clk_sel.hw, - [CLKID_AXI] =3D &meson8b_axi_clk_gate.hw, - [CLKID_L2_DRAM_SEL] =3D &meson8b_l2_dram_clk_sel.hw, - [CLKID_L2_DRAM] =3D &meson8b_l2_dram_clk_gate.hw, + [CLKID_APB_SEL] =3D &meson8b_apb_sel.hw, + [CLKID_APB] =3D &meson8b_apb.hw, + [CLKID_PERIPH_SEL] =3D &meson8b_periph_sel.hw, + [CLKID_PERIPH] =3D &meson8b_periph.hw, + [CLKID_AXI_SEL] =3D &meson8b_axi_sel.hw, + [CLKID_AXI] =3D &meson8b_axi.hw, + [CLKID_L2_DRAM_SEL] =3D &meson8b_l2_dram_sel.hw, + [CLKID_L2_DRAM] =3D &meson8b_l2_dram.hw, [CLKID_HDMI_PLL_LVDS_OUT] =3D &meson8b_hdmi_pll_lvds_out.hw, [CLKID_HDMI_PLL_HDMI_OUT] =3D &meson8b_hdmi_pll_hdmi_out.hw, [CLKID_VID_PLL_IN_SEL] =3D &meson8b_vid_pll_in_sel.hw, @@ -3178,27 +3138,27 @@ static struct clk_hw *meson8b_hw_clks[] =3D { [CLKID_VCLK_IN_SEL] =3D &meson8b_vclk_in_sel.hw, [CLKID_VCLK_IN_EN] =3D &meson8b_vclk_in_en.hw, [CLKID_VCLK_EN] =3D &meson8b_vclk_en.hw, - [CLKID_VCLK_DIV1] =3D &meson8b_vclk_div1_gate.hw, + [CLKID_VCLK_DIV1] =3D &meson8b_vclk_div1.hw, [CLKID_VCLK_DIV2_DIV] =3D &meson8b_vclk_div2_div.hw, - [CLKID_VCLK_DIV2] =3D &meson8b_vclk_div2_div_gate.hw, + [CLKID_VCLK_DIV2] =3D &meson8b_vclk_div2.hw, [CLKID_VCLK_DIV4_DIV] =3D &meson8b_vclk_div4_div.hw, - [CLKID_VCLK_DIV4] =3D &meson8b_vclk_div4_div_gate.hw, + [CLKID_VCLK_DIV4] =3D &meson8b_vclk_div4.hw, [CLKID_VCLK_DIV6_DIV] =3D &meson8b_vclk_div6_div.hw, - [CLKID_VCLK_DIV6] =3D &meson8b_vclk_div6_div_gate.hw, + [CLKID_VCLK_DIV6] =3D &meson8b_vclk_div6.hw, [CLKID_VCLK_DIV12_DIV] =3D &meson8b_vclk_div12_div.hw, - [CLKID_VCLK_DIV12] =3D &meson8b_vclk_div12_div_gate.hw, + [CLKID_VCLK_DIV12] =3D &meson8b_vclk_div12.hw, [CLKID_VCLK2_IN_SEL] =3D &meson8b_vclk2_in_sel.hw, - [CLKID_VCLK2_IN_EN] =3D &meson8b_vclk2_clk_in_en.hw, - [CLKID_VCLK2_EN] =3D &meson8b_vclk2_clk_en.hw, - [CLKID_VCLK2_DIV1] =3D &meson8b_vclk2_div1_gate.hw, + [CLKID_VCLK2_IN_EN] =3D &meson8b_vclk2_in_en.hw, + [CLKID_VCLK2_EN] =3D &meson8b_vclk2_en.hw, + [CLKID_VCLK2_DIV1] =3D &meson8b_vclk2_div1.hw, [CLKID_VCLK2_DIV2_DIV] =3D &meson8b_vclk2_div2_div.hw, - [CLKID_VCLK2_DIV2] =3D &meson8b_vclk2_div2_div_gate.hw, + [CLKID_VCLK2_DIV2] =3D &meson8b_vclk2_div2.hw, [CLKID_VCLK2_DIV4_DIV] =3D &meson8b_vclk2_div4_div.hw, - [CLKID_VCLK2_DIV4] =3D &meson8b_vclk2_div4_div_gate.hw, + [CLKID_VCLK2_DIV4] =3D &meson8b_vclk2_div4.hw, [CLKID_VCLK2_DIV6_DIV] =3D &meson8b_vclk2_div6_div.hw, - [CLKID_VCLK2_DIV6] =3D &meson8b_vclk2_div6_div_gate.hw, + [CLKID_VCLK2_DIV6] =3D &meson8b_vclk2_div6.hw, [CLKID_VCLK2_DIV12_DIV] =3D &meson8b_vclk2_div12_div.hw, - [CLKID_VCLK2_DIV12] =3D &meson8b_vclk2_div12_div_gate.hw, + [CLKID_VCLK2_DIV12] =3D &meson8b_vclk2_div12.hw, [CLKID_CTS_ENCT_SEL] =3D &meson8b_cts_enct_sel.hw, [CLKID_CTS_ENCT] =3D &meson8b_cts_enct.hw, [CLKID_CTS_ENCP_SEL] =3D &meson8b_cts_encp_sel.hw, @@ -3256,18 +3216,18 @@ static struct clk_hw *meson8b_hw_clks[] =3D { }; =20 static struct clk_hw *meson8m2_hw_clks[] =3D { - [CLKID_PLL_FIXED] =3D &meson8b_fixed_pll.hw, - [CLKID_PLL_VID] =3D &meson8b_vid_pll.hw, - [CLKID_PLL_SYS] =3D &meson8b_sys_pll.hw, - [CLKID_FCLK_DIV2] =3D &meson8b_fclk_div2.hw, - [CLKID_FCLK_DIV3] =3D &meson8b_fclk_div3.hw, - [CLKID_FCLK_DIV4] =3D &meson8b_fclk_div4.hw, - [CLKID_FCLK_DIV5] =3D &meson8b_fclk_div5.hw, - [CLKID_FCLK_DIV7] =3D &meson8b_fclk_div7.hw, - [CLKID_CPUCLK] =3D &meson8b_cpu_clk.hw, - [CLKID_MPEG_SEL] =3D &meson8b_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &meson8b_mpeg_clk_div.hw, - [CLKID_CLK81] =3D &meson8b_clk81.hw, + [CLKID_PLL_FIXED] =3D &meson8b_fixed_pll.hw, + [CLKID_PLL_VID] =3D &meson8b_vid_pll.hw, + [CLKID_PLL_SYS] =3D &meson8b_sys_pll.hw, + [CLKID_FCLK_DIV2] =3D &meson8b_fclk_div2.hw, + [CLKID_FCLK_DIV3] =3D &meson8b_fclk_div3.hw, + [CLKID_FCLK_DIV4] =3D &meson8b_fclk_div4.hw, + [CLKID_FCLK_DIV5] =3D &meson8b_fclk_div5.hw, + [CLKID_FCLK_DIV7] =3D &meson8b_fclk_div7.hw, + [CLKID_CPUCLK] =3D &meson8b_cpu_clk.hw, + [CLKID_MPEG_SEL] =3D &meson8b_clk81_sel.hw, + [CLKID_MPEG_DIV] =3D &meson8b_clk81_div.hw, + [CLKID_CLK81] =3D &meson8b_clk81.hw, [CLKID_DDR] =3D &meson8b_ddr.hw, [CLKID_DOS] =3D &meson8b_dos.hw, [CLKID_ISA] =3D &meson8b_isa.hw, @@ -3364,7 +3324,7 @@ static struct clk_hw *meson8m2_hw_clks[] =3D { [CLKID_FCLK_DIV7_DIV] =3D &meson8b_fclk_div7_div.hw, [CLKID_NAND_SEL] =3D &meson8b_nand_clk_sel.hw, [CLKID_NAND_DIV] =3D &meson8b_nand_clk_div.hw, - [CLKID_NAND_CLK] =3D &meson8b_nand_clk_gate.hw, + [CLKID_NAND_CLK] =3D &meson8b_nand_clk.hw, [CLKID_PLL_FIXED_DCO] =3D &meson8b_fixed_pll_dco.hw, [CLKID_HDMI_PLL_DCO] =3D &meson8b_hdmi_pll_dco.hw, [CLKID_PLL_SYS_DCO] =3D &meson8b_sys_pll_dco.hw, @@ -3375,14 +3335,14 @@ static struct clk_hw *meson8m2_hw_clks[] =3D { [CLKID_CPU_CLK_DIV6] =3D &meson8b_cpu_clk_div6.hw, [CLKID_CPU_CLK_DIV7] =3D &meson8b_cpu_clk_div7.hw, [CLKID_CPU_CLK_DIV8] =3D &meson8b_cpu_clk_div8.hw, - [CLKID_APB_SEL] =3D &meson8b_apb_clk_sel.hw, - [CLKID_APB] =3D &meson8b_apb_clk_gate.hw, - [CLKID_PERIPH_SEL] =3D &meson8b_periph_clk_sel.hw, - [CLKID_PERIPH] =3D &meson8b_periph_clk_gate.hw, - [CLKID_AXI_SEL] =3D &meson8b_axi_clk_sel.hw, - [CLKID_AXI] =3D &meson8b_axi_clk_gate.hw, - [CLKID_L2_DRAM_SEL] =3D &meson8b_l2_dram_clk_sel.hw, - [CLKID_L2_DRAM] =3D &meson8b_l2_dram_clk_gate.hw, + [CLKID_APB_SEL] =3D &meson8b_apb_sel.hw, + [CLKID_APB] =3D &meson8b_apb.hw, + [CLKID_PERIPH_SEL] =3D &meson8b_periph_sel.hw, + [CLKID_PERIPH] =3D &meson8b_periph.hw, + [CLKID_AXI_SEL] =3D &meson8b_axi_sel.hw, + [CLKID_AXI] =3D &meson8b_axi.hw, + [CLKID_L2_DRAM_SEL] =3D &meson8b_l2_dram_sel.hw, + [CLKID_L2_DRAM] =3D &meson8b_l2_dram.hw, [CLKID_HDMI_PLL_LVDS_OUT] =3D &meson8b_hdmi_pll_lvds_out.hw, [CLKID_HDMI_PLL_HDMI_OUT] =3D &meson8b_hdmi_pll_hdmi_out.hw, [CLKID_VID_PLL_IN_SEL] =3D &meson8b_vid_pll_in_sel.hw, @@ -3393,27 +3353,27 @@ static struct clk_hw *meson8m2_hw_clks[] =3D { [CLKID_VCLK_IN_SEL] =3D &meson8b_vclk_in_sel.hw, [CLKID_VCLK_IN_EN] =3D &meson8b_vclk_in_en.hw, [CLKID_VCLK_EN] =3D &meson8b_vclk_en.hw, - [CLKID_VCLK_DIV1] =3D &meson8b_vclk_div1_gate.hw, + [CLKID_VCLK_DIV1] =3D &meson8b_vclk_div1.hw, [CLKID_VCLK_DIV2_DIV] =3D &meson8b_vclk_div2_div.hw, - [CLKID_VCLK_DIV2] =3D &meson8b_vclk_div2_div_gate.hw, + [CLKID_VCLK_DIV2] =3D &meson8b_vclk_div2.hw, [CLKID_VCLK_DIV4_DIV] =3D &meson8b_vclk_div4_div.hw, - [CLKID_VCLK_DIV4] =3D &meson8b_vclk_div4_div_gate.hw, + [CLKID_VCLK_DIV4] =3D &meson8b_vclk_div4.hw, [CLKID_VCLK_DIV6_DIV] =3D &meson8b_vclk_div6_div.hw, - [CLKID_VCLK_DIV6] =3D &meson8b_vclk_div6_div_gate.hw, + [CLKID_VCLK_DIV6] =3D &meson8b_vclk_div6.hw, [CLKID_VCLK_DIV12_DIV] =3D &meson8b_vclk_div12_div.hw, - [CLKID_VCLK_DIV12] =3D &meson8b_vclk_div12_div_gate.hw, + [CLKID_VCLK_DIV12] =3D &meson8b_vclk_div12.hw, [CLKID_VCLK2_IN_SEL] =3D &meson8b_vclk2_in_sel.hw, - [CLKID_VCLK2_IN_EN] =3D &meson8b_vclk2_clk_in_en.hw, - [CLKID_VCLK2_EN] =3D &meson8b_vclk2_clk_en.hw, - [CLKID_VCLK2_DIV1] =3D &meson8b_vclk2_div1_gate.hw, + [CLKID_VCLK2_IN_EN] =3D &meson8b_vclk2_in_en.hw, + [CLKID_VCLK2_EN] =3D &meson8b_vclk2_en.hw, + [CLKID_VCLK2_DIV1] =3D &meson8b_vclk2_div1.hw, [CLKID_VCLK2_DIV2_DIV] =3D &meson8b_vclk2_div2_div.hw, - [CLKID_VCLK2_DIV2] =3D &meson8b_vclk2_div2_div_gate.hw, + [CLKID_VCLK2_DIV2] =3D &meson8b_vclk2_div2.hw, [CLKID_VCLK2_DIV4_DIV] =3D &meson8b_vclk2_div4_div.hw, - [CLKID_VCLK2_DIV4] =3D &meson8b_vclk2_div4_div_gate.hw, + [CLKID_VCLK2_DIV4] =3D &meson8b_vclk2_div4.hw, [CLKID_VCLK2_DIV6_DIV] =3D &meson8b_vclk2_div6_div.hw, - [CLKID_VCLK2_DIV6] =3D &meson8b_vclk2_div6_div_gate.hw, + [CLKID_VCLK2_DIV6] =3D &meson8b_vclk2_div6.hw, [CLKID_VCLK2_DIV12_DIV] =3D &meson8b_vclk2_div12_div.hw, - [CLKID_VCLK2_DIV12] =3D &meson8b_vclk2_div12_div_gate.hw, + [CLKID_VCLK2_DIV12] =3D &meson8b_vclk2_div12.hw, [CLKID_CTS_ENCT_SEL] =3D &meson8b_cts_enct_sel.hw, [CLKID_CTS_ENCT] =3D &meson8b_cts_enct.hw, [CLKID_CTS_ENCP_SEL] =3D &meson8b_cts_encp_sel.hw, --=20 2.47.2 From nobody Wed Oct 8 03:53:54 2025 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate 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Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=66675; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=0iwTbwU3c4h3tACHgSyfJtBl9bT45xtnT02E/ppaego=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoZU/B8vIOGbFrfQG+ivjtQoP8p4ck00pKLcMRk QpsvOqoLmWJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaGVPwQAKCRDm/A8cN/La haZtD/41kmB6QedC41SG7x8mXbxhgj7aYYUY/P5LwU347Tfbq9k3UXfyx2w/Wa8PF35aONQyciK 3MpfSapS0/2fhQZJtyKZdfwbOUEG75/6AoTCPP5E755OtOuaaO711xGm/kgAoyo00GXsIrwUfZG pMmeNQnGgwuHH2267h57Rd3GEX+FaLjkV1/aV+lYubWaQZrlTcT6gQSYabv4G4RtbS0IfXWPxOu fc+buWaZqfyaOOx+k4QbZt5xgxV7gTsYpRYUXGTYcfgtATcrm0yFTty+JRPQSSD0VOOLbFrCpaU cs83g8kOqHzUyB7JEsIqDGr7iAkeLxNwY1hk2ezINtZTyYTRIoIdb1PRl2iJjdK4iKF82dp0Uyk TamrQ9Y2Uq6I+MoYq5LwzFXO/mzD8yLT+55yoeOVzOHpplWrr1IZm7lnT70JURVjF4v9L6IoUcr J7souRSr80Ch/Feym2FpQlnGTD7t8MA9m9PBX+PmD0e9HBdJldJaXe9Ona0wvQfdrFK+bbj25rn //+5GZ+GsElY/GbCsVDhtKgU0qX9ySR+V9xjgz3HFxJ1EbXLR6pmlEL3BqqyA2yIxq6IwJgNyY2 mNkCpupQpwcCjhewC8zhoRYSCgkP/i5frGegatsH5qIgxkWOhJGo4+1Po6dlylHHWQnIz31oxjx U0iPUak9lfHO3bg== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet Reviewed-by: Chuan Liu --- drivers/clk/meson/s4-peripherals.c | 746 ++++++++++++++++++---------------= ---- 1 file changed, 370 insertions(+), 376 deletions(-) diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index c9400cf54c84c3dc7c63d0636933951b0cac230c..9bcd35f12836de5e318fd1ad9c9= ae15a2bfc3dd7 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -182,8 +182,8 @@ static struct clk_regmap s4_rtc_clk =3D { }; =20 /* The index 5 is AXI_CLK, which is dedicated to AXI. So skip it. */ -static u32 mux_table_sys_ab_clk_sel[] =3D { 0, 1, 2, 3, 4, 6, 7 }; -static const struct clk_parent_data sys_ab_clk_parent_data[] =3D { +static u32 s4_sysclk_parents_val_table[] =3D { 0, 1, 2, 3, 4, 6, 7 }; +static const struct clk_parent_data s4_sysclk_parents[] =3D { { .fw_name =3D "xtal" }, { .fw_name =3D "fclk_div2" }, { .fw_name =3D "fclk_div3" }, @@ -205,13 +205,13 @@ static struct clk_regmap s4_sysclk_b_sel =3D { .offset =3D CLKCTRL_SYS_CLK_CTRL0, .mask =3D 0x7, .shift =3D 26, - .table =3D mux_table_sys_ab_clk_sel, + .table =3D s4_sysclk_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "sysclk_b_sel", .ops =3D &clk_regmap_mux_ro_ops, - .parent_data =3D sys_ab_clk_parent_data, - .num_parents =3D ARRAY_SIZE(sys_ab_clk_parent_data), + .parent_data =3D s4_sysclk_parents, + .num_parents =3D ARRAY_SIZE(s4_sysclk_parents), }, }; =20 @@ -251,13 +251,13 @@ static struct clk_regmap s4_sysclk_a_sel =3D { .offset =3D CLKCTRL_SYS_CLK_CTRL0, .mask =3D 0x7, .shift =3D 10, - .table =3D mux_table_sys_ab_clk_sel, + .table =3D s4_sysclk_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "sysclk_a_sel", .ops =3D &clk_regmap_mux_ro_ops, - .parent_data =3D sys_ab_clk_parent_data, - .num_parents =3D ARRAY_SIZE(sys_ab_clk_parent_data), + .parent_data =3D s4_sysclk_parents, + .num_parents =3D ARRAY_SIZE(s4_sysclk_parents), }, }; =20 @@ -523,24 +523,24 @@ static struct clk_regmap s4_cecb_32k_clkout =3D { }, }; =20 -static const struct clk_parent_data s4_sc_parent_data[] =3D { +static const struct clk_parent_data s4_sc_clk_parents[] =3D { { .fw_name =3D "fclk_div4" }, { .fw_name =3D "fclk_div3" }, { .fw_name =3D "fclk_div5" }, { .fw_name =3D "xtal", } }; =20 -static struct clk_regmap s4_sc_clk_mux =3D { +static struct clk_regmap s4_sc_clk_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_SC_CLK_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "sc_clk_mux", + .name =3D "sc_clk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_sc_parent_data, - .num_parents =3D ARRAY_SIZE(s4_sc_parent_data), + .parent_data =3D s4_sc_clk_parents, + .num_parents =3D ARRAY_SIZE(s4_sc_clk_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -555,20 +555,20 @@ static struct clk_regmap s4_sc_clk_div =3D { .name =3D "sc_clk_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_sc_clk_mux.hw + &s4_sc_clk_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_sc_clk_gate =3D { +static struct clk_regmap s4_sc_clk =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_SC_CLK_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "sc_clk_gate", + .name =3D "sc_clk", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_sc_clk_div.hw @@ -578,13 +578,13 @@ static struct clk_regmap s4_sc_clk_gate =3D { }, }; =20 -static struct clk_regmap s4_12_24M_clk_gate =3D { +static struct clk_regmap s4_12_24M =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_CLK12_24_CTRL, .bit_idx =3D 11, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "12_24m_gate", + .name =3D "12_24M", .ops =3D &clk_regmap_gate_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "xtal", } @@ -593,32 +593,32 @@ static struct clk_regmap s4_12_24M_clk_gate =3D { }, }; =20 -static struct clk_fixed_factor s4_12M_clk_div =3D { +static struct clk_fixed_factor s4_12M_div =3D { .mult =3D 1, .div =3D 2, .hw.init =3D &(struct clk_init_data){ - .name =3D "12M", + .name =3D "12M_div", .ops =3D &clk_fixed_factor_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_12_24M_clk_gate.hw + &s4_12_24M.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_12_24M_clk =3D { +static struct clk_regmap s4_12_24M_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_CLK12_24_CTRL, .mask =3D 0x1, .shift =3D 10, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "12_24m", + .name =3D "12_24M_sel", .ops =3D &clk_regmap_mux_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_12_24M_clk_gate.hw, - &s4_12M_clk_div.hw, + &s4_12_24M.hw, + &s4_12M_div.hw, }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, @@ -687,7 +687,7 @@ static struct clk_regmap s4_vid_pll =3D { }, }; =20 -static const struct clk_parent_data s4_vclk_parent_data[] =3D { +static const struct clk_parent_data s4_vclk_parents[] =3D { { .hw =3D &s4_vid_pll.hw }, { .fw_name =3D "gp0_pll", }, { .fw_name =3D "hifi_pll", }, @@ -707,8 +707,8 @@ static struct clk_regmap s4_vclk_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vclk_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vclk_parent_data), + .parent_data =3D s4_vclk_parents, + .num_parents =3D ARRAY_SIZE(s4_vclk_parents), .flags =3D 0, }, }; @@ -722,8 +722,8 @@ static struct clk_regmap s4_vclk2_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vclk2_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vclk_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vclk_parent_data), + .parent_data =3D s4_vclk_parents, + .num_parents =3D ARRAY_SIZE(s4_vclk_parents), .flags =3D 0, }, }; @@ -1071,8 +1071,8 @@ static struct clk_fixed_factor s4_vclk2_div12 =3D { }; =20 /* The 5,6,7 indexes corresponds to no real clock, so there are not used. = */ -static u32 mux_table_cts_sel[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; -static const struct clk_hw *s4_cts_parent_hws[] =3D { +static u32 s4_cts_parents_val_table[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11, 1= 2 }; +static const struct clk_hw *s4_cts_parents[] =3D { &s4_vclk_div1.hw, &s4_vclk_div2.hw, &s4_vclk_div4.hw, @@ -1090,13 +1090,13 @@ static struct clk_regmap s4_cts_enci_sel =3D { .offset =3D CLKCTRL_VID_CLK_DIV, .mask =3D 0xf, .shift =3D 28, - .table =3D mux_table_cts_sel, + .table =3D s4_cts_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_enci_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_cts_parent_hws), + .parent_hws =3D s4_cts_parents, + .num_parents =3D ARRAY_SIZE(s4_cts_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1106,13 +1106,13 @@ static struct clk_regmap s4_cts_encp_sel =3D { .offset =3D CLKCTRL_VID_CLK_DIV, .mask =3D 0xf, .shift =3D 20, - .table =3D mux_table_cts_sel, + .table =3D s4_cts_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_encp_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_cts_parent_hws), + .parent_hws =3D s4_cts_parents, + .num_parents =3D ARRAY_SIZE(s4_cts_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1122,20 +1122,20 @@ static struct clk_regmap s4_cts_vdac_sel =3D { .offset =3D CLKCTRL_VIID_CLK_DIV, .mask =3D 0xf, .shift =3D 28, - .table =3D mux_table_cts_sel, + .table =3D s4_cts_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "cts_vdac_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_cts_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_cts_parent_hws), + .parent_hws =3D s4_cts_parents, + .num_parents =3D ARRAY_SIZE(s4_cts_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; =20 /* The 5,6,7 indexes corresponds to no real clock, so there are not used. = */ -static u32 mux_table_hdmi_tx_sel[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; -static const struct clk_hw *s4_cts_hdmi_tx_parent_hws[] =3D { +static u32 s4_hdmi_tx_parents_val_table[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 1= 1, 12 }; +static const struct clk_hw *s4_hdmi_tx_parents[] =3D { &s4_vclk_div1.hw, &s4_vclk_div2.hw, &s4_vclk_div4.hw, @@ -1153,13 +1153,13 @@ static struct clk_regmap s4_hdmi_tx_sel =3D { .offset =3D CLKCTRL_HDMI_CLK_CTRL, .mask =3D 0xf, .shift =3D 16, - .table =3D mux_table_hdmi_tx_sel, + .table =3D s4_hdmi_tx_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "hdmi_tx_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_cts_hdmi_tx_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_cts_hdmi_tx_parent_hws), + .parent_hws =3D s4_hdmi_tx_parents, + .num_parents =3D ARRAY_SIZE(s4_hdmi_tx_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1229,7 +1229,7 @@ static struct clk_regmap s4_hdmi_tx =3D { }; =20 /* HDMI Clocks */ -static const struct clk_parent_data s4_hdmi_parent_data[] =3D { +static const struct clk_parent_data s4_hdmi_parents[] =3D { { .fw_name =3D "xtal", }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, @@ -1246,8 +1246,8 @@ static struct clk_regmap s4_hdmi_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "hdmi_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_hdmi_parent_data, - .num_parents =3D ARRAY_SIZE(s4_hdmi_parent_data), + .parent_data =3D s4_hdmi_parents, + .num_parents =3D ARRAY_SIZE(s4_hdmi_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1298,7 +1298,7 @@ static struct clk_regmap s4_ts_clk_div =3D { }, }; =20 -static struct clk_regmap s4_ts_clk_gate =3D { +static struct clk_regmap s4_ts_clk =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_TS_CLK_CTRL, .bit_idx =3D 8, @@ -1320,7 +1320,7 @@ static struct clk_regmap s4_ts_clk_gate =3D { * mux because it does top-to-bottom updates the each clock tree and * switches to the "inactive" one when CLK_SET_RATE_GATE is set. */ -static const struct clk_parent_data s4_mali_0_1_parent_data[] =3D { +static const struct clk_parent_data s4_mali_parents[] =3D { { .fw_name =3D "xtal", }, { .fw_name =3D "gp0_pll", }, { .fw_name =3D "hifi_pll", }, @@ -1340,8 +1340,8 @@ static struct clk_regmap s4_mali_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "mali_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_mali_0_1_parent_data, - .num_parents =3D ARRAY_SIZE(s4_mali_0_1_parent_data), + .parent_data =3D s4_mali_parents, + .num_parents =3D ARRAY_SIZE(s4_mali_parents), /* * Don't request the parent to change the rate because * all GPU frequencies can be derived from the fclk_* @@ -1394,8 +1394,8 @@ static struct clk_regmap s4_mali_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "mali_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_mali_0_1_parent_data, - .num_parents =3D ARRAY_SIZE(s4_mali_0_1_parent_data), + .parent_data =3D s4_mali_parents, + .num_parents =3D ARRAY_SIZE(s4_mali_parents), .flags =3D 0, }, }; @@ -1433,28 +1433,26 @@ static struct clk_regmap s4_mali_1 =3D { }, }; =20 -static const struct clk_hw *s4_mali_parent_hws[] =3D { - &s4_mali_0.hw, - &s4_mali_1.hw -}; - -static struct clk_regmap s4_mali_mux =3D { +static struct clk_regmap s4_mali_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_MALI_CLK_CTRL, .mask =3D 1, .shift =3D 31, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "mali", + .name =3D "mali_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_mali_parent_hws, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_mali_0.hw, + &s4_mali_1.hw, + }, .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 /* VDEC clocks */ -static const struct clk_parent_data s4_dec_parent_data[] =3D { +static const struct clk_parent_data s4_dec_parents[] =3D { { .fw_name =3D "fclk_div2p5", }, { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div4", }, @@ -1465,7 +1463,7 @@ static const struct clk_parent_data s4_dec_parent_dat= a[] =3D { { .fw_name =3D "xtal", } }; =20 -static struct clk_regmap s4_vdec_p0_mux =3D { +static struct clk_regmap s4_vdec_p0_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDEC_CLK_CTRL, .mask =3D 0x7, @@ -1473,10 +1471,10 @@ static struct clk_regmap s4_vdec_p0_mux =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vdec_p0_mux", + .name =3D "vdec_p0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_dec_parent_data, - .num_parents =3D ARRAY_SIZE(s4_dec_parent_data), + .parent_data =3D s4_dec_parents, + .num_parents =3D ARRAY_SIZE(s4_dec_parents), .flags =3D 0, }, }; @@ -1492,7 +1490,7 @@ static struct clk_regmap s4_vdec_p0_div =3D { .name =3D "vdec_p0_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_vdec_p0_mux.hw + &s4_vdec_p0_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1515,7 +1513,7 @@ static struct clk_regmap s4_vdec_p0 =3D { }, }; =20 -static struct clk_regmap s4_vdec_p1_mux =3D { +static struct clk_regmap s4_vdec_p1_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDEC3_CLK_CTRL, .mask =3D 0x7, @@ -1523,10 +1521,10 @@ static struct clk_regmap s4_vdec_p1_mux =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vdec_p1_mux", + .name =3D "vdec_p1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_dec_parent_data, - .num_parents =3D ARRAY_SIZE(s4_dec_parent_data), + .parent_data =3D s4_dec_parents, + .num_parents =3D ARRAY_SIZE(s4_dec_parents), .flags =3D 0, }, }; @@ -1542,7 +1540,7 @@ static struct clk_regmap s4_vdec_p1_div =3D { .name =3D "vdec_p1_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_vdec_p1_mux.hw + &s4_vdec_p1_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1565,27 +1563,25 @@ static struct clk_regmap s4_vdec_p1 =3D { }, }; =20 -static const struct clk_hw *s4_vdec_mux_parent_hws[] =3D { - &s4_vdec_p0.hw, - &s4_vdec_p1.hw -}; - -static struct clk_regmap s4_vdec_mux =3D { +static struct clk_regmap s4_vdec_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDEC3_CLK_CTRL, .mask =3D 0x1, .shift =3D 15, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vdec_mux", + .name =3D "vdec_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_vdec_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_vdec_mux_parent_hws), + .parent_hws =3D (const struct clk_hw *[]) { + &s4_vdec_p0.hw, + &s4_vdec_p1.hw, + }, + .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_hevcf_p0_mux =3D { +static struct clk_regmap s4_hevcf_p0_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDEC2_CLK_CTRL, .mask =3D 0x7, @@ -1593,10 +1589,10 @@ static struct clk_regmap s4_hevcf_p0_mux =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "hevcf_p0_mux", + .name =3D "hevcf_p0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_dec_parent_data, - .num_parents =3D ARRAY_SIZE(s4_dec_parent_data), + .parent_data =3D s4_dec_parents, + .num_parents =3D ARRAY_SIZE(s4_dec_parents), .flags =3D 0, }, }; @@ -1612,7 +1608,7 @@ static struct clk_regmap s4_hevcf_p0_div =3D { .name =3D "hevcf_p0_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_hevcf_p0_mux.hw + &s4_hevcf_p0_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1625,7 +1621,7 @@ static struct clk_regmap s4_hevcf_p0 =3D { .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "hevcf_p0_gate", + .name =3D "hevcf_p0", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_hevcf_p0_div.hw @@ -1635,7 +1631,7 @@ static struct clk_regmap s4_hevcf_p0 =3D { }, }; =20 -static struct clk_regmap s4_hevcf_p1_mux =3D { +static struct clk_regmap s4_hevcf_p1_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDEC4_CLK_CTRL, .mask =3D 0x7, @@ -1643,10 +1639,10 @@ static struct clk_regmap s4_hevcf_p1_mux =3D { .flags =3D CLK_MUX_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "hevcf_p1_mux", + .name =3D "hevcf_p1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_dec_parent_data, - .num_parents =3D ARRAY_SIZE(s4_dec_parent_data), + .parent_data =3D s4_dec_parents, + .num_parents =3D ARRAY_SIZE(s4_dec_parents), .flags =3D 0, }, }; @@ -1662,7 +1658,7 @@ static struct clk_regmap s4_hevcf_p1_div =3D { .name =3D "hevcf_p1_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_hevcf_p1_mux.hw + &s4_hevcf_p1_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1685,28 +1681,26 @@ static struct clk_regmap s4_hevcf_p1 =3D { }, }; =20 -static const struct clk_hw *s4_hevcf_mux_parent_hws[] =3D { - &s4_hevcf_p0.hw, - &s4_hevcf_p1.hw -}; - -static struct clk_regmap s4_hevcf_mux =3D { +static struct clk_regmap s4_hevcf_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDEC4_CLK_CTRL, .mask =3D 0x1, .shift =3D 15, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "hevcf", + .name =3D "hevcf_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_hevcf_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_hevcf_mux_parent_hws), + .parent_hws =3D (const struct clk_hw *[]) { + &s4_hevcf_p0.hw, + &s4_hevcf_p1.hw, + }, + .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 /* VPU Clock */ -static const struct clk_parent_data s4_vpu_parent_data[] =3D { +static const struct clk_parent_data s4_vpu_parents[] =3D { { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div5", }, @@ -1726,8 +1720,8 @@ static struct clk_regmap s4_vpu_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vpu_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vpu_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vpu_parent_data), + .parent_data =3D s4_vpu_parents, + .num_parents =3D ARRAY_SIZE(s4_vpu_parents), .flags =3D 0, }, }; @@ -1770,8 +1764,8 @@ static struct clk_regmap s4_vpu_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vpu_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vpu_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vpu_parent_data), + .parent_data =3D s4_vpu_parents, + .num_parents =3D ARRAY_SIZE(s4_vpu_parents), .flags =3D 0, }, }; @@ -1823,24 +1817,24 @@ static struct clk_regmap s4_vpu =3D { }, }; =20 -static const struct clk_parent_data vpu_clkb_tmp_parent_data[] =3D { +static const struct clk_parent_data vpu_clkb_tmp_parents[] =3D { { .hw =3D &s4_vpu.hw }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div5", }, { .fw_name =3D "fclk_div7", } }; =20 -static struct clk_regmap s4_vpu_clkb_tmp_mux =3D { +static struct clk_regmap s4_vpu_clkb_tmp_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VPU_CLKB_CTRL, .mask =3D 0x3, .shift =3D 20, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vpu_clkb_tmp_mux", + .name =3D "vpu_clkb_tmp_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D vpu_clkb_tmp_parent_data, - .num_parents =3D ARRAY_SIZE(vpu_clkb_tmp_parent_data), + .parent_data =3D vpu_clkb_tmp_parents, + .num_parents =3D ARRAY_SIZE(vpu_clkb_tmp_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -1855,7 +1849,7 @@ static struct clk_regmap s4_vpu_clkb_tmp_div =3D { .name =3D "vpu_clkb_tmp_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_vpu_clkb_tmp_mux.hw + &s4_vpu_clkb_tmp_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1911,7 +1905,7 @@ static struct clk_regmap s4_vpu_clkb =3D { }, }; =20 -static const struct clk_parent_data s4_vpu_clkc_parent_data[] =3D { +static const struct clk_parent_data s4_vpu_clkc_parents[] =3D { { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div5", }, @@ -1922,17 +1916,17 @@ static const struct clk_parent_data s4_vpu_clkc_par= ent_data[] =3D { { .fw_name =3D "gp0_pll", }, }; =20 -static struct clk_regmap s4_vpu_clkc_p0_mux =3D { +static struct clk_regmap s4_vpu_clkc_p0_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VPU_CLKC_CTRL, .mask =3D 0x7, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vpu_clkc_p0_mux", + .name =3D "vpu_clkc_p0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vpu_clkc_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vpu_clkc_parent_data), + .parent_data =3D s4_vpu_clkc_parents, + .num_parents =3D ARRAY_SIZE(s4_vpu_clkc_parents), .flags =3D 0, }, }; @@ -1947,7 +1941,7 @@ static struct clk_regmap s4_vpu_clkc_p0_div =3D { .name =3D "vpu_clkc_p0_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_vpu_clkc_p0_mux.hw + &s4_vpu_clkc_p0_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1970,17 +1964,17 @@ static struct clk_regmap s4_vpu_clkc_p0 =3D { }, }; =20 -static struct clk_regmap s4_vpu_clkc_p1_mux =3D { +static struct clk_regmap s4_vpu_clkc_p1_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VPU_CLKC_CTRL, .mask =3D 0x7, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vpu_clkc_p1_mux", + .name =3D "vpu_clkc_p1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vpu_clkc_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vpu_clkc_parent_data), + .parent_data =3D s4_vpu_clkc_parents, + .num_parents =3D ARRAY_SIZE(s4_vpu_clkc_parents), .flags =3D 0, }, }; @@ -1995,7 +1989,7 @@ static struct clk_regmap s4_vpu_clkc_p1_div =3D { .name =3D "vpu_clkc_p1_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_vpu_clkc_p1_mux.hw + &s4_vpu_clkc_p1_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2018,28 +2012,26 @@ static struct clk_regmap s4_vpu_clkc_p1 =3D { }, }; =20 -static const struct clk_hw *s4_vpu_mux_parent_hws[] =3D { - &s4_vpu_clkc_p0.hw, - &s4_vpu_clkc_p1.hw -}; - -static struct clk_regmap s4_vpu_clkc_mux =3D { +static struct clk_regmap s4_vpu_clkc_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VPU_CLKC_CTRL, .mask =3D 0x1, .shift =3D 31, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vpu_clkc_mux", + .name =3D "vpu_clkc_sel", .ops =3D &clk_regmap_mux_ops, - .parent_hws =3D s4_vpu_mux_parent_hws, - .num_parents =3D ARRAY_SIZE(s4_vpu_mux_parent_hws), + .parent_hws =3D (const struct clk_hw *[]) { + &s4_vpu_clkc_p0.hw, + &s4_vpu_clkc_p1.hw, + }, + .num_parents =3D 2, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 /* VAPB Clock */ -static const struct clk_parent_data s4_vapb_parent_data[] =3D { +static const struct clk_parent_data s4_vapb_parents[] =3D { { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div5", }, @@ -2059,8 +2051,8 @@ static struct clk_regmap s4_vapb_0_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vapb_0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vapb_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vapb_parent_data), + .parent_data =3D s4_vapb_parents, + .num_parents =3D ARRAY_SIZE(s4_vapb_parents), .flags =3D 0, }, }; @@ -2107,8 +2099,8 @@ static struct clk_regmap s4_vapb_1_sel =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "vapb_1_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vapb_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vapb_parent_data), + .parent_data =3D s4_vapb_parents, + .num_parents =3D ARRAY_SIZE(s4_vapb_parents), .flags =3D 0, }, }; @@ -2164,13 +2156,13 @@ static struct clk_regmap s4_vapb =3D { }, }; =20 -static struct clk_regmap s4_ge2d_gate =3D { +static struct clk_regmap s4_ge2d =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_VAPBCLK_CTRL, .bit_idx =3D 30, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "ge2d_clk", + .name =3D "ge2d", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_vapb.hw }, .num_parents =3D 1, @@ -2178,24 +2170,24 @@ static struct clk_regmap s4_ge2d_gate =3D { }, }; =20 -static const struct clk_parent_data s4_esmclk_parent_data[] =3D { +static const struct clk_parent_data s4_hdcp22_esmclk_parents[] =3D { { .fw_name =3D "fclk_div7", }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div5", }, }; =20 -static struct clk_regmap s4_hdcp22_esmclk_mux =3D { +static struct clk_regmap s4_hdcp22_esmclk_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_HDCP22_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "hdcp22_esmclk_mux", + .name =3D "hdcp22_esmclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_esmclk_parent_data, - .num_parents =3D ARRAY_SIZE(s4_esmclk_parent_data), + .parent_data =3D s4_hdcp22_esmclk_parents, + .num_parents =3D ARRAY_SIZE(s4_hdcp22_esmclk_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2210,20 +2202,20 @@ static struct clk_regmap s4_hdcp22_esmclk_div =3D { .name =3D "hdcp22_esmclk_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_hdcp22_esmclk_mux.hw + &s4_hdcp22_esmclk_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_hdcp22_esmclk_gate =3D { +static struct clk_regmap s4_hdcp22_esmclk =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_HDCP22_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "hdcp22_esmclk_gate", + .name =3D "hdcp22_esmclk", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_hdcp22_esmclk_div.hw @@ -2233,24 +2225,24 @@ static struct clk_regmap s4_hdcp22_esmclk_gate =3D { }, }; =20 -static const struct clk_parent_data s4_skpclk_parent_data[] =3D { +static const struct clk_parent_data s4_hdcp22_skpclk_parents[] =3D { { .fw_name =3D "xtal", }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, { .fw_name =3D "fclk_div5", }, }; =20 -static struct clk_regmap s4_hdcp22_skpclk_mux =3D { +static struct clk_regmap s4_hdcp22_skpclk_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_HDCP22_CTRL, .mask =3D 0x3, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "hdcp22_skpclk_mux", + .name =3D "hdcp22_skpclk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_skpclk_parent_data, - .num_parents =3D ARRAY_SIZE(s4_skpclk_parent_data), + .parent_data =3D s4_hdcp22_skpclk_parents, + .num_parents =3D ARRAY_SIZE(s4_hdcp22_skpclk_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2265,20 +2257,20 @@ static struct clk_regmap s4_hdcp22_skpclk_div =3D { .name =3D "hdcp22_skpclk_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_hdcp22_skpclk_mux.hw + &s4_hdcp22_skpclk_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_hdcp22_skpclk_gate =3D { +static struct clk_regmap s4_hdcp22_skpclk =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_HDCP22_CTRL, .bit_idx =3D 24, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "hdcp22_skpclk_gate", + .name =3D "hdcp22_skpclk", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_hdcp22_skpclk_div.hw @@ -2288,7 +2280,7 @@ static struct clk_regmap s4_hdcp22_skpclk_gate =3D { }, }; =20 -static const struct clk_parent_data s4_vdin_parent_data[] =3D { +static const struct clk_parent_data s4_vdin_parents[] =3D { { .fw_name =3D "xtal", }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, @@ -2296,17 +2288,17 @@ static const struct clk_parent_data s4_vdin_parent_= data[] =3D { { .hw =3D &s4_vid_pll.hw } }; =20 -static struct clk_regmap s4_vdin_meas_mux =3D { +static struct clk_regmap s4_vdin_meas_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VDIN_MEAS_CLK_CTRL, .mask =3D 0x7, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "vdin_meas_mux", + .name =3D "vdin_meas_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_vdin_parent_data, - .num_parents =3D ARRAY_SIZE(s4_vdin_parent_data), + .parent_data =3D s4_vdin_parents, + .num_parents =3D ARRAY_SIZE(s4_vdin_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2321,20 +2313,20 @@ static struct clk_regmap s4_vdin_meas_div =3D { .name =3D "vdin_meas_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_vdin_meas_mux.hw + &s4_vdin_meas_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_vdin_meas_gate =3D { +static struct clk_regmap s4_vdin_meas =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_VDIN_MEAS_CLK_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "vdin_meas_gate", + .name =3D "vdin_meas", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_vdin_meas_div.hw @@ -2345,7 +2337,7 @@ static struct clk_regmap s4_vdin_meas_gate =3D { }; =20 /* EMMC/NAND clock */ -static const struct clk_parent_data s4_sd_emmc_clk0_parent_data[] =3D { +static const struct clk_parent_data s4_sd_emmc_clk0_parents[] =3D { { .fw_name =3D "xtal", }, { .fw_name =3D "fclk_div2", }, { .fw_name =3D "fclk_div3", }, @@ -2365,8 +2357,8 @@ static struct clk_regmap s4_sd_emmc_c_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_c_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(s4_sd_emmc_clk0_parent_data), + .parent_data =3D s4_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(s4_sd_emmc_clk0_parents), .flags =3D 0, }, }; @@ -2413,8 +2405,8 @@ static struct clk_regmap s4_sd_emmc_a_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_a_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(s4_sd_emmc_clk0_parent_data), + .parent_data =3D s4_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(s4_sd_emmc_clk0_parents), .flags =3D 0, }, }; @@ -2461,8 +2453,8 @@ static struct clk_regmap s4_sd_emmc_b_clk0_sel =3D { .hw.init =3D &(struct clk_init_data) { .name =3D "sd_emmc_b_clk0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_sd_emmc_clk0_parent_data, - .num_parents =3D ARRAY_SIZE(s4_sd_emmc_clk0_parent_data), + .parent_data =3D s4_sd_emmc_clk0_parents, + .num_parents =3D ARRAY_SIZE(s4_sd_emmc_clk0_parents), .flags =3D 0, }, }; @@ -2501,7 +2493,7 @@ static struct clk_regmap s4_sd_emmc_b_clk0 =3D { }; =20 /* SPICC Clock */ -static const struct clk_parent_data s4_spicc_parent_data[] =3D { +static const struct clk_parent_data s4_spicc_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &s4_sys_clk.hw }, { .fw_name =3D "fclk_div4", }, @@ -2511,17 +2503,17 @@ static const struct clk_parent_data s4_spicc_parent= _data[] =3D { { .fw_name =3D "fclk_div7", }, }; =20 -static struct clk_regmap s4_spicc0_mux =3D { +static struct clk_regmap s4_spicc0_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_SPICC_CLK_CTRL, .mask =3D 0x7, .shift =3D 7, }, .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc0_mux", + .name =3D "spicc0_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_spicc_parent_data, - .num_parents =3D ARRAY_SIZE(s4_spicc_parent_data), + .parent_data =3D s4_spicc_parents, + .num_parents =3D ARRAY_SIZE(s4_spicc_parents), .flags =3D CLK_SET_RATE_PARENT, }, }; @@ -2536,20 +2528,20 @@ static struct clk_regmap s4_spicc0_div =3D { .name =3D "spicc0_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_spicc0_mux.hw + &s4_spicc0_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_spicc0_gate =3D { +static struct clk_regmap s4_spicc0_en =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_SPICC_CLK_CTRL, .bit_idx =3D 6, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "spicc0", + .name =3D "spicc0_en", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_spicc0_div.hw @@ -2560,24 +2552,24 @@ static struct clk_regmap s4_spicc0_gate =3D { }; =20 /* PWM Clock */ -static const struct clk_parent_data s4_pwm_parent_data[] =3D { +static const struct clk_parent_data s4_pwm_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &s4_vid_pll.hw }, { .fw_name =3D "fclk_div4", }, { .fw_name =3D "fclk_div3", }, }; =20 -static struct clk_regmap s4_pwm_a_mux =3D { +static struct clk_regmap s4_pwm_a_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_a_mux", + .name =3D "pwm_a_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2592,14 +2584,14 @@ static struct clk_regmap s4_pwm_a_div =3D { .name =3D "pwm_a_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_a_mux.hw + &s4_pwm_a_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_a_gate =3D { +static struct clk_regmap s4_pwm_a =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, .bit_idx =3D 8, @@ -2615,17 +2607,17 @@ static struct clk_regmap s4_pwm_a_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_b_mux =3D { +static struct clk_regmap s4_pwm_b_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, .mask =3D 0x3, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_b_mux", + .name =3D "pwm_b_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2640,20 +2632,20 @@ static struct clk_regmap s4_pwm_b_div =3D { .name =3D "pwm_b_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_b_mux.hw + &s4_pwm_b_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_b_gate =3D { +static struct clk_regmap s4_pwm_b =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, .bit_idx =3D 24, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_b_gate", + .name =3D "pwm_b", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_b_div.hw @@ -2663,7 +2655,7 @@ static struct clk_regmap s4_pwm_b_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_c_mux =3D { +static struct clk_regmap s4_pwm_c_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, .mask =3D 0x3, @@ -2672,8 +2664,8 @@ static struct clk_regmap s4_pwm_c_mux =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "pwm_c_mux", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2688,19 +2680,19 @@ static struct clk_regmap s4_pwm_c_div =3D { .name =3D "pwm_c_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_c_mux.hw + &s4_pwm_c_sel.hw }, .num_parents =3D 1, }, }; =20 -static struct clk_regmap s4_pwm_c_gate =3D { +static struct clk_regmap s4_pwm_c =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_c_gate", + .name =3D "pwm_c", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_c_div.hw @@ -2710,17 +2702,17 @@ static struct clk_regmap s4_pwm_c_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_d_mux =3D { +static struct clk_regmap s4_pwm_d_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, .mask =3D 0x3, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_d_mux", + .name =3D "pwm_d_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2735,20 +2727,20 @@ static struct clk_regmap s4_pwm_d_div =3D { .name =3D "pwm_d_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_d_mux.hw + &s4_pwm_d_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_d_gate =3D { +static struct clk_regmap s4_pwm_d =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, .bit_idx =3D 24, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_d_gate", + .name =3D "pwm_d", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_d_div.hw @@ -2758,17 +2750,17 @@ static struct clk_regmap s4_pwm_d_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_e_mux =3D { +static struct clk_regmap s4_pwm_e_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_e_mux", + .name =3D "pwm_e_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2783,20 +2775,20 @@ static struct clk_regmap s4_pwm_e_div =3D { .name =3D "pwm_e_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_e_mux.hw + &s4_pwm_e_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_e_gate =3D { +static struct clk_regmap s4_pwm_e =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_e_gate", + .name =3D "pwm_e", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_e_div.hw @@ -2806,17 +2798,17 @@ static struct clk_regmap s4_pwm_e_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_f_mux =3D { +static struct clk_regmap s4_pwm_f_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, .mask =3D 0x3, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_f_mux", + .name =3D "pwm_f_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2831,20 +2823,20 @@ static struct clk_regmap s4_pwm_f_div =3D { .name =3D "pwm_f_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_f_mux.hw + &s4_pwm_f_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_f_gate =3D { +static struct clk_regmap s4_pwm_f =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, .bit_idx =3D 24, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_f_gate", + .name =3D "pwm_f", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_f_div.hw @@ -2854,17 +2846,17 @@ static struct clk_regmap s4_pwm_f_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_g_mux =3D { +static struct clk_regmap s4_pwm_g_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_g_mux", + .name =3D "pwm_g_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2879,20 +2871,20 @@ static struct clk_regmap s4_pwm_g_div =3D { .name =3D "pwm_g_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_g_mux.hw + &s4_pwm_g_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_g_gate =3D { +static struct clk_regmap s4_pwm_g =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_g_gate", + .name =3D "pwm_g", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_g_div.hw @@ -2902,17 +2894,17 @@ static struct clk_regmap s4_pwm_g_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_h_mux =3D { +static struct clk_regmap s4_pwm_h_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, .mask =3D 0x3, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_h_mux", + .name =3D "pwm_h_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2927,20 +2919,20 @@ static struct clk_regmap s4_pwm_h_div =3D { .name =3D "pwm_h_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_h_mux.hw + &s4_pwm_h_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_h_gate =3D { +static struct clk_regmap s4_pwm_h =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, .bit_idx =3D 24, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_h_gate", + .name =3D "pwm_h", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_h_div.hw @@ -2950,17 +2942,17 @@ static struct clk_regmap s4_pwm_h_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_i_mux =3D { +static struct clk_regmap s4_pwm_i_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_i_mux", + .name =3D "pwm_i_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -2975,20 +2967,20 @@ static struct clk_regmap s4_pwm_i_div =3D { .name =3D "pwm_i_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_i_mux.hw + &s4_pwm_i_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_i_gate =3D { +static struct clk_regmap s4_pwm_i =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_i_gate", + .name =3D "pwm_i", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_i_div.hw @@ -2998,17 +2990,17 @@ static struct clk_regmap s4_pwm_i_gate =3D { }, }; =20 -static struct clk_regmap s4_pwm_j_mux =3D { +static struct clk_regmap s4_pwm_j_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, .mask =3D 0x3, .shift =3D 25, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_j_mux", + .name =3D "pwm_j_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parent_data, - .num_parents =3D ARRAY_SIZE(s4_pwm_parent_data), + .parent_data =3D s4_pwm_parents, + .num_parents =3D ARRAY_SIZE(s4_pwm_parents), .flags =3D 0, }, }; @@ -3023,20 +3015,20 @@ static struct clk_regmap s4_pwm_j_div =3D { .name =3D "pwm_j_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_j_mux.hw + &s4_pwm_j_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_pwm_j_gate =3D { +static struct clk_regmap s4_pwm_j =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, .bit_idx =3D 24, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_j_gate", + .name =3D "pwm_j", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_pwm_j_div.hw @@ -3046,14 +3038,14 @@ static struct clk_regmap s4_pwm_j_gate =3D { }, }; =20 -static struct clk_regmap s4_saradc_mux =3D { +static struct clk_regmap s4_saradc_sel =3D { .data =3D &(struct clk_regmap_mux_data) { .offset =3D CLKCTRL_SAR_CLK_CTRL, .mask =3D 0x3, .shift =3D 9, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "saradc_mux", + .name =3D "saradc_sel", .ops =3D &clk_regmap_mux_ops, .parent_data =3D (const struct clk_parent_data []) { { .fw_name =3D "xtal", }, @@ -3074,20 +3066,20 @@ static struct clk_regmap s4_saradc_div =3D { .name =3D "saradc_div", .ops =3D &clk_regmap_divider_ops, .parent_hws =3D (const struct clk_hw *[]) { - &s4_saradc_mux.hw + &s4_saradc_sel.hw }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, }, }; =20 -static struct clk_regmap s4_saradc_gate =3D { +static struct clk_regmap s4_saradc =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D CLKCTRL_SAR_CLK_CTRL, .bit_idx =3D 8, }, .hw.init =3D &(struct clk_init_data){ - .name =3D "saradc_clk", + .name =3D "saradc", .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &s4_saradc_div.hw @@ -3102,9 +3094,8 @@ static struct clk_regmap s4_saradc_gate =3D { * corresponding clock sources are not described in the clock tree and int= ernal clock * for debug, so they are skipped. */ -static u32 s4_gen_clk_mux_table[] =3D { 0, 4, 5, 7, 19, 21, 22, - 23, 24, 25, 26, 27, 28 }; -static const struct clk_parent_data s4_gen_clk_parent_data[] =3D { +static u32 s4_gen_clk_parents_val_table[] =3D { 0, 4, 5, 7, 19, 21, 22, 23= , 24, 25, 26, 27, 28 }; +static const struct clk_parent_data s4_gen_clk_parents[] =3D { { .fw_name =3D "xtal", }, { .hw =3D &s4_vid_pll.hw }, { .fw_name =3D "gp0_pll", }, @@ -3125,13 +3116,13 @@ static struct clk_regmap s4_gen_clk_sel =3D { .offset =3D CLKCTRL_GEN_CLK_CTRL, .mask =3D 0x1f, .shift =3D 12, - .table =3D s4_gen_clk_mux_table, + .table =3D s4_gen_clk_parents_val_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "gen_clk_sel", .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_gen_clk_parent_data, - .num_parents =3D ARRAY_SIZE(s4_gen_clk_parent_data), + .parent_data =3D s4_gen_clk_parents, + .num_parents =3D ARRAY_SIZE(s4_gen_clk_parents), /* * Because the GEN clock can be connected to an external pad * and may be set up directly from the device tree. Don't @@ -3174,61 +3165,64 @@ static struct clk_regmap s4_gen_clk =3D { }, }; =20 -#define MESON_GATE(_name, _reg, _bit) \ +#define S4_PCLK(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw) =20 -static MESON_GATE(s4_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0); -static MESON_GATE(s4_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1); -static MESON_GATE(s4_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4); -static MESON_GATE(s4_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6); -static MESON_GATE(s4_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13); -static MESON_GATE(s4_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14); -static MESON_GATE(s4_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16); -static MESON_GATE(s4_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24); -static MESON_GATE(s4_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25); -static MESON_GATE(s4_nand, CLKCTRL_SYS_CLK_EN0_REG0, 26); -static MESON_GATE(s4_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27); -static MESON_GATE(s4_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28); -static MESON_GATE(s4_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29); -static MESON_GATE(s4_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30); -static MESON_GATE(s4_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31); -static MESON_GATE(s4_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0); -static MESON_GATE(s4_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3); -static MESON_GATE(s4_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5); -static MESON_GATE(s4_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6); -static MESON_GATE(s4_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7); -static MESON_GATE(s4_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8); -static MESON_GATE(s4_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9); -static MESON_GATE(s4_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11); -static MESON_GATE(s4_ts_ddr, CLKCTRL_SYS_CLK_EN0_REG1, 15); -static MESON_GATE(s4_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16); -static MESON_GATE(s4_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20); -static MESON_GATE(s4_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21); -static MESON_GATE(s4_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26); -static MESON_GATE(s4_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30); -static MESON_GATE(s4_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31); -static MESON_GATE(s4_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0); -static MESON_GATE(s4_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1); -static MESON_GATE(s4_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2); -static MESON_GATE(s4_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4); -static MESON_GATE(s4_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5); -static MESON_GATE(s4_usb1_to_ddr, CLKCTRL_SYS_CLK_EN0_REG2, 8); -static MESON_GATE(s4_hdcp22, CLKCTRL_SYS_CLK_EN0_REG2, 10); -static MESON_GATE(s4_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11); -static MESON_GATE(s4_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18); -static MESON_GATE(s4_cpu_debug, CLKCTRL_SYS_CLK_EN0_REG2, 19); -static MESON_GATE(s4_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25); -static MESON_GATE(s4_demod, CLKCTRL_SYS_CLK_EN0_REG2, 27); -static MESON_GATE(s4_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28); -static MESON_GATE(s4_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30); -static MESON_GATE(s4_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7); -static MESON_GATE(s4_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8); -static MESON_GATE(s4_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9); -static MESON_GATE(s4_pwm_gh, CLKCTRL_SYS_CLK_EN0_REG3, 10); -static MESON_GATE(s4_pwm_ij, CLKCTRL_SYS_CLK_EN0_REG3, 11); +static S4_PCLK(s4_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0); +static S4_PCLK(s4_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1); +static S4_PCLK(s4_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4); +static S4_PCLK(s4_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6); +static S4_PCLK(s4_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13); +static S4_PCLK(s4_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14); +static S4_PCLK(s4_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16); +static S4_PCLK(s4_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24); +static S4_PCLK(s4_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25); +static S4_PCLK(s4_nand, CLKCTRL_SYS_CLK_EN0_REG0, 26); +static S4_PCLK(s4_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27); +static S4_PCLK(s4_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28); +static S4_PCLK(s4_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29); +static S4_PCLK(s4_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30); +static S4_PCLK(s4_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31); + +static S4_PCLK(s4_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0); +static S4_PCLK(s4_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3); +static S4_PCLK(s4_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5); +static S4_PCLK(s4_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6); +static S4_PCLK(s4_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7); +static S4_PCLK(s4_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8); +static S4_PCLK(s4_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9); +static S4_PCLK(s4_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11); +static S4_PCLK(s4_ts_ddr, CLKCTRL_SYS_CLK_EN0_REG1, 15); +static S4_PCLK(s4_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16); +static S4_PCLK(s4_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20); +static S4_PCLK(s4_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21); +static S4_PCLK(s4_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26); +static S4_PCLK(s4_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30); +static S4_PCLK(s4_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31); + +static S4_PCLK(s4_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0); +static S4_PCLK(s4_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1); +static S4_PCLK(s4_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2); +static S4_PCLK(s4_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4); +static S4_PCLK(s4_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5); +static S4_PCLK(s4_usb1_to_ddr, CLKCTRL_SYS_CLK_EN0_REG2, 8); +static S4_PCLK(s4_hdcp22, CLKCTRL_SYS_CLK_EN0_REG2, 10); +static S4_PCLK(s4_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11); +static S4_PCLK(s4_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18); +static S4_PCLK(s4_cpu_debug, CLKCTRL_SYS_CLK_EN0_REG2, 19); +static S4_PCLK(s4_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25); +static S4_PCLK(s4_demod, CLKCTRL_SYS_CLK_EN0_REG2, 27); +static S4_PCLK(s4_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28); +static S4_PCLK(s4_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30); + +static S4_PCLK(s4_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7); +static S4_PCLK(s4_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8); +static S4_PCLK(s4_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9); +static S4_PCLK(s4_pwm_gh, CLKCTRL_SYS_CLK_EN0_REG3, 10); +static S4_PCLK(s4_pwm_ij, CLKCTRL_SYS_CLK_EN0_REG3, 11); =20 /* Array of all clocks provided by this provider */ -static struct clk_hw *s4_periphs_hw_clks[] =3D { +static struct clk_hw *s4_peripherals_hw_clks[] =3D { [CLKID_RTC_32K_CLKIN] =3D &s4_rtc_32k_by_oscin_clkin.hw, [CLKID_RTC_32K_DIV] =3D &s4_rtc_32k_by_oscin_div.hw, [CLKID_RTC_32K_SEL] =3D &s4_rtc_32k_by_oscin_sel.hw, @@ -3251,12 +3245,12 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_CECB_32K_SEL_PRE] =3D &s4_cecb_32k_sel_pre.hw, [CLKID_CECB_32K_SEL] =3D &s4_cecb_32k_sel.hw, [CLKID_CECB_32K_CLKOUT] =3D &s4_cecb_32k_clkout.hw, - [CLKID_SC_CLK_SEL] =3D &s4_sc_clk_mux.hw, + [CLKID_SC_CLK_SEL] =3D &s4_sc_clk_sel.hw, [CLKID_SC_CLK_DIV] =3D &s4_sc_clk_div.hw, - [CLKID_SC] =3D &s4_sc_clk_gate.hw, - [CLKID_12_24M] =3D &s4_12_24M_clk_gate.hw, - [CLKID_12M_CLK_DIV] =3D &s4_12M_clk_div.hw, - [CLKID_12_24M_CLK_SEL] =3D &s4_12_24M_clk.hw, + [CLKID_SC] =3D &s4_sc_clk.hw, + [CLKID_12_24M] =3D &s4_12_24M.hw, + [CLKID_12M_CLK_DIV] =3D &s4_12M_div.hw, + [CLKID_12_24M_CLK_SEL] =3D &s4_12_24M_sel.hw, [CLKID_VID_PLL_DIV] =3D &s4_vid_pll_div.hw, [CLKID_VID_PLL_SEL] =3D &s4_vid_pll_sel.hw, [CLKID_VID_PLL] =3D &s4_vid_pll.hw, @@ -3298,28 +3292,28 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_HDMI_DIV] =3D &s4_hdmi_div.hw, [CLKID_HDMI] =3D &s4_hdmi.hw, [CLKID_TS_CLK_DIV] =3D &s4_ts_clk_div.hw, - [CLKID_TS] =3D &s4_ts_clk_gate.hw, + [CLKID_TS] =3D &s4_ts_clk.hw, [CLKID_MALI_0_SEL] =3D &s4_mali_0_sel.hw, [CLKID_MALI_0_DIV] =3D &s4_mali_0_div.hw, [CLKID_MALI_0] =3D &s4_mali_0.hw, [CLKID_MALI_1_SEL] =3D &s4_mali_1_sel.hw, [CLKID_MALI_1_DIV] =3D &s4_mali_1_div.hw, [CLKID_MALI_1] =3D &s4_mali_1.hw, - [CLKID_MALI_SEL] =3D &s4_mali_mux.hw, - [CLKID_VDEC_P0_SEL] =3D &s4_vdec_p0_mux.hw, + [CLKID_MALI_SEL] =3D &s4_mali_sel.hw, + [CLKID_VDEC_P0_SEL] =3D &s4_vdec_p0_sel.hw, [CLKID_VDEC_P0_DIV] =3D &s4_vdec_p0_div.hw, [CLKID_VDEC_P0] =3D &s4_vdec_p0.hw, - [CLKID_VDEC_P1_SEL] =3D &s4_vdec_p1_mux.hw, + [CLKID_VDEC_P1_SEL] =3D &s4_vdec_p1_sel.hw, [CLKID_VDEC_P1_DIV] =3D &s4_vdec_p1_div.hw, [CLKID_VDEC_P1] =3D &s4_vdec_p1.hw, - [CLKID_VDEC_SEL] =3D &s4_vdec_mux.hw, - [CLKID_HEVCF_P0_SEL] =3D &s4_hevcf_p0_mux.hw, + [CLKID_VDEC_SEL] =3D &s4_vdec_sel.hw, + [CLKID_HEVCF_P0_SEL] =3D &s4_hevcf_p0_sel.hw, [CLKID_HEVCF_P0_DIV] =3D &s4_hevcf_p0_div.hw, [CLKID_HEVCF_P0] =3D &s4_hevcf_p0.hw, - [CLKID_HEVCF_P1_SEL] =3D &s4_hevcf_p1_mux.hw, + [CLKID_HEVCF_P1_SEL] =3D &s4_hevcf_p1_sel.hw, [CLKID_HEVCF_P1_DIV] =3D &s4_hevcf_p1_div.hw, [CLKID_HEVCF_P1] =3D &s4_hevcf_p1.hw, - [CLKID_HEVCF_SEL] =3D &s4_hevcf_mux.hw, + [CLKID_HEVCF_SEL] =3D &s4_hevcf_sel.hw, [CLKID_VPU_0_SEL] =3D &s4_vpu_0_sel.hw, [CLKID_VPU_0_DIV] =3D &s4_vpu_0_div.hw, [CLKID_VPU_0] =3D &s4_vpu_0.hw, @@ -3327,18 +3321,18 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_VPU_1_DIV] =3D &s4_vpu_1_div.hw, [CLKID_VPU_1] =3D &s4_vpu_1.hw, [CLKID_VPU] =3D &s4_vpu.hw, - [CLKID_VPU_CLKB_TMP_SEL] =3D &s4_vpu_clkb_tmp_mux.hw, + [CLKID_VPU_CLKB_TMP_SEL] =3D &s4_vpu_clkb_tmp_sel.hw, [CLKID_VPU_CLKB_TMP_DIV] =3D &s4_vpu_clkb_tmp_div.hw, [CLKID_VPU_CLKB_TMP] =3D &s4_vpu_clkb_tmp.hw, [CLKID_VPU_CLKB_DIV] =3D &s4_vpu_clkb_div.hw, [CLKID_VPU_CLKB] =3D &s4_vpu_clkb.hw, - [CLKID_VPU_CLKC_P0_SEL] =3D &s4_vpu_clkc_p0_mux.hw, + [CLKID_VPU_CLKC_P0_SEL] =3D &s4_vpu_clkc_p0_sel.hw, [CLKID_VPU_CLKC_P0_DIV] =3D &s4_vpu_clkc_p0_div.hw, [CLKID_VPU_CLKC_P0] =3D &s4_vpu_clkc_p0.hw, - [CLKID_VPU_CLKC_P1_SEL] =3D &s4_vpu_clkc_p1_mux.hw, + [CLKID_VPU_CLKC_P1_SEL] =3D &s4_vpu_clkc_p1_sel.hw, [CLKID_VPU_CLKC_P1_DIV] =3D &s4_vpu_clkc_p1_div.hw, [CLKID_VPU_CLKC_P1] =3D &s4_vpu_clkc_p1.hw, - [CLKID_VPU_CLKC_SEL] =3D &s4_vpu_clkc_mux.hw, + [CLKID_VPU_CLKC_SEL] =3D &s4_vpu_clkc_sel.hw, [CLKID_VAPB_0_SEL] =3D &s4_vapb_0_sel.hw, [CLKID_VAPB_0_DIV] =3D &s4_vapb_0_div.hw, [CLKID_VAPB_0] =3D &s4_vapb_0.hw, @@ -3346,10 +3340,10 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_VAPB_1_DIV] =3D &s4_vapb_1_div.hw, [CLKID_VAPB_1] =3D &s4_vapb_1.hw, [CLKID_VAPB] =3D &s4_vapb.hw, - [CLKID_GE2D] =3D &s4_ge2d_gate.hw, - [CLKID_VDIN_MEAS_SEL] =3D &s4_vdin_meas_mux.hw, + [CLKID_GE2D] =3D &s4_ge2d.hw, + [CLKID_VDIN_MEAS_SEL] =3D &s4_vdin_meas_sel.hw, [CLKID_VDIN_MEAS_DIV] =3D &s4_vdin_meas_div.hw, - [CLKID_VDIN_MEAS] =3D &s4_vdin_meas_gate.hw, + [CLKID_VDIN_MEAS] =3D &s4_vdin_meas.hw, [CLKID_SD_EMMC_C_CLK_SEL] =3D &s4_sd_emmc_c_clk0_sel.hw, [CLKID_SD_EMMC_C_CLK_DIV] =3D &s4_sd_emmc_c_clk0_div.hw, [CLKID_SD_EMMC_C] =3D &s4_sd_emmc_c_clk0.hw, @@ -3359,42 +3353,42 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_SD_EMMC_B_CLK_SEL] =3D &s4_sd_emmc_b_clk0_sel.hw, [CLKID_SD_EMMC_B_CLK_DIV] =3D &s4_sd_emmc_b_clk0_div.hw, [CLKID_SD_EMMC_B] =3D &s4_sd_emmc_b_clk0.hw, - [CLKID_SPICC0_SEL] =3D &s4_spicc0_mux.hw, + [CLKID_SPICC0_SEL] =3D &s4_spicc0_sel.hw, [CLKID_SPICC0_DIV] =3D &s4_spicc0_div.hw, - [CLKID_SPICC0_EN] =3D &s4_spicc0_gate.hw, - [CLKID_PWM_A_SEL] =3D &s4_pwm_a_mux.hw, + [CLKID_SPICC0_EN] =3D &s4_spicc0_en.hw, + [CLKID_PWM_A_SEL] =3D &s4_pwm_a_sel.hw, [CLKID_PWM_A_DIV] =3D &s4_pwm_a_div.hw, - [CLKID_PWM_A] =3D &s4_pwm_a_gate.hw, - [CLKID_PWM_B_SEL] =3D &s4_pwm_b_mux.hw, + [CLKID_PWM_A] =3D &s4_pwm_a.hw, + [CLKID_PWM_B_SEL] =3D &s4_pwm_b_sel.hw, [CLKID_PWM_B_DIV] =3D &s4_pwm_b_div.hw, - [CLKID_PWM_B] =3D &s4_pwm_b_gate.hw, - [CLKID_PWM_C_SEL] =3D &s4_pwm_c_mux.hw, + [CLKID_PWM_B] =3D &s4_pwm_b.hw, + [CLKID_PWM_C_SEL] =3D &s4_pwm_c_sel.hw, [CLKID_PWM_C_DIV] =3D &s4_pwm_c_div.hw, - [CLKID_PWM_C] =3D &s4_pwm_c_gate.hw, - [CLKID_PWM_D_SEL] =3D &s4_pwm_d_mux.hw, + [CLKID_PWM_C] =3D &s4_pwm_c.hw, + [CLKID_PWM_D_SEL] =3D &s4_pwm_d_sel.hw, [CLKID_PWM_D_DIV] =3D &s4_pwm_d_div.hw, - [CLKID_PWM_D] =3D &s4_pwm_d_gate.hw, - [CLKID_PWM_E_SEL] =3D &s4_pwm_e_mux.hw, + [CLKID_PWM_D] =3D &s4_pwm_d.hw, + [CLKID_PWM_E_SEL] =3D &s4_pwm_e_sel.hw, [CLKID_PWM_E_DIV] =3D &s4_pwm_e_div.hw, - [CLKID_PWM_E] =3D &s4_pwm_e_gate.hw, - [CLKID_PWM_F_SEL] =3D &s4_pwm_f_mux.hw, + [CLKID_PWM_E] =3D &s4_pwm_e.hw, + [CLKID_PWM_F_SEL] =3D &s4_pwm_f_sel.hw, [CLKID_PWM_F_DIV] =3D &s4_pwm_f_div.hw, - [CLKID_PWM_F] =3D &s4_pwm_f_gate.hw, - [CLKID_PWM_G_SEL] =3D &s4_pwm_g_mux.hw, + [CLKID_PWM_F] =3D &s4_pwm_f.hw, + [CLKID_PWM_G_SEL] =3D &s4_pwm_g_sel.hw, [CLKID_PWM_G_DIV] =3D &s4_pwm_g_div.hw, - [CLKID_PWM_G] =3D &s4_pwm_g_gate.hw, - [CLKID_PWM_H_SEL] =3D &s4_pwm_h_mux.hw, + [CLKID_PWM_G] =3D &s4_pwm_g.hw, + [CLKID_PWM_H_SEL] =3D &s4_pwm_h_sel.hw, [CLKID_PWM_H_DIV] =3D &s4_pwm_h_div.hw, - [CLKID_PWM_H] =3D &s4_pwm_h_gate.hw, - [CLKID_PWM_I_SEL] =3D &s4_pwm_i_mux.hw, + [CLKID_PWM_H] =3D &s4_pwm_h.hw, + [CLKID_PWM_I_SEL] =3D &s4_pwm_i_sel.hw, [CLKID_PWM_I_DIV] =3D &s4_pwm_i_div.hw, - [CLKID_PWM_I] =3D &s4_pwm_i_gate.hw, - [CLKID_PWM_J_SEL] =3D &s4_pwm_j_mux.hw, + [CLKID_PWM_I] =3D &s4_pwm_i.hw, + [CLKID_PWM_J_SEL] =3D &s4_pwm_j_sel.hw, [CLKID_PWM_J_DIV] =3D &s4_pwm_j_div.hw, - [CLKID_PWM_J] =3D &s4_pwm_j_gate.hw, - [CLKID_SARADC_SEL] =3D &s4_saradc_mux.hw, + [CLKID_PWM_J] =3D &s4_pwm_j.hw, + [CLKID_SARADC_SEL] =3D &s4_saradc_sel.hw, [CLKID_SARADC_DIV] =3D &s4_saradc_div.hw, - [CLKID_SARADC] =3D &s4_saradc_gate.hw, + [CLKID_SARADC] =3D &s4_saradc.hw, [CLKID_GEN_SEL] =3D &s4_gen_clk_sel.hw, [CLKID_GEN_DIV] =3D &s4_gen_clk_div.hw, [CLKID_GEN] =3D &s4_gen_clk.hw, @@ -3447,27 +3441,27 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_PWM_EF] =3D &s4_pwm_ef.hw, [CLKID_PWM_GH] =3D &s4_pwm_gh.hw, [CLKID_PWM_IJ] =3D &s4_pwm_ij.hw, - [CLKID_HDCP22_ESMCLK_SEL] =3D &s4_hdcp22_esmclk_mux.hw, + [CLKID_HDCP22_ESMCLK_SEL] =3D &s4_hdcp22_esmclk_sel.hw, [CLKID_HDCP22_ESMCLK_DIV] =3D &s4_hdcp22_esmclk_div.hw, - [CLKID_HDCP22_ESMCLK] =3D &s4_hdcp22_esmclk_gate.hw, - [CLKID_HDCP22_SKPCLK_SEL] =3D &s4_hdcp22_skpclk_mux.hw, + [CLKID_HDCP22_ESMCLK] =3D &s4_hdcp22_esmclk.hw, + [CLKID_HDCP22_SKPCLK_SEL] =3D &s4_hdcp22_skpclk_sel.hw, [CLKID_HDCP22_SKPCLK_DIV] =3D &s4_hdcp22_skpclk_div.hw, - [CLKID_HDCP22_SKPCLK] =3D &s4_hdcp22_skpclk_gate.hw, + [CLKID_HDCP22_SKPCLK] =3D &s4_hdcp22_skpclk.hw, }; =20 -static const struct regmap_config clkc_regmap_config =3D { +static const struct regmap_config s4_peripherals_regmap_cfg =3D { .reg_bits =3D 32, .val_bits =3D 32, .reg_stride =3D 4, .max_register =3D CLKCTRL_DEMOD_CLK_CTRL, }; =20 -static struct meson_clk_hw_data s4_periphs_clks =3D { - .hws =3D s4_periphs_hw_clks, - .num =3D ARRAY_SIZE(s4_periphs_hw_clks), +static struct meson_clk_hw_data s4_peripherals_clks =3D { + .hws =3D s4_peripherals_hw_clks, + .num =3D ARRAY_SIZE(s4_peripherals_hw_clks), }; =20 -static int meson_s4_periphs_probe(struct platform_device *pdev) +static int s4_peripherals_clkc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct regmap *regmap; @@ -3479,41 +3473,41 @@ static int meson_s4_periphs_probe(struct platform_d= evice *pdev) return dev_err_probe(dev, PTR_ERR(base), "can't ioremap resource\n"); =20 - regmap =3D devm_regmap_init_mmio(dev, base, &clkc_regmap_config); + regmap =3D devm_regmap_init_mmio(dev, base, &s4_peripherals_regmap_cfg); if (IS_ERR(regmap)) return dev_err_probe(dev, PTR_ERR(regmap), "can't init regmap mmio region\n"); =20 - for (i =3D 0; i < s4_periphs_clks.num; i++) { + for (i =3D 0; i < s4_peripherals_clks.num; i++) { /* array might be sparse */ - if (!s4_periphs_clks.hws[i]) + if (!s4_peripherals_clks.hws[i]) continue; =20 - ret =3D devm_clk_hw_register(dev, s4_periphs_clks.hws[i]); + ret =3D devm_clk_hw_register(dev, s4_peripherals_clks.hws[i]); if (ret) return dev_err_probe(dev, ret, "clock[%d] registration failed\n", i); } =20 - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &s4_periphs_clk= s); + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &s4_peripherals= _clks); } =20 -static const struct of_device_id clkc_match_table[] =3D { +static const struct of_device_id s4_peripherals_clkc_match_table[] =3D { { .compatible =3D "amlogic,s4-peripherals-clkc", }, {} }; -MODULE_DEVICE_TABLE(of, clkc_match_table); +MODULE_DEVICE_TABLE(of, s4_peripherals_clkc_match_table); =20 -static struct platform_driver s4_driver =3D { - .probe =3D meson_s4_periphs_probe, +static struct platform_driver s4_peripherals_clkc_driver =3D { + .probe =3D s4_peripherals_clkc_probe, .driver =3D { - .name =3D "s4-periphs-clkc", - .of_match_table =3D clkc_match_table, + .name =3D "s4-peripherals-clkc", + .of_match_table =3D s4_peripherals_clkc_match_table, }, }; -module_platform_driver(s4_driver); +module_platform_driver(s4_peripherals_clkc_driver); =20 MODULE_DESCRIPTION("Amlogic S4 Peripherals Clock Controller driver"); MODULE_AUTHOR("Yu Tu "); --=20 2.47.2 From nobody Wed Oct 8 03:53:54 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53E6A2D77F9 for ; Wed, 2 Jul 2025 15:27:29 +0000 (UTC) Authentication-Results: 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linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5678; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=dC9fR8dCdw4MCQUXs1TojL+gHHZbG5T/NoHzphabgSQ=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoZU/Cb4CPYZbTpqqMqeEnIIzKTx98YsF4CpOXs g22PqNoH+qJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaGVPwgAKCRDm/A8cN/La hbj3D/9AlTWRQKxJvRMqH0OwhcZmalTSE/pG2jXaJzmTrcfcgpDcCzFzXAxcZuDxcyUcN6g9ttK 6bwS1tayEcEjBu/LXNB03lvhsWpqQoPWhDDhzTteUghXJ9yHuRF+9ZwWkHn+IM89yvK6YN7BqsY kGusxRPWqn2zCm46iXxQGOAfD5dX8kfjZ8DoDgubSsQNzxIy5z3yH/3W+uDJWigcyPr9qRhG167 JzC4heYPQAKRfNKmBUIidV+ZBWtXkWPAG/+J03isGCff0MrDpl0C7ADP4gTmbcBEJsqEsN/mgrL qigVFg4POSi7VUbqP3x3XtKbGqu441Y7s4ZNz1QxrStvwkKlywplK2bYlj/siFgODuD8uqoaZIW FMo+S6wD95tNtE0Ctlvefq4iFQcLC3UM+KrEhyWuzTYJj2Gh5975BlJf2dQZqwCz9eYBldWc1XU 3vtKQ4ZXLxK+4Kfdsn/gFDzqoysdpSElhbpiC0OPgxTnx9ZmC/MMV7i13vfVFZiJKEuv/26x0Sc U/rxZbo6DqStQSxWXQ23/xcAjbyt3ek7ugPVE3iYizo6X1nUK6XD5P4TGkOKifIpo5napvHp7dl JxZLEVlonS2j27OeI5/I1wWDVW7jDzo0EaK2sA1vSPfzQpCFHDCE+B1/F9rDozcGbBEOJxLD2gQ HUlXyDIhr1HhK+g== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet Reviewed-by: Chuan Liu --- drivers/clk/meson/s4-pll.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c index 3d689d2f003e21658016b84918bf1b7b1954c05a..6a266bcafd6257937c1de50cbc5= 606dcc6f8207b 100644 --- a/drivers/clk/meson/s4-pll.c +++ b/drivers/clk/meson/s4-pll.c @@ -281,7 +281,7 @@ static const struct pll_mult_range s4_gp0_pll_mult_rang= e =3D { /* * Internal gp0 pll emulation configuration parameters */ -static const struct reg_sequence s4_gp0_init_regs[] =3D { +static const struct reg_sequence s4_gp0_pll_init_regs[] =3D { { .reg =3D ANACTRL_GP0PLL_CTRL1, .def =3D 0x00000000 }, { .reg =3D ANACTRL_GP0PLL_CTRL2, .def =3D 0x00000000 }, { .reg =3D ANACTRL_GP0PLL_CTRL3, .def =3D 0x48681c00 }, @@ -318,8 +318,8 @@ static struct clk_regmap s4_gp0_pll_dco =3D { .width =3D 1, }, .range =3D &s4_gp0_pll_mult_range, - .init_regs =3D s4_gp0_init_regs, - .init_count =3D ARRAY_SIZE(s4_gp0_init_regs), + .init_regs =3D s4_gp0_pll_init_regs, + .init_count =3D ARRAY_SIZE(s4_gp0_pll_init_regs), }, .hw.init =3D &(struct clk_init_data){ .name =3D "gp0_pll_dco", @@ -353,7 +353,7 @@ static struct clk_regmap s4_gp0_pll =3D { /* * Internal hifi pll emulation configuration parameters */ -static const struct reg_sequence s4_hifi_init_regs[] =3D { +static const struct reg_sequence s4_hifi_pll_init_regs[] =3D { { .reg =3D ANACTRL_HIFIPLL_CTRL2, .def =3D 0x00000000 }, { .reg =3D ANACTRL_HIFIPLL_CTRL3, .def =3D 0x6a285c00 }, { .reg =3D ANACTRL_HIFIPLL_CTRL4, .def =3D 0x65771290 }, @@ -394,8 +394,8 @@ static struct clk_regmap s4_hifi_pll_dco =3D { .width =3D 1, }, .range =3D &s4_gp0_pll_mult_range, - .init_regs =3D s4_hifi_init_regs, - .init_count =3D ARRAY_SIZE(s4_hifi_init_regs), + .init_regs =3D s4_hifi_pll_init_regs, + .init_count =3D ARRAY_SIZE(s4_hifi_pll_init_regs), .frac_max =3D 100000, .flags =3D CLK_MESON_PLL_ROUND_CLOSEST, }, @@ -794,11 +794,11 @@ static struct clk_hw *s4_pll_hw_clks[] =3D { [CLKID_MPLL3] =3D &s4_mpll3.hw, }; =20 -static const struct reg_sequence s4_init_regs[] =3D { +static const struct reg_sequence s4_pll_init_regs[] =3D { { .reg =3D ANACTRL_MPLL_CTRL0, .def =3D 0x00000543 }, }; =20 -static const struct regmap_config clkc_regmap_config =3D { +static const struct regmap_config s4_pll_clkc_regmap_cfg =3D { .reg_bits =3D 32, .val_bits =3D 32, .reg_stride =3D 4, @@ -810,7 +810,7 @@ static struct meson_clk_hw_data s4_pll_clks =3D { .num =3D ARRAY_SIZE(s4_pll_hw_clks), }; =20 -static int meson_s4_pll_probe(struct platform_device *pdev) +static int s4_pll_clkc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct regmap *regmap; @@ -822,12 +822,12 @@ static int meson_s4_pll_probe(struct platform_device = *pdev) return dev_err_probe(dev, PTR_ERR(base), "can't ioremap resource\n"); =20 - regmap =3D devm_regmap_init_mmio(dev, base, &clkc_regmap_config); + regmap =3D devm_regmap_init_mmio(dev, base, &s4_pll_clkc_regmap_cfg); if (IS_ERR(regmap)) return dev_err_probe(dev, PTR_ERR(regmap), "can't init regmap mmio region\n"); =20 - ret =3D regmap_multi_reg_write(regmap, s4_init_regs, ARRAY_SIZE(s4_init_r= egs)); + ret =3D regmap_multi_reg_write(regmap, s4_pll_init_regs, ARRAY_SIZE(s4_pl= l_init_regs)); if (ret) return dev_err_probe(dev, ret, "Failed to init registers\n"); @@ -848,22 +848,22 @@ static int meson_s4_pll_probe(struct platform_device = *pdev) &s4_pll_clks); } =20 -static const struct of_device_id clkc_match_table[] =3D { +static const struct of_device_id s4_pll_clkc_match_table[] =3D { { .compatible =3D "amlogic,s4-pll-clkc", }, {} }; -MODULE_DEVICE_TABLE(of, clkc_match_table); +MODULE_DEVICE_TABLE(of, s4_pll_clkc_match_table); =20 -static struct platform_driver s4_driver =3D { - .probe =3D meson_s4_pll_probe, +static struct platform_driver s4_pll_clkc_driver =3D { + .probe =3D s4_pll_clkc_probe, .driver =3D { .name =3D "s4-pll-clkc", - .of_match_table =3D clkc_match_table, + .of_match_table =3D s4_pll_clkc_match_table, }, }; -module_platform_driver(s4_driver); +module_platform_driver(s4_pll_clkc_driver); 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson8-ddr.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/clk/meson/meson8-ddr.c b/drivers/clk/meson/meson8-ddr.c index 1975fc3987e2cb28823ffd69a5e2aa7b33f4853e..6a9efde9b570d8a2609c118d7d3= 8334a3b4a5dcc 100644 --- a/drivers/clk/meson/meson8-ddr.c +++ b/drivers/clk/meson/meson8-ddr.c @@ -12,6 +12,7 @@ =20 #include "clk-regmap.h" #include "clk-pll.h" +#include "meson-clkc-utils.h" =20 #define AM_DDR_PLL_CNTL 0x00 #define AM_DDR_PLL_CNTL1 0x04 @@ -77,15 +78,17 @@ static struct clk_regmap meson8_ddr_pll =3D { }, }; =20 -static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data =3D { - .hws =3D { - [DDR_CLKID_DDR_PLL_DCO] =3D &meson8_ddr_pll_dco.hw, - [DDR_CLKID_DDR_PLL] =3D &meson8_ddr_pll.hw, - }, - .num =3D 2, +static struct clk_hw *meson8_ddr_hw_clks[] =3D { + [DDR_CLKID_DDR_PLL_DCO] =3D &meson8_ddr_pll_dco.hw, + [DDR_CLKID_DDR_PLL] =3D &meson8_ddr_pll.hw, +}; + +static struct meson_clk_hw_data meson8_ddr_clks =3D { + .hws =3D meson8_ddr_hw_clks, + .num =3D ARRAY_SIZE(meson8_ddr_hw_clks), }; =20 -static const struct regmap_config meson8_ddr_clkc_regmap_config =3D { +static const struct regmap_config meson8_ddr_regmap_cfg =3D { .reg_bits =3D 8, .val_bits =3D 32, .reg_stride =3D 4, @@ -104,13 +107,13 @@ static int meson8_ddr_clkc_probe(struct platform_devi= ce *pdev) return PTR_ERR(base); =20 regmap =3D devm_regmap_init_mmio(&pdev->dev, base, - &meson8_ddr_clkc_regmap_config); + &meson8_ddr_regmap_cfg); if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 /* Register all clks */ - for (i =3D 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) { - hw =3D meson8_ddr_clk_hw_onecell_data.hws[i]; + for (i =3D 0; i < meson8_ddr_clks.num; i++) { + hw =3D meson8_ddr_clks.hws[i]; =20 ret =3D devm_clk_hw_register(&pdev->dev, hw); if (ret) { @@ -119,8 +122,8 @@ static int meson8_ddr_clkc_probe(struct platform_device= *pdev) } } =20 - return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, - &meson8_ddr_clk_hw_onecell_data); + return devm_of_clk_add_hw_provider(&pdev->dev, meson_clk_hw_get, + &meson8_ddr_clks); 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 What is being done by the Amlogic clock controller registration helper for EE controllers could benefit other controllers. As such, having a specific module for this makes little sense. Move the helper function to clkc-utils and rename it to describe what it does, registering syscon based controller, instead of what it serves. Signed-off-by: Jerome Brunet --- drivers/clk/meson/Kconfig | 13 +++----- drivers/clk/meson/Makefile | 1 - drivers/clk/meson/axg.c | 6 ++-- drivers/clk/meson/g12a.c | 28 ++++++++--------- drivers/clk/meson/gxbb.c | 8 ++--- drivers/clk/meson/meson-clkc-utils.c | 50 +++++++++++++++++++++++++++++- drivers/clk/meson/meson-clkc-utils.h | 10 ++++++ drivers/clk/meson/meson-eeclk.c | 60 --------------------------------= ---- drivers/clk/meson/meson-eeclk.h | 24 --------------- 9 files changed, 85 insertions(+), 115 deletions(-) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 7197d23543b8bb8a9020cde316170b50bc359a6c..71481607a6d55d14898f9ecca68= f004ccc6f6231 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -36,6 +36,8 @@ config COMMON_CLK_MESON_VCLK select COMMON_CLK_MESON_REGMAP =20 config COMMON_CLK_MESON_CLKC_UTILS + select REGMAP + select MFD_SYSCON tristate =20 config COMMON_CLK_MESON_AO_CLKC @@ -44,11 +46,6 @@ config COMMON_CLK_MESON_AO_CLKC select COMMON_CLK_MESON_CLKC_UTILS select RESET_CONTROLLER =20 -config COMMON_CLK_MESON_EE_CLKC - tristate - select COMMON_CLK_MESON_REGMAP - select COMMON_CLK_MESON_CLKC_UTILS - config COMMON_CLK_MESON_CPU_DYNDIV tristate select COMMON_CLK_MESON_REGMAP @@ -73,12 +70,12 @@ config COMMON_CLK_GXBB depends on ARM64 default ARCH_MESON select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_VID_PLL_DIV select COMMON_CLK_MESON_MPLL select COMMON_CLK_MESON_PLL select COMMON_CLK_MESON_AO_CLKC - select COMMON_CLK_MESON_EE_CLKC select MFD_SYSCON help Support for the clock controller on AmLogic S905 devices, aka gxbb. @@ -89,11 +86,11 @@ config COMMON_CLK_AXG depends on ARM64 default ARCH_MESON select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_MPLL select COMMON_CLK_MESON_PLL select COMMON_CLK_MESON_AO_CLKC - select COMMON_CLK_MESON_EE_CLKC select MFD_SYSCON help Support for the clock controller on AmLogic A113D devices, aka axg. @@ -167,11 +164,11 @@ config COMMON_CLK_G12A depends on ARM64 default ARCH_MESON select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_MPLL select COMMON_CLK_MESON_PLL select COMMON_CLK_MESON_AO_CLKC - select COMMON_CLK_MESON_EE_CLKC select COMMON_CLK_MESON_CPU_DYNDIV select COMMON_CLK_MESON_VID_PLL_DIV select COMMON_CLK_MESON_VCLK diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index bc56a47931c1d27db7dde72b73d9842c93e74f62..c6998e752c683ec9d1736a6811b= 1cfd71559b289 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_COMMON_CLK_MESON_CLKC_UTILS) +=3D meson-clkc-u= tils.o obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) +=3D meson-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) +=3D clk-cpu-dyndiv.o obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) +=3D clk-dualdiv.o -obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) +=3D meson-eeclk.o obj-$(CONFIG_COMMON_CLK_MESON_MPLL) +=3D clk-mpll.o obj-$(CONFIG_COMMON_CLK_MESON_PHASE) +=3D clk-phase.o obj-$(CONFIG_COMMON_CLK_MESON_PLL) +=3D clk-pll.o diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 3839dfe9c7c540c2aec731be84e4e6520264c525..675f051ea5241b0f51e54a23847= 0e4fe947e5ba5 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -18,7 +18,7 @@ #include "clk-regmap.h" #include "clk-pll.h" #include "clk-mpll.h" -#include "meson-eeclk.h" +#include "meson-clkc-utils.h" =20 #include =20 @@ -2110,7 +2110,7 @@ static struct clk_hw *axg_hw_clks[] =3D { [CLKID_VDIN_MEAS] =3D &axg_vdin_meas.hw, }; =20 -static const struct meson_eeclkc_data axg_clkc_data =3D { +static const struct meson_clkc_data axg_clkc_data =3D { .hw_clks =3D { .hws =3D axg_hw_clks, .num =3D ARRAY_SIZE(axg_hw_clks), @@ -2124,7 +2124,7 @@ static const struct of_device_id axg_clkc_match_table= [] =3D { MODULE_DEVICE_TABLE(of, axg_clkc_match_table); =20 static struct platform_driver axg_clkc_driver =3D { - .probe =3D meson_eeclkc_probe, + .probe =3D meson_clkc_syscon_probe, .driver =3D { .name =3D "axg-clkc", .of_match_table =3D axg_clkc_match_table, diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 9de0531821a8f0297273189b44a81024d8bf9093..cdaaa165a0ff1f3b4d5250a9642= 8c54cc3e37381 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -23,7 +23,7 @@ #include "clk-cpu-dyndiv.h" #include "vid-pll-div.h" #include "vclk.h" -#include "meson-eeclk.h" +#include "meson-clkc-utils.h" =20 #include =20 @@ -5360,26 +5360,26 @@ static int g12a_dvfs_setup(struct platform_device *= pdev) } =20 struct g12a_clkc_data { - const struct meson_eeclkc_data eeclkc_data; + const struct meson_clkc_data clkc_data; int (*dvfs_setup)(struct platform_device *pdev); }; =20 static int g12a_clkc_probe(struct platform_device *pdev) { - const struct meson_eeclkc_data *eeclkc_data; + const struct meson_clkc_data *clkc_data; const struct g12a_clkc_data *g12a_data; int ret; =20 - eeclkc_data =3D of_device_get_match_data(&pdev->dev); - if (!eeclkc_data) + clkc_data =3D of_device_get_match_data(&pdev->dev); + if (!clkc_data) return -EINVAL; =20 - ret =3D meson_eeclkc_probe(pdev); + ret =3D meson_clkc_syscon_probe(pdev); if (ret) return ret; =20 - g12a_data =3D container_of(eeclkc_data, struct g12a_clkc_data, - eeclkc_data); + g12a_data =3D container_of(clkc_data, struct g12a_clkc_data, + clkc_data); =20 if (g12a_data->dvfs_setup) return g12a_data->dvfs_setup(pdev); @@ -5388,7 +5388,7 @@ static int g12a_clkc_probe(struct platform_device *pd= ev) } =20 static const struct g12a_clkc_data g12a_clkc_data =3D { - .eeclkc_data =3D { + .clkc_data =3D { .hw_clks =3D { .hws =3D g12a_hw_clks, .num =3D ARRAY_SIZE(g12a_hw_clks), @@ -5400,7 +5400,7 @@ static const struct g12a_clkc_data g12a_clkc_data =3D= { }; =20 static const struct g12a_clkc_data g12b_clkc_data =3D { - .eeclkc_data =3D { + .clkc_data =3D { .hw_clks =3D { .hws =3D g12b_hw_clks, .num =3D ARRAY_SIZE(g12b_hw_clks), @@ -5410,7 +5410,7 @@ static const struct g12a_clkc_data g12b_clkc_data =3D= { }; =20 static const struct g12a_clkc_data sm1_clkc_data =3D { - .eeclkc_data =3D { + .clkc_data =3D { .hw_clks =3D { .hws =3D sm1_hw_clks, .num =3D ARRAY_SIZE(sm1_hw_clks), @@ -5422,15 +5422,15 @@ static const struct g12a_clkc_data sm1_clkc_data = =3D { static const struct of_device_id g12a_clkc_match_table[] =3D { { .compatible =3D "amlogic,g12a-clkc", - .data =3D &g12a_clkc_data.eeclkc_data + .data =3D &g12a_clkc_data.clkc_data }, { .compatible =3D "amlogic,g12b-clkc", - .data =3D &g12b_clkc_data.eeclkc_data + .data =3D &g12b_clkc_data.clkc_data }, { .compatible =3D "amlogic,sm1-clkc", - .data =3D &sm1_clkc_data.eeclkc_data + .data =3D &sm1_clkc_data.clkc_data }, {} }; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index f969e3cf9566de5dff615d59360729d963507b36..a57cdf884ae900f8651b2cd84c5= 019270e684026 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -13,7 +13,7 @@ #include "clk-regmap.h" #include "clk-pll.h" #include "clk-mpll.h" -#include "meson-eeclk.h" +#include "meson-clkc-utils.h" #include "vid-pll-div.h" =20 #include @@ -3234,14 +3234,14 @@ static struct clk_hw *gxl_hw_clks[] =3D { [CLKID_ACODEC] =3D &gxl_acodec.hw, }; =20 -static const struct meson_eeclkc_data gxbb_clkc_data =3D { +static const struct meson_clkc_data gxbb_clkc_data =3D { .hw_clks =3D { .hws =3D gxbb_hw_clks, .num =3D ARRAY_SIZE(gxbb_hw_clks), }, }; =20 -static const struct meson_eeclkc_data gxl_clkc_data =3D { +static const struct meson_clkc_data gxl_clkc_data =3D { .hw_clks =3D { .hws =3D gxl_hw_clks, .num =3D ARRAY_SIZE(gxl_hw_clks), @@ -3256,7 +3256,7 @@ static const struct of_device_id gxbb_clkc_match_tabl= e[] =3D { MODULE_DEVICE_TABLE(of, gxbb_clkc_match_table); =20 static struct platform_driver gxbb_clkc_driver =3D { - .probe =3D meson_eeclkc_probe, + .probe =3D meson_clkc_syscon_probe, .driver =3D { .name =3D "gxbb-clkc", .of_match_table =3D gxbb_clkc_match_table, diff --git a/drivers/clk/meson/meson-clkc-utils.c b/drivers/clk/meson/meson= -clkc-utils.c index 6937d1482719bda00da127381025a165907e5db6..49f562d0f203b9a7d15b5119100= 216564c10cb21 100644 --- a/drivers/clk/meson/meson-clkc-utils.c +++ b/drivers/clk/meson/meson-clkc-utils.c @@ -3,9 +3,13 @@ * Copyright (c) 2023 Neil Armstrong */ =20 -#include #include +#include #include +#include +#include +#include + #include "meson-clkc-utils.h" =20 struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk= _hw_data) @@ -22,6 +26,50 @@ struct clk_hw *meson_clk_hw_get(struct of_phandle_args *= clkspec, void *clk_hw_da } EXPORT_SYMBOL_NS_GPL(meson_clk_hw_get, "CLK_MESON"); =20 +int meson_clkc_syscon_probe(struct platform_device *pdev) +{ + const struct meson_clkc_data *data; + struct device *dev =3D &pdev->dev; + struct device_node *np; + struct regmap *map; + struct clk_hw *hw; + int ret, i; + + data =3D of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + np =3D of_get_parent(dev->of_node); + map =3D syscon_node_to_regmap(np); + of_node_put(np); + if (IS_ERR(map)) { + dev_err(dev, + "failed to get parent syscon regmap\n"); + return PTR_ERR(map); + } + + if (data->init_count) + regmap_multi_reg_write(map, data->init_regs, data->init_count); + + for (i =3D 0; i < data->hw_clks.num; i++) { + hw =3D data->hw_clks.hws[i]; + + /* array might be sparse */ + if (!hw) + continue; + + ret =3D devm_clk_hw_register(dev, hw); + if (ret) { + dev_err(dev, "registering %s clock failed\n", + hw->init->name); + return ret; + } + } + + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->= hw_clks); +} +EXPORT_SYMBOL_NS_GPL(meson_clkc_syscon_probe, "CLK_MESON"); + MODULE_DESCRIPTION("Amlogic Clock Controller Utilities"); MODULE_LICENSE("GPL"); MODULE_IMPORT_NS("CLK_MESON"); diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index fe6f407289496c5c4821b7c9e5a6b6e8a45068b2..26cd47544302b28ca1a342e1789= 56559a84b152a 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -9,6 +9,8 @@ #include #include =20 +struct platform_device; + struct meson_clk_hw_data { struct clk_hw **hws; unsigned int num; @@ -16,4 +18,12 @@ struct meson_clk_hw_data { =20 struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk= _hw_data); =20 +struct meson_clkc_data { + const struct reg_sequence *init_regs; + unsigned int init_count; + struct meson_clk_hw_data hw_clks; +}; + +int meson_clkc_syscon_probe(struct platform_device *pdev); + #endif diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eecl= k.c deleted file mode 100644 index 6236bf970d79e85b1e739c713c03f35a00c291b9..000000000000000000000000000= 0000000000000 --- a/drivers/clk/meson/meson-eeclk.c +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet - */ - -#include -#include -#include -#include -#include -#include - -#include "clk-regmap.h" -#include "meson-eeclk.h" - -int meson_eeclkc_probe(struct platform_device *pdev) -{ - const struct meson_eeclkc_data *data; - struct device *dev =3D &pdev->dev; - struct device_node *np; - struct regmap *map; - int ret, i; - - data =3D of_device_get_match_data(dev); - if (!data) - return -EINVAL; - - /* Get the hhi system controller node */ - np =3D of_get_parent(dev->of_node); - map =3D syscon_node_to_regmap(np); - of_node_put(np); - if (IS_ERR(map)) { - dev_err(dev, - "failed to get HHI regmap\n"); - return PTR_ERR(map); - } - - if (data->init_count) - regmap_multi_reg_write(map, data->init_regs, data->init_count); - - for (i =3D 0; i < data->hw_clks.num; i++) { - /* array might be sparse */ - if (!data->hw_clks.hws[i]) - continue; - - ret =3D devm_clk_hw_register(dev, data->hw_clks.hws[i]); - if (ret) { - dev_err(dev, "Clock registration failed\n"); - return ret; - } - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->= hw_clks); -} -EXPORT_SYMBOL_NS_GPL(meson_eeclkc_probe, "CLK_MESON"); - -MODULE_DESCRIPTION("Amlogic Main Clock Controller Helpers"); -MODULE_LICENSE("GPL"); -MODULE_IMPORT_NS("CLK_MESON"); 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Add a 2nd probe function helper for mmio based controllers, which are getting the memory region from a resource instead of a syscon. Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson-clkc-utils.c | 65 ++++++++++++++++++++++++++++----= ---- drivers/clk/meson/meson-clkc-utils.h | 1 + 2 files changed, 53 insertions(+), 13 deletions(-) diff --git a/drivers/clk/meson/meson-clkc-utils.c b/drivers/clk/meson/meson= -clkc-utils.c index 49f562d0f203b9a7d15b5119100216564c10cb21..272b2dd8c95e73e6c021cbf8852= dd64733fa00e0 100644 --- a/drivers/clk/meson/meson-clkc-utils.c +++ b/drivers/clk/meson/meson-clkc-utils.c @@ -26,12 +26,9 @@ struct clk_hw *meson_clk_hw_get(struct of_phandle_args *= clkspec, void *clk_hw_da } EXPORT_SYMBOL_NS_GPL(meson_clk_hw_get, "CLK_MESON"); =20 -int meson_clkc_syscon_probe(struct platform_device *pdev) +static int meson_clkc_init(struct device *dev, struct regmap *map) { const struct meson_clkc_data *data; - struct device *dev =3D &pdev->dev; - struct device_node *np; - struct regmap *map; struct clk_hw *hw; int ret, i; =20 @@ -39,15 +36,6 @@ int meson_clkc_syscon_probe(struct platform_device *pdev) if (!data) return -EINVAL; =20 - np =3D of_get_parent(dev->of_node); - map =3D syscon_node_to_regmap(np); - of_node_put(np); - if (IS_ERR(map)) { - dev_err(dev, - "failed to get parent syscon regmap\n"); - return PTR_ERR(map); - } - if (data->init_count) regmap_multi_reg_write(map, data->init_regs, data->init_count); =20 @@ -68,8 +56,59 @@ int meson_clkc_syscon_probe(struct platform_device *pdev) =20 return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->= hw_clks); } + +int meson_clkc_syscon_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np; + struct regmap *map; + + np =3D of_get_parent(dev->of_node); + map =3D syscon_node_to_regmap(np); + of_node_put(np); + if (IS_ERR(map)) { + dev_err(dev, "failed to get parent syscon regmap\n"); + return PTR_ERR(map); + } + + return meson_clkc_init(dev, map); +} EXPORT_SYMBOL_NS_GPL(meson_clkc_syscon_probe, "CLK_MESON"); =20 +static const struct regmap_config base_clkc_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +int meson_clkc_mmio_probe(struct platform_device *pdev) +{ + const struct meson_clkc_data *data; + struct device *dev =3D &pdev->dev; + struct regmap_config regmap_cfg; + struct resource *res; + void __iomem *base; + struct regmap *map; + + data =3D of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(base)) + return PTR_ERR(base); + + memcpy(®map_cfg, &base_clkc_regmap_cfg, sizeof(regmap_cfg)); + regmap_cfg.max_register =3D resource_size(res) - 4; + + map =3D devm_regmap_init_mmio(dev, base, ®map_cfg); + if (IS_ERR(map)) + return PTR_ERR(map); + + return meson_clkc_init(dev, map); +} +EXPORT_SYMBOL_NS_GPL(meson_clkc_mmio_probe, "CLK_MESON"); + MODULE_DESCRIPTION("Amlogic Clock Controller Utilities"); MODULE_LICENSE("GPL"); MODULE_IMPORT_NS("CLK_MESON"); diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index 26cd47544302b28ca1a342e178956559a84b152a..b45f85f630d7190fb6509b088f0= 5f17ca91fa1c8 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -25,5 +25,6 @@ struct meson_clkc_data { }; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Factorize the probe function of the mmio based amlogic clock controllers using the newly introduced probe helper. This removes a fair amount of duplicated code. Signed-off-by: Jerome Brunet Reviewed-by: Chuan Liu --- drivers/clk/meson/a1-peripherals.c | 52 +++++++-------------------------- drivers/clk/meson/a1-pll.c | 52 +++++++-------------------------- drivers/clk/meson/c3-peripherals.c | 51 +++++--------------------------- drivers/clk/meson/c3-pll.c | 49 +++++-------------------------- drivers/clk/meson/meson8-ddr.c | 57 +++++++++-------------------------= -- drivers/clk/meson/s4-peripherals.c | 49 +++++-------------------------- drivers/clk/meson/s4-pll.c | 60 +++++++---------------------------= ---- 7 files changed, 66 insertions(+), 304 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peri= pherals.c index 9e352dba54775c22126ee8bf7861ee1d981d6c88..b2feb8fe4775e38a17d8aa9ce9b= 992b3e1fb2bb8 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -2057,54 +2057,24 @@ static struct clk_hw *a1_peripherals_hw_clks[] =3D { [CLKID_DMC_SEL2] =3D &a1_dmc_sel2.hw, }; =20 -static const struct regmap_config a1_peripherals_regmap_cfg =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D DMC_CLK_CTRL, -}; - -static struct meson_clk_hw_data a1_peripherals_clks =3D { - .hws =3D a1_peripherals_hw_clks, - .num =3D ARRAY_SIZE(a1_peripherals_hw_clks), -}; - -static int a1_peripherals_clkc_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - void __iomem *base; - struct regmap *map; - int clkid, err; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return dev_err_probe(dev, PTR_ERR(base), - "can't ioremap resource\n"); - - map =3D devm_regmap_init_mmio(dev, base, &a1_peripherals_regmap_cfg); - if (IS_ERR(map)) - return dev_err_probe(dev, PTR_ERR(map), - "can't init regmap mmio region\n"); - - for (clkid =3D 0; clkid < a1_peripherals_clks.num; clkid++) { - err =3D devm_clk_hw_register(dev, a1_peripherals_clks.hws[clkid]); - if (err) - return dev_err_probe(dev, err, - "clock[%d] registration failed\n", - clkid); - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_peripherals= _clks); -} +static const struct meson_clkc_data a1_peripherals_clkc_data =3D { + .hw_clks =3D { + .hws =3D a1_peripherals_hw_clks, + .num =3D ARRAY_SIZE(a1_peripherals_hw_clks), + }, +}; =20 static const struct of_device_id a1_peripherals_clkc_match_table[] =3D { - { .compatible =3D "amlogic,a1-peripherals-clkc", }, + { + .compatible =3D "amlogic,a1-peripherals-clkc", + .data =3D &a1_peripherals_clkc_data, + }, {} }; MODULE_DEVICE_TABLE(of, a1_peripherals_clkc_match_table); =20 static struct platform_driver a1_peripherals_clkc_driver =3D { - .probe =3D a1_peripherals_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "a1-peripherals-clkc", .of_match_table =3D a1_peripherals_clkc_match_table, diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index 79ef4cbe955326ecedceb68cda7f59bb8882b165..1f82e9c7c14ebeae5d43cf2623c= 3ab69427a8504 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -295,56 +295,24 @@ static struct clk_hw *a1_pll_hw_clks[] =3D { [CLKID_HIFI_PLL] =3D &a1_hifi_pll.hw, }; =20 -static const struct regmap_config a1_pll_regmap_cfg =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D ANACTRL_HIFIPLL_STS, -}; - -static struct meson_clk_hw_data a1_pll_clks =3D { - .hws =3D a1_pll_hw_clks, - .num =3D ARRAY_SIZE(a1_pll_hw_clks), +static const struct meson_clkc_data a1_pll_clkc_data =3D { + .hw_clks =3D { + .hws =3D a1_pll_hw_clks, + .num =3D ARRAY_SIZE(a1_pll_hw_clks), + }, }; =20 -static int a1_pll_clkc_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - void __iomem *base; - struct regmap *map; - int clkid, err; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return dev_err_probe(dev, PTR_ERR(base), - "can't ioremap resource\n"); - - map =3D devm_regmap_init_mmio(dev, base, &a1_pll_regmap_cfg); - if (IS_ERR(map)) - return dev_err_probe(dev, PTR_ERR(map), - "can't init regmap mmio region\n"); - - /* Register clocks */ - for (clkid =3D 0; clkid < a1_pll_clks.num; clkid++) { - err =3D devm_clk_hw_register(dev, a1_pll_clks.hws[clkid]); - if (err) - return dev_err_probe(dev, err, - "clock[%d] registration failed\n", - clkid); - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, - &a1_pll_clks); -} - static const struct of_device_id a1_pll_clkc_match_table[] =3D { - { .compatible =3D "amlogic,a1-pll-clkc", }, + { + .compatible =3D "amlogic,a1-pll-clkc", + .data =3D &a1_pll_clkc_data, + }, {} }; MODULE_DEVICE_TABLE(of, a1_pll_clkc_match_table); =20 static struct platform_driver a1_pll_clkc_driver =3D { - .probe =3D a1_pll_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "a1-pll-clkc", .of_match_table =3D a1_pll_clkc_match_table, diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c index a09cb1435ab108b2dcc209c6557bcd1988c4ba1a..e9c1ef99be13d0542b8a972ceff= e69c8a9977118 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -2091,52 +2091,17 @@ static struct clk_hw *c3_peripherals_hw_clks[] =3D { [CLKID_VAPB] =3D &c3_vapb.hw, }; =20 -static const struct regmap_config c3_peripherals_regmap_cfg =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D NNA_CLK_CTRL, -}; - -static struct meson_clk_hw_data c3_peripherals_clks =3D { - .hws =3D c3_peripherals_hw_clks, - .num =3D ARRAY_SIZE(c3_peripherals_hw_clks), -}; - -static int c3_peripherals_clkc_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct regmap *regmap; - void __iomem *base; - int clkid, ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - regmap =3D devm_regmap_init_mmio(dev, base, &c3_peripherals_regmap_cfg); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - for (clkid =3D 0; clkid < c3_peripherals_clks.num; clkid++) { - /* array might be sparse */ - if (!c3_peripherals_clks.hws[clkid]) - continue; - - ret =3D devm_clk_hw_register(dev, c3_peripherals_clks.hws[clkid]); - if (ret) { - dev_err(dev, "Clock registration failed\n"); - return ret; - } - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, - &c3_peripherals_clks); -} +static const struct meson_clkc_data c3_peripherals_clkc_data =3D { + .hw_clks =3D { + .hws =3D c3_peripherals_hw_clks, + .num =3D ARRAY_SIZE(c3_peripherals_hw_clks), + }, +}; =20 static const struct of_device_id c3_peripherals_clkc_match_table[] =3D { { .compatible =3D "amlogic,c3-peripherals-clkc", + .data =3D &c3_peripherals_clkc_data, }, { /* sentinel */ } }; @@ -2144,7 +2109,7 @@ static const struct of_device_id c3_peripherals_clkc_= match_table[] =3D { MODULE_DEVICE_TABLE(of, c3_peripherals_clkc_match_table); =20 static struct platform_driver c3_peripherals_clkc_driver =3D { - .probe =3D c3_peripherals_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "c3-peripherals-clkc", .of_match_table =3D c3_peripherals_clkc_match_table, diff --git a/drivers/clk/meson/c3-pll.c b/drivers/clk/meson/c3-pll.c index ccfcd4b5be8996592c27df31fa62d4871c826926..dd047d17488c1309dcc4607dfb5= 5582ea978528d 100644 --- a/drivers/clk/meson/c3-pll.c +++ b/drivers/clk/meson/c3-pll.c @@ -653,59 +653,24 @@ static struct clk_hw *c3_pll_hw_clks[] =3D { [CLKID_MCLK1] =3D &c3_mclk1.hw }; =20 -static const struct regmap_config c3_pll_regmap_cfg =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D ANACTRL_MPLL_CTRL4, -}; - -static struct meson_clk_hw_data c3_pll_clks =3D { - .hws =3D c3_pll_hw_clks, - .num =3D ARRAY_SIZE(c3_pll_hw_clks), +static const struct meson_clkc_data c3_pll_clkc_data =3D { + .hw_clks =3D { + .hws =3D c3_pll_hw_clks, + .num =3D ARRAY_SIZE(c3_pll_hw_clks), + }, }; =20 -static int c3_pll_clkc_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct regmap *regmap; - void __iomem *base; - int clkid, ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - regmap =3D devm_regmap_init_mmio(dev, base, &c3_pll_regmap_cfg); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - for (clkid =3D 0; clkid < c3_pll_clks.num; clkid++) { - /* array might be sparse */ - if (!c3_pll_clks.hws[clkid]) - continue; - - ret =3D devm_clk_hw_register(dev, c3_pll_clks.hws[clkid]); - if (ret) { - dev_err(dev, "Clock registration failed\n"); - return ret; - } - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, - &c3_pll_clks); -} - static const struct of_device_id c3_pll_clkc_match_table[] =3D { { .compatible =3D "amlogic,c3-pll-clkc", + .data =3D &c3_pll_clkc_data, }, {} }; MODULE_DEVICE_TABLE(of, c3_pll_clkc_match_table); =20 static struct platform_driver c3_pll_clkc_driver =3D { - .probe =3D c3_pll_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "c3-pll-clkc", .of_match_table =3D c3_pll_clkc_match_table, diff --git a/drivers/clk/meson/meson8-ddr.c b/drivers/clk/meson/meson8-ddr.c index 6a9efde9b570d8a2609c118d7d38334a3b4a5dcc..0f93774f73718d29afca87b4c60= 1bd32b9745d30 100644 --- a/drivers/clk/meson/meson8-ddr.c +++ b/drivers/clk/meson/meson8-ddr.c @@ -83,57 +83,26 @@ static struct clk_hw *meson8_ddr_hw_clks[] =3D { [DDR_CLKID_DDR_PLL] =3D &meson8_ddr_pll.hw, }; =20 -static struct meson_clk_hw_data meson8_ddr_clks =3D { - .hws =3D meson8_ddr_hw_clks, - .num =3D ARRAY_SIZE(meson8_ddr_hw_clks), -}; - -static const struct regmap_config meson8_ddr_regmap_cfg =3D { - .reg_bits =3D 8, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D DDR_CLK_STS, +static const struct meson_clkc_data meson8_ddr_clkc_data =3D { + .hw_clks =3D { + .hws =3D meson8_ddr_hw_clks, + .num =3D ARRAY_SIZE(meson8_ddr_hw_clks), + }, }; =20 -static int meson8_ddr_clkc_probe(struct platform_device *pdev) -{ - struct regmap *regmap; - void __iomem *base; - struct clk_hw *hw; - int ret, i; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - regmap =3D devm_regmap_init_mmio(&pdev->dev, base, - &meson8_ddr_regmap_cfg); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* Register all clks */ - for (i =3D 0; i < meson8_ddr_clks.num; i++) { - hw =3D meson8_ddr_clks.hws[i]; - - ret =3D devm_clk_hw_register(&pdev->dev, hw); - if (ret) { - dev_err(&pdev->dev, "Clock registration failed\n"); - return ret; - } - } - - return devm_of_clk_add_hw_provider(&pdev->dev, meson_clk_hw_get, - &meson8_ddr_clks); -} - static const struct of_device_id meson8_ddr_clkc_match_table[] =3D { - { .compatible =3D "amlogic,meson8-ddr-clkc" }, - { .compatible =3D "amlogic,meson8b-ddr-clkc" }, + { + .compatible =3D "amlogic,meson8-ddr-clkc", + .data =3D &meson8_ddr_clkc_data, + }, { + .compatible =3D "amlogic,meson8b-ddr-clkc", + .data =3D &meson8_ddr_clkc_data, + }, { /* sentinel */ } }; =20 static struct platform_driver meson8_ddr_clkc_driver =3D { - .probe =3D meson8_ddr_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "meson8-ddr-clkc", .of_match_table =3D meson8_ddr_clkc_match_table, diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index 9bcd35f12836de5e318fd1ad9c9ae15a2bfc3dd7..fc1500df926d056ce17252987dd= 91095a8399b55 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -3449,59 +3449,24 @@ static struct clk_hw *s4_peripherals_hw_clks[] =3D { [CLKID_HDCP22_SKPCLK] =3D &s4_hdcp22_skpclk.hw, }; =20 -static const struct regmap_config s4_peripherals_regmap_cfg =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D CLKCTRL_DEMOD_CLK_CTRL, -}; - -static struct meson_clk_hw_data s4_peripherals_clks =3D { - .hws =3D s4_peripherals_hw_clks, - .num =3D ARRAY_SIZE(s4_peripherals_hw_clks), +static const struct meson_clkc_data s4_peripherals_clkc_data =3D { + .hw_clks =3D { + .hws =3D s4_peripherals_hw_clks, + .num =3D ARRAY_SIZE(s4_peripherals_hw_clks), + }, }; =20 -static int s4_peripherals_clkc_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct regmap *regmap; - void __iomem *base; - int ret, i; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return dev_err_probe(dev, PTR_ERR(base), - "can't ioremap resource\n"); - - regmap =3D devm_regmap_init_mmio(dev, base, &s4_peripherals_regmap_cfg); - if (IS_ERR(regmap)) - return dev_err_probe(dev, PTR_ERR(regmap), - "can't init regmap mmio region\n"); - - for (i =3D 0; i < s4_peripherals_clks.num; i++) { - /* array might be sparse */ - if (!s4_peripherals_clks.hws[i]) - continue; - - ret =3D devm_clk_hw_register(dev, s4_peripherals_clks.hws[i]); - if (ret) - return dev_err_probe(dev, ret, - "clock[%d] registration failed\n", i); - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &s4_peripherals= _clks); -} - static const struct of_device_id s4_peripherals_clkc_match_table[] =3D { { .compatible =3D "amlogic,s4-peripherals-clkc", + .data =3D &s4_peripherals_clkc_data, }, {} }; MODULE_DEVICE_TABLE(of, s4_peripherals_clkc_match_table); =20 static struct platform_driver s4_peripherals_clkc_driver =3D { - .probe =3D s4_peripherals_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "s4-peripherals-clkc", .of_match_table =3D s4_peripherals_clkc_match_table, diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c index 6a266bcafd6257937c1de50cbc5606dcc6f8207b..56ce6f566e537a26e932db245ed= e17d900d9f093 100644 --- a/drivers/clk/meson/s4-pll.c +++ b/drivers/clk/meson/s4-pll.c @@ -798,66 +798,26 @@ static const struct reg_sequence s4_pll_init_regs[] = =3D { { .reg =3D ANACTRL_MPLL_CTRL0, .def =3D 0x00000543 }, }; =20 -static const struct regmap_config s4_pll_clkc_regmap_cfg =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D ANACTRL_HDMIPLL_CTRL0, -}; - -static struct meson_clk_hw_data s4_pll_clks =3D { - .hws =3D s4_pll_hw_clks, - .num =3D ARRAY_SIZE(s4_pll_hw_clks), -}; - -static int s4_pll_clkc_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct regmap *regmap; - void __iomem *base; - int ret, i; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return dev_err_probe(dev, PTR_ERR(base), - "can't ioremap resource\n"); - - regmap =3D devm_regmap_init_mmio(dev, base, &s4_pll_clkc_regmap_cfg); - if (IS_ERR(regmap)) - return dev_err_probe(dev, PTR_ERR(regmap), - "can't init regmap mmio region\n"); - - ret =3D regmap_multi_reg_write(regmap, s4_pll_init_regs, ARRAY_SIZE(s4_pl= l_init_regs)); - if (ret) - return dev_err_probe(dev, ret, - "Failed to init registers\n"); - - /* Register clocks */ - for (i =3D 0; i < s4_pll_clks.num; i++) { - /* array might be sparse */ - if (!s4_pll_clks.hws[i]) - continue; - - ret =3D devm_clk_hw_register(dev, s4_pll_clks.hws[i]); - if (ret) - return dev_err_probe(dev, ret, - "clock[%d] registration failed\n", i); - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, - &s4_pll_clks); -} +static const struct meson_clkc_data s4_pll_clkc_data =3D { + .hw_clks =3D { + .hws =3D s4_pll_hw_clks, + .num =3D ARRAY_SIZE(s4_pll_hw_clks), + }, + .init_regs =3D s4_pll_init_regs, + .init_count =3D ARRAY_SIZE(s4_pll_init_regs), +}; =20 static const struct of_device_id s4_pll_clkc_match_table[] =3D { { .compatible =3D "amlogic,s4-pll-clkc", + .data =3D &s4_pll_clkc_data, }, {} }; MODULE_DEVICE_TABLE(of, s4_pll_clkc_match_table); =20 static struct platform_driver s4_pll_clkc_driver =3D { - .probe =3D s4_pll_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "s4-pll-clkc", .of_match_table =3D s4_pll_clkc_match_table, --=20 2.47.2 From nobody Wed Oct 8 03:53:54 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B63162E7BAF for ; Wed, 2 Jul 2025 15:27:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751470057; cv=none; b=siz1XLwoFUtyOWOK2XdBYNIejTC5p4U/fERNX50cPIFeKoErgybEDXWqvib207Tgkq8ci/DO9UBfS6hpxr587xaVZ5PLIAi281v0wLl5ETpKB9r1c4c957h9XILhan7FjUTGX3RlFD0gLuXPfqoHKx4HLaSiWkENNjS2ZqxT9qU= ARC-Message-Signature: i=1; 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Wed, 02 Jul 2025 08:27:31 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:5542:4bad:e07b:9489]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-454a9bcf35csm869205e9.20.2025.07.02.08.27.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jul 2025 08:27:31 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:26:16 +0200 Subject: [PATCH 18/26] clk: amlogic: aoclk: use clkc-utils syscon probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-18-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 The clock related part of aoclk probe function duplicates what the clkc-utils syscon helper does. Factorize this to have a single path to maintain. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg-aoclk.c | 10 ++++++---- drivers/clk/meson/g12a-aoclk.c | 10 ++++++---- drivers/clk/meson/gxbb-aoclk.c | 10 ++++++---- drivers/clk/meson/meson-aoclk.c | 32 ++++++++++++++------------------ drivers/clk/meson/meson-aoclk.h | 2 +- 5 files changed, 33 insertions(+), 31 deletions(-) diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c index a0c58dc8e950a05c340c3427af4f6ff7661fa84e..efc33fd18c197df233d537e5f82= 44a376d4d0924 100644 --- a/drivers/clk/meson/axg-aoclk.c +++ b/drivers/clk/meson/axg-aoclk.c @@ -300,16 +300,18 @@ static const struct meson_aoclk_data axg_ao_clkc_data= =3D { .reset_reg =3D AO_RTI_GEN_CNTL_REG0, .num_reset =3D ARRAY_SIZE(axg_ao_reset), .reset =3D axg_ao_reset, - .hw_clks =3D { - .hws =3D axg_ao_hw_clks, - .num =3D ARRAY_SIZE(axg_ao_hw_clks), + .clkc_data =3D { + .hw_clks =3D { + .hws =3D axg_ao_hw_clks, + .num =3D ARRAY_SIZE(axg_ao_hw_clks), + }, }, }; =20 static const struct of_device_id axg_ao_clkc_match_table[] =3D { { .compatible =3D "amlogic,meson-axg-aoclkc", - .data =3D &axg_ao_clkc_data, + .data =3D &axg_ao_clkc_data.clkc_data, }, { } }; diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c index 3eaf1db16f45a0adf0acd901ed7ae1f51a9c8dc1..872a7b800bb86bdf1ead56c3eec= 7e47f30637dbd 100644 --- a/drivers/clk/meson/g12a-aoclk.c +++ b/drivers/clk/meson/g12a-aoclk.c @@ -424,16 +424,18 @@ static const struct meson_aoclk_data g12a_ao_clkc_dat= a =3D { .reset_reg =3D AO_RTI_GEN_CNTL_REG0, .num_reset =3D ARRAY_SIZE(g12a_ao_reset), .reset =3D g12a_ao_reset, - .hw_clks =3D { - .hws =3D g12a_ao_hw_clks, - .num =3D ARRAY_SIZE(g12a_ao_hw_clks), + .clkc_data =3D { + .hw_clks =3D { + .hws =3D g12a_ao_hw_clks, + .num =3D ARRAY_SIZE(g12a_ao_hw_clks), + }, }, }; =20 static const struct of_device_id g12a_ao_clkc_match_table[] =3D { { .compatible =3D "amlogic,meson-g12a-aoclkc", - .data =3D &g12a_ao_clkc_data, + .data =3D &g12a_ao_clkc_data.clkc_data, }, { } }; diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 11b11fa7791eb1903938c0d3ee46121a23b94a46..ce8d2e9e071759ab8b8aa8619ad= 7400f1513c319 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c @@ -258,16 +258,18 @@ static const struct meson_aoclk_data gxbb_ao_clkc_dat= a =3D { .reset_reg =3D AO_RTI_GEN_CNTL_REG0, .num_reset =3D ARRAY_SIZE(gxbb_ao_reset), .reset =3D gxbb_ao_reset, - .hw_clks =3D { - .hws =3D gxbb_ao_hw_clks, - .num =3D ARRAY_SIZE(gxbb_ao_hw_clks), + .clkc_data =3D { + .hw_clks =3D { + .hws =3D gxbb_ao_hw_clks, + .num =3D ARRAY_SIZE(gxbb_ao_hw_clks), + }, }, }; =20 static const struct of_device_id gxbb_ao_clkc_match_table[] =3D { { .compatible =3D "amlogic,meson-gx-aoclkc", - .data =3D &gxbb_ao_clkc_data, + .data =3D &gxbb_ao_clkc_data.clkc_data, }, { } }; diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aocl= k.c index 894c02fda072ddd0733165d5f60efe1d0da2388d..8f6bdea181197cc647398bd607d= 8b004ac81f747 100644 --- a/drivers/clk/meson/meson-aoclk.c +++ b/drivers/clk/meson/meson-aoclk.c @@ -37,15 +37,23 @@ static const struct reset_control_ops meson_aoclk_reset= _ops =3D { int meson_aoclkc_probe(struct platform_device *pdev) { struct meson_aoclk_reset_controller *rstc; - struct meson_aoclk_data *data; + const struct meson_clkc_data *clkc_data; + const struct meson_aoclk_data *data; struct device *dev =3D &pdev->dev; struct device_node *np; struct regmap *regmap; - int ret, clkid; + int ret; =20 - data =3D (struct meson_aoclk_data *) of_device_get_match_data(dev); - if (!data) - return -ENODEV; + clkc_data =3D of_device_get_match_data(dev); + if (!clkc_data) + return -EINVAL; + + ret =3D meson_clkc_syscon_probe(pdev); + if (ret) + return ret; + + data =3D container_of(clkc_data, struct meson_aoclk_data, + clkc_data); =20 rstc =3D devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL); if (!rstc) @@ -71,19 +79,7 @@ int meson_aoclkc_probe(struct platform_device *pdev) return ret; } =20 - /* Register all clks */ - for (clkid =3D 0; clkid < data->hw_clks.num; clkid++) { - if (!data->hw_clks.hws[clkid]) - continue; - - ret =3D devm_clk_hw_register(dev, data->hw_clks.hws[clkid]); - if (ret) { - dev_err(dev, "Clock registration failed\n"); - return ret; - } - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->= hw_clks); + return 0; } EXPORT_SYMBOL_NS_GPL(meson_aoclkc_probe, "CLK_MESON"); =20 diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aocl= k.h index ea5fc61308af14c63489b7c72410d9d981d8745b..2c83e73d3a7753c2094d2acc7c7= 5b524edb5bb9e 100644 --- a/drivers/clk/meson/meson-aoclk.h +++ b/drivers/clk/meson/meson-aoclk.h @@ -20,10 +20,10 @@ #include "meson-clkc-utils.h" =20 struct meson_aoclk_data { + const struct meson_clkc_data clkc_data; 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Wed, 02 Jul 2025 08:27:32 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:5542:4bad:e07b:9489]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-454a9bcf35csm869205e9.20.2025.07.02.08.27.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jul 2025 08:27:32 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:26:17 +0200 Subject: [PATCH 19/26] clk: amlogic: move PCLK definition to clkc-utils Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-19-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 clk-regmap was always meant to stay generic, without any amlogic specifics. The hope was that it could move out of the amlogic directory one day. Even if this may actually not become true, it should remain generic. Move the amlogic peripheral clock definition out of clk-regmap header. Signed-off-by: Jerome Brunet --- drivers/clk/meson/clk-regmap.h | 20 -------------------- drivers/clk/meson/meson-clkc-utils.h | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 20 deletions(-) diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h index f8cac2df5755b0f894570305604485f54c17ea49..8e5c39b023e1334e37d5a9e0594= 436727f16c4f2 100644 --- a/drivers/clk/meson/clk-regmap.h +++ b/drivers/clk/meson/clk-regmap.h @@ -118,24 +118,4 @@ clk_get_regmap_mux_data(struct clk_regmap *clk) extern const struct clk_ops clk_regmap_mux_ops; extern const struct clk_ops clk_regmap_mux_ro_ops; =20 -#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ -struct clk_regmap _name =3D { \ - .data =3D &(struct clk_regmap_gate_data){ \ - .offset =3D (_reg), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name, \ - .ops =3D _ops, \ - .parent_hws =3D (const struct clk_hw *[]) { _pname }, \ - .num_parents =3D 1, \ - .flags =3D (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ - }, \ -} - -#define MESON_PCLK(_name, _reg, _bit, _pname) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) - -#define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) #endif /* __CLK_REGMAP_H */ diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index b45f85f630d7190fb6509b088f05f17ca91fa1c8..0c228a6723bb2bddc0b9a4f9251= 5f05850a5613a 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -27,4 +27,25 @@ struct meson_clkc_data { int meson_clkc_syscon_probe(struct platform_device *pdev); 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Wed, 02 Jul 2025 08:27:33 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:5542:4bad:e07b:9489]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-454a9bcf35csm869205e9.20.2025.07.02.08.27.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jul 2025 08:27:32 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:26:18 +0200 Subject: [PATCH 20/26] clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-20-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 On Amlogic SoCs, the rate of a peripheral clock should not be changed, let alone the rate of the parent PLL. These clocks are meant to be used as provided by the parent PLL. Changing the rate would be dangerous and would likely break a lot of devices running from the same PLL. Don't propagate any rate change request that may come from these clocks and drop the corresponding flag. Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson-clkc-utils.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index 0c228a6723bb2bddc0b9a4f92515f05850a5613a..3e1fb7efe6da1f5d8e55993541d= 12d40464a47f5 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -38,7 +38,7 @@ struct clk_regmap _name =3D { \ .ops =3D _ops, \ .parent_hws =3D (const struct clk_hw *[]) { _pname }, \ .num_parents =3D 1, \ - .flags =3D (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ + .flags =3D CLK_IGNORE_UNUSED, \ }, \ } =20 --=20 2.47.2 From nobody Wed Oct 8 03:53:54 2025 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C413F2F85C7 for ; Wed, 2 Jul 2025 15:27:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Every usage of CLK_IGNORE_UNUSED should be explicitly motivated and documented. However, the PCLK macros used by most Amlogic platforms are adding that flag systematically. Because of this, all pclks are marked with CLK_IGNORE_UNUSED, without any form of distinction or motivation. This may have been fine in the early days of CCF but it is not anymore. Just removing the flag is not an option at this stage since it could cause regression on existing platforms. Instead, drop the flag from the macro definition and add it to the each clock definition, for the existing clocks. This makes quite a nasty change but it will make it a lot easier for people to contribute to fixing the problem, clock by clock. It will also prevent new platform from being added with a silent use of the flag. Signed-off-by: Jerome Brunet Reviewed-by: Chuan Liu --- drivers/clk/meson/a1-peripherals.c | 125 ++++++++++++----------- drivers/clk/meson/axg-aoclk.c | 18 ++-- drivers/clk/meson/axg.c | 110 ++++++++++---------- drivers/clk/meson/g12a-aoclk.c | 49 ++++----- drivers/clk/meson/g12a.c | 176 ++++++++++++++++---------------- drivers/clk/meson/gxbb-aoclk.c | 16 +-- drivers/clk/meson/gxbb.c | 188 ++++++++++++++++++-------------= ---- drivers/clk/meson/meson-clkc-utils.h | 12 +-- drivers/clk/meson/meson8b.c | 183 ++++++++++++++++++-------------= --- drivers/clk/meson/s4-peripherals.c | 119 ++++++++++++---------- 10 files changed, 528 insertions(+), 468 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peri= pherals.c index b2feb8fe4775e38a17d8aa9ce9b992b3e1fb2bb8..a7bd3822df18f5e043e58e2d7bb= caa24345ea404 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -1840,64 +1840,73 @@ static struct clk_regmap a1_cecb_32k_out =3D { }, }; =20 -#define A1_PCLK(_name, _reg, _bit) \ - MESON_PCLK(a1_##_name, _reg, _bit, &a1_sys.hw) - -static A1_PCLK(clktree, SYS_CLK_EN0, 0); -static A1_PCLK(reset_ctrl, SYS_CLK_EN0, 1); -static A1_PCLK(analog_ctrl, SYS_CLK_EN0, 2); -static A1_PCLK(pwr_ctrl, SYS_CLK_EN0, 3); -static A1_PCLK(pad_ctrl, SYS_CLK_EN0, 4); -static A1_PCLK(sys_ctrl, SYS_CLK_EN0, 5); -static A1_PCLK(temp_sensor, SYS_CLK_EN0, 6); -static A1_PCLK(am2axi_dev, SYS_CLK_EN0, 7); -static A1_PCLK(spicc_b, SYS_CLK_EN0, 8); -static A1_PCLK(spicc_a, SYS_CLK_EN0, 9); -static A1_PCLK(msr, SYS_CLK_EN0, 10); -static A1_PCLK(audio, SYS_CLK_EN0, 11); -static A1_PCLK(jtag_ctrl, SYS_CLK_EN0, 12); -static A1_PCLK(saradc_en, SYS_CLK_EN0, 13); -static A1_PCLK(pwm_ef, SYS_CLK_EN0, 14); -static A1_PCLK(pwm_cd, SYS_CLK_EN0, 15); -static A1_PCLK(pwm_ab, SYS_CLK_EN0, 16); -static A1_PCLK(cec, SYS_CLK_EN0, 17); -static A1_PCLK(i2c_s, SYS_CLK_EN0, 18); -static A1_PCLK(ir_ctrl, SYS_CLK_EN0, 19); -static A1_PCLK(i2c_m_d, SYS_CLK_EN0, 20); -static A1_PCLK(i2c_m_c, SYS_CLK_EN0, 21); -static A1_PCLK(i2c_m_b, SYS_CLK_EN0, 22); -static A1_PCLK(i2c_m_a, SYS_CLK_EN0, 23); -static A1_PCLK(acodec, SYS_CLK_EN0, 24); -static A1_PCLK(otp, SYS_CLK_EN0, 25); -static A1_PCLK(sd_emmc_a, SYS_CLK_EN0, 26); -static A1_PCLK(usb_phy, SYS_CLK_EN0, 27); -static A1_PCLK(usb_ctrl, SYS_CLK_EN0, 28); -static A1_PCLK(sys_dspb, SYS_CLK_EN0, 29); -static A1_PCLK(sys_dspa, SYS_CLK_EN0, 30); -static A1_PCLK(dma, SYS_CLK_EN0, 31); - -static A1_PCLK(irq_ctrl, SYS_CLK_EN1, 0); -static A1_PCLK(nic, SYS_CLK_EN1, 1); -static A1_PCLK(gic, SYS_CLK_EN1, 2); -static A1_PCLK(uart_c, SYS_CLK_EN1, 3); -static A1_PCLK(uart_b, SYS_CLK_EN1, 4); -static A1_PCLK(uart_a, SYS_CLK_EN1, 5); -static A1_PCLK(sys_psram, SYS_CLK_EN1, 6); -static A1_PCLK(rsa, SYS_CLK_EN1, 8); -static A1_PCLK(coresight, SYS_CLK_EN1, 9); - -static A1_PCLK(am2axi_vad, AXI_CLK_EN, 0); -static A1_PCLK(audio_vad, AXI_CLK_EN, 1); -static A1_PCLK(axi_dmc, AXI_CLK_EN, 3); -static A1_PCLK(axi_psram, AXI_CLK_EN, 4); -static A1_PCLK(ramb, AXI_CLK_EN, 5); -static A1_PCLK(rama, AXI_CLK_EN, 6); -static A1_PCLK(axi_spifc, AXI_CLK_EN, 7); -static A1_PCLK(axi_nic, AXI_CLK_EN, 8); -static A1_PCLK(axi_dma, AXI_CLK_EN, 9); -static A1_PCLK(cpu_ctrl, AXI_CLK_EN, 10); -static A1_PCLK(rom, AXI_CLK_EN, 11); -static A1_PCLK(prod_i2c, AXI_CLK_EN, 12); +#define A1_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(a1_##_name, _reg, _bit, &a1_sys.hw, _flags) + +/* + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +static A1_PCLK(clktree, SYS_CLK_EN0, 0, CLK_IGNORE_UNUSED); +static A1_PCLK(reset_ctrl, SYS_CLK_EN0, 1, CLK_IGNORE_UNUSED); +static A1_PCLK(analog_ctrl, SYS_CLK_EN0, 2, CLK_IGNORE_UNUSED); +static A1_PCLK(pwr_ctrl, SYS_CLK_EN0, 3, CLK_IGNORE_UNUSED); +static A1_PCLK(pad_ctrl, SYS_CLK_EN0, 4, CLK_IGNORE_UNUSED); +static A1_PCLK(sys_ctrl, SYS_CLK_EN0, 5, CLK_IGNORE_UNUSED); +static A1_PCLK(temp_sensor, SYS_CLK_EN0, 6, CLK_IGNORE_UNUSED); +static A1_PCLK(am2axi_dev, SYS_CLK_EN0, 7, CLK_IGNORE_UNUSED); +static A1_PCLK(spicc_b, SYS_CLK_EN0, 8, CLK_IGNORE_UNUSED); +static A1_PCLK(spicc_a, SYS_CLK_EN0, 9, CLK_IGNORE_UNUSED); +static A1_PCLK(msr, SYS_CLK_EN0, 10, CLK_IGNORE_UNUSED); +static A1_PCLK(audio, SYS_CLK_EN0, 11, CLK_IGNORE_UNUSED); +static A1_PCLK(jtag_ctrl, SYS_CLK_EN0, 12, CLK_IGNORE_UNUSED); +static A1_PCLK(saradc_en, SYS_CLK_EN0, 13, CLK_IGNORE_UNUSED); +static A1_PCLK(pwm_ef, SYS_CLK_EN0, 14, CLK_IGNORE_UNUSED); +static A1_PCLK(pwm_cd, SYS_CLK_EN0, 15, CLK_IGNORE_UNUSED); +static A1_PCLK(pwm_ab, SYS_CLK_EN0, 16, CLK_IGNORE_UNUSED); +static A1_PCLK(cec, SYS_CLK_EN0, 17, CLK_IGNORE_UNUSED); +static A1_PCLK(i2c_s, SYS_CLK_EN0, 18, CLK_IGNORE_UNUSED); +static A1_PCLK(ir_ctrl, SYS_CLK_EN0, 19, CLK_IGNORE_UNUSED); +static A1_PCLK(i2c_m_d, SYS_CLK_EN0, 20, CLK_IGNORE_UNUSED); +static A1_PCLK(i2c_m_c, SYS_CLK_EN0, 21, CLK_IGNORE_UNUSED); +static A1_PCLK(i2c_m_b, SYS_CLK_EN0, 22, CLK_IGNORE_UNUSED); +static A1_PCLK(i2c_m_a, SYS_CLK_EN0, 23, CLK_IGNORE_UNUSED); +static A1_PCLK(acodec, SYS_CLK_EN0, 24, CLK_IGNORE_UNUSED); +static A1_PCLK(otp, SYS_CLK_EN0, 25, CLK_IGNORE_UNUSED); +static A1_PCLK(sd_emmc_a, SYS_CLK_EN0, 26, CLK_IGNORE_UNUSED); +static A1_PCLK(usb_phy, SYS_CLK_EN0, 27, CLK_IGNORE_UNUSED); +static A1_PCLK(usb_ctrl, SYS_CLK_EN0, 28, CLK_IGNORE_UNUSED); +static A1_PCLK(sys_dspb, SYS_CLK_EN0, 29, CLK_IGNORE_UNUSED); +static A1_PCLK(sys_dspa, SYS_CLK_EN0, 30, CLK_IGNORE_UNUSED); +static A1_PCLK(dma, SYS_CLK_EN0, 31, CLK_IGNORE_UNUSED); + +static A1_PCLK(irq_ctrl, SYS_CLK_EN1, 0, CLK_IGNORE_UNUSED); +static A1_PCLK(nic, SYS_CLK_EN1, 1, CLK_IGNORE_UNUSED); +static A1_PCLK(gic, SYS_CLK_EN1, 2, CLK_IGNORE_UNUSED); +static A1_PCLK(uart_c, SYS_CLK_EN1, 3, CLK_IGNORE_UNUSED); +static A1_PCLK(uart_b, SYS_CLK_EN1, 4, CLK_IGNORE_UNUSED); +static A1_PCLK(uart_a, SYS_CLK_EN1, 5, CLK_IGNORE_UNUSED); +static A1_PCLK(sys_psram, SYS_CLK_EN1, 6, CLK_IGNORE_UNUSED); +static A1_PCLK(rsa, SYS_CLK_EN1, 8, CLK_IGNORE_UNUSED); +static A1_PCLK(coresight, SYS_CLK_EN1, 9, CLK_IGNORE_UNUSED); + +static A1_PCLK(am2axi_vad, AXI_CLK_EN, 0, CLK_IGNORE_UNUSED); +static A1_PCLK(audio_vad, AXI_CLK_EN, 1, CLK_IGNORE_UNUSED); +static A1_PCLK(axi_dmc, AXI_CLK_EN, 3, CLK_IGNORE_UNUSED); +static A1_PCLK(axi_psram, AXI_CLK_EN, 4, CLK_IGNORE_UNUSED); +static A1_PCLK(ramb, AXI_CLK_EN, 5, CLK_IGNORE_UNUSED); +static A1_PCLK(rama, AXI_CLK_EN, 6, CLK_IGNORE_UNUSED); +static A1_PCLK(axi_spifc, AXI_CLK_EN, 7, CLK_IGNORE_UNUSED); +static A1_PCLK(axi_nic, AXI_CLK_EN, 8, CLK_IGNORE_UNUSED); +static A1_PCLK(axi_dma, AXI_CLK_EN, 9, CLK_IGNORE_UNUSED); +static A1_PCLK(cpu_ctrl, AXI_CLK_EN, 10, CLK_IGNORE_UNUSED); +static A1_PCLK(rom, AXI_CLK_EN, 11, CLK_IGNORE_UNUSED); +static A1_PCLK(prod_i2c, AXI_CLK_EN, 12, CLK_IGNORE_UNUSED); =20 /* Array of all clocks registered by this provider */ static struct clk_hw *a1_peripherals_hw_clks[] =3D { diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c index efc33fd18c197df233d537e5f8244a376d4d0924..74c2f51424f11cc04a80a3a4918= e4de0a5d11d08 100644 --- a/drivers/clk/meson/axg-aoclk.c +++ b/drivers/clk/meson/axg-aoclk.c @@ -34,7 +34,7 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define AXG_AO_GATE(_name, _bit) \ +#define AXG_AO_GATE(_name, _bit, _flags) \ static struct clk_regmap axg_ao_##_name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D (AO_RTI_GEN_CNTL_REG0), \ @@ -47,17 +47,17 @@ static struct clk_regmap axg_ao_##_name =3D { \ .fw_name =3D "mpeg-clk", \ }, \ .num_parents =3D 1, \ - .flags =3D CLK_IGNORE_UNUSED, \ + .flags =3D (_flags), \ }, \ } =20 -AXG_AO_GATE(remote, 0); -AXG_AO_GATE(i2c_master, 1); -AXG_AO_GATE(i2c_slave, 2); -AXG_AO_GATE(uart1, 3); -AXG_AO_GATE(uart2, 5); -AXG_AO_GATE(ir_blaster, 6); -AXG_AO_GATE(saradc, 7); +AXG_AO_GATE(remote, 0, CLK_IGNORE_UNUSED); +AXG_AO_GATE(i2c_master, 1, CLK_IGNORE_UNUSED); +AXG_AO_GATE(i2c_slave, 2, CLK_IGNORE_UNUSED); +AXG_AO_GATE(uart1, 3, CLK_IGNORE_UNUSED); +AXG_AO_GATE(uart2, 5, CLK_IGNORE_UNUSED); +AXG_AO_GATE(ir_blaster, 6, CLK_IGNORE_UNUSED); +AXG_AO_GATE(saradc, 7, CLK_IGNORE_UNUSED); =20 static struct clk_regmap axg_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 675f051ea5241b0f51e54a238470e4fe947e5ba5..d83482d5da6ddc09b3dfaf77c68= 98456ef9f0d39 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -1915,59 +1915,69 @@ static struct clk_regmap axg_gen_clk =3D { }, }; =20 -#define AXG_PCLK(_name, _reg, _bit) \ - MESON_PCLK(axg_##_name, _reg, _bit, &axg_clk81.hw) - -/* Everything Else (EE) domain gates */ -static AXG_PCLK(ddr, HHI_GCLK_MPEG0, 0); -static AXG_PCLK(audio_locker, HHI_GCLK_MPEG0, 2); -static AXG_PCLK(mipi_dsi_host, HHI_GCLK_MPEG0, 3); -static AXG_PCLK(isa, HHI_GCLK_MPEG0, 5); -static AXG_PCLK(pl301, HHI_GCLK_MPEG0, 6); -static AXG_PCLK(periphs, HHI_GCLK_MPEG0, 7); -static AXG_PCLK(spicc_0, HHI_GCLK_MPEG0, 8); -static AXG_PCLK(i2c, HHI_GCLK_MPEG0, 9); -static AXG_PCLK(rng0, HHI_GCLK_MPEG0, 12); -static AXG_PCLK(uart0, HHI_GCLK_MPEG0, 13); -static AXG_PCLK(mipi_dsi_phy, HHI_GCLK_MPEG0, 14); -static AXG_PCLK(spicc_1, HHI_GCLK_MPEG0, 15); -static AXG_PCLK(pcie_a, HHI_GCLK_MPEG0, 16); -static AXG_PCLK(pcie_b, HHI_GCLK_MPEG0, 17); -static AXG_PCLK(hiu_reg, HHI_GCLK_MPEG0, 19); -static AXG_PCLK(assist_misc, HHI_GCLK_MPEG0, 23); -static AXG_PCLK(emmc_b, HHI_GCLK_MPEG0, 25); -static AXG_PCLK(emmc_c, HHI_GCLK_MPEG0, 26); -static AXG_PCLK(dma, HHI_GCLK_MPEG0, 27); -static AXG_PCLK(spi, HHI_GCLK_MPEG0, 30); - -static AXG_PCLK(audio, HHI_GCLK_MPEG1, 0); -static AXG_PCLK(eth_core, HHI_GCLK_MPEG1, 3); -static AXG_PCLK(uart1, HHI_GCLK_MPEG1, 16); -static AXG_PCLK(g2d, HHI_GCLK_MPEG1, 20); -static AXG_PCLK(usb0, HHI_GCLK_MPEG1, 21); -static AXG_PCLK(usb1, HHI_GCLK_MPEG1, 22); -static AXG_PCLK(reset, HHI_GCLK_MPEG1, 23); -static AXG_PCLK(usb_general, HHI_GCLK_MPEG1, 26); -static AXG_PCLK(ahb_arb0, HHI_GCLK_MPEG1, 29); -static AXG_PCLK(efuse, HHI_GCLK_MPEG1, 30); -static AXG_PCLK(boot_rom, HHI_GCLK_MPEG1, 31); - -static AXG_PCLK(ahb_data_bus, HHI_GCLK_MPEG2, 1); -static AXG_PCLK(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static AXG_PCLK(usb1_to_ddr, HHI_GCLK_MPEG2, 8); -static AXG_PCLK(usb0_to_ddr, HHI_GCLK_MPEG2, 9); -static AXG_PCLK(mmc_pclk, HHI_GCLK_MPEG2, 11); -static AXG_PCLK(vpu_intr, HHI_GCLK_MPEG2, 25); -static AXG_PCLK(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); -static AXG_PCLK(gic, HHI_GCLK_MPEG2, 30); +#define AXG_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(axg_##_name, _reg, _bit, &axg_clk81.hw, _flags) + +/* + * Everything Else (EE) domain gates + * + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +static AXG_PCLK(ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); +static AXG_PCLK(audio_locker, HHI_GCLK_MPEG0, 2, CLK_IGNORE_UNUSED); +static AXG_PCLK(mipi_dsi_host, HHI_GCLK_MPEG0, 3, CLK_IGNORE_UNUSED); +static AXG_PCLK(isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); +static AXG_PCLK(pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); +static AXG_PCLK(periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED); +static AXG_PCLK(spicc_0, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); +static AXG_PCLK(i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); +static AXG_PCLK(rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); +static AXG_PCLK(uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); +static AXG_PCLK(mipi_dsi_phy, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); +static AXG_PCLK(spicc_1, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED); +static AXG_PCLK(pcie_a, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED); +static AXG_PCLK(pcie_b, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED); +static AXG_PCLK(hiu_reg, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED); +static AXG_PCLK(assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED); +static AXG_PCLK(emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED); +static AXG_PCLK(emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED); +static AXG_PCLK(dma, HHI_GCLK_MPEG0, 27, CLK_IGNORE_UNUSED); +static AXG_PCLK(spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED); + +static AXG_PCLK(audio, HHI_GCLK_MPEG1, 0, CLK_IGNORE_UNUSED); +static AXG_PCLK(eth_core, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); +static AXG_PCLK(uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); +static AXG_PCLK(g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); +static AXG_PCLK(usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED); +static AXG_PCLK(usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED); +static AXG_PCLK(reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); +static AXG_PCLK(usb_general, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); +static AXG_PCLK(ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED); +static AXG_PCLK(efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED); +static AXG_PCLK(boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED); + +static AXG_PCLK(ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED); +static AXG_PCLK(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED); +static AXG_PCLK(usb1_to_ddr, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED); +static AXG_PCLK(usb0_to_ddr, HHI_GCLK_MPEG2, 9, CLK_IGNORE_UNUSED); +static AXG_PCLK(mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED); +static AXG_PCLK(vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED); +static AXG_PCLK(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_IGNORE_UNUSED= ); +static AXG_PCLK(gic, HHI_GCLK_MPEG2, 30, CLK_IGNORE_UNUSED); =20 /* Always On (AO) domain gates */ =20 -static AXG_PCLK(ao_media_cpu, HHI_GCLK_AO, 0); -static AXG_PCLK(ao_ahb_sram, HHI_GCLK_AO, 1); -static AXG_PCLK(ao_ahb_bus, HHI_GCLK_AO, 2); -static AXG_PCLK(ao_iface, HHI_GCLK_AO, 3); -static AXG_PCLK(ao_i2c, HHI_GCLK_AO, 4); +static AXG_PCLK(ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED); +static AXG_PCLK(ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED); +static AXG_PCLK(ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED); +static AXG_PCLK(ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED); +static AXG_PCLK(ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED); =20 /* Array of all clocks provided by this provider */ =20 diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c index 872a7b800bb86bdf1ead56c3eec7e47f30637dbd..45e4df393feb6f916b6e035ad71= e379e6e30ee99 100644 --- a/drivers/clk/meson/g12a-aoclk.c +++ b/drivers/clk/meson/g12a-aoclk.c @@ -37,13 +37,7 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -/* - * Like every other peripheral clock gate in Amlogic Clock drivers, - * we are using CLK_IGNORE_UNUSED here, so we keep the state of the - * bootloader. The goal is to remove this flag at some point. - * Actually removing it will require some extensive test to be done safely. - */ -#define G12A_AO_PCLK(_name, _reg, _bit) \ +#define G12A_AO_PCLK(_name, _reg, _bit, _flags) \ static struct clk_regmap g12a_ao_##_name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D (_reg), \ @@ -56,26 +50,35 @@ static struct clk_regmap g12a_ao_##_name =3D { \ .fw_name =3D "mpeg-clk", \ }, \ .num_parents =3D 1, \ - .flags =3D CLK_IGNORE_UNUSED, \ + .flags =3D (_flags), \ }, \ } =20 -G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0); -G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1); -G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2); -G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3); -G12A_AO_PCLK(uart, AO_CLK_GATE0, 4); -G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5); -G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6); -G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7); -G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8); +/* + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(uart, AO_CLK_GATE0, 4, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8, CLK_IGNORE_UNUSED); =20 -G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0); -G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1); -G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2); -G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3); -G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4); -G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5); +G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5, CLK_IGNORE_UNUSED); =20 static struct clk_regmap g12a_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index cdaaa165a0ff1f3b4d5250a96428c54cc3e37381..7a737bfde4e62ec3d18db570e62= cc77fb415676c 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -4384,89 +4384,99 @@ static struct clk_regmap sm1_nna_core_clk =3D { }, }; =20 -#define G12A_PCLK(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw) - -#define G12A_PCLK_RO(_name, _reg, _bit) \ - MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw) - -/* Everything Else (EE) domain gates */ -static G12A_PCLK(g12a_ddr, HHI_GCLK_MPEG0, 0); -static G12A_PCLK(g12a_dos, HHI_GCLK_MPEG0, 1); -static G12A_PCLK(g12a_audio_locker, HHI_GCLK_MPEG0, 2); -static G12A_PCLK(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3); -static G12A_PCLK(g12a_eth_phy, HHI_GCLK_MPEG0, 4); -static G12A_PCLK(g12a_isa, HHI_GCLK_MPEG0, 5); -static G12A_PCLK(g12a_pl301, HHI_GCLK_MPEG0, 6); -static G12A_PCLK(g12a_periphs, HHI_GCLK_MPEG0, 7); -static G12A_PCLK(g12a_spicc_0, HHI_GCLK_MPEG0, 8); -static G12A_PCLK(g12a_i2c, HHI_GCLK_MPEG0, 9); -static G12A_PCLK(g12a_sana, HHI_GCLK_MPEG0, 10); -static G12A_PCLK(g12a_sd, HHI_GCLK_MPEG0, 11); -static G12A_PCLK(g12a_rng0, HHI_GCLK_MPEG0, 12); -static G12A_PCLK(g12a_uart0, HHI_GCLK_MPEG0, 13); -static G12A_PCLK(g12a_spicc_1, HHI_GCLK_MPEG0, 14); -static G12A_PCLK(g12a_hiu_reg, HHI_GCLK_MPEG0, 19); -static G12A_PCLK(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20); -static G12A_PCLK(g12a_assist_misc, HHI_GCLK_MPEG0, 23); -static G12A_PCLK(g12a_emmc_a, HHI_GCLK_MPEG0, 24); -static G12A_PCLK(g12a_emmc_b, HHI_GCLK_MPEG0, 25); -static G12A_PCLK(g12a_emmc_c, HHI_GCLK_MPEG0, 26); -static G12A_PCLK(g12a_audio_codec, HHI_GCLK_MPEG0, 28); - -static G12A_PCLK(g12a_audio, HHI_GCLK_MPEG1, 0); -static G12A_PCLK(g12a_eth_core, HHI_GCLK_MPEG1, 3); -static G12A_PCLK(g12a_demux, HHI_GCLK_MPEG1, 4); -static G12A_PCLK(g12a_audio_ififo, HHI_GCLK_MPEG1, 11); -static G12A_PCLK(g12a_adc, HHI_GCLK_MPEG1, 13); -static G12A_PCLK(g12a_uart1, HHI_GCLK_MPEG1, 16); -static G12A_PCLK(g12a_g2d, HHI_GCLK_MPEG1, 20); -static G12A_PCLK(g12a_reset, HHI_GCLK_MPEG1, 23); -static G12A_PCLK(g12a_pcie_comb, HHI_GCLK_MPEG1, 24); -static G12A_PCLK(g12a_parser, HHI_GCLK_MPEG1, 25); -static G12A_PCLK(g12a_usb_general, HHI_GCLK_MPEG1, 26); -static G12A_PCLK(g12a_pcie_phy, HHI_GCLK_MPEG1, 27); -static G12A_PCLK(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29); - -static G12A_PCLK(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1); -static G12A_PCLK(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static G12A_PCLK(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3); -static G12A_PCLK(g12a_htx_pclk, HHI_GCLK_MPEG2, 4); -static G12A_PCLK(g12a_bt656, HHI_GCLK_MPEG2, 6); -static G12A_PCLK(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8); -static G12A_PCLK(g12b_mipi_isp_gate, HHI_GCLK_MPEG2, 17); -static G12A_PCLK(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11); -static G12A_PCLK(g12a_uart2, HHI_GCLK_MPEG2, 15); -static G12A_PCLK(g12a_vpu_intr, HHI_GCLK_MPEG2, 25); -static G12A_PCLK(g12b_csi_phy1, HHI_GCLK_MPEG2, 28); -static G12A_PCLK(g12b_csi_phy0, HHI_GCLK_MPEG2, 29); -static G12A_PCLK(g12a_gic, HHI_GCLK_MPEG2, 30); - -static G12A_PCLK(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1); -static G12A_PCLK(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2); -static G12A_PCLK(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3); -static G12A_PCLK(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4); -static G12A_PCLK(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5); -static G12A_PCLK(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6); -static G12A_PCLK(g12a_vclk2_other, HHI_GCLK_OTHER, 7); -static G12A_PCLK(g12a_vclk2_enci, HHI_GCLK_OTHER, 8); -static G12A_PCLK(g12a_vclk2_encp, HHI_GCLK_OTHER, 9); -static G12A_PCLK(g12a_dac_clk, HHI_GCLK_OTHER, 10); -static G12A_PCLK(g12a_aoclk_gate, HHI_GCLK_OTHER, 14); -static G12A_PCLK(g12a_iec958_gate, HHI_GCLK_OTHER, 16); -static G12A_PCLK(g12a_enc480p, HHI_GCLK_OTHER, 20); -static G12A_PCLK(g12a_rng1, HHI_GCLK_OTHER, 21); -static G12A_PCLK(g12a_vclk2_enct, HHI_GCLK_OTHER, 22); -static G12A_PCLK(g12a_vclk2_encl, HHI_GCLK_OTHER, 23); -static G12A_PCLK(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24); -static G12A_PCLK(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25); -static G12A_PCLK(g12a_vclk2_other1, HHI_GCLK_OTHER, 26); - -static G12A_PCLK_RO(g12a_dma, HHI_GCLK_OTHER2, 0); -static G12A_PCLK_RO(g12a_efuse, HHI_GCLK_OTHER2, 1); -static G12A_PCLK_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2); -static G12A_PCLK_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3); -static G12A_PCLK_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4); +#define G12A_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw, _flags) + +#define G12A_PCLK_RO(_name, _reg, _bit, _flags) \ + MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw, _flags) + +/* + * Everything Else (EE) domain gates + * + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +static G12A_PCLK(g12a_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_audio_locker, HHI_GCLK_MPEG0, 2, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3, CLK_IGNORE_UNUSE= D); +static G12A_PCLK(g12a_eth_phy, HHI_GCLK_MPEG0, 4, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_spicc_0, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_sana, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_sd, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_spicc_1, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_hiu_reg, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_emmc_a, HHI_GCLK_MPEG0, 24, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_audio_codec, HHI_GCLK_MPEG0, 28, CLK_IGNORE_UNUSED); + +static G12A_PCLK(g12a_audio, HHI_GCLK_MPEG1, 0, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_eth_core, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_audio_ififo, HHI_GCLK_MPEG1, 11, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_adc, HHI_GCLK_MPEG1, 13, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_pcie_comb, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_usb_general, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_pcie_phy, HHI_GCLK_MPEG1, 27, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED); + +static G12A_PCLK(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_htx_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_bt656, HHI_GCLK_MPEG2, 6, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12b_mipi_isp_gate, HHI_GCLK_MPEG2, 17, CLK_IGNORE_UNUSE= D); +static G12A_PCLK(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12b_csi_phy1, HHI_GCLK_MPEG2, 28, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12b_csi_phy0, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_gic, HHI_GCLK_MPEG2, 30, CLK_IGNORE_UNUSED); + +static G12A_PCLK(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_vclk2_other, HHI_GCLK_OTHER, 7, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vclk2_enci, HHI_GCLK_OTHER, 8, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vclk2_encp, HHI_GCLK_OTHER, 9, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vclk2_enct, HHI_GCLK_OTHER, 22, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vclk2_encl, HHI_GCLK_OTHER, 23, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24, CLK_IGNORE_UNUS= ED); +static G12A_PCLK(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vclk2_other1, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED= ); + +static G12A_PCLK_RO(g12a_dma, HHI_GCLK_OTHER2, 0, 0); +static G12A_PCLK_RO(g12a_efuse, HHI_GCLK_OTHER2, 1, 0); +static G12A_PCLK_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2, 0); +static G12A_PCLK_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3, 0); +static G12A_PCLK_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4, 0); =20 /* Array of all clocks provided by this provider */ static struct clk_hw *g12a_hw_clks[] =3D { diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index ce8d2e9e071759ab8b8aa8619ad7400f1513c319..2bf45fd7fe4ba0783e736fbbb12= 6209870985b22 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c @@ -23,7 +23,7 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define GXBB_AO_PCLK(_name, _bit) \ +#define GXBB_AO_PCLK(_name, _bit, _flags) \ static struct clk_regmap gxbb_ao_##_name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D AO_RTI_GEN_CNTL_REG0, \ @@ -36,16 +36,16 @@ static struct clk_regmap gxbb_ao_##_name =3D { \ .fw_name =3D "mpeg-clk", \ }, \ .num_parents =3D 1, \ - .flags =3D CLK_IGNORE_UNUSED, \ + .flags =3D (_flags), \ }, \ } =20 -GXBB_AO_PCLK(remote, 0); -GXBB_AO_PCLK(i2c_master, 1); -GXBB_AO_PCLK(i2c_slave, 2); -GXBB_AO_PCLK(uart1, 3); -GXBB_AO_PCLK(uart2, 5); -GXBB_AO_PCLK(ir_blaster, 6); +GXBB_AO_PCLK(remote, 0, CLK_IGNORE_UNUSED); +GXBB_AO_PCLK(i2c_master, 1, CLK_IGNORE_UNUSED); +GXBB_AO_PCLK(i2c_slave, 2, CLK_IGNORE_UNUSED); +GXBB_AO_PCLK(uart1, 3, CLK_IGNORE_UNUSED); +GXBB_AO_PCLK(uart2, 5, CLK_IGNORE_UNUSED); +GXBB_AO_PCLK(ir_blaster, 6, CLK_IGNORE_UNUSED); =20 static struct clk_regmap gxbb_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index a57cdf884ae900f8651b2cd84c5019270e684026..e2a88dc29901fe4617427907b38= 2e878ae6ff7ae 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -2721,100 +2721,110 @@ static struct clk_regmap gxbb_gen_clk =3D { }, }; =20 -#define GXBB_PCLK(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw) - -/* Everything Else (EE) domain gates */ -static GXBB_PCLK(gxbb_ddr, HHI_GCLK_MPEG0, 0); -static GXBB_PCLK(gxbb_dos, HHI_GCLK_MPEG0, 1); -static GXBB_PCLK(gxbb_isa, HHI_GCLK_MPEG0, 5); -static GXBB_PCLK(gxbb_pl301, HHI_GCLK_MPEG0, 6); -static GXBB_PCLK(gxbb_periphs, HHI_GCLK_MPEG0, 7); -static GXBB_PCLK(gxbb_spicc, HHI_GCLK_MPEG0, 8); -static GXBB_PCLK(gxbb_i2c, HHI_GCLK_MPEG0, 9); -static GXBB_PCLK(gxbb_sana, HHI_GCLK_MPEG0, 10); -static GXBB_PCLK(gxbb_smart_card, HHI_GCLK_MPEG0, 11); -static GXBB_PCLK(gxbb_rng0, HHI_GCLK_MPEG0, 12); -static GXBB_PCLK(gxbb_uart0, HHI_GCLK_MPEG0, 13); -static GXBB_PCLK(gxbb_sdhc, HHI_GCLK_MPEG0, 14); -static GXBB_PCLK(gxbb_stream, HHI_GCLK_MPEG0, 15); -static GXBB_PCLK(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); -static GXBB_PCLK(gxbb_sdio, HHI_GCLK_MPEG0, 17); -static GXBB_PCLK(gxbb_abuf, HHI_GCLK_MPEG0, 18); -static GXBB_PCLK(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); -static GXBB_PCLK(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); -static GXBB_PCLK(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); -static GXBB_PCLK(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); -static GXBB_PCLK(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); -static GXBB_PCLK(gxl_acodec, HHI_GCLK_MPEG0, 28); -static GXBB_PCLK(gxbb_spi, HHI_GCLK_MPEG0, 30); - -static GXBB_PCLK(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); -static GXBB_PCLK(gxbb_eth, HHI_GCLK_MPEG1, 3); -static GXBB_PCLK(gxbb_demux, HHI_GCLK_MPEG1, 4); -static GXBB_PCLK(gxbb_blkmv, HHI_GCLK_MPEG1, 14); -static GXBB_PCLK(gxbb_aiu, HHI_GCLK_MPEG1, 15); -static GXBB_PCLK(gxbb_uart1, HHI_GCLK_MPEG1, 16); -static GXBB_PCLK(gxbb_g2d, HHI_GCLK_MPEG1, 20); -static GXBB_PCLK(gxbb_usb0, HHI_GCLK_MPEG1, 21); -static GXBB_PCLK(gxbb_usb1, HHI_GCLK_MPEG1, 22); -static GXBB_PCLK(gxbb_reset, HHI_GCLK_MPEG1, 23); -static GXBB_PCLK(gxbb_nand, HHI_GCLK_MPEG1, 24); -static GXBB_PCLK(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); -static GXBB_PCLK(gxbb_usb, HHI_GCLK_MPEG1, 26); -static GXBB_PCLK(gxbb_vdin1, HHI_GCLK_MPEG1, 28); -static GXBB_PCLK(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); -static GXBB_PCLK(gxbb_efuse, HHI_GCLK_MPEG1, 30); -static GXBB_PCLK(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); - -static GXBB_PCLK(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); -static GXBB_PCLK(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static GXBB_PCLK(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); -static GXBB_PCLK(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); -static GXBB_PCLK(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); -static GXBB_PCLK(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); -static GXBB_PCLK(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); -static GXBB_PCLK(gxbb_dvin, HHI_GCLK_MPEG2, 12); -static GXBB_PCLK(gxbb_uart2, HHI_GCLK_MPEG2, 15); -static GXBB_PCLK(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); -static GXBB_PCLK(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); -static GXBB_PCLK(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); -static GXBB_PCLK(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); - -static GXBB_PCLK(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); -static GXBB_PCLK(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); -static GXBB_PCLK(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); -static GXBB_PCLK(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); -static GXBB_PCLK(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); -static GXBB_PCLK(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); -static GXBB_PCLK(gxbb_dac_clk, HHI_GCLK_OTHER, 10); -static GXBB_PCLK(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); -static GXBB_PCLK(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); -static GXBB_PCLK(gxbb_enc480p, HHI_GCLK_OTHER, 20); -static GXBB_PCLK(gxbb_rng1, HHI_GCLK_OTHER, 21); -static GXBB_PCLK(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); -static GXBB_PCLK(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); -static GXBB_PCLK(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); -static GXBB_PCLK(gxbb_vclk_other, HHI_GCLK_OTHER, 26); -static GXBB_PCLK(gxbb_edp, HHI_GCLK_OTHER, 31); +#define GXBB_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw, _flags) + +/* + * Everything Else (EE) domain gates + * + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +static GXBB_PCLK(gxbb_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_spicc, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_sana, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_smart_card, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_sdhc, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_stream, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_async_fifo, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_sdio, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_abuf, HHI_GCLK_MPEG0, 18, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_emmc_a, HHI_GCLK_MPEG0, 24, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxl_acodec, HHI_GCLK_MPEG0, 28, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED); + +static GXBB_PCLK(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_eth, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_blkmv, HHI_GCLK_MPEG1, 14, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_aiu, HHI_GCLK_MPEG1, 15, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_nand, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_dos_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_usb, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_vdin1, HHI_GCLK_MPEG1, 28, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED); + +static GXBB_PCLK(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3, CLK_IGNORE_UNUSE= D); +static GXBB_PCLK(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUS= ED); +static GXBB_PCLK(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9, CLK_IGNORE_UNUS= ED); +static GXBB_PCLK(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_dvin, HHI_GCLK_MPEG2, 12, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_sar_adc, HHI_GCLK_MPEG2, 22, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_IGNORE_= UNUSED); +static GXBB_PCLK(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUSED); + +static GXBB_PCLK(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8, CLK_IGNORE_UNUS= ED); +static GXBB_PCLK(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9, CLK_IGNORE_UNUSE= D); +static GXBB_PCLK(gxbb_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22, CLK_IGNORE_UNUS= ED); +static GXBB_PCLK(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24, CLK_IGNORE_UNUSE= D); +static GXBB_PCLK(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_vclk_other, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED); =20 /* Always On (AO) domain gates */ =20 -static GXBB_PCLK(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); -static GXBB_PCLK(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); -static GXBB_PCLK(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); -static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3); -static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4); +static GXBB_PCLK(gxbb_ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED); =20 /* AIU gates */ -static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw); -static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw); +static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw, CLK_IGN= ORE_UNUSED); +static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw, CLK= _IGNORE_UNUSED); +static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw, CL= K_IGNORE_UNUSED); +static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw, CLK_= IGNORE_UNUSED); +static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw, CL= K_IGNORE_UNUSED); +static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw, CLK_= IGNORE_UNUSED); +static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw,= CLK_IGNORE_UNUSED); +static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw, CLK_IG= NORE_UNUSED); =20 /* Array of all clocks provided by this provider */ =20 diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index 3e1fb7efe6da1f5d8e55993541d12d40464a47f5..03e38992c4c73ff4ee24f0fa99b= 7c34134376992 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -27,7 +27,7 @@ struct meson_clkc_data { int meson_clkc_syscon_probe(struct platform_device *pdev); int meson_clkc_mmio_probe(struct platform_device *pdev); =20 -#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ +#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname, _flags) \ struct clk_regmap _name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D (_reg), \ @@ -38,14 +38,14 @@ struct clk_regmap _name =3D { \ .ops =3D _ops, \ .parent_hws =3D (const struct clk_hw *[]) { _pname }, \ .num_parents =3D 1, \ - .flags =3D CLK_IGNORE_UNUSED, \ + .flags =3D (_flags), \ }, \ } =20 -#define MESON_PCLK(_name, _reg, _bit, _pname) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) +#define MESON_PCLK(_name, _reg, _bit, _pname, _flags) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname, _flags) =20 -#define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) +#define MESON_PCLK_RO(_name, _reg, _bit, _pname, _flags) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname, _flags) =20 #endif diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 446e57d45d8deeab9516a923ddddcba7fa274203..a16ebbbf664cdd56b2c74db4f88= a8d0a22d2ddc3 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -2701,100 +2701,109 @@ static struct clk_regmap meson8b_cts_i958 =3D { }, }; =20 -#define MESON8B_PCLK(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw) - -/* Everything Else (EE) domain gates */ - -static MESON8B_PCLK(meson8b_ddr, HHI_GCLK_MPEG0, 0); -static MESON8B_PCLK(meson8b_dos, HHI_GCLK_MPEG0, 1); -static MESON8B_PCLK(meson8b_isa, HHI_GCLK_MPEG0, 5); -static MESON8B_PCLK(meson8b_pl301, HHI_GCLK_MPEG0, 6); -static MESON8B_PCLK(meson8b_periphs, HHI_GCLK_MPEG0, 7); -static MESON8B_PCLK(meson8b_spicc, HHI_GCLK_MPEG0, 8); -static MESON8B_PCLK(meson8b_i2c, HHI_GCLK_MPEG0, 9); -static MESON8B_PCLK(meson8b_sar_adc, HHI_GCLK_MPEG0, 10); -static MESON8B_PCLK(meson8b_smart_card, HHI_GCLK_MPEG0, 11); -static MESON8B_PCLK(meson8b_rng0, HHI_GCLK_MPEG0, 12); -static MESON8B_PCLK(meson8b_uart0, HHI_GCLK_MPEG0, 13); -static MESON8B_PCLK(meson8b_sdhc, HHI_GCLK_MPEG0, 14); -static MESON8B_PCLK(meson8b_stream, HHI_GCLK_MPEG0, 15); -static MESON8B_PCLK(meson8b_async_fifo, HHI_GCLK_MPEG0, 16); -static MESON8B_PCLK(meson8b_sdio, HHI_GCLK_MPEG0, 17); -static MESON8B_PCLK(meson8b_abuf, HHI_GCLK_MPEG0, 18); -static MESON8B_PCLK(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19); -static MESON8B_PCLK(meson8b_assist_misc, HHI_GCLK_MPEG0, 23); -static MESON8B_PCLK(meson8b_spi, HHI_GCLK_MPEG0, 30); - -static MESON8B_PCLK(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2); -static MESON8B_PCLK(meson8b_eth, HHI_GCLK_MPEG1, 3); -static MESON8B_PCLK(meson8b_demux, HHI_GCLK_MPEG1, 4); -static MESON8B_PCLK(meson8b_blkmv, HHI_GCLK_MPEG1, 14); -static MESON8B_PCLK(meson8b_aiu, HHI_GCLK_MPEG1, 15); -static MESON8B_PCLK(meson8b_uart1, HHI_GCLK_MPEG1, 16); -static MESON8B_PCLK(meson8b_g2d, HHI_GCLK_MPEG1, 20); -static MESON8B_PCLK(meson8b_usb0, HHI_GCLK_MPEG1, 21); -static MESON8B_PCLK(meson8b_usb1, HHI_GCLK_MPEG1, 22); -static MESON8B_PCLK(meson8b_reset, HHI_GCLK_MPEG1, 23); -static MESON8B_PCLK(meson8b_nand, HHI_GCLK_MPEG1, 24); -static MESON8B_PCLK(meson8b_dos_parser, HHI_GCLK_MPEG1, 25); -static MESON8B_PCLK(meson8b_usb, HHI_GCLK_MPEG1, 26); -static MESON8B_PCLK(meson8b_vdin1, HHI_GCLK_MPEG1, 28); -static MESON8B_PCLK(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29); -static MESON8B_PCLK(meson8b_efuse, HHI_GCLK_MPEG1, 30); -static MESON8B_PCLK(meson8b_boot_rom, HHI_GCLK_MPEG1, 31); - -static MESON8B_PCLK(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1); -static MESON8B_PCLK(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static MESON8B_PCLK(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); -static MESON8B_PCLK(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4); -static MESON8B_PCLK(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); -static MESON8B_PCLK(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); -static MESON8B_PCLK(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11); -static MESON8B_PCLK(meson8b_dvin, HHI_GCLK_MPEG2, 12); -static MESON8B_PCLK(meson8b_uart2, HHI_GCLK_MPEG2, 15); -static MESON8B_PCLK(meson8b_sana, HHI_GCLK_MPEG2, 22); -static MESON8B_PCLK(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25); -static MESON8B_PCLK(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); -static MESON8B_PCLK(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29); - -static MESON8B_PCLK(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1); -static MESON8B_PCLK(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2); -static MESON8B_PCLK(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3); -static MESON8B_PCLK(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4); -static MESON8B_PCLK(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8); -static MESON8B_PCLK(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9); -static MESON8B_PCLK(meson8b_dac_clk, HHI_GCLK_OTHER, 10); -static MESON8B_PCLK(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14); -static MESON8B_PCLK(meson8b_iec958_gate, HHI_GCLK_OTHER, 16); -static MESON8B_PCLK(meson8b_enc480p, HHI_GCLK_OTHER, 20); -static MESON8B_PCLK(meson8b_rng1, HHI_GCLK_OTHER, 21); -static MESON8B_PCLK(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22); -static MESON8B_PCLK(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24); -static MESON8B_PCLK(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25); -static MESON8B_PCLK(meson8b_vclk2_other, HHI_GCLK_OTHER, 26); -static MESON8B_PCLK(meson8b_edp, HHI_GCLK_OTHER, 31); +#define MESON8B_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw, _flags) + +/* + * Everything Else (EE) domain gates + * + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +static MESON8B_PCLK(meson8b_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSE= D); +static MESON8B_PCLK(meson8b_spicc, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_sar_adc, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSE= D); +static MESON8B_PCLK(meson8b_smart_card, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_sdhc, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_stream, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED= ); +static MESON8B_PCLK(meson8b_async_fifo, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_sdio, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_abuf, HHI_GCLK_MPEG0, 18, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNU= SED); +static MESON8B_PCLK(meson8b_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED); + +static MESON8B_PCLK(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2, CLK_IGNORE_UNU= SED); +static MESON8B_PCLK(meson8b_eth, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_blkmv, HHI_GCLK_MPEG1, 14, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_aiu, HHI_GCLK_MPEG1, 15, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_nand, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_dos_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_usb, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_vdin1, HHI_GCLK_MPEG1, 28, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUS= ED); +static MESON8B_PCLK(meson8b_efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUS= ED); + +static MESON8B_PCLK(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_U= NUSED); +static MESON8B_PCLK(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_U= NUSED); +static MESON8B_PCLK(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3, CLK_IGNORE= _UNUSED); +static MESON8B_PCLK(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNU= SED); +static MESON8B_PCLK(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8, CLK_IGNOR= E_UNUSED); +static MESON8B_PCLK(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9, CLK_IGNOR= E_UNUSED); +static MESON8B_PCLK(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUS= ED); +static MESON8B_PCLK(meson8b_dvin, HHI_GCLK_MPEG2, 12, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_sana, HHI_GCLK_MPEG2, 22, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUS= ED); +static MESON8B_PCLK(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_I= GNORE_UNUSED); +static MESON8B_PCLK(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUS= ED); + +static MESON8B_PCLK(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_U= NUSED); +static MESON8B_PCLK(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_U= NUSED); +static MESON8B_PCLK(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_U= NUSED); +static MESON8B_PCLK(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_U= NUSED); +static MESON8B_PCLK(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8, CLK_IGNORE= _UNUSED); +static MESON8B_PCLK(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9, CLK_IGNORE= _UNUSED); +static MESON8B_PCLK(meson8b_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSE= D); +static MESON8B_PCLK(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSE= D); +static MESON8B_PCLK(meson8b_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22, CLK_IGNORE= _UNUSED); +static MESON8B_PCLK(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24, CLK_IGNORE= _UNUSED); +static MESON8B_PCLK(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_vclk2_other, HHI_GCLK_OTHER, 26, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED); =20 /* AIU gates */ -static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw); +static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw, CL= K_IGNORE_UNUSED); =20 -#define MESON_AIU_PCLK(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw) +#define MESON_AIU_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw, _flags) =20 -static MESON_AIU_PCLK(meson8b_iec958, HHI_GCLK_MPEG1, 7); -static MESON_AIU_PCLK(meson8b_i2s_out, HHI_GCLK_MPEG1, 8); -static MESON_AIU_PCLK(meson8b_amclk, HHI_GCLK_MPEG1, 9); -static MESON_AIU_PCLK(meson8b_aififo2, HHI_GCLK_MPEG1, 10); -static MESON_AIU_PCLK(meson8b_mixer, HHI_GCLK_MPEG1, 11); -static MESON_AIU_PCLK(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12); -static MESON_AIU_PCLK(meson8b_adc, HHI_GCLK_MPEG1, 13); +static MESON_AIU_PCLK(meson8b_iec958, HHI_GCLK_MPEG1, 7, CLK_IGNORE_UNUS= ED); +static MESON_AIU_PCLK(meson8b_i2s_out, HHI_GCLK_MPEG1, 8, CLK_IGNORE_UNU= SED); +static MESON_AIU_PCLK(meson8b_amclk, HHI_GCLK_MPEG1, 9, CLK_IGNORE_UNUSE= D); +static MESON_AIU_PCLK(meson8b_aififo2, HHI_GCLK_MPEG1, 10, CLK_IGNORE_UNU= SED); +static MESON_AIU_PCLK(meson8b_mixer, HHI_GCLK_MPEG1, 11, CLK_IGNORE_UNUSE= D); +static MESON_AIU_PCLK(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12, CLK_IGNORE_= UNUSED); +static MESON_AIU_PCLK(meson8b_adc, HHI_GCLK_MPEG1, 13, CLK_IGNORE_UNUSED); =20 /* Always On (AO) domain gates */ =20 -static MESON8B_PCLK(meson8b_ao_media_cpu, HHI_GCLK_AO, 0); -static MESON8B_PCLK(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1); -static MESON8B_PCLK(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2); -static MESON8B_PCLK(meson8b_ao_iface, HHI_GCLK_AO, 3); +static MESON8B_PCLK(meson8b_ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSE= D); +static MESON8B_PCLK(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED= ); +static MESON8B_PCLK(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED= ); +static MESON8B_PCLK(meson8b_ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED); =20 static struct clk_hw *meson8_hw_clks[] =3D { [CLKID_PLL_FIXED] =3D &meson8b_fixed_pll.hw, diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index fc1500df926d056ce17252987dd91095a8399b55..23b51d84d8de40aa540dbc6dd5d= b9fb627e579de 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -3165,61 +3165,70 @@ static struct clk_regmap s4_gen_clk =3D { }, }; =20 -#define S4_PCLK(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw) - -static S4_PCLK(s4_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0); -static S4_PCLK(s4_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1); -static S4_PCLK(s4_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4); -static S4_PCLK(s4_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6); -static S4_PCLK(s4_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13); -static S4_PCLK(s4_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14); -static S4_PCLK(s4_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16); -static S4_PCLK(s4_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24); -static S4_PCLK(s4_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25); -static S4_PCLK(s4_nand, CLKCTRL_SYS_CLK_EN0_REG0, 26); -static S4_PCLK(s4_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27); -static S4_PCLK(s4_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28); -static S4_PCLK(s4_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29); -static S4_PCLK(s4_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30); -static S4_PCLK(s4_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31); - -static S4_PCLK(s4_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0); -static S4_PCLK(s4_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3); -static S4_PCLK(s4_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5); -static S4_PCLK(s4_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6); -static S4_PCLK(s4_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7); -static S4_PCLK(s4_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8); -static S4_PCLK(s4_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9); -static S4_PCLK(s4_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11); -static S4_PCLK(s4_ts_ddr, CLKCTRL_SYS_CLK_EN0_REG1, 15); -static S4_PCLK(s4_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16); -static S4_PCLK(s4_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20); -static S4_PCLK(s4_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21); -static S4_PCLK(s4_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26); -static S4_PCLK(s4_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30); -static S4_PCLK(s4_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31); - -static S4_PCLK(s4_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0); -static S4_PCLK(s4_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1); -static S4_PCLK(s4_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2); -static S4_PCLK(s4_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4); -static S4_PCLK(s4_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5); -static S4_PCLK(s4_usb1_to_ddr, CLKCTRL_SYS_CLK_EN0_REG2, 8); -static S4_PCLK(s4_hdcp22, CLKCTRL_SYS_CLK_EN0_REG2, 10); -static S4_PCLK(s4_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11); -static S4_PCLK(s4_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18); -static S4_PCLK(s4_cpu_debug, CLKCTRL_SYS_CLK_EN0_REG2, 19); -static S4_PCLK(s4_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25); -static S4_PCLK(s4_demod, CLKCTRL_SYS_CLK_EN0_REG2, 27); -static S4_PCLK(s4_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28); -static S4_PCLK(s4_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30); - -static S4_PCLK(s4_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7); -static S4_PCLK(s4_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8); -static S4_PCLK(s4_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9); -static S4_PCLK(s4_pwm_gh, CLKCTRL_SYS_CLK_EN0_REG3, 10); -static S4_PCLK(s4_pwm_ij, CLKCTRL_SYS_CLK_EN0_REG3, 11); +#define S4_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw, _flags) + +/* + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +static S4_PCLK(s4_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_nand, CLKCTRL_SYS_CLK_EN0_REG0, 26, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27, CLK_IGNORE_UNUS= ED); +static S4_PCLK(s4_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31, CLK_IGNORE_UNUSED= ); + +static S4_PCLK(s4_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_ts_ddr, CLKCTRL_SYS_CLK_EN0_REG1, 15, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31, CLK_IGNORE_UNUSED= ); + +static S4_PCLK(s4_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4, CLK_IGNORE_UNU= SED); +static S4_PCLK(s4_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_usb1_to_ddr, CLKCTRL_SYS_CLK_EN0_REG2, 8, CLK_IGNORE_UN= USED); +static S4_PCLK(s4_hdcp22, CLKCTRL_SYS_CLK_EN0_REG2, 10, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_cpu_debug, CLKCTRL_SYS_CLK_EN0_REG2, 19, CLK_IGNORE_UNUS= ED); +static S4_PCLK(s4_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25, CLK_IGNORE_UNUSE= D); +static S4_PCLK(s4_demod, CLKCTRL_SYS_CLK_EN0_REG2, 27, CLK_IGNORE_UNUSED); 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Wed, 02 Jul 2025 08:27:35 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:5542:4bad:e07b:9489]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-454a9bcf35csm869205e9.20.2025.07.02.08.27.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jul 2025 08:27:34 -0700 (PDT) From: Jerome Brunet Date: Wed, 02 Jul 2025 17:26:20 +0200 Subject: [PATCH 22/26] clk: amlogic: introduce a common pclk definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-meson-clk-cleanup-24-v1-22-e163c9a1fc21@baylibre.com> References: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> In-Reply-To: <20250702-meson-clk-cleanup-24-v1-0-e163c9a1fc21@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 All Amlogic peripheral clocks are more or less the same. The only thing that differs is the parent data. Adapt the common pclk definition so it takes clk_parent_data and can be used by all controllers. Signed-off-by: Jerome Brunet Reviewed-by: Chuan Liu --- drivers/clk/meson/a1-peripherals.c | 4 +++- drivers/clk/meson/axg.c | 4 +++- drivers/clk/meson/g12a.c | 6 ++++-- drivers/clk/meson/gxbb.c | 26 +++++++++++++++++--------- drivers/clk/meson/meson-clkc-utils.h | 12 ++++++------ drivers/clk/meson/meson8b.c | 31 ++++++++++++++++++------------- drivers/clk/meson/s4-peripherals.c | 4 +++- 7 files changed, 54 insertions(+), 33 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peri= pherals.c index a7bd3822df18f5e043e58e2d7bbcaa24345ea404..5e0d58c01405c1925a5c25ee6d0= a547fd2e69911 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -1840,8 +1840,10 @@ static struct clk_regmap a1_cecb_32k_out =3D { }, }; =20 +static const struct clk_parent_data a1_pclk_parents =3D { .hw =3D &a1_sys.= hw }; + #define A1_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(a1_##_name, _reg, _bit, &a1_sys.hw, _flags) + MESON_PCLK(a1_##_name, _reg, _bit, &a1_pclk_parents, _flags) =20 /* * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index d83482d5da6ddc09b3dfaf77c6898456ef9f0d39..e41d1ead28ce2e949cb65955fc9= ae9dc0d788c08 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -1915,8 +1915,10 @@ static struct clk_regmap axg_gen_clk =3D { }, }; =20 +static const struct clk_parent_data axg_pclk_parents =3D { .hw =3D &axg_cl= k81.hw }; + #define AXG_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(axg_##_name, _reg, _bit, &axg_clk81.hw, _flags) + MESON_PCLK(axg_##_name, _reg, _bit, &axg_pclk_parents, _flags) =20 /* * Everything Else (EE) domain gates diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 7a737bfde4e62ec3d18db570e62cc77fb415676c..edd70b1d5df8a0581ef930d599e= 633171434e34e 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -4384,11 +4384,13 @@ static struct clk_regmap sm1_nna_core_clk =3D { }, }; =20 +static const struct clk_parent_data g12a_pclk_parents =3D { .hw =3D &g12a_= clk81.hw }; + #define G12A_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw, _flags) + MESON_PCLK(_name, _reg, _bit, &g12a_pclk_parents, _flags) =20 #define G12A_PCLK_RO(_name, _reg, _bit, _flags) \ - MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw, _flags) + MESON_PCLK_RO(_name, _reg, _bit, &g12a_pclk_parents, _flags) =20 /* * Everything Else (EE) domain gates diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index e2a88dc29901fe4617427907b382e878ae6ff7ae..4c253d001be9c0604fc87bb3d6e= a5241b489948b 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -2721,8 +2721,10 @@ static struct clk_regmap gxbb_gen_clk =3D { }, }; =20 +static const struct clk_parent_data gxbb_pclk_parents =3D { .hw =3D &gxbb_= clk81.hw }; + #define GXBB_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw, _flags) + MESON_PCLK(_name, _reg, _bit, &gxbb_pclk_parents, _flags) =20 /* * Everything Else (EE) domain gates @@ -2817,14 +2819,20 @@ static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3, CL= K_IGNORE_UNUSED); static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED); =20 /* AIU gates */ -static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw, CLK_IGN= ORE_UNUSED); -static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw, CLK= _IGNORE_UNUSED); -static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw, CL= K_IGNORE_UNUSED); -static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw, CLK_= IGNORE_UNUSED); -static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw, CL= K_IGNORE_UNUSED); -static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw, CLK_= IGNORE_UNUSED); -static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw,= CLK_IGNORE_UNUSED); -static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw, CLK_IG= NORE_UNUSED); +static const struct clk_parent_data gxbb_aiu_glue_parents =3D { .hw =3D &g= xbb_aiu.hw }; +static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu_glue_parent= s, CLK_IGNORE_UNUSED); + +static const struct clk_parent_data gxbb_aiu_pclk_parents =3D { .hw =3D &g= xbb_aiu_glue.hw }; +#define GXBB_AIU_PCLK(_name, _bit, _flags) \ + MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &gxbb_aiu_pclk_parents, _flags) + +static GXBB_AIU_PCLK(gxbb_iec958, 7, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_i2s_out, 8, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_amclk, 9, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_aififo2, 10, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_mixer, 11, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_mixer_iface, 12, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_adc, 13, CLK_IGNORE_UNUSED); =20 /* Array of all clocks provided by this provider */ =20 diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index 03e38992c4c73ff4ee24f0fa99b7c34134376992..95d9f85f7ca22f63a16f8665d6f= 7a250b21bfdb8 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -27,7 +27,7 @@ struct meson_clkc_data { int meson_clkc_syscon_probe(struct platform_device *pdev); int meson_clkc_mmio_probe(struct platform_device *pdev); =20 -#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname, _flags) \ +#define __MESON_PCLK(_name, _reg, _bit, _ops, _pdata, _flags) \ struct clk_regmap _name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D (_reg), \ @@ -36,16 +36,16 @@ struct clk_regmap _name =3D { \ .hw.init =3D &(struct clk_init_data) { \ .name =3D #_name, \ .ops =3D _ops, \ - .parent_hws =3D (const struct clk_hw *[]) { _pname }, \ + .parent_data =3D (_pdata), \ .num_parents =3D 1, \ .flags =3D (_flags), \ }, \ } =20 -#define MESON_PCLK(_name, _reg, _bit, _pname, _flags) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname, _flags) +#define MESON_PCLK(_name, _reg, _bit, _pdata, _flags) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pdata, _flags) =20 -#define MESON_PCLK_RO(_name, _reg, _bit, _pname, _flags) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname, _flags) +#define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags) =20 #endif diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index a16ebbbf664cdd56b2c74db4f88a8d0a22d2ddc3..95d0b9cbd90404ee1c7ec551a27= 48665b4ef9ccd 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -2701,8 +2701,10 @@ static struct clk_regmap meson8b_cts_i958 =3D { }, }; =20 +static const struct clk_parent_data meson8b_pclk_parents =3D { .hw =3D &me= son8b_clk81.hw }; + #define MESON8B_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw, _flags) + MESON_PCLK(_name, _reg, _bit, &meson8b_pclk_parents, _flags) =20 /* * Everything Else (EE) domain gates @@ -2785,18 +2787,21 @@ static MESON8B_PCLK(meson8b_vclk2_other, HHI_GCLK_O= THER, 26, CLK_IGNORE_UNUSED); static MESON8B_PCLK(meson8b_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED); =20 /* AIU gates */ -static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw, CL= K_IGNORE_UNUSED); - -#define MESON_AIU_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw, _flags) - -static MESON_AIU_PCLK(meson8b_iec958, HHI_GCLK_MPEG1, 7, CLK_IGNORE_UNUS= ED); -static MESON_AIU_PCLK(meson8b_i2s_out, HHI_GCLK_MPEG1, 8, CLK_IGNORE_UNU= SED); -static MESON_AIU_PCLK(meson8b_amclk, HHI_GCLK_MPEG1, 9, CLK_IGNORE_UNUSE= D); -static MESON_AIU_PCLK(meson8b_aififo2, HHI_GCLK_MPEG1, 10, CLK_IGNORE_UNU= SED); -static MESON_AIU_PCLK(meson8b_mixer, HHI_GCLK_MPEG1, 11, CLK_IGNORE_UNUSE= D); -static MESON_AIU_PCLK(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12, CLK_IGNORE_= UNUSED); -static MESON_AIU_PCLK(meson8b_adc, HHI_GCLK_MPEG1, 13, CLK_IGNORE_UNUSED); +static const struct clk_parent_data meson8b_aiu_glue_parents =3D { .hw =3D= &meson8b_aiu.hw }; +static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, + &meson8b_aiu_glue_parents, CLK_IGNORE_UNUSED); + +static const struct clk_parent_data meson8b_aiu_pclk_parents =3D { .hw =3D= &meson8b_aiu_glue.hw }; +#define MESON8B_AIU_PCLK(_name, _bit, _flags) \ + MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &meson8b_aiu_pclk_parents, _flags) + +static MESON8B_AIU_PCLK(meson8b_iec958, 7, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_i2s_out, 8, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_amclk, 9, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_aififo2, 10, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_mixer, 11, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_mixer_iface, 12, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_adc, 13, CLK_IGNORE_UNUSED); =20 /* Always On (AO) domain gates */ =20 diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index 23b51d84d8de40aa540dbc6dd5db9fb627e579de..3e048e645b080f9e5982ef908e3= f9c43578a0b5f 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -3165,8 +3165,10 @@ static struct clk_regmap s4_gen_clk =3D { }, }; =20 +static const struct clk_parent_data s4_pclk_parents =3D { .hw =3D &s4_sys_= clk.hw }; + #define S4_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw, _flags) + MESON_PCLK(_name, _reg, _bit, &s4_pclk_parents, _flags) =20 /* * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons --=20 2.47.2 From nobody Wed Oct 8 03:53:54 2025 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D92842FF467 for ; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Replace marcros defining pclks with the common one, reducing code duplication. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg-aoclk.c | 35 +++++++++----------------- drivers/clk/meson/c3-peripherals.c | 34 +++++++------------------- drivers/clk/meson/g12a-aoclk.c | 50 +++++++++++++++-------------------= ---- drivers/clk/meson/gxbb-aoclk.c | 33 +++++++++---------------- 4 files changed, 51 insertions(+), 101 deletions(-) diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c index 74c2f51424f11cc04a80a3a4918e4de0a5d11d08..902fbd34039cc06d512f1237a1e= 5d9050fd00b4b 100644 --- a/drivers/clk/meson/axg-aoclk.c +++ b/drivers/clk/meson/axg-aoclk.c @@ -34,30 +34,19 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define AXG_AO_GATE(_name, _bit, _flags) \ -static struct clk_regmap axg_ao_##_name =3D { \ - .data =3D &(struct clk_regmap_gate_data) { \ - .offset =3D (AO_RTI_GEN_CNTL_REG0), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "axg_ao_" #_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_data =3D &(const struct clk_parent_data) { \ - .fw_name =3D "mpeg-clk", \ - }, \ - .num_parents =3D 1, \ - .flags =3D (_flags), \ - }, \ -} +static const struct clk_parent_data axg_ao_pclk_parents =3D { .fw_name =3D= "mpeg-clk" }; =20 -AXG_AO_GATE(remote, 0, CLK_IGNORE_UNUSED); -AXG_AO_GATE(i2c_master, 1, CLK_IGNORE_UNUSED); -AXG_AO_GATE(i2c_slave, 2, CLK_IGNORE_UNUSED); -AXG_AO_GATE(uart1, 3, CLK_IGNORE_UNUSED); -AXG_AO_GATE(uart2, 5, CLK_IGNORE_UNUSED); -AXG_AO_GATE(ir_blaster, 6, CLK_IGNORE_UNUSED); -AXG_AO_GATE(saradc, 7, CLK_IGNORE_UNUSED); +#define AXG_AO_GATE(_name, _bit, _flags) \ + MESON_PCLK(axg_ao_##_name, AO_RTI_GEN_CNTL_REG0, _bit, \ + &axg_ao_pclk_parents, _flags) + +static AXG_AO_GATE(remote, 0, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(i2c_master, 1, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(i2c_slave, 2, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(uart1, 3, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(uart2, 5, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(ir_blaster, 6, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(saradc, 7, CLK_IGNORE_UNUSED); =20 static struct clk_regmap axg_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c index e9c1ef99be13d0542b8a972ceffe69c8a9977118..02c9820cd98655e57a290859b59= 5cf09d39e5fe3 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -164,30 +164,13 @@ static struct clk_regmap c3_rtc_clk =3D { }, }; =20 -#define C3_PCLK(_name, _reg, _bit, _fw_name, _ops, _flags) \ -struct clk_regmap c3_##_name =3D { \ - .data =3D &(struct clk_regmap_gate_data){ \ - .offset =3D (_reg), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "c3_" #_name, \ - .ops =3D _ops, \ - .parent_data =3D &(const struct clk_parent_data) { \ - .fw_name =3D (_fw_name), \ - }, \ - .num_parents =3D 1, \ - .flags =3D (_flags), \ - }, \ -} +static const struct clk_parent_data c3_sys_pclk_parents =3D { .fw_name =3D= "sysclk" }; =20 -#define C3_SYS_PCLK(_name, _reg, _bit, _flags) \ - C3_PCLK(_name, _reg, _bit, "sysclk", \ - &clk_regmap_gate_ops, _flags) +#define C3_SYS_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, _flags) =20 -#define C3_SYS_PCLK_RO(_name, _reg, _bit) \ - C3_PCLK(_name, _reg, _bit, "sysclk", \ - &clk_regmap_gate_ro_ops, 0) +#define C3_SYS_PCLK_RO(_name, _reg, _bit) \ + MESON_PCLK_RO(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, 0) =20 static C3_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0); static C3_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0); @@ -290,9 +273,10 @@ static C3_SYS_PCLK(sys_vc9000e, SYS_CLK_EN0_REG2, 2, = 0); static C3_SYS_PCLK(sys_pwm_mn, SYS_CLK_EN0_REG2, 3, 0); static C3_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG2, 4, 0); =20 -#define C3_AXI_PCLK(_name, _reg, _bit, _flags) \ - C3_PCLK(_name, _reg, _bit, "axiclk", \ - &clk_regmap_gate_ops, _flags) +static const struct clk_parent_data c3_axi_pclk_parents =3D { .fw_name =3D= "axiclk" }; + +#define C3_AXI_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(c3_##_name, _reg, _bit, &c3_axi_pclk_parents, _flags) =20 /* * NOTE: axi_sys_nic provides the clock to the AXI bus of the system NIC. = After diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c index 45e4df393feb6f916b6e035ad71e379e6e30ee99..96981da271fa1453ebbe433e36c= ff4409661fa6a 100644 --- a/drivers/clk/meson/g12a-aoclk.c +++ b/drivers/clk/meson/g12a-aoclk.c @@ -37,22 +37,10 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define G12A_AO_PCLK(_name, _reg, _bit, _flags) \ -static struct clk_regmap g12a_ao_##_name =3D { \ - .data =3D &(struct clk_regmap_gate_data) { \ - .offset =3D (_reg), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "g12a_ao_" #_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_data =3D &(const struct clk_parent_data) { \ - .fw_name =3D "mpeg-clk", \ - }, \ - .num_parents =3D 1, \ - .flags =3D (_flags), \ - }, \ -} +static const struct clk_parent_data g12a_ao_pclk_parents =3D { .fw_name = =3D "mpeg-clk" }; + +#define G12A_AO_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(g12a_ao_##_name, _reg, _bit, &g12a_ao_pclk_parents, _flags) =20 /* * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons @@ -63,22 +51,22 @@ static struct clk_regmap g12a_ao_##_name =3D { \ * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le * for a particular clock. */ -G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(uart, AO_CLK_GATE0, 4, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(uart, AO_CLK_GATE0, 4, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8, CLK_IGNORE_UNUSED); =20 -G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5, CLK_IGNORE_UNUSED); =20 static struct clk_regmap g12a_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 2bf45fd7fe4ba0783e736fbbb126209870985b22..c7dfb3a06cb5f70c98f65bb91b9= 37e1b870b34fe 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c @@ -23,29 +23,18 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define GXBB_AO_PCLK(_name, _bit, _flags) \ -static struct clk_regmap gxbb_ao_##_name =3D { \ - .data =3D &(struct clk_regmap_gate_data) { \ - .offset =3D AO_RTI_GEN_CNTL_REG0, \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "gxbb_ao_" #_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_data =3D &(const struct clk_parent_data) { \ - .fw_name =3D "mpeg-clk", \ - }, \ - .num_parents =3D 1, \ - .flags =3D (_flags), \ - }, \ -} +static const struct clk_parent_data gxbb_ao_pclk_parents =3D { .fw_name = =3D "mpeg-clk" }; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Device composite clocks tend to reproduce the usual sel/div/gate arrangement. Add macros to help define simple composite clocks in the system. The idea is _not_ to replace all instances of mux, div or gate with those macros. It is rather to use it for recurring and/or simple composite clocks, reducing controller verbosity where it makes sense. This should help reviews focus on the tricky parts. Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson-clkc-utils.h | 57 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 57 insertions(+) diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index 95d9f85f7ca22f63a16f8665d6f7a250b21bfdb8..ddadf14b4923781d8807546f35a= 1ba2e6a8a894a 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -48,4 +48,61 @@ struct clk_regmap _name =3D { \ #define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \ __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags) =20 +/* Helpers for the usual sel/div/gate composite clocks */ +#define MESON_COMP_SEL(_prefix, _name, _reg, _shift, _mask, _pdata, \ + _table, _dflags, _iflags) \ +struct clk_regmap _prefix##_name##_sel =3D { \ + .data =3D &(struct clk_regmap_mux_data) { \ + .offset =3D (_reg), \ + .mask =3D (_mask), \ + .shift =3D (_shift), \ + .flags =3D (_dflags), \ + .table =3D (_table), \ + }, \ + .hw.init =3D &(struct clk_init_data){ \ + .name =3D #_name "_sel", \ + .ops =3D &clk_regmap_mux_ops, \ + .parent_data =3D _pdata, \ + .num_parents =3D ARRAY_SIZE(_pdata), \ + .flags =3D (_iflags), \ + }, \ +} + +#define MESON_COMP_DIV(_prefix, _name, _reg, _shift, _width, \ + _dflags, _iflags) \ +struct clk_regmap _prefix##_name##_div =3D { \ + .data =3D &(struct clk_regmap_div_data) { \ + .offset =3D (_reg), \ + .shift =3D (_shift), \ + .width =3D (_width), \ + .flags =3D (_dflags), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name "_div", \ + .ops =3D &clk_regmap_divider_ops, \ + .parent_hws =3D (const struct clk_hw *[]) { \ + &_prefix##_name##_sel.hw \ + }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#define MESON_COMP_GATE(_prefix, _name, _reg, _bit, _iflags) \ +struct clk_regmap _prefix##_name =3D { \ + .data =3D &(struct clk_regmap_gate_data) { \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_hws =3D (const struct clk_hw *[]) { \ + &_prefix##_name##_div.hw \ + }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + #endif --=20 2.47.2 From nobody Wed Oct 8 03:53:54 2025 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5373A2FF482 for ; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 s4 and c3 follow exactly the same structure when it comes to PWM clocks but differ in the way these clocks are described, for no obvious reason. Align the description of the pwm clocks of these SoCs with the composite clock helpers. Signed-off-by: Jerome Brunet Reviewed-by: Chuan Liu --- drivers/clk/meson/c3-peripherals.c | 204 +++++---------- drivers/clk/meson/s4-peripherals.c | 508 +++------------------------------= ---- 2 files changed, 103 insertions(+), 609 deletions(-) diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c index 02c9820cd98655e57a290859b595cf09d39e5fe3..fd35f9b7994720d069c5f72142d= 6064790d40b60 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -48,6 +48,15 @@ #define SPIFC_CLK_CTRL 0x1a0 #define NNA_CLK_CTRL 0x220 =20 +#define C3_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ + MESON_COMP_SEL(c3_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) + +#define C3_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(c3_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define C3_COMP_GATE(_name, _reg, _bit) \ + MESON_COMP_GATE(c3_, _name, _reg, _bit, CLK_SET_RATE_PARENT) + static struct clk_regmap c3_rtc_xtal_clkin =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D RTC_BY_OSCIN_CTRL0, @@ -512,146 +521,61 @@ static const struct clk_parent_data c3_pwm_parents[]= =3D { { .fw_name =3D "fdiv3" } }; =20 -#define C3_PWM_CLK_MUX(_name, _reg, _shift) { \ - .data =3D &(struct clk_regmap_mux_data) { \ - .offset =3D _reg, \ - .mask =3D 0x3, \ - .shift =3D _shift, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name "_sel", \ - .ops =3D &clk_regmap_mux_ops, \ - .parent_data =3D c3_pwm_parents, \ - .num_parents =3D ARRAY_SIZE(c3_pwm_parents), \ - }, \ -} - -#define C3_PWM_CLK_DIV(_name, _reg, _shift) { \ - .data =3D &(struct clk_regmap_div_data) { \ - .offset =3D _reg, \ - .shift =3D _shift, \ - .width =3D 8, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name "_div", \ - .ops =3D &clk_regmap_divider_ops, \ - .parent_names =3D (const char *[]) { #_name "_sel" },\ - .num_parents =3D 1, \ - .flags =3D CLK_SET_RATE_PARENT, \ - }, \ -} - -#define C3_PWM_CLK_GATE(_name, _reg, _bit) { \ - .data =3D &(struct clk_regmap_gate_data) { \ - .offset =3D _reg, \ - .bit_idx =3D _bit, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_names =3D (const char *[]) { #_name "_div" },\ - .num_parents =3D 1, \ - .flags =3D CLK_SET_RATE_PARENT, \ - }, \ -} - -static struct clk_regmap c3_pwm_a_sel =3D - C3_PWM_CLK_MUX(pwm_a, PWM_CLK_AB_CTRL, 9); -static struct clk_regmap c3_pwm_a_div =3D - C3_PWM_CLK_DIV(pwm_a, PWM_CLK_AB_CTRL, 0); -static struct clk_regmap c3_pwm_a =3D - C3_PWM_CLK_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); - -static struct clk_regmap c3_pwm_b_sel =3D - C3_PWM_CLK_MUX(pwm_b, PWM_CLK_AB_CTRL, 25); -static struct clk_regmap c3_pwm_b_div =3D - C3_PWM_CLK_DIV(pwm_b, PWM_CLK_AB_CTRL, 16); -static struct clk_regmap c3_pwm_b =3D - C3_PWM_CLK_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); - -static struct clk_regmap c3_pwm_c_sel =3D - C3_PWM_CLK_MUX(pwm_c, PWM_CLK_CD_CTRL, 9); -static struct clk_regmap c3_pwm_c_div =3D - C3_PWM_CLK_DIV(pwm_c, PWM_CLK_CD_CTRL, 0); -static struct clk_regmap c3_pwm_c =3D - C3_PWM_CLK_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); - -static struct clk_regmap c3_pwm_d_sel =3D - C3_PWM_CLK_MUX(pwm_d, PWM_CLK_CD_CTRL, 25); -static struct clk_regmap c3_pwm_d_div =3D - C3_PWM_CLK_DIV(pwm_d, PWM_CLK_CD_CTRL, 16); -static struct clk_regmap c3_pwm_d =3D - C3_PWM_CLK_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); - -static struct clk_regmap c3_pwm_e_sel =3D - C3_PWM_CLK_MUX(pwm_e, PWM_CLK_EF_CTRL, 9); -static struct clk_regmap c3_pwm_e_div =3D - C3_PWM_CLK_DIV(pwm_e, PWM_CLK_EF_CTRL, 0); -static struct clk_regmap c3_pwm_e =3D - C3_PWM_CLK_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); - -static struct clk_regmap c3_pwm_f_sel =3D - C3_PWM_CLK_MUX(pwm_f, PWM_CLK_EF_CTRL, 25); -static struct clk_regmap c3_pwm_f_div =3D - C3_PWM_CLK_DIV(pwm_f, PWM_CLK_EF_CTRL, 16); -static struct clk_regmap c3_pwm_f =3D - C3_PWM_CLK_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); - -static struct clk_regmap c3_pwm_g_sel =3D - C3_PWM_CLK_MUX(pwm_g, PWM_CLK_GH_CTRL, 9); -static struct clk_regmap c3_pwm_g_div =3D - C3_PWM_CLK_DIV(pwm_g, PWM_CLK_GH_CTRL, 0); -static struct clk_regmap c3_pwm_g =3D - C3_PWM_CLK_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); - -static struct clk_regmap c3_pwm_h_sel =3D - C3_PWM_CLK_MUX(pwm_h, PWM_CLK_GH_CTRL, 25); -static struct clk_regmap c3_pwm_h_div =3D - C3_PWM_CLK_DIV(pwm_h, PWM_CLK_GH_CTRL, 16); -static struct clk_regmap c3_pwm_h =3D - C3_PWM_CLK_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); - -static struct clk_regmap c3_pwm_i_sel =3D - C3_PWM_CLK_MUX(pwm_i, PWM_CLK_IJ_CTRL, 9); -static struct clk_regmap c3_pwm_i_div =3D - C3_PWM_CLK_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0); -static struct clk_regmap c3_pwm_i =3D - C3_PWM_CLK_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8); - -static struct clk_regmap c3_pwm_j_sel =3D - C3_PWM_CLK_MUX(pwm_j, PWM_CLK_IJ_CTRL, 25); -static struct clk_regmap c3_pwm_j_div =3D - C3_PWM_CLK_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16); -static struct clk_regmap c3_pwm_j =3D - C3_PWM_CLK_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24); - -static struct clk_regmap c3_pwm_k_sel =3D - C3_PWM_CLK_MUX(pwm_k, PWM_CLK_KL_CTRL, 9); -static struct clk_regmap c3_pwm_k_div =3D - C3_PWM_CLK_DIV(pwm_k, PWM_CLK_KL_CTRL, 0); -static struct clk_regmap c3_pwm_k =3D - C3_PWM_CLK_GATE(pwm_k, PWM_CLK_KL_CTRL, 8); - -static struct clk_regmap c3_pwm_l_sel =3D - C3_PWM_CLK_MUX(pwm_l, PWM_CLK_KL_CTRL, 25); -static struct clk_regmap c3_pwm_l_div =3D - C3_PWM_CLK_DIV(pwm_l, PWM_CLK_KL_CTRL, 16); -static struct clk_regmap c3_pwm_l =3D - C3_PWM_CLK_GATE(pwm_l, PWM_CLK_KL_CTRL, 24); - -static struct clk_regmap c3_pwm_m_sel =3D - C3_PWM_CLK_MUX(pwm_m, PWM_CLK_MN_CTRL, 9); -static struct clk_regmap c3_pwm_m_div =3D - C3_PWM_CLK_DIV(pwm_m, PWM_CLK_MN_CTRL, 0); -static struct clk_regmap c3_pwm_m =3D - C3_PWM_CLK_GATE(pwm_m, PWM_CLK_MN_CTRL, 8); - -static struct clk_regmap c3_pwm_n_sel =3D - C3_PWM_CLK_MUX(pwm_n, PWM_CLK_MN_CTRL, 25); -static struct clk_regmap c3_pwm_n_div =3D - C3_PWM_CLK_DIV(pwm_n, PWM_CLK_MN_CTRL, 16); -static struct clk_regmap c3_pwm_n =3D - C3_PWM_CLK_GATE(pwm_n, PWM_CLK_MN_CTRL, 24); +static C3_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8); +static C3_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); + +static C3_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8); +static C3_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); + +static C3_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8); +static C3_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); + +static C3_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8); +static C3_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); + +static C3_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8); +static C3_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); + +static C3_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8); +static C3_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); + +static C3_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8); +static C3_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); + +static C3_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8); +static C3_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); + +static C3_COMP_SEL(pwm_i, PWM_CLK_IJ_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0, 8); +static C3_COMP_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8); + +static C3_COMP_SEL(pwm_j, PWM_CLK_IJ_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16, 8); +static C3_COMP_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24); + +static C3_COMP_SEL(pwm_k, PWM_CLK_KL_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_k, PWM_CLK_KL_CTRL, 0, 8); +static C3_COMP_GATE(pwm_k, PWM_CLK_KL_CTRL, 8); + +static C3_COMP_SEL(pwm_l, PWM_CLK_KL_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_l, PWM_CLK_KL_CTRL, 16, 8); +static C3_COMP_GATE(pwm_l, PWM_CLK_KL_CTRL, 24); + +static C3_COMP_SEL(pwm_m, PWM_CLK_MN_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_m, PWM_CLK_MN_CTRL, 0, 8); +static C3_COMP_GATE(pwm_m, PWM_CLK_MN_CTRL, 8); + +static C3_COMP_SEL(pwm_n, PWM_CLK_MN_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_n, PWM_CLK_MN_CTRL, 16, 8); +static C3_COMP_GATE(pwm_n, PWM_CLK_MN_CTRL, 24); =20 static const struct clk_parent_data c3_spicc_parents[] =3D { { .fw_name =3D "oscin" }, diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index 3e048e645b080f9e5982ef908e3f9c43578a0b5f..6d69b132d1e1f5950d73757c45b= 920c9c9052344 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -62,6 +62,15 @@ #define CLKCTRL_PWM_CLK_IJ_CTRL 0x190 #define CLKCTRL_DEMOD_CLK_CTRL 0x200 =20 +#define S4_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ + MESON_COMP_SEL(s4_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) + +#define S4_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(s4_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define S4_COMP_GATE(_name, _reg, _bit) \ + MESON_COMP_GATE(s4_, _name, _reg, _bit, CLK_SET_RATE_PARENT) + static struct clk_regmap s4_rtc_32k_by_oscin_clkin =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_RTC_BY_OSCIN_CTRL0, @@ -2559,484 +2568,45 @@ static const struct clk_parent_data s4_pwm_parents= [] =3D { { .fw_name =3D "fclk_div3", }, }; =20 -static struct clk_regmap s4_pwm_a_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_a_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_a_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_a_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_a_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_a =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_a_gate", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_a_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_b_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_b_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_b_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_b_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_b_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_b =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_b", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_b_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_c_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_c_mux", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_c_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_c_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_c_sel.hw - }, - .num_parents =3D 1, - }, -}; - -static struct clk_regmap s4_pwm_c =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_c", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_c_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_d_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_d_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_d_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_d_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_d_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_d =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_d", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_d_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_e_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_e_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_e_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_e_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_e_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_e =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_e", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_e_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_f_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_f_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; +static S4_COMP_SEL(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0, 8); +static S4_COMP_GATE(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8); =20 -static struct clk_regmap s4_pwm_f_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_f_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_f_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16, 8); +static S4_COMP_GATE(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24); =20 -static struct clk_regmap s4_pwm_f =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_f", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_f_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0, 8); +static S4_COMP_GATE(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8); =20 -static struct clk_regmap s4_pwm_g_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_g_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; +static S4_COMP_SEL(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16, 8); +static S4_COMP_GATE(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24); =20 -static struct clk_regmap s4_pwm_g_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_g_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_g_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0, 8); +static S4_COMP_GATE(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8); =20 -static struct clk_regmap s4_pwm_g =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_g", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_g_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16, 8); +static S4_COMP_GATE(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24); =20 -static struct clk_regmap s4_pwm_h_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_h_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; +static S4_COMP_SEL(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 0, 8); +static S4_COMP_GATE(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 8); =20 -static struct clk_regmap s4_pwm_h_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_h_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_h_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 16, 8); +static S4_COMP_GATE(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 24); =20 -static struct clk_regmap s4_pwm_h =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_h", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_h_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 0, 8); +static S4_COMP_GATE(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 8); =20 -static struct clk_regmap s4_pwm_i_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_i_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_i_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_i_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_i_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_i =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_i", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_i_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_j_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_j_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_j_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_j_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_j_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_j =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_j", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_j_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 16, 8); +static S4_COMP_GATE(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 24); =20 static struct clk_regmap s4_saradc_sel =3D { .data =3D &(struct clk_regmap_mux_data) { --=20 2.47.2 From nobody Wed Oct 8 03:53:54 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39A5E2FF496 for ; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Use the composite clock helpers to define simple composite clocks of the c3-peripherals clock controller. This reduces the verbosity of the controller code on these very simple parts, making maintenance simpler. Signed-off-by: Jerome Brunet Reviewed-by: Chuan Liu --- drivers/clk/meson/c3-peripherals.c | 1029 +++-----------------------------= ---- 1 file changed, 63 insertions(+), 966 deletions(-) diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c index fd35f9b7994720d069c5f72142d6064790d40b60..b158756cfee4dd4bad5c0c9576d= a02d2cb8ee515 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -467,52 +467,9 @@ static const struct clk_parent_data c3_saradc_parents[= ] =3D { { .fw_name =3D "sysclk" } }; =20 -static struct clk_regmap c3_saradc_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SAR_CLK_CTRL0, - .mask =3D 0x1, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "saradc_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_saradc_parents, - .num_parents =3D ARRAY_SIZE(c3_saradc_parents), - }, -}; - -static struct clk_regmap c3_saradc_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SAR_CLK_CTRL0, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "saradc_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_saradc_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_saradc =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SAR_CLK_CTRL0, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "saradc", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_saradc_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, c3_saradc_parents); +static C3_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8); +static C3_COMP_GATE(saradc, SAR_CLK_CTRL0, 8); =20 static const struct clk_parent_data c3_pwm_parents[] =3D { { .fw_name =3D "oscin" }, @@ -588,99 +545,13 @@ static const struct clk_parent_data c3_spicc_parents[= ] =3D { { .fw_name =3D "gp1" } }; =20 -static struct clk_regmap c3_spicc_a_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SPICC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_a_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_spicc_parents, - .num_parents =3D ARRAY_SIZE(c3_spicc_parents), - }, -}; - -static struct clk_regmap c3_spicc_a_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SPICC_CLK_CTRL, - .shift =3D 0, - .width =3D 6, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_a_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spicc_a_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_spicc_a =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SPICC_CLK_CTRL, - .bit_idx =3D 6, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_a", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spicc_a_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_spicc_b_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SPICC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 23, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_b_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_spicc_parents, - .num_parents =3D ARRAY_SIZE(c3_spicc_parents), - }, -}; - -static struct clk_regmap c3_spicc_b_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SPICC_CLK_CTRL, - .shift =3D 16, - .width =3D 6, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_b_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spicc_b_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(spicc_a, SPICC_CLK_CTRL, 7, 0x7, c3_spicc_parents); +static C3_COMP_DIV(spicc_a, SPICC_CLK_CTRL, 0, 6); +static C3_COMP_GATE(spicc_a, SPICC_CLK_CTRL, 6); =20 -static struct clk_regmap c3_spicc_b =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SPICC_CLK_CTRL, - .bit_idx =3D 22, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_b", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spicc_b_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(spicc_b, SPICC_CLK_CTRL, 23, 0x7, c3_spicc_parents); +static C3_COMP_DIV(spicc_b, SPICC_CLK_CTRL, 16, 6); +static C3_COMP_GATE(spicc_b, SPICC_CLK_CTRL, 22); =20 static const struct clk_parent_data c3_spifc_parents[] =3D { { .fw_name =3D "gp0" }, @@ -693,52 +564,9 @@ static const struct clk_parent_data c3_spifc_parents[]= =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_spifc_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SPIFC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spifc_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_spifc_parents, - .num_parents =3D ARRAY_SIZE(c3_spifc_parents), - }, -}; - -static struct clk_regmap c3_spifc_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SPIFC_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spifc_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spifc_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_spifc =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SPIFC_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spifc", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spifc_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(spifc, SPIFC_CLK_CTRL, 9, 0x7, c3_spifc_parents); +static C3_COMP_DIV(spifc, SPIFC_CLK_CTRL, 0, 7); +static C3_COMP_GATE(spifc, SPIFC_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_sd_emmc_parents[] =3D { { .fw_name =3D "oscin" }, @@ -751,146 +579,17 @@ static const struct clk_parent_data c3_sd_emmc_paren= ts[] =3D { { .fw_name =3D "gp0" } }; =20 -static struct clk_regmap c3_sd_emmc_a_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_a_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_sd_emmc_parents, - .num_parents =3D ARRAY_SIZE(c3_sd_emmc_parents), - }, -}; - -static struct clk_regmap c3_sd_emmc_a_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_a_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_a_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_sd_emmc_a =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .bit_idx =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_a", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_a_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_sd_emmc_b_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_b_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_sd_emmc_parents, - .num_parents =3D ARRAY_SIZE(c3_sd_emmc_parents), - }, -}; - -static struct clk_regmap c3_sd_emmc_b_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .shift =3D 16, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_b_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_b_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_sd_emmc_b =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .bit_idx =3D 23, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_b", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_b_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_sd_emmc_c_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D NAND_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_c_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_sd_emmc_parents, - .num_parents =3D ARRAY_SIZE(c3_sd_emmc_parents), - }, -}; +static C3_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, c3_sd_emmc_parents= ); +static C3_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7); +static C3_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7); =20 -static struct clk_regmap c3_sd_emmc_c_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D NAND_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_c_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_c_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL, 25, 0x7, c3_sd_emmc_parent= s); +static C3_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL, 16, 7); +static C3_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL, 23); =20 -static struct clk_regmap c3_sd_emmc_c =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D NAND_CLK_CTRL, - .bit_idx =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_c", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_c_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, c3_sd_emmc_parents); +static C3_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7); +static C3_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7); =20 static struct clk_regmap c3_ts_div =3D { .data =3D &(struct clk_regmap_div_data) { @@ -996,52 +695,9 @@ static const struct clk_parent_data c3_mipi_dsi_meas_p= arents[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_mipi_dsi_meas_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VDIN_MEAS_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 21, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "mipi_dsi_meas_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_mipi_dsi_meas_parents, - .num_parents =3D ARRAY_SIZE(c3_mipi_dsi_meas_parents), - }, -}; - -static struct clk_regmap c3_mipi_dsi_meas_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VDIN_MEAS_CLK_CTRL, - .shift =3D 12, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "mipi_dsi_meas_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_mipi_dsi_meas_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_mipi_dsi_meas =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VDIN_MEAS_CLK_CTRL, - .bit_idx =3D 20, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "mipi_dsi_meas", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_mipi_dsi_meas_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 21, 0x7, c3_mipi_dsi= _meas_parents); +static C3_COMP_DIV(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 12, 7); +static C3_COMP_GATE(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 20); =20 static const struct clk_parent_data c3_dsi_phy_parents[] =3D { { .fw_name =3D "gp1" }, @@ -1054,52 +710,9 @@ static const struct clk_parent_data c3_dsi_phy_parent= s[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_dsi_phy_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D MIPIDSI_PHY_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 12, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dsi_phy_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_dsi_phy_parents, - .num_parents =3D ARRAY_SIZE(c3_dsi_phy_parents), - }, -}; - -static struct clk_regmap c3_dsi_phy_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D MIPIDSI_PHY_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dsi_phy_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_dsi_phy_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_dsi_phy =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D MIPIDSI_PHY_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dsi_phy", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_dsi_phy_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 12, 0x7, c3_dsi_phy_pare= nts); +static C3_COMP_DIV(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 0, 7); +static C3_COMP_GATE(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_vout_mclk_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1112,52 +725,9 @@ static const struct clk_parent_data c3_vout_mclk_pare= nts[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_vout_mclk_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VOUTENC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_mclk_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vout_mclk_parents, - .num_parents =3D ARRAY_SIZE(c3_vout_mclk_parents), - }, -}; - -static struct clk_regmap c3_vout_mclk_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VOUTENC_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_mclk_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vout_mclk_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vout_mclk =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VOUTENC_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_mclk", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vout_mclk_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vout_mclk, VOUTENC_CLK_CTRL, 9, 0x7, c3_vout_mclk_paren= ts); +static C3_COMP_DIV(vout_mclk, VOUTENC_CLK_CTRL, 0, 7); +static C3_COMP_GATE(vout_mclk, VOUTENC_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_vout_enc_parents[] =3D { { .fw_name =3D "gp1" }, @@ -1170,52 +740,9 @@ static const struct clk_parent_data c3_vout_enc_paren= ts[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_vout_enc_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VOUTENC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_enc_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vout_enc_parents, - .num_parents =3D ARRAY_SIZE(c3_vout_enc_parents), - }, -}; - -static struct clk_regmap c3_vout_enc_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VOUTENC_CLK_CTRL, - .shift =3D 16, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_enc_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vout_enc_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vout_enc =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VOUTENC_CLK_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_enc", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vout_enc_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vout_enc, VOUTENC_CLK_CTRL, 25, 0x7, c3_vout_enc_parent= s); +static C3_COMP_DIV(vout_enc, VOUTENC_CLK_CTRL, 16, 7); +static C3_COMP_GATE(vout_enc, VOUTENC_CLK_CTRL, 24); =20 static const struct clk_parent_data c3_hcodec_pre_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1228,99 +755,13 @@ static const struct clk_parent_data c3_hcodec_pre_pa= rents[] =3D { { .fw_name =3D "oscin" } }; =20 -static struct clk_regmap c3_hcodec_0_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VDEC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_0_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_hcodec_pre_parents, - .num_parents =3D ARRAY_SIZE(c3_hcodec_pre_parents), - }, -}; +static C3_COMP_SEL(hcodec_0, VDEC_CLK_CTRL, 9, 0x7, c3_hcodec_pre_parents= ); +static C3_COMP_DIV(hcodec_0, VDEC_CLK_CTRL, 0, 7); +static C3_COMP_GATE(hcodec_0, VDEC_CLK_CTRL, 8); =20 -static struct clk_regmap c3_hcodec_0_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VDEC_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_0_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_hcodec_0_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_hcodec_0 =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VDEC_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_0", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_hcodec_0_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_hcodec_1_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VDEC3_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_1_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_hcodec_pre_parents, - .num_parents =3D ARRAY_SIZE(c3_hcodec_pre_parents), - }, -}; - -static struct clk_regmap c3_hcodec_1_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VDEC3_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_1_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_hcodec_1_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_hcodec_1 =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VDEC3_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_1", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_hcodec_1_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(hcodec_1, VDEC3_CLK_CTRL, 9, 0x7, c3_hcodec_pre_parents= ); +static C3_COMP_DIV(hcodec_1, VDEC3_CLK_CTRL, 0, 7); +static C3_COMP_GATE(hcodec_1, VDEC3_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_hcodec_parents[] =3D { { .hw =3D &c3_hcodec_0.hw }, @@ -1353,99 +794,13 @@ static const struct clk_parent_data c3_vc9000e_paren= ts[] =3D { { .fw_name =3D "gp0" } }; =20 -static struct clk_regmap c3_vc9000e_aclk_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VC9000E_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_aclk_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vc9000e_parents, - .num_parents =3D ARRAY_SIZE(c3_vc9000e_parents), - }, -}; - -static struct clk_regmap c3_vc9000e_aclk_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VC9000E_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_aclk_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vc9000e_aclk_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vc9000e_aclk =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VC9000E_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_aclk", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vc9000e_aclk_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vc9000e_core_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VC9000E_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_core_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vc9000e_parents, - .num_parents =3D ARRAY_SIZE(c3_vc9000e_parents), - }, -}; - -static struct clk_regmap c3_vc9000e_core_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VC9000E_CLK_CTRL, - .shift =3D 16, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_core_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vc9000e_core_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vc9000e_aclk, VC9000E_CLK_CTRL, 9, 0x7, c3_vc9000e_pare= nts); +static C3_COMP_DIV(vc9000e_aclk, VC9000E_CLK_CTRL, 0, 7); +static C3_COMP_GATE(vc9000e_aclk, VC9000E_CLK_CTRL, 8); =20 -static struct clk_regmap c3_vc9000e_core =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VC9000E_CLK_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_core", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vc9000e_core_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vc9000e_core, VC9000E_CLK_CTRL, 25, 0x7, c3_vc9000e_par= ents); +static C3_COMP_DIV(vc9000e_core, VC9000E_CLK_CTRL, 16, 7); +static C3_COMP_GATE(vc9000e_core, VC9000E_CLK_CTRL, 24); =20 static const struct clk_parent_data c3_csi_phy_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1458,52 +813,9 @@ static const struct clk_parent_data c3_csi_phy_parent= s[] =3D { { .fw_name =3D "oscin" } }; =20 -static struct clk_regmap c3_csi_phy0_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D ISP0_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "csi_phy0_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_csi_phy_parents, - .num_parents =3D ARRAY_SIZE(c3_csi_phy_parents), - }, -}; - -static struct clk_regmap c3_csi_phy0_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D ISP0_CLK_CTRL, - .shift =3D 16, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "csi_phy0_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_csi_phy0_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_csi_phy0 =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D ISP0_CLK_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "csi_phy0", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_csi_phy0_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(csi_phy0, ISP0_CLK_CTRL, 25, 0x7, c3_csi_phy_parents); +static C3_COMP_DIV(csi_phy0, ISP0_CLK_CTRL, 16, 7); +static C3_COMP_GATE(csi_phy0, ISP0_CLK_CTRL, 24); =20 static const struct clk_parent_data c3_dewarpa_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1516,52 +828,9 @@ static const struct clk_parent_data c3_dewarpa_parent= s[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_dewarpa_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D DEWARPA_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dewarpa_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_dewarpa_parents, - .num_parents =3D ARRAY_SIZE(c3_dewarpa_parents), - }, -}; - -static struct clk_regmap c3_dewarpa_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D DEWARPA_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dewarpa_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_dewarpa_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_dewarpa =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D DEWARPA_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dewarpa", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_dewarpa_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(dewarpa, DEWARPA_CLK_CTRL, 9, 0x7, c3_dewarpa_parents); +static C3_COMP_DIV(dewarpa, DEWARPA_CLK_CTRL, 0, 7); +static C3_COMP_GATE(dewarpa, DEWARPA_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_isp_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1574,52 +843,9 @@ static const struct clk_parent_data c3_isp_parents[] = =3D { { .fw_name =3D "oscin" } }; =20 -static struct clk_regmap c3_isp0_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D ISP0_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "isp0_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_isp_parents, - .num_parents =3D ARRAY_SIZE(c3_isp_parents), - }, -}; - -static struct clk_regmap c3_isp0_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D ISP0_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "isp0_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_isp0_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_isp0 =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D ISP0_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "isp0", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_isp0_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(isp0, ISP0_CLK_CTRL, 9, 0x7, c3_isp_parents); +static C3_COMP_DIV(isp0, ISP0_CLK_CTRL, 0, 7); +static C3_COMP_GATE(isp0, ISP0_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_nna_core_parents[] =3D { { .fw_name =3D "oscin" }, @@ -1632,52 +858,9 @@ static const struct clk_parent_data c3_nna_core_paren= ts[] =3D { { .fw_name =3D "hifi" } }; =20 -static struct clk_regmap c3_nna_core_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D NNA_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "nna_core_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_nna_core_parents, - .num_parents =3D ARRAY_SIZE(c3_nna_core_parents), - }, -}; - -static struct clk_regmap c3_nna_core_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D NNA_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "nna_core_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_nna_core_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_nna_core =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D NNA_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "nna_core", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_nna_core_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(nna_core, NNA_CLK_CTRL, 9, 0x7, c3_nna_core_parents); +static C3_COMP_DIV(nna_core, NNA_CLK_CTRL, 0, 7); +static C3_COMP_GATE(nna_core, NNA_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_ge2d_parents[] =3D { { .fw_name =3D "oscin" }, @@ -1690,52 +873,9 @@ static const struct clk_parent_data c3_ge2d_parents[]= =3D { { .hw =3D &c3_rtc_clk.hw } }; =20 -static struct clk_regmap c3_ge2d_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D GE2D_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "ge2d_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_ge2d_parents, - .num_parents =3D ARRAY_SIZE(c3_ge2d_parents), - }, -}; - -static struct clk_regmap c3_ge2d_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D GE2D_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "ge2d_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_ge2d_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_ge2d =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D GE2D_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "ge2d", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_ge2d_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(ge2d, GE2D_CLK_CTRL, 9, 0x7, c3_ge2d_parents); +static C3_COMP_DIV(ge2d, GE2D_CLK_CTRL, 0, 7); +static C3_COMP_GATE(ge2d, GE2D_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_vapb_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1748,52 +888,9 @@ static const struct clk_parent_data c3_vapb_parents[]= =3D { { .fw_name =3D "oscin" }, }; =20 -static struct clk_regmap c3_vapb_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VAPB_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vapb_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vapb_parents, - .num_parents =3D ARRAY_SIZE(c3_vapb_parents), - }, -}; - -static struct clk_regmap c3_vapb_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VAPB_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vapb_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vapb_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vapb =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VAPB_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vapb", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vapb_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vapb, VAPB_CLK_CTRL, 9, 0x7, c3_vapb_parents); +static C3_COMP_DIV(vapb, VAPB_CLK_CTRL, 0, 7); +static C3_COMP_GATE(vapb, VAPB_CLK_CTRL, 8); =20 static struct clk_hw *c3_peripherals_hw_clks[] =3D { [CLKID_RTC_XTAL_CLKIN] =3D &c3_rtc_xtal_clkin.hw, --=20 2.47.2