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Wed, 02 Jul 2025 02:22:16 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:8827:d0e:25e:834a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4538a406489sm195844165e9.27.2025.07.02.02.22.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jul 2025 02:22:16 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 02 Jul 2025 11:22:09 +0200 Subject: [PATCH v2 2/8] gpio: mxc: use lock guards for the generic GPIO chip lock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250702-gpio-mmio-rework-v2-2-6b77aab684d8@linaro.org> References: <20250702-gpio-mmio-rework-v2-0-6b77aab684d8@linaro.org> In-Reply-To: <20250702-gpio-mmio-rework-v2-0-6b77aab684d8@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Simplify the code by using lock guards for the bgpio_lock. Reviewed-by: Linus Walleij Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-mxc.c | 50 ++++++++++++++++++++++-----------------------= ---- 1 file changed, 22 insertions(+), 28 deletions(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 4af5a2972d12f68909dd87d9396921c80445f87c..1c37168c8d0a657d7f93067d9ac= 95cfbd821f757 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -7,6 +7,7 @@ // Authors: Daniel Mack, Juergen Beisert. // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserv= ed. =20 +#include #include #include #include @@ -161,7 +162,6 @@ static int gpio_set_irq_type(struct irq_data *d, u32 ty= pe) { struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(d); struct mxc_gpio_port *port =3D gc->private; - unsigned long flags; u32 bit, val; u32 gpio_idx =3D d->hwirq; int edge; @@ -200,41 +200,38 @@ static int gpio_set_irq_type(struct irq_data *d, u32 = type) return -EINVAL; } =20 - raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags); + scoped_guard(raw_spinlock_irqsave, &port->gc.bgpio_lock) { + if (GPIO_EDGE_SEL >=3D 0) { + val =3D readl(port->base + GPIO_EDGE_SEL); + if (edge =3D=3D GPIO_INT_BOTH_EDGES) + writel(val | (1 << gpio_idx), + port->base + GPIO_EDGE_SEL); + else + writel(val & ~(1 << gpio_idx), + port->base + GPIO_EDGE_SEL); + } =20 - if (GPIO_EDGE_SEL >=3D 0) { - val =3D readl(port->base + GPIO_EDGE_SEL); - if (edge =3D=3D GPIO_INT_BOTH_EDGES) - writel(val | (1 << gpio_idx), - port->base + GPIO_EDGE_SEL); - else - writel(val & ~(1 << gpio_idx), - port->base + GPIO_EDGE_SEL); + if (edge !=3D GPIO_INT_BOTH_EDGES) { + reg +=3D GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper regist= er */ + bit =3D gpio_idx & 0xf; + val =3D readl(reg) & ~(0x3 << (bit << 1)); + writel(val | (edge << (bit << 1)), reg); + } + + writel(1 << gpio_idx, port->base + GPIO_ISR); + port->pad_type[gpio_idx] =3D type; } =20 - if (edge !=3D GPIO_INT_BOTH_EDGES) { - reg +=3D GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper registe= r */ - bit =3D gpio_idx & 0xf; - val =3D readl(reg) & ~(0x3 << (bit << 1)); - writel(val | (edge << (bit << 1)), reg); - } - - writel(1 << gpio_idx, port->base + GPIO_ISR); - port->pad_type[gpio_idx] =3D type; - - raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); - return port->gc.direction_input(&port->gc, gpio_idx); } =20 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) { void __iomem *reg =3D port->base; - unsigned long flags; u32 bit, val; int edge; =20 - raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags); + guard(raw_spinlock_irqsave)(&port->gc.bgpio_lock); =20 reg +=3D GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ bit =3D gpio & 0xf; @@ -250,12 +247,9 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, = u32 gpio) } else { pr_err("mxc: invalid configuration for GPIO %d: %x\n", gpio, edge); - goto unlock; + return; } writel(val | (edge << (bit << 1)), reg); - -unlock: - raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); } =20 /* handle 32 interrupts in one status register */ --=20 2.48.1