From nobody Wed Oct 8 05:39:38 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F415E27E7DA; Tue, 1 Jul 2025 16:58:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389089; cv=none; b=bXCISWv9I4LDWpGaHWOVNrrfGaQXvSadAfL7meJxrAz4V3g9rZBFqUMkmToAQiSwpSW7fsWaaA4CAwF0CEctJjWXQqMQ0iN9dxiFhkNrdo8v3AeCE1EnIDiNI7SlaIKUX3LCNrFfbEuHE6VCD93gRTgOXYIyb5pBfS0GTvwssjQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389089; c=relaxed/simple; bh=8pDXLMIdjg7l7iGhqLIn7yMNQfVsnJSkhXUt6bPrRgU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BNUCJJGJIWHg/r+xAJRbZTqdiI+ljiqM2QyvcIumnypow4ROUFKZaEZqU0wBnD8qYc20strBGHr4nnGMSo+JuRlE7MS4utmv5HT5AKUgbKhXL/SaO8DttsMGSSthsHiEVfT3Os215kBfKL5ZxdC476bBGntfqoHe1AaCG76oY3U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KKksomHT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KKksomHT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 566BFC4AF09; Tue, 1 Jul 2025 16:58:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751389088; bh=8pDXLMIdjg7l7iGhqLIn7yMNQfVsnJSkhXUt6bPrRgU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KKksomHTMgLqBBFiBPxvB+hjcKob5ZBWNC+cf16cQnyeN3zn7FNwg3T1Se4O+HUbb XAKnJ4ZG56d4vJHn7SY8I5qNigfV+X/m2QHqEq8ynCnTzZKRv0DtEaePp4CaOJypQp HNiQTRNGM8falFXgu8tEfwPu55FsNlptolffnikgexSorzEWkX6aCUDZrS2Haxr08Z RF3WJ4cVoxjOCqY6Qs7CeNNdplPKBf9QuFNwibYOPVEamFGS92IFIaQxYJqZDhsd16 WXN8NekLqQ1lNX4GVTfGN4fM2FGflCkHtx/b8NmQPtvX5yt322IN9Y3JA1ZeRgZYGL N04+sQXcqxt5g== Received: by wens.tw (Postfix, from userid 1000) id B3A745F71D; Wed, 2 Jul 2025 00:58:05 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH RFT net-next 01/10] dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible Date: Wed, 2 Jul 2025 00:57:47 +0800 Message-Id: <20250701165756.258356-2-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250701165756.258356-1-wens@kernel.org> References: <20250701165756.258356-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a compatible string entry for it, and work in the requirements for a second clock and a power domain. Signed-off-by: Chen-Yu Tsai Reviewed-by: Rob Herring (Arm) --- .../net/allwinner,sun8i-a83t-emac.yaml | 68 ++++++++++++++++++- 1 file changed, 66 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-ema= c.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.ya= ml index 2ac709a4c472..1058e5af92ba 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -26,6 +26,9 @@ properties: - allwinner,sun50i-h616-emac0 - allwinner,sun55i-a523-gmac0 - const: allwinner,sun50i-a64-emac + - items: + - const: allwinner,sun55i-a523-gmac200 + - const: snps,dwmac-4.20a =20 reg: maxItems: 1 @@ -37,14 +40,19 @@ properties: const: macirq =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 clock-names: - const: stmmaceth + minItems: 1 + maxItems: 2 =20 phy-supply: description: PHY regulator =20 + power-domains: + maxItems: 1 + syscon: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -75,6 +83,7 @@ allOf: - allwinner,sun8i-h3-emac - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac + - allwinner,sun55i-a523-gmac200 =20 then: properties: @@ -191,6 +200,31 @@ allOf: - mdio-parent-bus - mdio@1 =20 + - if: + properties: + compatible: + contains: + const: allwinner,sun55i-a523-gmac200 + then: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: stmmaceth + - const: mbus + required: + - power-domains + else: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: stmmaceth + power-domains: false + + unevaluatedProperties: false =20 examples: @@ -323,4 +357,34 @@ examples: }; }; =20 + - | + ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu 117>, <&ccu 79>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu 43>; + reset-names =3D "stmmaceth"; + interrupts =3D <0 47 4>; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 4>; + syscon =3D <&syscon>; + phy-handle =3D <&ext_rgmii_phy_1>; + phy-mode =3D "rgmii-id"; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ext_rgmii_phy_1: ethernet-phy@1 { + reg =3D <1>; + }; + }; + }; ... --=20 2.39.5 From nobody Wed Oct 8 05:39:38 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6E1627D770; Tue, 1 Jul 2025 16:58:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389088; cv=none; b=I9JW7YTr1UeEY7AoelBPVscMVp3uepwyYYeexPKf/0bkVTlTQhy6pNLSEhThFvrxhnM/q6nBrzpWbjpzwnGWGm94EJkQ1l+W55Z9nZBivHNL5N33MrM3MwzmKH0Kk7o9DRZw39E4A75V/9am+RsDxE+zBqU2TQm6A2Za+RTa/8g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389088; c=relaxed/simple; bh=tkHyeHhe978iLmEL52su/S//+oFBWOSPglnafAUOcnQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UwtVOEpQ2qP5dQ3Fwjhs/st0jN6fY5q8o1L8lr0XM78NZaCYWoSQS5pSf0iMESrPdylH7MSI8x6FOkl6f1l5FR9Sc1i89t1yKA9ObPMdv1+P1o+GiJ+iI+c2Nbs7TfJOlSwaOc6AE5RKgEGQA2ABpF2Aps/FdEmd/+JRnZTIk0E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Fj2Hkuyr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Fj2Hkuyr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 51CF9C4CEF6; Tue, 1 Jul 2025 16:58:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751389088; bh=tkHyeHhe978iLmEL52su/S//+oFBWOSPglnafAUOcnQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Fj2HkuyrxSHJtC73resG2YM149zkQFFeo6bNhvu9omZ8oKQ374odeajBhcbSlT7MI E1KTKKtHsBb4tY3Rp242GzaIFnkqs9wVfjaQjWWa463q5ZLh6eYe7AwSW7vcqCFvfi L2j6YXiB1evUmb3M+XRHbFURFNFNT4RNF254kuNbLAaghUzmaobpJqsmHVfLdMDDJb X2A53ilSqCO8oSuswNLBGTnEQE3EBWVE49usPMQEyZoNR/8I2X7HjvZWVqCPkuPrWL zzfnbTQzsVKPIqwUeZdfVdmn/iAADAD6VdqD6SdCigZtljhDk/RDlPrwXlyuGOKlmv QCmTONwDxcVmA== Received: by wens.tw (Postfix, from userid 1000) id C8D775FEF5; Wed, 2 Jul 2025 00:58:05 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH RFT net-next 02/10] net: stmmac: Add support for Allwinner A523 GMAC200 Date: Wed, 2 Jul 2025 00:57:48 +0800 Message-Id: <20250701165756.258356-3-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250701165756.258356-1-wens@kernel.org> References: <20250701165756.258356-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a new driver for this hardware supporting the integration layer. Signed-off-by: Chen-Yu Tsai --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-sun55i.c | 161 ++++++++++++++++++ 3 files changed, 174 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 67fa879b1e52..38ce9a0cfb5b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -263,6 +263,18 @@ config DWMAC_SUN8I stmmac device driver. This driver is used for H3/A83T/A64 EMAC ethernet controller. =20 +config DWMAC_SUN55I + tristate "Allwinner sun55i GMAC200 support" + default ARCH_SUNXI + depends on OF && (ARCH_SUNXI || COMPILE_TEST) + select MDIO_BUS_MUX + help + Support for Allwinner A523/T527 GMAC200 ethernet controllers. + + This selects Allwinner SoC glue layer support for the + stmmac device driver. This driver is used for A523/T527 + GMAC200 ethernet controller. + config DWMAC_THEAD tristate "T-HEAD dwmac support" depends on OF && (ARCH_THEAD || COMPILE_TEST) diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index b591d93f8503..51e068e26ce4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_DWMAC_STI) +=3D dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) +=3D dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) +=3D dwmac-sunxi.o obj-$(CONFIG_DWMAC_SUN8I) +=3D dwmac-sun8i.o +obj-$(CONFIG_DWMAC_SUN55I) +=3D dwmac-sun55i.o obj-$(CONFIG_DWMAC_THEAD) +=3D dwmac-thead.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) +=3D dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) +=3D dwmac-intel-plat.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c b/drivers/n= et/ethernet/stmicro/stmmac/dwmac-sun55i.c new file mode 100644 index 000000000000..7fadb90e3098 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dwmac-sun55i.c - Allwinner sun55i GMAC200 specific glue layer + * + * Copyright (C) 2025 Chen-Yu Tsai + * + * syscon parts taken from dwmac-sun8i.c, which is + * + * Copyright (C) 2017 Corentin Labbe + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac.h" +#include "stmmac_platform.h" + +#define SYSCON_REG 0x34 + +/* RMII specific bits */ +#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ +/* Generic system control EMAC_CLK bits */ +#define SYSCON_ETXDC_MASK GENMASK(12, 10) +#define SYSCON_ERXDC_MASK GENMASK(9, 5) +/* EMAC PHY Interface Type */ +#define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ +#define SYSCON_ETCS_MASK GENMASK(1, 0) +#define SYSCON_ETCS_MII 0x0 +#define SYSCON_ETCS_EXT_GMII 0x1 +#define SYSCON_ETCS_INT_GMII 0x2 + +#define MASK_TO_VAL(mask) ((mask) >> (__builtin_ffsll(mask) - 1)) + +static int sun55i_gmac200_set_syscon(struct device *dev, + struct plat_stmmacenet_data *plat) +{ + struct device_node *node =3D dev->of_node; + struct regmap *regmap; + u32 val, reg =3D 0; + + regmap =3D syscon_regmap_lookup_by_phandle(node, "syscon"); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Unable to map syscon\n"); + + if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { + if (val % 100) { + dev_err(dev, "tx-delay must be a multiple of 100\n"); + return -EINVAL; + } + val /=3D 100; + dev_dbg(dev, "set tx-delay to %x\n", val); + if (val > MASK_TO_VAL(SYSCON_ETXDC_MASK)) + return dev_err_probe(dev, -EINVAL, + "Invalid TX clock delay: %d\n", + val); + + reg |=3D FIELD_PREP(SYSCON_ETXDC_MASK, val); + } + + if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { + if (val % 100) { + dev_err(dev, "rx-delay must be a multiple of 100\n"); + return -EINVAL; + } + val /=3D 100; + dev_dbg(dev, "set rx-delay to %x\n", val); + if (val > MASK_TO_VAL(SYSCON_ERXDC_MASK)) + return dev_err_probe(dev, -EINVAL, + "Invalid RX clock delay: %d\n", + val); + + reg |=3D FIELD_PREP(SYSCON_ERXDC_MASK, val); + } + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + /* default */ + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + reg |=3D SYSCON_EPIT | SYSCON_ETCS_INT_GMII; + break; + case PHY_INTERFACE_MODE_RMII: + reg |=3D SYSCON_RMII_EN; + break; + default: + dev_err(dev, "Unsupported interface mode: %s", + phy_modes(plat->mac_interface)); + return -EINVAL; + } + + regmap_write(regmap, SYSCON_REG, reg); + + return 0; +} + +static int sun55i_gmac200_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct device *dev =3D &pdev->dev; + struct clk *clk; + int ret; + + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + /* BSP disables it */ + plat_dat->flags |=3D STMMAC_FLAG_SPH_DISABLE; + plat_dat->host_dma_width =3D 32; + + ret =3D sun55i_gmac200_set_syscon(dev, plat_dat); + if (ret) + return ret; + + clk =3D devm_clk_get_enabled(dev, "mbus"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to get or enable MBUS clock\n"); + + ret =3D devm_regulator_get_enable_optional(dev, "phy"); + if (ret) + return dev_err_probe(dev, ret, "Failed to get or enable PHY supply\n"); + + return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); +} + +static const struct of_device_id sun55i_gmac200_match[] =3D { + { .compatible =3D "allwinner,sun55i-a523-gmac200" }, + { } +}; +MODULE_DEVICE_TABLE(of, sun55i_gmac200_match); + +static struct platform_driver sun55i_gmac200_driver =3D { + .probe =3D sun55i_gmac200_probe, + .driver =3D { + .name =3D "sun55i-gmac200", + .pm =3D &stmmac_pltfr_pm_ops, + .of_match_table =3D sun55i_gmac200_match, + }, +}; +module_platform_driver(sun55i_gmac200_driver); + +MODULE_AUTHOR("Chen-Yu Tsai "); +MODULE_DESCRIPTION("Allwinner sun55i GMAC200 specific glue layer"); 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Wed, 2 Jul 2025 00:58:05 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH RFT net-next 03/10] soc: sunxi: sram: add entry for a523 Date: Wed, 2 Jul 2025 00:57:49 +0800 Message-Id: <20250701165756.258356-4-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250701165756.258356-1-wens@kernel.org> References: <20250701165756.258356-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523 has two Ethernet controllers. So in the system controller address space, there are two registers for Ethernet clock delays, one for each controller. Add a new entry for the A523 system controller that allows access to the second register. Signed-off-by: Chen-Yu Tsai --- drivers/soc/sunxi/sunxi_sram.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index 08e264ea0697..4f8d510b7e1e 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -320,6 +320,10 @@ static const struct sunxi_sramc_variant sun50i_h616_sr= amc_variant =3D { .has_ths_offset =3D true, }; =20 +static const struct sunxi_sramc_variant sun55i_a523_sramc_variant =3D { + .num_emac_clocks =3D 2, +}; + #define SUNXI_SRAM_THS_OFFSET_REG 0x0 #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30 #define SUNXI_SYS_LDO_CTRL_REG 0x150 @@ -440,6 +444,10 @@ static const struct of_device_id sunxi_sram_dt_match[]= =3D { .compatible =3D "allwinner,sun50i-h616-system-control", .data =3D &sun50i_h616_sramc_variant, }, + { + .compatible =3D "allwinner,sun55i-a523-system-control", + .data =3D &sun55i_a523_sramc_variant, + }, { }, }; MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match); --=20 2.39.5 From nobody Wed Oct 8 05:39:38 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0042F27E7DB; Tue, 1 Jul 2025 16:58:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389089; cv=none; b=SjSSXJDnUG5w/AgbnShTVpN8Bk72rQWBemFmI8acbJ1+TJeR1SVD3Tfkf6SVQ2tuFjyPNqScnCKq8Id6zUB2gs12oN63TVNiZn7PxT2WK1DuZ2LuTmj4W5ePonTbHJ6ameyCDLJkNmuGvluoGRYuCNpNAnocdZk2RsGiDatJRDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389089; c=relaxed/simple; bh=I/bJFFYuJYTgGBIDN+smaPh81pdclQ4NTY0/0vTHG0Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nUHA8xQN/io/hx6p9jK2PRdEOi6U4UGOv7waEHqAA2QSVK4CiakWPpFpC8ZfWoTtoE7Y8SIWJBBAS6gnwXCTeYGncI0Ao3ZGxzhtmXktcZU7Me0JjCn9hb838l065Y5iOSk5jl/+3hukzgss0xaAHnE6ny9bFQ0K791Wuqew4cQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZmNrt4MU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZmNrt4MU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 53288C4CEF8; Tue, 1 Jul 2025 16:58:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751389088; bh=I/bJFFYuJYTgGBIDN+smaPh81pdclQ4NTY0/0vTHG0Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZmNrt4MUMKTDeLpB9MdnSdSE18qRibwY8Nbtz/Isya33gvsd8q4Pkzx8o2FY7QY23 SF70tJKMuR70mbxPbgxJ+OB2jTM4ieHcxzYC89iAxmEd5LYUVdoVYQ4pz1Ig512DPh GvGRXMHs154G81LOE2/Fdng7K4HVDTb+e/ZT2JBluFArZ00QQck7u5rxkcSc/1eTlz f1bC6E2NJZm7uSCtKL1Z2heRMhw6DHwT21YnOVz74U8AIdaq6I4WjYpN6AiUZdlxo7 2mhy1zKf2y3EAzRZcNbtZvjA49GA6fwiTFEwQ4WGCuUQAgzBxGDLgt1im6e/n/1QMC Xe79bZgFiuqOw== Received: by wens.tw (Postfix, from userid 1000) id E2E595FF71; Wed, 2 Jul 2025 00:58:05 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH RFT net-next 04/10] soc: sunxi: sram: register regmap as syscon Date: Wed, 2 Jul 2025 00:57:50 +0800 Message-Id: <20250701165756.258356-5-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250701165756.258356-1-wens@kernel.org> References: <20250701165756.258356-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai Until now, if the system controller had a ethernet controller glue layer control register, a limited access regmap would be registered and tied to the system controller struct device for the ethernet driver to use. Signed-off-by: Chen-Yu Tsai --- drivers/soc/sunxi/sunxi_sram.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index 4f8d510b7e1e..63c23bdffa78 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -12,6 +12,7 @@ =20 #include #include +#include #include #include #include @@ -377,6 +378,7 @@ static int __init sunxi_sram_probe(struct platform_devi= ce *pdev) const struct sunxi_sramc_variant *variant; struct device *dev =3D &pdev->dev; struct regmap *regmap; + int ret; =20 sram_dev =3D &pdev->dev; =20 @@ -394,6 +396,10 @@ static int __init sunxi_sram_probe(struct platform_dev= ice *pdev) regmap =3D devm_regmap_init_mmio(dev, base, &sunxi_sram_regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); + + ret =3D of_syscon_register_regmap(dev->of_node, regmap); + if (IS_ERR(ret)) + return ret; } =20 of_platform_populate(dev->of_node, NULL, NULL, dev); --=20 2.39.5 From nobody Wed Oct 8 05:39:38 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1CF22820A7; Tue, 1 Jul 2025 16:58:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389090; cv=none; b=UbVtiRuNN6pZZJJNsi0kO0OZ178kL7F1TRtramQ62nYpPEUBsp1RALG+KS2J52oWbIJqcdfEp/iXFblgSX6U7lhdZ6BiDzXr966v7sv8iw2XYEOu0+8Kr7w5rmV+wrRKKQpvAgj0EyZy2RyR2ZiDvbqsO1PQE9KKvGGjSxP22Ac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389090; c=relaxed/simple; bh=BQIohLNyX6fFH5M+mDocAy98v2BgzyzdocJ6lj2XgXY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YtcAGiiglfp7E3Cb8hFYC5Ike9zrBCTJMxdTnlvF2JfQmyVHz3HWzv5O3Zk4JDZ+r6DAZz4V48hPNr5Xsbb2I956zsBiT6bXR2kt0jsFgc1E14jd5tvwCM+lxtXf+ZRqUbDU5nkb4+tfIvCKDVRsjZR9tbXrN+7nIQ2C4LBmoaA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dnrhBQMj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dnrhBQMj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28309C4CEF6; Tue, 1 Jul 2025 16:58:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751389090; bh=BQIohLNyX6fFH5M+mDocAy98v2BgzyzdocJ6lj2XgXY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dnrhBQMjibtH8o+b43mbPrGzj/EnBoOCbPRS8XHKnGWFnmMogRJ7/vO5rBrcAQHLY 3aVB/5d71QOBFmHnGk6dIk6EbM/ImTxzhjeSVZlBa5SJTnGYigRQcTtYSHkutZMz/0 2eLSuolosC1YiX9+CixV0fNRVhzLaxea9LhBvo8vyyhWAXs8iaxg/6ZAGZbImAiEpH IYJ1as6z/GB7yCdtO+E4hJbopKq4zzsPg5T2imJ82fVnAtu8JfR3hSNaR0gmmbsDdv Obb01FMwBf6kIMvU7UF0UTw4dBysctgiSuKJYXkEHKA54nXcC96OYgQrP7janHhga+ KPxBMfC5YZgOQ== Received: by wens.tw (Postfix, from userid 1000) id EC24E5FFD1; Wed, 2 Jul 2025 00:58:05 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH RFT net-next 05/10] arm64: dts: allwinner: a523: Add GMAC200 ethernet controller Date: Wed, 2 Jul 2025 00:57:51 +0800 Message-Id: <20250701165756.258356-6-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250701165756.258356-1-wens@kernel.org> References: <20250701165756.258356-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523 SoC family has a second ethernet controller, called the GMAC200. It is not exposed on all the SoCs in the family. Add a device node for it. All the hardware specific settings are from the vendor BSP. Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 65779754427d..5787ad72a918 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -165,6 +165,16 @@ rgmii0_pins: rgmii0-pins { bias-disable; }; =20 + rgmii1_pins: rgmii1-pins { + pins =3D "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", + "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", + "PJ11", "PJ12", "PJ13", "PJ14", "PJ15"; + allwinner,pinmux =3D <5>; + function =3D "gmac1"; + drive-strength =3D <40>; + bias-disable; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; allwinner,pinmux =3D <2>; @@ -619,6 +629,51 @@ mdio0: mdio { }; }; =20 + gmac1: ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu RST_BUS_EMAC1>; + reset-names =3D "stmmaceth"; + interrupts =3D ; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 PD_VO1>; + syscon =3D <&syscon>; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config =3D <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config =3D <&gmac1_mtl_tx_setup>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + + queue0 {}; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <0xf>; + snps,rd_osr_lmt =3D <0xf>; + snps,blen =3D <256 128 64 32 16 8 4>; + }; + + gmac1_mtl_tx_setup: tx_queues-config { + snps,tx-queues-to-use =3D <1>; + + queue0 {}; + }; + }; + ppu: power-controller@7001400 { compatible =3D "allwinner,sun55i-a523-ppu"; reg =3D <0x07001400 0x400>; --=20 2.39.5 From nobody Wed Oct 8 05:39:38 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30B91280A47; Tue, 1 Jul 2025 16:58:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389090; cv=none; b=vCCdNc2Jw4Sn+b7iQ6EcAm7rq+fRqq8wS8EMJ/eq7/+MKVSLYFA2szC3++knIRB6SckiJXpnY3o9FnrEZ8YFmWpW8hH00uFVwRLAHKEDlGysAle47ro5BkwyEd6NUQZFlBdlz0A06TgXxvJ/5az2ZoGcLCswVSI+NCA9/DH4M8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389090; c=relaxed/simple; bh=U6fvNMCsGOs7GguX88DJTDBdJBFw0TBsVo/+de4qj2c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ib1OkOJbrqC6jzybjoIMbnwzOr4GQSOhXZbmxfLuNWlMY3GQB16QSyGT7rjA4I3SwPt28sBTuMLxQWueIHlPcui35blgF/xkzSvyqnQ7s7IkHEbjXcqTYYI1J9ihlFyvVqCu/nCRdvi2Ex5Wavvx69tJLk59ddNl+deItpEr9uY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=C3b8YLwT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="C3b8YLwT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E630BC4CEF1; Tue, 1 Jul 2025 16:58:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751389090; bh=U6fvNMCsGOs7GguX88DJTDBdJBFw0TBsVo/+de4qj2c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C3b8YLwTKxbahAbpltwNB2iIlZOrvvODQST3QVSVwG5GeDR5ICAJr84aVPmjf66pM NN78mzr+OEvHnRQeoZ04dQwASpLaepWzWXKFNxUPsLaHpcTe7OpIb/ADdNNWHXjRHi BiCZMTDL0ZCi/vYWL1nmBFbXeIThq0YjfCUJObJC8z/wTNTNAhe6OF6X9Dovs7g229 nOEY9eoE+a2zHYmr8EtgN+OsYQxmp3RrAjRyi8AwQVDje9sKdHIFrfNyur6AiSOP96 m9THrXlRArTtH+fLK0OGkEepv65ZvYVtWqI6xccDoqNoYwpjQPSVogxiLKGXi0pvVu pYfCoIAspvvTQ== Received: by wens.tw (Postfix, from userid 1000) id 057D95FFF4; Wed, 2 Jul 2025 00:58:05 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH RFT net-next 06/10] arm64: dts: allwinner: a527: cubie-a5e: Add ethernet PHY reset setting Date: Wed, 2 Jul 2025 00:57:52 +0800 Message-Id: <20250701165756.258356-7-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250701165756.258356-1-wens@kernel.org> References: <20250701165756.258356-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The external Ethernet PHY has a reset pin that is connected to the SoC. It is missing from the original submission. Add it to complete the description. Fixes: acca163f3f51 ("arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E b= oard") Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 8bc0f2c72a24..c57ecc420aed 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -70,6 +70,9 @@ &mdio0 { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; }; }; =20 --=20 2.39.5 From nobody Wed Oct 8 05:39:38 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15073283130; Tue, 1 Jul 2025 16:58:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389091; cv=none; b=hSuqQk2www7v1NWStG/5lpwVn6CcDLB5/pWCw7g/+lSlZezVCQDy99ZofYSddE+TPazirjL8moV7k0tGprcXwnMfq2QIA8RRww3QcgoRWTpEIbRPo3LYJ1C+KMku6J3JSzNHh7iFW2SCK8c027JLzo/WVLyusahYMBJOrOUbAMU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389091; c=relaxed/simple; bh=dAv9swBTXYpTgm3Qv9LPGFYo4DAoeOgGawWIkj4FOhE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cxZTslpHTklWvU0GiYn58OQ2NDSu/XZqiHz2je9qgs/EbwHiVTVp1Xj3ibJODUKydei8QeIj+KHul86CcEzPBXg6yvkJw5O4BUKbuaRajHRD5CXPxCllGCLkEFUNT9/ClY1d+vYV1dTT9q00c9edEPZJcNt3epG70gbzBsZL4CY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rZbqGJ1m; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rZbqGJ1m" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A56D4C4AF09; Tue, 1 Jul 2025 16:58:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751389090; bh=dAv9swBTXYpTgm3Qv9LPGFYo4DAoeOgGawWIkj4FOhE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rZbqGJ1mEesj+ZV6HEbQsK0OPAOaoCE53MwQR0juTCpT3NyAnFKm7mlThMpt2g9tN Eh+PE7/z8C5gUHmpMMO5B+O3sDjus0WqmXHwOu+pie5gaFSl0wZ3A+W5H/Jp+fkCzE R9kc/A0eD2nzxgaIYjrwzxLxd0G/Q1N1mhvKbCG8KDc04rLtMQxtbIYBZ+ZUafnRyb XyzQ/FAVMFXn+GbBWwDB0G1C7yzbdaAlXEentmiAsyLUX2LlfHscO7XWB6PcAuFfYr jpULkLxHLUVv+XozwqNoP4+tmkTF7JsIxTy8y/XctzbO2FOHycZnwYBGIao6+/Z4ta hkTO4/mIWk4gw== Received: by wens.tw (Postfix, from userid 1000) id 0C7125FFF8; Wed, 2 Jul 2025 00:58:06 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH RFT net-next 07/10] arm64: dts: allwinner: a527: cubie-a5e: Enable second Ethernet port Date: Wed, 2 Jul 2025 00:57:53 +0800 Message-Id: <20250701165756.258356-8-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250701165756.258356-1-wens@kernel.org> References: <20250701165756.258356-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Radxa Cubie A5E board, the second Ethernet controller, aka the GMAC200, is connected to a second external Maxio MAE0621A PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index c57ecc420aed..4b510a460123 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -13,6 +13,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -57,7 +58,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_cldo3>; =20 allwinner,tx-delay-ps =3D <300>; @@ -66,8 +67,19 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_cldo4>; + + allwinner,tx-delay-ps =3D <300>; + allwinner,rx-delay-ps =3D <400>; + + status =3D "okay"; +}; + &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -76,6 +88,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.39.5 From nobody Wed Oct 8 05:39:38 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14FE528312F; Tue, 1 Jul 2025 16:58:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389091; cv=none; b=qViCnpJwmEYxO3iYBiRCOgDMnSkMZytoEq6DZGUFjL5rQrBZHqlS30t9xVGmksuo1EplnjnmlIiPf4hP0//1k+U2OP/3YtCFvkyuG5YGGOrjZKAWn3//3ZkpUrAHFNx3+k0rz7A71viyl9FTGz01Ft7IK9PQdlOoHyN93ufS1Vo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389091; c=relaxed/simple; bh=nAHJWVBqBIFgDdvlPNmXu9yu+XCBTnN7iRiEX4QfvyM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=G14SkEs2ZBkhD8mkZQD6O7dAfGmQ2V/KUmgCkFW9tXUnvUCNr1rF1vYkkbcHPnyxrTLdBDooFQ36ElO5Oo9y3KV3RRd5vv39oATm/17yPpRDGv8EcqFNmmhdp1/6Iey4MOPAgNdpJrQgzERQsvKYwIK5tASyjvM1QSdJvTdcNY4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hOHIx/Z9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hOHIx/Z9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7EABBC4CEF1; Tue, 1 Jul 2025 16:58:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751389090; bh=nAHJWVBqBIFgDdvlPNmXu9yu+XCBTnN7iRiEX4QfvyM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hOHIx/Z9SgqL7SqpGSUO7dGaLCALAHGW31NBjZxyaYZYoZ4CsOoEPiCpHlgzsPjQT HmUNHMR7pb/agQnxGX+QPaEQZ5Zm8om+tDxoPZ3Eklvro//MoKclPZOWLrk51yBCgT CSvjUkSQ/CYqC1lwazTAFqQvRcdrOXKY80i/KWM6Mga4G8UPqgtnWBhIAAsbxH4QUd GF+G4sNNQcftc6FRmjUnn7DoEcFwcnq2WJoAqb21iWTSrto0TkK2BthlrjJ2oVLdWd 7I0WreVfstImBI+etS9GY77zTv0SlEE3aYLrxOpIPk6q6Y8Kf3TPVI/HH4/xIkUgnq KmDF+C/mYpG7Q== Received: by wens.tw (Postfix, from userid 1000) id 13D555FF19; Wed, 2 Jul 2025 00:58:06 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH RFT net-next 08/10] arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset setting Date: Wed, 2 Jul 2025 00:57:54 +0800 Message-Id: <20250701165756.258356-9-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250701165756.258356-1-wens@kernel.org> References: <20250701165756.258356-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The external Ethernet PHY has a reset pin that is connected to the SoC. It is missing from the original submission. Add it to complete the description. Fixes: c6800f15998b ("arm64: dts: allwinner: t527: add EMAC0 to Avaota-A1 b= oard") Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index 142177c1f737..9a2f29201d3c 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -80,6 +80,9 @@ &mdio0 { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; }; }; =20 --=20 2.39.5 From nobody Wed Oct 8 05:39:38 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15530283138; Tue, 1 Jul 2025 16:58:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389091; cv=none; b=SSt7n253mWelBiquEWyu7jjtNEYQO2OznuhfpGd0QL6uYZL/MEe7pKGl/ZyE5A7OY5eAxqRgfe4cV4wf3PNX9QtqNNfXRthSekYx4qZo8niYPgvYOoxWgU+mTgJeMqGXmsVlrHE+ycOvWFhqg4kKRLXkK0WGWhe7PEPHS3qJW2Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389091; c=relaxed/simple; bh=2Z/sxjaBMHzyciR0Amj3yQU+atAainaF8NZKa+qbDFE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=c9BBbLKshJp50AgHjU4GC1bGgI5pAns9p3GrqaeNnk0IsELKHKpRd9ZYSgn73+N6/pveUfgSZ8B0PLB+IaX+wqZnYNGk6vZEBHvsCW1z/TA7NE9UX48MB+NavTogXdF9eiZp8RxJ3mZFkspkSlJU9x/A1Ps28OypzH0qgLcMtX4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OkPUm/PU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OkPUm/PU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A569EC4CEF2; Tue, 1 Jul 2025 16:58:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751389090; bh=2Z/sxjaBMHzyciR0Amj3yQU+atAainaF8NZKa+qbDFE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OkPUm/PU7LW9I3SOA8qW+bkFi+253rrDVigh2nSqieuGt1WWZ2DEIAbG5Fun5F0U6 J4uH7mQrqHQH6l/xxsKFo3GTn1tMecCHsYCYQ6RzFRCYJpmSnz1OowvOSbG+UZcoxG wbgdqaINBCIKgTzkAZ/SfdS2Txwe3Got4APL+maZitPIbcBYkkfp+A81OJ3GNotn9v A8iwyKoZv6lrqxBNhf1GOh/1hkO5a5dol+UGbr1DKn3TIStxfP8qLo6Z2rBJdsmf91 YQE9Lg6IDVLD5/DhYCY0gsqMSivymnB+IJL1aAg9GaIjNXPFbzW/S3Zyo+uPYeyeN1 kEfRVqxjR6jcw== Received: by wens.tw (Postfix, from userid 1000) id 1BE306013F; Wed, 2 Jul 2025 00:58:06 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH RFT net-next 09/10] arm64: dts: allwinner: t527: avaota-a1: enable second Ethernet port Date: Wed, 2 Jul 2025 00:57:55 +0800 Message-Id: <20250701165756.258356-10-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250701165756.258356-1-wens@kernel.org> References: <20250701165756.258356-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Avaota A1 board, the second Ethernet controller, aka the GMAC200, is connected to a second external RTL8211F-CG PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun55i-t527-avaota-a1.dts | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index 9a2f29201d3c..62bc9a6b0292 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -13,6 +13,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -67,7 +68,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_dcdc4>; =20 allwinner,tx-delay-ps =3D <100>; @@ -76,8 +77,19 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_dcdc4>; + + allwinner,tx-delay-ps =3D <100>; + allwinner,rx-delay-ps =3D <100>; + + status =3D "okay"; +}; + &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -86,6 +98,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.39.5 From nobody Wed Oct 8 05:39:38 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 150E2283137; Tue, 1 Jul 2025 16:58:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389091; cv=none; b=eTlxdEhsdL1Dfac4rtZws6vXDuaz+/DUC7j56te5FIQyt/Kc3xEt97r75JZB2wxhrP2ufpe0wHBT+etheF4CGezNtfJ8Uaovg5BpotnmJDWOTElHBeffvCYTXTHt9y6YGxSL86zr4EhdMu+DefiHd4HzgF/fi3MewnvUQ71+zKY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751389091; c=relaxed/simple; bh=j7Lagu/ioOP+Y5D/rwX6JgmvfumPp+N8fvcZmVNzTSw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ae/T7t9/67cjMvWGldSQGjmtSyvKmpRRnZzhh2BvImVy/0tIPdzGfy8Rc/o/te34jM5bjYP6qOfkNwlj/ttEOQTIZW9YFKXV6v+5NJeJYgjRKB6Nl2w7wPiTKG1xeWcKT3K2IhtuveMU8Sv6qnryNXeq1TialIn1gZv98OZoWjU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=C6PJlYcF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="C6PJlYcF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A57DBC4AF0C; Tue, 1 Jul 2025 16:58:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751389090; bh=j7Lagu/ioOP+Y5D/rwX6JgmvfumPp+N8fvcZmVNzTSw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C6PJlYcF2qBb+/ZYvfG329LCeiaiH6rmhvyQV7WOEJ+4NYO1ZxnXnaxSSO8r59TOL 0O0vvYjFEhWkIqVFDNGaFCTbeZKekyvNZfsPCkvLzElCwLHCcfUmzAHDJQRmB8XrB4 XeIkPgL7KB/a4HCdY3z82n4YovYPK5AXlq1CcmuY0XO76Akvf9y4J2AH7C747ZieNM JUk2Xc7tGGdDQA9SM7KqORMiozFcoQDoPZKi5QT3SlxXGbNwGj/UW0QIBZqiLt329v OiGiPNIZnkBBJAL5XlnYQljC4PKTznTmz+H0XSSojW/DrJsLU7hFq+I4OM1xKof9Sa Xa1EX00DjtuKA== Received: by wens.tw (Postfix, from userid 1000) id 27BC260157; Wed, 2 Jul 2025 00:58:06 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH RFT net-next 10/10] arm64: dts: allwinner: t527: orangepi-4a: Enable Ethernet port Date: Wed, 2 Jul 2025 00:57:56 +0800 Message-Id: <20250701165756.258356-11-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250701165756.258356-1-wens@kernel.org> References: <20250701165756.258356-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Orangepi 4A board, the second Ethernet controller, aka the GMAC200, is connected to an external Motorcomm YT8531 PHY. The PHY uses an external 25MHz crystal, has the SoC's PI15 pin connected to its reset pin, and the PI16 pin for its interrupt pin. Enable it. Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index 5f97505ec8f9..83bc359029ba 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -15,6 +15,7 @@ / { compatible =3D "xunlong,orangepi-4a", "allwinner,sun55i-t527"; =20 aliases { + ethernet0 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -95,6 +96,28 @@ &ehci1 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii_phy>; + phy-supply =3D <®_cldo4>; + + allwinner,tx-delay-ps =3D <0>; + allwinner,rx-delay-ps =3D <300>; + + status =3D "okay"; +}; + +&mdio1 { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + interrupts-extended =3D <&pio 8 16 IRQ_TYPE_LEVEL_LOW>; /* PI16 */ + reset-gpios =3D <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.39.5