From nobody Wed Oct 8 05:39:37 2025 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62FC726C39C for ; Tue, 1 Jul 2025 09:11:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361112; cv=none; b=tdxJ55BOPZsnWdIBhE5XpKvh1ancbMN+e4Ztq2X4UPIRGjUTr9qFkH7i9mWzyLMUqE0jWpuWy8s3rKJtIFo6wFX8R+powvEabmZ/5SX73OjyP8rDbRDQe28s0RYcoOSsYJQ4MjprmbCtwA34Tb2pUKgHdu0DZ5/veVBma9I38Jg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361112; c=relaxed/simple; bh=1i0ryR5cBWV6GtdEGU8s3EojruIksTv9gJs15V/sUpU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ozaCOfhMyV7sQ+pber3XepL5yE8DKfRJq99ufbahi0VnUyDIJIt9HD+hOSBZcwC+3o8Lx7rLYSUuKAsN9gi/BmrGlSvgen4lgz7MkEejYtWMkd4WeZhEGXWit16TZZPwp0qcZ+nGNzSUoGug5Z6vWXz9luM3LYAS4G4widyw5VE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=SM2FqGem; arc=none smtp.client-ip=209.85.210.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="SM2FqGem" Received: by mail-pf1-f181.google.com with SMTP id d2e1a72fcca58-748feca4a61so1717685b3a.3 for ; Tue, 01 Jul 2025 02:11:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1751361110; x=1751965910; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s7ZtbDhifmulp6X+CGsmi42q8oGid7NOjLwBd1zaIRg=; b=SM2FqGemMkfIVO+UDTjx2N0aDWsd896H0/mWq5qKSCsB6F6btDV7CDIY+Mof/sBdF1 YdVhqX+x+Q6kfOj5tPvqdXL4xvdkDKE5wtBIvOgMJ3+f0zDbdhpKe5EE2fUofGiC2Ljd lUX2kqq6TEOqMbKrEBIEh5pADAZjDMPy8m7j4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751361110; x=1751965910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s7ZtbDhifmulp6X+CGsmi42q8oGid7NOjLwBd1zaIRg=; b=T4WSMIF8ntG5lUNMEHnzkWF1ZnLHCcuyqp0bZm0K39jrfBVFZyU+SNby3DNkzGucXb cs3jOUI/hDAbEOaMej0YJmuWyBASmH6o9fgIYmq9Du8ssDaRkF5t7BhaCUW/1xVPUysV 5X8tpkYqviM87lhLd1HHnpK62UiganC2RbbVx7Dw3J7T0RkBnvduEu4EeF78EkwY9TG7 /VLzjmGk6YfY3DQVbhFAKN8CZLUGSv9RdlhhoC/SQm8iZvssaCTkRIyMqU/uG1a2Yf9m lO1wrouLJepSFeHN0vbf1kEU7jcy1QbpAAbGf8we1HDK5sxnBUv7dtymjEC8dBGoFnTt Q+QQ== X-Forwarded-Encrypted: i=1; AJvYcCXQNPi92Nuk3i6L3HHuE3IVmvVBcc2cRs+CS/rhgv8a7z9L5/mztgddDGlZWBN1jpGgBGY1NTSKZr1G4T4=@vger.kernel.org X-Gm-Message-State: AOJu0Yy9mPzbS/7rFdLmW+mEp6WPFsbMsWSiq962Z9SbLbjSiTZElF0K qJPspMBdK0EKNcnETW/TtKgl8zuS9MLt4Kcx622o3POi6wnj2eEMg1u2zknl5okTGQ== X-Gm-Gg: ASbGncu9YSlaj3dWf8R5XmpnfMwOuoWapt/cT5Abz+oc3j8RIuMAQmbiTsjTarnCxKo n+zZikFDfJhV5uq+mGLpeDSJtI2+fzdegjJ50t3kbx5kkO+qfUEGQwL9E8svxsP7RdsT2r6BhBP xSM9E9nEju42UXQ8ftZ5Egl/lbN/dDQPgZtqBEbwFWVsjLZF0z2JrYifB2oULmosZ5O4BzLe/7E clQEPpNM3QZ70Sy/hkmwyx8RVHghZ13SlrNGuXqBwAAE7z4bgXc+XDiHrCipevhU+h80jnzNpTe /idcj+kpWw0G5l14e2LAhaenraxx5NsDlEPmUzO9M8IA1xSbR36XzNvRkW4BFNRAeIWBBPl2hvf 48EJgI5HArNopDFzvfQPvVdOeiE7c X-Google-Smtp-Source: AGHT+IFgJDHAkl2TOYiic4+miA72HcRH5YO5MM7i/Qv0249LYR+6NMvnvGl+aUIzCISEeLulTfE1PQ== X-Received: by 2002:a05:6a20:3d8d:b0:220:1ca5:957c with SMTP id adf61e73a8af0-220a16c4113mr31231334637.31.1751361110519; Tue, 01 Jul 2025 02:11:50 -0700 (PDT) Received: from localhost.localdomain ([192.19.203.250]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b34e30201c1sm8893603a12.22.2025.07.01.02.11.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 02:11:50 -0700 (PDT) From: Vikas Gupta To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, andrew+netdev@lunn.ch, horms@kernel.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, michael.chan@broadcom.com, pavan.chebbi@broadcom.com, vsrama-krishna.nemani@broadcom.com, Vikas Gupta , Bhargava Chenna Marreddy , Rajashekar Hudumula Subject: [net-next, v3 01/10] bng_en: Add PCI interface Date: Tue, 1 Jul 2025 14:34:59 +0000 Message-ID: <20250701143511.280702-2-vikas.gupta@broadcom.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250701143511.280702-1-vikas.gupta@broadcom.com> References: <20250701143511.280702-1-vikas.gupta@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add basic pci interface to the driver which supports the BCM5770X NIC family. Signed-off-by: Vikas Gupta Reviewed-by: Bhargava Chenna Marreddy Reviewed-by: Rajashekar Hudumula --- MAINTAINERS | 6 + drivers/net/ethernet/broadcom/Kconfig | 8 + drivers/net/ethernet/broadcom/Makefile | 1 + drivers/net/ethernet/broadcom/bnge/Makefile | 5 + drivers/net/ethernet/broadcom/bnge/bnge.h | 16 ++ .../net/ethernet/broadcom/bnge/bnge_core.c | 141 ++++++++++++++++++ 6 files changed, 177 insertions(+) create mode 100644 drivers/net/ethernet/broadcom/bnge/Makefile create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge.h create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_core.c diff --git a/MAINTAINERS b/MAINTAINERS index bb9df569a3ff..4a9b9d14e0df 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4853,6 +4853,12 @@ F: drivers/firmware/broadcom/tee_bnxt_fw.c F: drivers/net/ethernet/broadcom/bnxt/ F: include/linux/firmware/broadcom/tee_bnxt_fw.h =20 +BROADCOM BNG_EN 800 GIGABIT ETHERNET DRIVER +M: Vikas Gupta +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/ethernet/broadcom/bnge/ + BROADCOM BRCM80211 IEEE802.11 WIRELESS DRIVERS M: Arend van Spriel L: linux-wireless@vger.kernel.org diff --git a/drivers/net/ethernet/broadcom/Kconfig b/drivers/net/ethernet/b= roadcom/Kconfig index 81a74e07464f..e2c1ac91708e 100644 --- a/drivers/net/ethernet/broadcom/Kconfig +++ b/drivers/net/ethernet/broadcom/Kconfig @@ -253,6 +253,14 @@ config BNXT_HWMON Say Y if you want to expose the thermal sensor data on NetXtreme-C/E devices, via the hwmon sysfs interface. =20 +config BNGE + tristate "Broadcom Ethernet device support" + depends on PCI + help + This driver supports Broadcom 50/100/200/400/800 gigabit Ethernet cards. + The module will be called bng_en. To compile this driver as a module, + choose M here. + config BCMASP tristate "Broadcom ASP 2.0 Ethernet support" depends on ARCH_BRCMSTB || COMPILE_TEST diff --git a/drivers/net/ethernet/broadcom/Makefile b/drivers/net/ethernet/= broadcom/Makefile index bac5cb6ad0cd..10cc1c92ecfc 100644 --- a/drivers/net/ethernet/broadcom/Makefile +++ b/drivers/net/ethernet/broadcom/Makefile @@ -18,3 +18,4 @@ obj-$(CONFIG_BGMAC_PLATFORM) +=3D bgmac-platform.o obj-$(CONFIG_SYSTEMPORT) +=3D bcmsysport.o obj-$(CONFIG_BNXT) +=3D bnxt/ obj-$(CONFIG_BCMASP) +=3D asp2/ +obj-$(CONFIG_BNGE) +=3D bnge/ diff --git a/drivers/net/ethernet/broadcom/bnge/Makefile b/drivers/net/ethe= rnet/broadcom/bnge/Makefile new file mode 100644 index 000000000000..0c3d632805d1 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_BNGE) +=3D bng_en.o + +bng_en-y :=3D bnge_core.o diff --git a/drivers/net/ethernet/broadcom/bnge/bnge.h b/drivers/net/ethern= et/broadcom/bnge/bnge.h new file mode 100644 index 000000000000..b49c51b44473 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2025 Broadcom */ + +#ifndef _BNGE_H_ +#define _BNGE_H_ + +#define DRV_NAME "bng_en" +#define DRV_SUMMARY "Broadcom 800G Ethernet Linux Driver" + +extern char bnge_driver_name[]; + +enum board_idx { + BCM57708, +}; + +#endif /* _BNGE_H_ */ diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_core.c b/drivers/net/e= thernet/broadcom/bnge/bnge_core.c new file mode 100644 index 000000000000..514602555cd1 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_core.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2025 Broadcom. + +#include +#include +#include +#include + +#include "bnge.h" + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION(DRV_SUMMARY); + +char bnge_driver_name[] =3D DRV_NAME; + +static const struct { + char *name; +} board_info[] =3D { + [BCM57708] =3D { "Broadcom BCM57708 50Gb/100Gb/200Gb/400Gb/800Gb Ethernet= " }, +}; + +static const struct pci_device_id bnge_pci_tbl[] =3D { + { PCI_VDEVICE(BROADCOM, 0x1780), .driver_data =3D BCM57708 }, + /* Required last entry */ + {0, } +}; +MODULE_DEVICE_TABLE(pci, bnge_pci_tbl); + +static void bnge_print_device_info(struct pci_dev *pdev, enum board_idx id= x) +{ + struct device *dev =3D &pdev->dev; + + dev_info(dev, "%s found at mem %lx\n", board_info[idx].name, + (long)pci_resource_start(pdev, 0)); + + pcie_print_link_status(pdev); +} + +static void bnge_pci_disable(struct pci_dev *pdev) +{ + pci_release_regions(pdev); + if (pci_is_enabled(pdev)) + pci_disable_device(pdev); +} + +static int bnge_pci_enable(struct pci_dev *pdev) +{ + int rc; + + rc =3D pci_enable_device(pdev); + if (rc) { + dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); + return rc; + } + + if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { + dev_err(&pdev->dev, + "Cannot find PCI device base address, aborting\n"); + rc =3D -ENODEV; + goto err_pci_disable; + } + + rc =3D pci_request_regions(pdev, bnge_driver_name); + if (rc) { + dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); + goto err_pci_disable; + } + + dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + + pci_set_master(pdev); + + return 0; + +err_pci_disable: + pci_disable_device(pdev); + return rc; +} + +static int bnge_probe_one(struct pci_dev *pdev, const struct pci_device_id= *ent) +{ + int rc; + + if (pci_is_bridge(pdev)) + return -ENODEV; + + if (!pdev->msix_cap) { + dev_err(&pdev->dev, "MSIX capability missing, aborting\n"); + return -ENODEV; + } + + if (is_kdump_kernel()) { + pci_clear_master(pdev); + pcie_flr(pdev); + } + + rc =3D bnge_pci_enable(pdev); + if (rc) + return rc; + + bnge_print_device_info(pdev, ent->driver_data); + + pci_save_state(pdev); + + return 0; +} + +static void bnge_remove_one(struct pci_dev *pdev) +{ + bnge_pci_disable(pdev); +} + +static void bnge_shutdown(struct pci_dev *pdev) +{ + pci_disable_device(pdev); + + if (system_state =3D=3D SYSTEM_POWER_OFF) { + pci_wake_from_d3(pdev, 0); + pci_set_power_state(pdev, PCI_D3hot); + } +} + +static struct pci_driver bnge_driver =3D { + .name =3D bnge_driver_name, + .id_table =3D bnge_pci_tbl, + .probe =3D bnge_probe_one, + .remove =3D bnge_remove_one, + .shutdown =3D bnge_shutdown, +}; + +static int __init bnge_init_module(void) +{ + return pci_register_driver(&bnge_driver); +} +module_init(bnge_init_module); + +static void __exit bnge_exit_module(void) +{ + pci_unregister_driver(&bnge_driver); +} +module_exit(bnge_exit_module); --=20 2.47.1 From nobody Wed Oct 8 05:39:37 2025 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F48D26E154 for ; Tue, 1 Jul 2025 09:11:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361117; cv=none; b=Oa+iUDr8gNi4EaQHwqsVa2I367F8zddFLPD5nWfB+E/+VzCl290UNtVzL4GqDWM+aSAXUcw2DW+y8KyfvNhPWIB92QpulAHdcSQ5X3T6qba1tM6BZm4euiHJ0SoP2kU0DB7l01cCf0c1bWyAlyvcN4QI1i+41Lp9ztPGbTTlwjE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361117; c=relaxed/simple; bh=W6cP78wIGMhoYyHYkrHnhShjuVMTLSpYdc7+nQOTa4w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GbSw8p0p2uiRCeslL401TrMhPfEin1XOFACvbJtJ6rjjhejHrNfhmErOYHWLp2GA97r6CIw0jl3DCiazAoiFI7j/IcpI4AidXcVAp3H38uEv8EQqxsP73dp15uMMe9yvKE7X+lCCQIKjxVs1UD6xImVDUJkgTiAtG/L8WmRHu/I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=ASTr3KMN; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="ASTr3KMN" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-2350fc2591dso50300075ad.1 for ; Tue, 01 Jul 2025 02:11:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1751361115; x=1751965915; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g1gBQftS2Fk6V7LZfv5a/Ar3bdUI/g78/+w8i6zo9Uo=; b=ASTr3KMN6ksHo/oij9hn+PUtLiTR9C7nK7ewEWCIbhTs0p15jV3Askeimt7cdhW0SI HeZRu/bscNcy/1Jj31l4Ya9IQNy94Ub+HxV0y+oV/Fj0ZGE9uqTTIjzfoQidZmktRCxU Mq5aXBtxWKdMRHwyoSHUW2lHOboZokPEjwoD0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751361115; x=1751965915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g1gBQftS2Fk6V7LZfv5a/Ar3bdUI/g78/+w8i6zo9Uo=; b=U9BEuMFVYzm0/gUjIkhpcgK1NcoBfrLJ4rLGa7XpTmzA5Ub6SKm3cRkPWWvVBNplqU 9b4vtHxhpS194Aw059kiJZhMmc6eEnqmK59e/xokgHFJCuNNEqWG8bZbVUrOc3LntQ7L LyuWmSfurncjTjH1FLCNxxL+ydbu2LWLYJ93S9sBGmZ8BV0e+YGnNiClZ/7PIdUTKwgP n02W0GBLYMbYMMVTil/1q0CP6vhsYRMntIFNxQbf1RKBgqKzxpuMEzk2dYqF0FZItBzO 10m6xYQmyKzovosCRvSE1BC9Rdv2+Io3uKRW9YH70dDlnKWDdlIjCUMJekpcqTqPjoUv /UPg== X-Forwarded-Encrypted: i=1; AJvYcCXN0NmjYS/bI3da4N6hxP2SYRo58eJ16uArmzQ/bNQMhJ6r4KljJXMKQ9jPVptGV9xbEX9rimra484A0lU=@vger.kernel.org X-Gm-Message-State: AOJu0YwDRzkkqD0Z0wDQ+/7xjHfCMkkK5qoagr2V1WrMUAEw0eeNJYzO TL6ojf36U20ClT+U9TRKPx/CplspRKZUqT2HwDVkkMeqQj+nSCP47xKuE9y2NQDwsw== X-Gm-Gg: ASbGncvxu4D9U6QNXAlh3hhTiQAbLOtxUBf7APUaafpt532NMkm79crLRPI3yYl6pHU jYBSWM4z2n8fIr3v3ulzXCKuxCGsJ+8BIjoooINpvZgs6O4YueDJhDVpxrvWAfYfFJIxp+rTqDV R1iAYPwzA+su9N1w5wJaKbao//rMxJvfyatQrzym8MlTC3KdBY+YrYDqQdDmSR/vzPF/I79h3mW Mr/gKLSPg7q1P83ONKW6uPxISfVrS3gGIiFiIPObAaE56fCPy3rPsgqcm9bmUkxUtXiEtxvGzY1 39beZV+TgsVm618HOWdTIBHWwmZfGCCaEzHqZU4Dxy1LVgNt6N8TBij1jFsdDIiCwA61ta1cxEt ZFQzVds0B9qtMrLjVjSiUIYu1I7Ks X-Google-Smtp-Source: AGHT+IEsR0fX4mu6qIR0dec/ZWIENXXucQzEdKkuwM/+snwoIUasS41gYQP+hlmbxTeAUtwsnl0Urw== X-Received: by 2002:a17:903:f8c:b0:221:1497:7b08 with SMTP id d9443c01a7336-23b355985d6mr50306475ad.23.1751361114685; Tue, 01 Jul 2025 02:11:54 -0700 (PDT) Received: from localhost.localdomain ([192.19.203.250]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b34e30201c1sm8893603a12.22.2025.07.01.02.11.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 02:11:54 -0700 (PDT) From: Vikas Gupta To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, andrew+netdev@lunn.ch, horms@kernel.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, michael.chan@broadcom.com, pavan.chebbi@broadcom.com, vsrama-krishna.nemani@broadcom.com, Vikas Gupta , Bhargava Chenna Marreddy , Rajashekar Hudumula Subject: [net-next, v3 02/10] bng_en: Add devlink interface Date: Tue, 1 Jul 2025 14:35:00 +0000 Message-ID: <20250701143511.280702-3-vikas.gupta@broadcom.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250701143511.280702-1-vikas.gupta@broadcom.com> References: <20250701143511.280702-1-vikas.gupta@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allocate a base device and devlink interface with minimal devlink ops. Add dsn and board related information. Map PCIe BAR (bar0), which helps to communicate with the firmware. Signed-off-by: Vikas Gupta Reviewed-by: Bhargava Chenna Marreddy Reviewed-by: Rajashekar Hudumula --- drivers/net/ethernet/broadcom/Kconfig | 1 + drivers/net/ethernet/broadcom/bnge/Makefile | 3 +- drivers/net/ethernet/broadcom/bnge/bnge.h | 11 ++ .../net/ethernet/broadcom/bnge/bnge_core.c | 39 +++++ .../net/ethernet/broadcom/bnge/bnge_devlink.c | 142 ++++++++++++++++++ .../net/ethernet/broadcom/bnge/bnge_devlink.h | 16 ++ 6 files changed, 211 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_devlink.c create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_devlink.h diff --git a/drivers/net/ethernet/broadcom/Kconfig b/drivers/net/ethernet/b= roadcom/Kconfig index e2c1ac91708e..0fc10e6c6902 100644 --- a/drivers/net/ethernet/broadcom/Kconfig +++ b/drivers/net/ethernet/broadcom/Kconfig @@ -256,6 +256,7 @@ config BNXT_HWMON config BNGE tristate "Broadcom Ethernet device support" depends on PCI + select NET_DEVLINK help This driver supports Broadcom 50/100/200/400/800 gigabit Ethernet cards. The module will be called bng_en. To compile this driver as a module, diff --git a/drivers/net/ethernet/broadcom/bnge/Makefile b/drivers/net/ethe= rnet/broadcom/bnge/Makefile index 0c3d632805d1..e021a14d2fa0 100644 --- a/drivers/net/ethernet/broadcom/bnge/Makefile +++ b/drivers/net/ethernet/broadcom/bnge/Makefile @@ -2,4 +2,5 @@ =20 obj-$(CONFIG_BNGE) +=3D bng_en.o =20 -bng_en-y :=3D bnge_core.o +bng_en-y :=3D bnge_core.o \ + bnge_devlink.o diff --git a/drivers/net/ethernet/broadcom/bnge/bnge.h b/drivers/net/ethern= et/broadcom/bnge/bnge.h index b49c51b44473..19d85aabab4e 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge.h @@ -13,4 +13,15 @@ enum board_idx { BCM57708, }; =20 +struct bnge_dev { + struct device *dev; + struct pci_dev *pdev; + u64 dsn; +#define BNGE_VPD_FLD_LEN 32 + char board_partno[BNGE_VPD_FLD_LEN]; + char board_serialno[BNGE_VPD_FLD_LEN]; + + void __iomem *bar0; +}; + #endif /* _BNGE_H_ */ diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_core.c b/drivers/net/e= thernet/broadcom/bnge/bnge_core.c index 514602555cd1..2596215f0639 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_core.c +++ b/drivers/net/ethernet/broadcom/bnge/bnge_core.c @@ -7,6 +7,7 @@ #include =20 #include "bnge.h" +#include "bnge_devlink.h" =20 MODULE_LICENSE("GPL"); MODULE_DESCRIPTION(DRV_SUMMARY); @@ -77,8 +78,19 @@ static int bnge_pci_enable(struct pci_dev *pdev) return rc; } =20 +static void bnge_unmap_bars(struct pci_dev *pdev) +{ + struct bnge_dev *bd =3D pci_get_drvdata(pdev); + + if (bd->bar0) { + pci_iounmap(pdev, bd->bar0); + bd->bar0 =3D NULL; + } +} + static int bnge_probe_one(struct pci_dev *pdev, const struct pci_device_id= *ent) { + struct bnge_dev *bd; int rc; =20 if (pci_is_bridge(pdev)) @@ -100,13 +112,40 @@ static int bnge_probe_one(struct pci_dev *pdev, const= struct pci_device_id *ent) =20 bnge_print_device_info(pdev, ent->driver_data); =20 + bd =3D bnge_devlink_alloc(pdev); + if (!bd) { + dev_err(&pdev->dev, "Devlink allocation failed\n"); + rc =3D -ENOMEM; + goto err_pci_disable; + } + + bd->bar0 =3D pci_ioremap_bar(pdev, 0); + if (!bd->bar0) { + dev_err(&pdev->dev, "Failed mapping BAR-0, aborting\n"); + rc =3D -ENOMEM; + goto err_devl_free; + } + pci_save_state(pdev); =20 return 0; + +err_devl_free: + bnge_devlink_free(bd); + +err_pci_disable: + bnge_pci_disable(pdev); + return rc; } =20 static void bnge_remove_one(struct pci_dev *pdev) { + struct bnge_dev *bd =3D pci_get_drvdata(pdev); + + bnge_unmap_bars(pdev); + + bnge_devlink_free(bd); + bnge_pci_disable(pdev); } =20 diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_devlink.c b/drivers/ne= t/ethernet/broadcom/bnge/bnge_devlink.c new file mode 100644 index 000000000000..d01cc32ce241 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_devlink.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2025 Broadcom. + +#include +#include +#include +#include + +#include "bnge.h" +#include "bnge_devlink.h" + +static int bnge_dl_info_put(struct bnge_dev *bd, struct devlink_info_req *= req, + enum bnge_dl_version_type type, const char *key, + char *buf) +{ + if (!strlen(buf)) + return 0; + + switch (type) { + case BNGE_VERSION_FIXED: + return devlink_info_version_fixed_put(req, key, buf); + case BNGE_VERSION_RUNNING: + return devlink_info_version_running_put(req, key, buf); + case BNGE_VERSION_STORED: + return devlink_info_version_stored_put(req, key, buf); + } + + return 0; +} + +static void bnge_vpd_read_info(struct bnge_dev *bd) +{ + struct pci_dev *pdev =3D bd->pdev; + unsigned int vpd_size, kw_len; + int pos, size; + u8 *vpd_data; + + vpd_data =3D pci_vpd_alloc(pdev, &vpd_size); + if (IS_ERR(vpd_data)) { + pci_warn(pdev, "Unable to read VPD\n"); + return; + } + + pos =3D pci_vpd_find_ro_info_keyword(vpd_data, vpd_size, + PCI_VPD_RO_KEYWORD_PARTNO, &kw_len); + if (pos < 0) + goto read_sn; + + size =3D min_t(int, kw_len, BNGE_VPD_FLD_LEN - 1); + memcpy(bd->board_partno, &vpd_data[pos], size); + +read_sn: + pos =3D pci_vpd_find_ro_info_keyword(vpd_data, vpd_size, + PCI_VPD_RO_KEYWORD_SERIALNO, + &kw_len); + if (pos < 0) + goto exit; + + size =3D min_t(int, kw_len, BNGE_VPD_FLD_LEN - 1); + memcpy(bd->board_serialno, &vpd_data[pos], size); + +exit: + kfree(vpd_data); +} + +static int bnge_devlink_info_get(struct devlink *devlink, + struct devlink_info_req *req, + struct netlink_ext_ack *extack) +{ + struct bnge_dev *bd =3D devlink_priv(devlink); + int rc; + + if (bd->dsn) { + char buf[32]; + u8 dsn[8]; + int rc; + + put_unaligned_le64(bd->dsn, dsn); + sprintf(buf, "%02X-%02X-%02X-%02X-%02X-%02X-%02X-%02X", + dsn[7], dsn[6], dsn[5], dsn[4], + dsn[3], dsn[2], dsn[1], dsn[0]); + rc =3D devlink_info_serial_number_put(req, buf); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, "Failed to set dsn"); + return rc; + } + } + + if (strlen(bd->board_serialno)) { + rc =3D devlink_info_board_serial_number_put(req, + bd->board_serialno); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to set board serial number"); + return rc; + } + } + + rc =3D bnge_dl_info_put(bd, req, BNGE_VERSION_FIXED, + DEVLINK_INFO_VERSION_GENERIC_BOARD_ID, + bd->board_partno); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, "Failed to set board part number"); + return rc; + } + + return rc; +} + +static const struct devlink_ops bnge_devlink_ops =3D { + .info_get =3D bnge_devlink_info_get, +}; + +void bnge_devlink_free(struct bnge_dev *bd) +{ + struct devlink *devlink =3D priv_to_devlink(bd); + + devlink_free(devlink); +} + +struct bnge_dev *bnge_devlink_alloc(struct pci_dev *pdev) +{ + struct devlink *devlink; + struct bnge_dev *bd; + + devlink =3D devlink_alloc(&bnge_devlink_ops, sizeof(*bd), &pdev->dev); + if (!devlink) + return NULL; + + bd =3D devlink_priv(devlink); + pci_set_drvdata(pdev, bd); + bd->dev =3D &pdev->dev; + bd->pdev =3D pdev; + + bd->dsn =3D pci_get_dsn(pdev); + if (!bd->dsn) + pci_warn(pdev, "Failed to get DSN\n"); + + bnge_vpd_read_info(bd); + + return bd; +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_devlink.h b/drivers/ne= t/ethernet/broadcom/bnge/bnge_devlink.h new file mode 100644 index 000000000000..497543918741 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_devlink.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2025 Broadcom */ + +#ifndef _BNGE_DEVLINK_H_ +#define _BNGE_DEVLINK_H_ + +enum bnge_dl_version_type { + BNGE_VERSION_FIXED, + BNGE_VERSION_RUNNING, + BNGE_VERSION_STORED, +}; + +void bnge_devlink_free(struct bnge_dev *bd); +struct bnge_dev *bnge_devlink_alloc(struct pci_dev *pdev); + +#endif /* _BNGE_DEVLINK_H_ */ --=20 2.47.1 From nobody Wed Oct 8 05:39:37 2025 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C8C126F476 for ; Tue, 1 Jul 2025 09:11:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361123; cv=none; b=rX4t1K88RGcJqvvlmvQ/QvqtSl6Iu4IRox+8ojgulcTktYpVdngM5qo+K/3da7SfLjR5AKMPuLqhl4A4t2DXvdMYiL3hCfe/O6MCcBkRQahvb2avmw2C3NqdvgEBuemL4Zlvah/epGYm+NE9j4cndMIjt3avBsZBUtJiz389y7s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361123; c=relaxed/simple; bh=0M+jnIzG5JBQfL4W9RbQoAmiigcbSve1OU2iJmgypPw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JqpoS+iyQDJ4Y0tMU/Y82hv59+D84wlUYkBLA69nmmq15WcvLN4kozaDjpJQoUTPN2cWUhexXE+w26x1jv7Sfs64XFxna9lq2ZxqaeMKcHonMWcXZC9MBcRXmZT8SNF6qcay8dZX1h1R51irIHWACRS4RmJtt3/vDOJypBpFU64= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=N+nY7xoP; arc=none smtp.client-ip=209.85.210.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="N+nY7xoP" Received: by mail-pf1-f178.google.com with SMTP id d2e1a72fcca58-748d982e92cso4162298b3a.1 for ; Tue, 01 Jul 2025 02:11:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1751361119; x=1751965919; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f/+UCb0NbSaC6ATXqK88dJW3nCH5LN3iVSgYvcJ05sM=; b=N+nY7xoPr4tTzYnmXu1CJqC5+GeSEq6sZRiRa+GcBysF9rW2af4A1iUH6mF9om+snd 5huNqexihCSk4WcYqB36onVFnxxhsyAGxaHiHJ17qhyZMCKxHz2pDnxb8NEUxcR/vNJF tJgF8K/qsGDB4WAAbLgPE198oC4MchgV9CROA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751361119; x=1751965919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f/+UCb0NbSaC6ATXqK88dJW3nCH5LN3iVSgYvcJ05sM=; b=mq591hZprvPxMCO0bVjmPFHs3zB/6SS1AUJn72gPgULpkuck1la4dQloPNSYIJd+U0 uFnlloS+o25APDTb9/GEu59/WdqIXbijX6TyCbEw6YXfJpbxUHAXhCHrxS1rpK5zy23a zFiVueMmRMw52u0zRPtnRJsdk/IVpQB4xkjkzXC6BO+s7ZBy7ScABhVQnVFZ90lFbeXO /9lA6udQHQUu24KgsyzJ6KU/+zTN0ffgi/UChz6PpJfofHvE4aY2qIAt+QZoaA2YBmS6 kY8C4fCaF/HsGkg4EhHY2L95gsQsR/EjGDUAhDmgiUWdCvdEs/71SVx4EnkieXBGQdUw Bs2A== X-Forwarded-Encrypted: i=1; AJvYcCU6AbGxe8gN5yPRFaRxFQvbcVgmnkRuHld+t0c6s9uisUVM0xImPCdwE2Tg/MOBsta8kZOpfTQ1wya/APU=@vger.kernel.org X-Gm-Message-State: AOJu0YzMLxj64Laq3bqS0REBWAPxl5s6MYEzYfQZ9HJkXk+vBXmXIJBM X76Crw6dxKRkZAl9XZAdNI5fHlPoFUp1wideM/yduJ6oL18AeJMCF6DpjMSIzvSxFA== X-Gm-Gg: ASbGncsmgke4AB1Ntn6kW41er/8PXfYTcXIhR/of0ZyHd82aE8HfjGnuiMnNl3ErlfG aToV+e7reYtP+JPdFLYSFNWxtShsDs71MCiPI0Sg8fIp7wDC4S4zfAsaANTjScawOnVqYg0CHEI o9EJGZfxoTidMhM/TNHZ2g/PVnSm2ecDze1vQLlxABmFoZVafNYfLErWcXHSqAYTpqxxuQpNBm1 TLBhz6pV+zyc9BBwc7+1w92GupEvsBn82OKq18u5A5u1uM5usWX/b0Cc6iKBxwEORV/a7We9GxB 2pP+WgVEf2URBuwlMx0TiA1HwrFaBE8RQMjTdyzy/Sl1xzVhoi5I9othw3mESttd4QL5+NO6l7b ozwOFn8L9RNOea1fwU2x5El9Fwz/q X-Google-Smtp-Source: AGHT+IHdDxwbW32aZszow4OyjIRJCjLCVPEcgjS8M2LGZmfDDM03cL3fAImXNgjM6YJKlyJEAHSuNw== X-Received: by 2002:a05:6a21:392:b0:21f:ed74:7068 with SMTP id adf61e73a8af0-220a169c7f9mr20432755637.23.1751361118945; Tue, 01 Jul 2025 02:11:58 -0700 (PDT) Received: from localhost.localdomain ([192.19.203.250]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b34e30201c1sm8893603a12.22.2025.07.01.02.11.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 02:11:58 -0700 (PDT) From: Vikas Gupta To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, andrew+netdev@lunn.ch, horms@kernel.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, michael.chan@broadcom.com, pavan.chebbi@broadcom.com, vsrama-krishna.nemani@broadcom.com, Vikas Gupta , Bhargava Chenna Marreddy , Rajashekar Hudumula Subject: [net-next, v3 03/10] bng_en: Add firmware communication mechanism Date: Tue, 1 Jul 2025 14:35:01 +0000 Message-ID: <20250701143511.280702-4-vikas.gupta@broadcom.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250701143511.280702-1-vikas.gupta@broadcom.com> References: <20250701143511.280702-1-vikas.gupta@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support to communicate with the firmware. Future patches will use these functions to send the messages to the firmware. Functions support allocating request/response buffers to send a particular command. Each command has certain timeout value to which the driver waits for response from the firmware. In error case, commands may be either timed out waiting on response from the firmware or may return a specific error code. Signed-off-by: Vikas Gupta Reviewed-by: Bhargava Chenna Marreddy Reviewed-by: Rajashekar Hudumula --- drivers/net/ethernet/broadcom/bnge/Makefile | 3 +- drivers/net/ethernet/broadcom/bnge/bnge.h | 13 + .../net/ethernet/broadcom/bnge/bnge_hwrm.c | 508 ++++++++++++++++++ .../net/ethernet/broadcom/bnge/bnge_hwrm.h | 111 ++++ 4 files changed, 634 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_hwrm.c create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_hwrm.h diff --git a/drivers/net/ethernet/broadcom/bnge/Makefile b/drivers/net/ethe= rnet/broadcom/bnge/Makefile index e021a14d2fa0..b296d7de56ce 100644 --- a/drivers/net/ethernet/broadcom/bnge/Makefile +++ b/drivers/net/ethernet/broadcom/bnge/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_BNGE) +=3D bng_en.o =20 bng_en-y :=3D bnge_core.o \ - bnge_devlink.o + bnge_devlink.o \ + bnge_hwrm.o diff --git a/drivers/net/ethernet/broadcom/bnge/bnge.h b/drivers/net/ethern= et/broadcom/bnge/bnge.h index 19d85aabab4e..8f2a562d9ae2 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge.h @@ -13,6 +13,8 @@ enum board_idx { BCM57708, }; =20 +#define INVALID_HW_RING_ID ((u16)-1) + struct bnge_dev { struct device *dev; struct pci_dev *pdev; @@ -22,6 +24,17 @@ struct bnge_dev { char board_serialno[BNGE_VPD_FLD_LEN]; =20 void __iomem *bar0; + + /* HWRM members */ + u16 hwrm_cmd_seq; + u16 hwrm_cmd_kong_seq; + struct dma_pool *hwrm_dma_pool; + struct hlist_head hwrm_pending_list; + u16 hwrm_max_req_len; + u16 hwrm_max_ext_req_len; + unsigned int hwrm_cmd_timeout; + unsigned int hwrm_cmd_max_timeout; + struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ }; =20 #endif /* _BNGE_H_ */ diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm.c b/drivers/net/e= thernet/broadcom/bnge/bnge_hwrm.c new file mode 100644 index 000000000000..0f971af24142 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_hwrm.c @@ -0,0 +1,508 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2025 Broadcom. + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bnge.h" +#include "bnge_hwrm.h" + +static u64 bnge_cal_sentinel(struct bnge_hwrm_ctx *ctx, u16 req_type) +{ + return (((uintptr_t)ctx) + req_type) ^ BNGE_HWRM_SENTINEL; +} + +int bnge_hwrm_req_create(struct bnge_dev *bd, void **req, u16 req_type, + u32 req_len) +{ + struct bnge_hwrm_ctx *ctx; + dma_addr_t dma_handle; + u8 *req_addr; + + if (req_len > BNGE_HWRM_CTX_OFFSET) + return -E2BIG; + + req_addr =3D dma_pool_alloc(bd->hwrm_dma_pool, GFP_KERNEL | __GFP_ZERO, + &dma_handle); + if (!req_addr) + return -ENOMEM; + + ctx =3D (struct bnge_hwrm_ctx *)(req_addr + BNGE_HWRM_CTX_OFFSET); + /* safety first, sentinel used to check for invalid requests */ + ctx->sentinel =3D bnge_cal_sentinel(ctx, req_type); + ctx->req_len =3D req_len; + ctx->req =3D (struct input *)req_addr; + ctx->resp =3D (struct output *)(req_addr + BNGE_HWRM_RESP_OFFSET); + ctx->dma_handle =3D dma_handle; + ctx->flags =3D 0; /* __GFP_ZERO, but be explicit regarding ownership */ + ctx->timeout =3D bd->hwrm_cmd_timeout ?: BNGE_DFLT_HWRM_CMD_TIMEOUT; + ctx->allocated =3D BNGE_HWRM_DMA_SIZE - BNGE_HWRM_CTX_OFFSET; + ctx->gfp =3D GFP_KERNEL; + ctx->slice_addr =3D NULL; + + /* initialize common request fields */ + ctx->req->req_type =3D cpu_to_le16(req_type); + ctx->req->resp_addr =3D cpu_to_le64(dma_handle + BNGE_HWRM_RESP_OFFSET); + ctx->req->cmpl_ring =3D cpu_to_le16(BNGE_HWRM_NO_CMPL_RING); + ctx->req->target_id =3D cpu_to_le16(BNGE_HWRM_TARGET); + *req =3D ctx->req; + + return 0; +} + +static struct bnge_hwrm_ctx *__hwrm_ctx_get(struct bnge_dev *bd, u8 *req_a= ddr) +{ + void *ctx_addr =3D req_addr + BNGE_HWRM_CTX_OFFSET; + struct input *req =3D (struct input *)req_addr; + struct bnge_hwrm_ctx *ctx =3D ctx_addr; + u64 sentinel; + + if (!req) { + dev_err(bd->dev, "null HWRM request"); + dump_stack(); + return NULL; + } + + /* HWRM API has no type safety, verify sentinel to validate address */ + sentinel =3D bnge_cal_sentinel(ctx, le16_to_cpu(req->req_type)); + if (ctx->sentinel !=3D sentinel) { + dev_err(bd->dev, "HWRM sentinel mismatch, req_type =3D %u\n", + (u32)le16_to_cpu(req->req_type)); + dump_stack(); + return NULL; + } + + return ctx; +} + +void bnge_hwrm_req_timeout(struct bnge_dev *bd, + void *req, unsigned int timeout) +{ + struct bnge_hwrm_ctx *ctx =3D __hwrm_ctx_get(bd, req); + + if (ctx) + ctx->timeout =3D timeout; +} + +void bnge_hwrm_req_alloc_flags(struct bnge_dev *bd, void *req, gfp_t gfp) +{ + struct bnge_hwrm_ctx *ctx =3D __hwrm_ctx_get(bd, req); + + if (ctx) + ctx->gfp =3D gfp; +} + +void bnge_hwrm_req_flags(struct bnge_dev *bd, void *req, + enum bnge_hwrm_ctx_flags flags) +{ + struct bnge_hwrm_ctx *ctx =3D __hwrm_ctx_get(bd, req); + + if (ctx) + ctx->flags |=3D (flags & BNGE_HWRM_API_FLAGS); +} + +void *bnge_hwrm_req_hold(struct bnge_dev *bd, void *req) +{ + struct bnge_hwrm_ctx *ctx =3D __hwrm_ctx_get(bd, req); + struct input *input =3D (struct input *)req; + + if (!ctx) + return NULL; + + if (ctx->flags & BNGE_HWRM_INTERNAL_CTX_OWNED) { + dev_err(bd->dev, "HWRM context already owned, req_type =3D %u\n", + (u32)le16_to_cpu(input->req_type)); + dump_stack(); + return NULL; + } + + ctx->flags |=3D BNGE_HWRM_INTERNAL_CTX_OWNED; + return ((u8 *)req) + BNGE_HWRM_RESP_OFFSET; +} + +static void __hwrm_ctx_invalidate(struct bnge_dev *bd, + struct bnge_hwrm_ctx *ctx) +{ + void *addr =3D ((u8 *)ctx) - BNGE_HWRM_CTX_OFFSET; + dma_addr_t dma_handle =3D ctx->dma_handle; /* save before invalidate */ + + /* unmap any auxiliary DMA slice */ + if (ctx->slice_addr) + dma_free_coherent(bd->dev, ctx->slice_size, + ctx->slice_addr, ctx->slice_handle); + + /* invalidate, ensure ownership, sentinel and dma_handle are cleared */ + memset(ctx, 0, sizeof(struct bnge_hwrm_ctx)); + + /* return the buffer to the DMA pool */ + if (dma_handle) + dma_pool_free(bd->hwrm_dma_pool, addr, dma_handle); +} + +void bnge_hwrm_req_drop(struct bnge_dev *bd, void *req) +{ + struct bnge_hwrm_ctx *ctx =3D __hwrm_ctx_get(bd, req); + + if (ctx) + __hwrm_ctx_invalidate(bd, ctx); +} + +static int bnge_map_hwrm_error(u32 hwrm_err) +{ + switch (hwrm_err) { + case HWRM_ERR_CODE_SUCCESS: + return 0; + case HWRM_ERR_CODE_RESOURCE_LOCKED: + return -EROFS; + case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED: + return -EACCES; + case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR: + return -ENOSPC; + case HWRM_ERR_CODE_INVALID_PARAMS: + case HWRM_ERR_CODE_INVALID_FLAGS: + case HWRM_ERR_CODE_INVALID_ENABLES: + case HWRM_ERR_CODE_UNSUPPORTED_TLV: + case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR: + return -EINVAL; + case HWRM_ERR_CODE_NO_BUFFER: + return -ENOMEM; + case HWRM_ERR_CODE_HOT_RESET_PROGRESS: + case HWRM_ERR_CODE_BUSY: + return -EAGAIN; + case HWRM_ERR_CODE_CMD_NOT_SUPPORTED: + return -EOPNOTSUPP; + case HWRM_ERR_CODE_PF_UNAVAILABLE: + return -ENODEV; + default: + return -EIO; + } +} + +static struct bnge_hwrm_wait_token * +bnge_hwrm_create_token(struct bnge_dev *bd, enum bnge_hwrm_chnl dst) +{ + struct bnge_hwrm_wait_token *token; + + token =3D kzalloc(sizeof(*token), GFP_KERNEL); + if (!token) + return NULL; + + mutex_lock(&bd->hwrm_cmd_lock); + + token->dst =3D dst; + token->state =3D BNGE_HWRM_PENDING; + if (dst =3D=3D BNGE_HWRM_CHNL_CHIMP) { + token->seq_id =3D bd->hwrm_cmd_seq++; + hlist_add_head_rcu(&token->node, &bd->hwrm_pending_list); + } else { + token->seq_id =3D bd->hwrm_cmd_kong_seq++; + } + + return token; +} + +static void +bnge_hwrm_destroy_token(struct bnge_dev *bd, struct bnge_hwrm_wait_token *= token) +{ + if (token->dst =3D=3D BNGE_HWRM_CHNL_CHIMP) { + hlist_del_rcu(&token->node); + kfree_rcu(token, rcu); + } else { + kfree(token); + } + mutex_unlock(&bd->hwrm_cmd_lock); +} + +static void bnge_hwrm_req_dbg(struct bnge_dev *bd, struct input *req) +{ + u32 ring =3D le16_to_cpu(req->cmpl_ring); + u32 type =3D le16_to_cpu(req->req_type); + u32 tgt =3D le16_to_cpu(req->target_id); + u32 seq =3D le16_to_cpu(req->seq_id); + char opt[32] =3D "\n"; + + if (unlikely(ring !=3D (u16)BNGE_HWRM_NO_CMPL_RING)) + snprintf(opt, 16, " ring %d\n", ring); + + if (unlikely(tgt !=3D BNGE_HWRM_TARGET)) + snprintf(opt + strlen(opt) - 1, 16, " tgt 0x%x\n", tgt); + + dev_dbg(bd->dev, "sent hwrm req_type 0x%x seq id 0x%x%s", + type, seq, opt); +} + +#define bnge_hwrm_err(bd, ctx, fmt, ...) \ + do { \ + if ((ctx)->flags & BNGE_HWRM_CTX_SILENT) \ + dev_dbg((bd)->dev, fmt, __VA_ARGS__); \ + else \ + dev_err((bd)->dev, fmt, __VA_ARGS__); \ + } while (0) + +static int __hwrm_send_ctx(struct bnge_dev *bd, struct bnge_hwrm_ctx *ctx) +{ + u32 doorbell_offset =3D BNGE_GRCPF_REG_CHIMP_COMM_TRIGGER; + enum bnge_hwrm_chnl dst =3D BNGE_HWRM_CHNL_CHIMP; + u32 bar_offset =3D BNGE_GRCPF_REG_CHIMP_COMM; + struct bnge_hwrm_wait_token *token =3D NULL; + u16 max_req_len =3D BNGE_HWRM_MAX_REQ_LEN; + unsigned int i, timeout, tmo_count; + u32 *data =3D (u32 *)ctx->req; + u32 msg_len =3D ctx->req_len; + int rc =3D -EBUSY; + u32 req_type; + u16 len =3D 0; + u8 *valid; + + if (ctx->flags & BNGE_HWRM_INTERNAL_RESP_DIRTY) + memset(ctx->resp, 0, PAGE_SIZE); + + req_type =3D le16_to_cpu(ctx->req->req_type); + + if (msg_len > BNGE_HWRM_MAX_REQ_LEN && + msg_len > bd->hwrm_max_ext_req_len) { + dev_warn(bd->dev, "oversized hwrm request, req_type 0x%x", + req_type); + rc =3D -E2BIG; + goto exit; + } + + token =3D bnge_hwrm_create_token(bd, dst); + if (!token) { + rc =3D -ENOMEM; + goto exit; + } + ctx->req->seq_id =3D cpu_to_le16(token->seq_id); + + /* Ensure any associated DMA buffers are written before doorbell */ + wmb(); + + /* Write request msg to hwrm channel */ + __iowrite32_copy(bd->bar0 + bar_offset, data, msg_len / 4); + + for (i =3D msg_len; i < max_req_len; i +=3D 4) + writel(0, bd->bar0 + bar_offset + i); + + /* Ring channel doorbell */ + writel(1, bd->bar0 + doorbell_offset); + + bnge_hwrm_req_dbg(bd, ctx->req); + + /* Limit timeout to an upper limit */ + timeout =3D min(ctx->timeout, + bd->hwrm_cmd_max_timeout ?: BNGE_HWRM_CMD_MAX_TIMEOUT); + /* convert timeout to usec */ + timeout *=3D 1000; + + i =3D 0; + /* Short timeout for the first few iterations: + * number of loops =3D number of loops for short timeout + + * number of loops for standard timeout. + */ + tmo_count =3D BNGE_HWRM_SHORT_TIMEOUT_COUNTER; + timeout =3D timeout - BNGE_HWRM_SHORT_MIN_TIMEOUT * + BNGE_HWRM_SHORT_TIMEOUT_COUNTER; + tmo_count +=3D DIV_ROUND_UP(timeout, BNGE_HWRM_MIN_TIMEOUT); + + if (le16_to_cpu(ctx->req->cmpl_ring) !=3D INVALID_HW_RING_ID) { + /* Wait until hwrm response cmpl interrupt is processed */ + while (READ_ONCE(token->state) < BNGE_HWRM_COMPLETE && + i++ < tmo_count) { + /* on first few passes, just barely sleep */ + if (i < BNGE_HWRM_SHORT_TIMEOUT_COUNTER) { + usleep_range(BNGE_HWRM_SHORT_MIN_TIMEOUT, + BNGE_HWRM_SHORT_MAX_TIMEOUT); + } else { + usleep_range(BNGE_HWRM_MIN_TIMEOUT, + BNGE_HWRM_MAX_TIMEOUT); + } + } + + if (READ_ONCE(token->state) !=3D BNGE_HWRM_COMPLETE) { + bnge_hwrm_err(bd, ctx, "No hwrm cmpl received: 0x%x\n", + req_type); + goto exit; + } + len =3D le16_to_cpu(READ_ONCE(ctx->resp->resp_len)); + valid =3D ((u8 *)ctx->resp) + len - 1; + } else { + __le16 seen_out_of_seq =3D ctx->req->seq_id; /* will never see */ + int j; + + /* Check if response len is updated */ + for (i =3D 0; i < tmo_count; i++) { + if (token && + READ_ONCE(token->state) =3D=3D BNGE_HWRM_DEFERRED) { + bnge_hwrm_destroy_token(bd, token); + token =3D NULL; + } + + len =3D le16_to_cpu(READ_ONCE(ctx->resp->resp_len)); + if (len) { + __le16 resp_seq =3D READ_ONCE(ctx->resp->seq_id); + + if (resp_seq =3D=3D ctx->req->seq_id) + break; + if (resp_seq !=3D seen_out_of_seq) { + dev_warn(bd->dev, "Discarding out of seq response: 0x%x for msg {0x%x= 0x%x}\n", + le16_to_cpu(resp_seq), req_type, le16_to_cpu(ctx->req->seq_id)); + seen_out_of_seq =3D resp_seq; + } + } + + /* on first few passes, just barely sleep */ + if (i < BNGE_HWRM_SHORT_TIMEOUT_COUNTER) { + usleep_range(BNGE_HWRM_SHORT_MIN_TIMEOUT, + BNGE_HWRM_SHORT_MAX_TIMEOUT); + } else { + usleep_range(BNGE_HWRM_MIN_TIMEOUT, + BNGE_HWRM_MAX_TIMEOUT); + } + } + + if (i >=3D tmo_count) { + bnge_hwrm_err(bd, ctx, + "Error (timeout: %u) msg {0x%x 0x%x} len:%d\n", + bnge_hwrm_timeout(i), req_type, + le16_to_cpu(ctx->req->seq_id), len); + goto exit; + } + + /* Last byte of resp contains valid bit */ + valid =3D ((u8 *)ctx->resp) + len - 1; + for (j =3D 0; j < BNGE_HWRM_FIN_WAIT_USEC; ) { + /* make sure we read from updated DMA memory */ + dma_rmb(); + if (*valid) + break; + if (j < 10) { + udelay(1); + j++; + } else { + usleep_range(20, 30); + j +=3D 20; + } + } + + if (j >=3D BNGE_HWRM_FIN_WAIT_USEC) { + bnge_hwrm_err(bd, ctx, "Error (timeout: %u) msg {0x%x 0x%x} len:%d v:%d= \n", + bnge_hwrm_timeout(i) + j, req_type, + le16_to_cpu(ctx->req->seq_id), len, *valid); + goto exit; + } + } + + /* Zero valid bit for compatibility. Valid bit in an older spec + * may become a new field in a newer spec. We must make sure that + * a new field not implemented by old spec will read zero. + */ + *valid =3D 0; + rc =3D le16_to_cpu(ctx->resp->error_code); + if (rc =3D=3D HWRM_ERR_CODE_BUSY && !(ctx->flags & BNGE_HWRM_CTX_SILENT)) + dev_warn(bd->dev, "FW returned busy, hwrm req_type 0x%x\n", + req_type); + else if (rc && rc !=3D HWRM_ERR_CODE_PF_UNAVAILABLE) + bnge_hwrm_err(bd, ctx, "hwrm req_type 0x%x seq id 0x%x error %d\n", + req_type, le16_to_cpu(ctx->req->seq_id), rc); + rc =3D bnge_map_hwrm_error(rc); + +exit: + if (token) + bnge_hwrm_destroy_token(bd, token); + if (ctx->flags & BNGE_HWRM_INTERNAL_CTX_OWNED) + ctx->flags |=3D BNGE_HWRM_INTERNAL_RESP_DIRTY; + else + __hwrm_ctx_invalidate(bd, ctx); + return rc; +} + +int bnge_hwrm_req_send(struct bnge_dev *bd, void *req) +{ + struct bnge_hwrm_ctx *ctx =3D __hwrm_ctx_get(bd, req); + + if (!ctx) + return -EINVAL; + + return __hwrm_send_ctx(bd, ctx); +} + +int bnge_hwrm_req_send_silent(struct bnge_dev *bd, void *req) +{ + bnge_hwrm_req_flags(bd, req, BNGE_HWRM_CTX_SILENT); + return bnge_hwrm_req_send(bd, req); +} + +void * +bnge_hwrm_req_dma_slice(struct bnge_dev *bd, void *req, u32 size, + dma_addr_t *dma_handle) +{ + struct bnge_hwrm_ctx *ctx =3D __hwrm_ctx_get(bd, req); + u8 *end =3D ((u8 *)req) + BNGE_HWRM_DMA_SIZE; + struct input *input =3D req; + u8 *addr, *req_addr =3D req; + u32 max_offset, offset; + + if (!ctx) + return NULL; + + max_offset =3D BNGE_HWRM_DMA_SIZE - ctx->allocated; + offset =3D max_offset - size; + offset =3D ALIGN_DOWN(offset, BNGE_HWRM_DMA_ALIGN); + addr =3D req_addr + offset; + + if (addr < req_addr + max_offset && req_addr + ctx->req_len <=3D addr) { + ctx->allocated =3D end - addr; + *dma_handle =3D ctx->dma_handle + offset; + return addr; + } + + if (ctx->slice_addr) { + dev_err(bd->dev, "HWRM refusing to reallocate DMA slice, req_type =3D %u= \n", + (u32)le16_to_cpu(input->req_type)); + dump_stack(); + return NULL; + } + + addr =3D dma_alloc_coherent(bd->dev, size, dma_handle, ctx->gfp); + if (!addr) + return NULL; + + ctx->slice_addr =3D addr; + ctx->slice_size =3D size; + ctx->slice_handle =3D *dma_handle; + + return addr; +} + +void bnge_cleanup_hwrm_resources(struct bnge_dev *bd) +{ + struct bnge_hwrm_wait_token *token; + + dma_pool_destroy(bd->hwrm_dma_pool); + bd->hwrm_dma_pool =3D NULL; + + rcu_read_lock(); + hlist_for_each_entry_rcu(token, &bd->hwrm_pending_list, node) + WRITE_ONCE(token->state, BNGE_HWRM_CANCELLED); + rcu_read_unlock(); +} + +int bnge_init_hwrm_resources(struct bnge_dev *bd) +{ + bd->hwrm_dma_pool =3D dma_pool_create("bnge_hwrm", bd->dev, + BNGE_HWRM_DMA_SIZE, + BNGE_HWRM_DMA_ALIGN, 0); + if (!bd->hwrm_dma_pool) + return -ENOMEM; + + INIT_HLIST_HEAD(&bd->hwrm_pending_list); + mutex_init(&bd->hwrm_cmd_lock); + + return 0; +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm.h b/drivers/net/e= thernet/broadcom/bnge/bnge_hwrm.h new file mode 100644 index 000000000000..c99aa8406b14 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_hwrm.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2025 Broadcom */ + +#ifndef _BNGE_HWRM_H_ +#define _BNGE_HWRM_H_ + +#include "../bnxt/bnxt_hsi.h" + +enum bnge_hwrm_ctx_flags { + BNGE_HWRM_INTERNAL_CTX_OWNED =3D BIT(0), + BNGE_HWRM_INTERNAL_RESP_DIRTY =3D BIT(1), + BNGE_HWRM_CTX_SILENT =3D BIT(2), + BNGE_HWRM_FULL_WAIT =3D BIT(3), +}; + +#define BNGE_HWRM_API_FLAGS (BNGE_HWRM_CTX_SILENT | BNGE_HWRM_FULL_WAIT) + +struct bnge_hwrm_ctx { + u64 sentinel; + dma_addr_t dma_handle; + struct output *resp; + struct input *req; + dma_addr_t slice_handle; + void *slice_addr; + u32 slice_size; + u32 req_len; + enum bnge_hwrm_ctx_flags flags; + unsigned int timeout; + u32 allocated; + gfp_t gfp; +}; + +enum bnge_hwrm_wait_state { + BNGE_HWRM_PENDING, + BNGE_HWRM_DEFERRED, + BNGE_HWRM_COMPLETE, + BNGE_HWRM_CANCELLED, +}; + +enum bnge_hwrm_chnl { BNGE_HWRM_CHNL_CHIMP, BNGE_HWRM_CHNL_KONG }; + +struct bnge_hwrm_wait_token { + struct rcu_head rcu; + struct hlist_node node; + enum bnge_hwrm_wait_state state; + enum bnge_hwrm_chnl dst; + u16 seq_id; +}; + +#define BNGE_DFLT_HWRM_CMD_TIMEOUT 500 + +#define BNGE_GRCPF_REG_CHIMP_COMM 0x0 +#define BNGE_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 + +#define BNGE_HWRM_MAX_REQ_LEN (bd->hwrm_max_req_len) +#define BNGE_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) +#define BNGE_HWRM_CMD_MAX_TIMEOUT 40000U +#define BNGE_SHORT_HWRM_CMD_TIMEOUT 20 +#define BNGE_HWRM_CMD_TIMEOUT (bd->hwrm_cmd_timeout) +#define BNGE_HWRM_RESET_TIMEOUT ((BNGE_HWRM_CMD_TIMEOUT) * 4) +#define BNGE_HWRM_TARGET 0xffff +#define BNGE_HWRM_NO_CMPL_RING -1 +#define BNGE_HWRM_REQ_MAX_SIZE 128 +#define BNGE_HWRM_DMA_SIZE (2 * PAGE_SIZE) /* space for req+resp */ +#define BNGE_HWRM_RESP_RESERVED PAGE_SIZE +#define BNGE_HWRM_RESP_OFFSET (BNGE_HWRM_DMA_SIZE - \ + BNGE_HWRM_RESP_RESERVED) +#define BNGE_HWRM_CTX_OFFSET (BNGE_HWRM_RESP_OFFSET - \ + sizeof(struct bnge_hwrm_ctx)) +#define BNGE_HWRM_DMA_ALIGN 16 +#define BNGE_HWRM_SENTINEL 0xb6e1f68a12e9a7eb /* arbitrary value */ +#define BNGE_HWRM_SHORT_MIN_TIMEOUT 3 +#define BNGE_HWRM_SHORT_MAX_TIMEOUT 10 +#define BNGE_HWRM_SHORT_TIMEOUT_COUNTER 5 + +#define BNGE_HWRM_MIN_TIMEOUT 25 +#define BNGE_HWRM_MAX_TIMEOUT 40 + +static inline unsigned int bnge_hwrm_timeout(unsigned int n) +{ + return n <=3D BNGE_HWRM_SHORT_TIMEOUT_COUNTER ? + n * BNGE_HWRM_SHORT_MIN_TIMEOUT : + BNGE_HWRM_SHORT_TIMEOUT_COUNTER * + BNGE_HWRM_SHORT_MIN_TIMEOUT + + (n - BNGE_HWRM_SHORT_TIMEOUT_COUNTER) * + BNGE_HWRM_MIN_TIMEOUT; +} + +#define BNGE_HWRM_FIN_WAIT_USEC 50000 + +void bnge_cleanup_hwrm_resources(struct bnge_dev *bd); +int bnge_init_hwrm_resources(struct bnge_dev *bd); + +int bnge_hwrm_req_create(struct bnge_dev *bd, void **req, u16 req_type, + u32 req_len); +#define bnge_hwrm_req_init(bd, req, req_type) \ + bnge_hwrm_req_create((bd), (void **)&(req), (req_type), \ + sizeof(*(req))) +void *bnge_hwrm_req_hold(struct bnge_dev *bd, void *req); +void bnge_hwrm_req_drop(struct bnge_dev *bd, void *req); +void bnge_hwrm_req_flags(struct bnge_dev *bd, void *req, + enum bnge_hwrm_ctx_flags flags); +void bnge_hwrm_req_timeout(struct bnge_dev *bd, void *req, + unsigned int timeout); +int bnge_hwrm_req_send(struct bnge_dev *bd, void *req); +int bnge_hwrm_req_send_silent(struct bnge_dev *bd, void *req); +void bnge_hwrm_req_alloc_flags(struct bnge_dev *bd, void *req, gfp_t flags= ); +void *bnge_hwrm_req_dma_slice(struct bnge_dev *bd, void *req, u32 size, + dma_addr_t *dma); + +#endif /* _BNGE_HWRM_H_ */ --=20 2.47.1 From nobody Wed Oct 8 05:39:37 2025 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20D2226FA53 for ; Tue, 1 Jul 2025 09:12:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361126; cv=none; b=tBUSsZYGUI6v4ha3y6KjdS6rfKshC0e8VG8lG7t2oSiRa2qQ1JXFsOg2yUXM5gtYoktq8SvexKlIaiAFAFIJqbp5CwpTTfPnbgSeKOXPftBtT8gdooI0GRIDX5dd4iJ15znkJakZTE4Ifsm7TMwZsaqOYQr1aEtbmzqjm+8goic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361126; c=relaxed/simple; bh=Wlez0zvhdgj2NMU7MK0vkWaBeyx9njhJ7cfIc8ZDq+Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dH5kJt6Bh+q1kr5cOVvE5XmYBbijMz3mB+CFOH83RWVsYZjXJbFaoNNXKhrf7F8EOhOylJcnYdx0s7mT3FbCrq5f/XDgtbMLmILBtjvTrhkyqGZZCGjPyNAytYv24Y4DhdW3D67ROugZYkOopPL/A5LWA7PebJDv/ZklrONdDiM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=CHL4LNSk; arc=none smtp.client-ip=209.85.210.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="CHL4LNSk" Received: by mail-pf1-f173.google.com with SMTP id d2e1a72fcca58-7494999de5cso4225012b3a.3 for ; Tue, 01 Jul 2025 02:12:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1751361123; x=1751965923; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=irBA5xf1kOPHNpG+0PZ9Bf0gcMLVOa5ZCjBsgWosHi4=; b=CHL4LNSkwahGxLJ7U9McthQU2X1q0hU+/9uSb3Gh0rQTtMdrx+gB4hyHJHJ+XXE3ih y/F6JUwdU0gtUhdG0wRgSJEd5QDvuafBx9adL/NV31JMKsBSuWHacj3UjsKYNuhES9+9 N+zupD0QLqeXbv+bnDE0YvkuB2sLUU0fJa69A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751361123; x=1751965923; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=irBA5xf1kOPHNpG+0PZ9Bf0gcMLVOa5ZCjBsgWosHi4=; b=ruLnHmcDm2HGBdqG3wxw/4LKwlRGaIMenQ2NjgB04oh58v5Mwoo9/JDIE7yaWfkeiw TmBtQZZWVpJRXnI0+spw3MBPFXOYxVcwgZeTVrEszLT2UHVhlu1JC4aNuSoXzxOgHMR9 jcn9zBAvyQwYhkiJO9A0AeK7zBIr43+hHr+c70517Y9jX3NANayr/5gGzTiDa4/bbYX2 U6wK5BVitm38O1/US5TyoX3uh10kWD0vbIqp6eUg0AlDH76uzcvBTP89q+rObkg2T8ME lE3Jix5lA6hJsHUBiaEZb61kCMJgnHJn7Elq0G1Tt5G12KhaPUpNIyR8fknpeYzC1P+5 xSFQ== X-Forwarded-Encrypted: i=1; AJvYcCX7kob1uUpTIhkKj4SGfEs7rTEbs107Qb+caiyhXm3H5ALizchoBFr5zwg0uK4+R0jCiru124ThiDGtb4E=@vger.kernel.org X-Gm-Message-State: AOJu0Yyi0Wqb2liraiD0AKenqMYPMIvWedAtx7eqPJjoftUbFjXlrf3x D2buGyo9HU3DloDZCrcMwNF1N9Jr8aO0R4/2/a6nTonoFYJiNln7DjIZ20pyJ2Na4w== X-Gm-Gg: ASbGncsopInx+LIXxPWNj58O0v0hxS0rkbesTmv0qbw9LVQvXR5ciFp33ICJLIT7Hiq 7AlFXaMs/pDhEg7Rs1xpE1A3FCnqMAeUYUkxclo6xIvGtETpzNHt9M2TVyUlsTSVdBlKAwiL5Is zjSupS4a2G40uXP5IwmcLK3PnJcv4PbWEqEShS38V+i4pEJvxRs6osGKYlObUPoFICle7+g7Ak1 HgHEncr/6HQSgCBJubfsEkuLGlMI/rDqvCvH/mInnroU9K9Hui4VnyfNnJgN+5hJ09DupVwOicD qTSzfTxKAdNlL85aABS7FMNK0NrQ+ypp5FiO6Z6ceLFW6UlDs8Nzs4YIT5RLnS55ki8Ku60g0/V YeVB0ZtSU/rEL2QP1c81TKGA/R6WH X-Google-Smtp-Source: AGHT+IHCyAQjCFHdxsOw3+jt9Hp58zbATfdUwR/r8/3aaArd3Gyl42KzwPu1AR42OmJ/wlHYOHrHJA== X-Received: by 2002:a05:6a21:5019:b0:222:d191:5bbd with SMTP id adf61e73a8af0-222d1915d3dmr482431637.39.1751361123354; Tue, 01 Jul 2025 02:12:03 -0700 (PDT) Received: from localhost.localdomain ([192.19.203.250]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b34e30201c1sm8893603a12.22.2025.07.01.02.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 02:12:02 -0700 (PDT) From: Vikas Gupta To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, andrew+netdev@lunn.ch, horms@kernel.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, michael.chan@broadcom.com, pavan.chebbi@broadcom.com, vsrama-krishna.nemani@broadcom.com, Vikas Gupta , Bhargava Chenna Marreddy , Rajashekar Hudumula Subject: [net-next, v3 04/10] bng_en: Add initial interaction with firmware Date: Tue, 1 Jul 2025 14:35:02 +0000 Message-ID: <20250701143511.280702-5-vikas.gupta@broadcom.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250701143511.280702-1-vikas.gupta@broadcom.com> References: <20250701143511.280702-1-vikas.gupta@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Query firmware with the help of basic firmware commands and cache the capabilities. With the help of basic commands start the initialization process of the driver with the firmware. Since basic information is available from the firmware, register with devlink. Signed-off-by: Vikas Gupta Reviewed-by: Bhargava Chenna Marreddy Reviewed-by: Rajashekar Hudumula --- drivers/net/ethernet/broadcom/bnge/Makefile | 3 +- drivers/net/ethernet/broadcom/bnge/bnge.h | 54 +++++ .../net/ethernet/broadcom/bnge/bnge_core.c | 71 ++++++ .../net/ethernet/broadcom/bnge/bnge_devlink.c | 164 ++++++++++++++ .../net/ethernet/broadcom/bnge/bnge_devlink.h | 2 + .../ethernet/broadcom/bnge/bnge_hwrm_lib.c | 213 ++++++++++++++++++ .../ethernet/broadcom/bnge/bnge_hwrm_lib.h | 16 ++ 7 files changed, 522 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.h diff --git a/drivers/net/ethernet/broadcom/bnge/Makefile b/drivers/net/ethe= rnet/broadcom/bnge/Makefile index b296d7de56ce..b8dbbc2d5972 100644 --- a/drivers/net/ethernet/broadcom/bnge/Makefile +++ b/drivers/net/ethernet/broadcom/bnge/Makefile @@ -4,4 +4,5 @@ obj-$(CONFIG_BNGE) +=3D bng_en.o =20 bng_en-y :=3D bnge_core.o \ bnge_devlink.o \ - bnge_hwrm.o + bnge_hwrm.o \ + bnge_hwrm_lib.o diff --git a/drivers/net/ethernet/broadcom/bnge/bnge.h b/drivers/net/ethern= et/broadcom/bnge/bnge.h index 8f2a562d9ae2..60af0517c45e 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge.h @@ -7,6 +7,13 @@ #define DRV_NAME "bng_en" #define DRV_SUMMARY "Broadcom 800G Ethernet Linux Driver" =20 +#include +#include "../bnxt/bnxt_hsi.h" + +#define DRV_VER_MAJ 1 +#define DRV_VER_MIN 15 +#define DRV_VER_UPD 1 + extern char bnge_driver_name[]; =20 enum board_idx { @@ -15,6 +22,36 @@ enum board_idx { =20 #define INVALID_HW_RING_ID ((u16)-1) =20 +enum { + BNGE_FW_CAP_SHORT_CMD =3D BIT_ULL(0), + BNGE_FW_CAP_LLDP_AGENT =3D BIT_ULL(1), + BNGE_FW_CAP_DCBX_AGENT =3D BIT_ULL(2), + BNGE_FW_CAP_IF_CHANGE =3D BIT_ULL(3), + BNGE_FW_CAP_KONG_MB_CHNL =3D BIT_ULL(4), + BNGE_FW_CAP_ERROR_RECOVERY =3D BIT_ULL(5), + BNGE_FW_CAP_PKG_VER =3D BIT_ULL(6), + BNGE_FW_CAP_CFA_ADV_FLOW =3D BIT_ULL(7), + BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 =3D BIT_ULL(8), + BNGE_FW_CAP_PCIE_STATS_SUPPORTED =3D BIT_ULL(9), + BNGE_FW_CAP_EXT_STATS_SUPPORTED =3D BIT_ULL(10), + BNGE_FW_CAP_ERR_RECOVER_RELOAD =3D BIT_ULL(11), + BNGE_FW_CAP_HOT_RESET =3D BIT_ULL(12), + BNGE_FW_CAP_RX_ALL_PKT_TS =3D BIT_ULL(13), + BNGE_FW_CAP_VLAN_RX_STRIP =3D BIT_ULL(14), + BNGE_FW_CAP_VLAN_TX_INSERT =3D BIT_ULL(15), + BNGE_FW_CAP_EXT_HW_STATS_SUPPORTED =3D BIT_ULL(16), + BNGE_FW_CAP_LIVEPATCH =3D BIT_ULL(17), + BNGE_FW_CAP_HOT_RESET_IF =3D BIT_ULL(18), + BNGE_FW_CAP_RING_MONITOR =3D BIT_ULL(19), + BNGE_FW_CAP_DBG_QCAPS =3D BIT_ULL(20), + BNGE_FW_CAP_THRESHOLD_TEMP_SUPPORTED =3D BIT_ULL(21), + BNGE_FW_CAP_DFLT_VLAN_TPID_PCP =3D BIT_ULL(22), + BNGE_FW_CAP_VNIC_TUNNEL_TPA =3D BIT_ULL(23), + BNGE_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO =3D BIT_ULL(24), + BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V3 =3D BIT_ULL(25), + BNGE_FW_CAP_VNIC_RE_FLUSH =3D BIT_ULL(26), +}; + struct bnge_dev { struct device *dev; struct pci_dev *pdev; @@ -25,6 +62,9 @@ struct bnge_dev { =20 void __iomem *bar0; =20 + u16 chip_num; + u8 chip_rev; + /* HWRM members */ u16 hwrm_cmd_seq; u16 hwrm_cmd_kong_seq; @@ -35,6 +75,20 @@ struct bnge_dev { unsigned int hwrm_cmd_timeout; unsigned int hwrm_cmd_max_timeout; struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ + + struct hwrm_ver_get_output ver_resp; +#define FW_VER_STR_LEN 32 + char fw_ver_str[FW_VER_STR_LEN]; + char hwrm_ver_supp[FW_VER_STR_LEN]; + char nvm_cfg_ver[FW_VER_STR_LEN]; + u64 fw_ver_code; +#define BNGE_FW_VER_CODE(maj, min, bld, rsv) \ + ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv)) + + unsigned long state; +#define BNGE_STATE_DRV_REGISTERED 0 + + u64 fw_cap; }; =20 #endif /* _BNGE_H_ */ diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_core.c b/drivers/net/e= thernet/broadcom/bnge/bnge_core.c index 2596215f0639..4d7b4ef1c466 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_core.c +++ b/drivers/net/ethernet/broadcom/bnge/bnge_core.c @@ -8,6 +8,8 @@ =20 #include "bnge.h" #include "bnge_devlink.h" +#include "bnge_hwrm.h" +#include "bnge_hwrm_lib.h" =20 MODULE_LICENSE("GPL"); MODULE_DESCRIPTION(DRV_SUMMARY); @@ -37,6 +39,51 @@ static void bnge_print_device_info(struct pci_dev *pdev,= enum board_idx idx) pcie_print_link_status(pdev); } =20 +static void bnge_nvm_cfg_ver_get(struct bnge_dev *bd) +{ + struct hwrm_nvm_get_dev_info_output nvm_info; + + if (!bnge_hwrm_nvm_dev_info(bd, &nvm_info)) + snprintf(bd->nvm_cfg_ver, FW_VER_STR_LEN, "%d.%d.%d", + nvm_info.nvm_cfg_ver_maj, nvm_info.nvm_cfg_ver_min, + nvm_info.nvm_cfg_ver_upd); +} + +static void bnge_fw_unregister_dev(struct bnge_dev *bd) +{ + bnge_hwrm_func_drv_unrgtr(bd); +} + +static int bnge_fw_register_dev(struct bnge_dev *bd) +{ + int rc; + + bd->fw_cap =3D 0; + rc =3D bnge_hwrm_ver_get(bd); + if (rc) { + dev_err(bd->dev, "Get Version command failed rc: %d\n", rc); + return rc; + } + + bnge_nvm_cfg_ver_get(bd); + + rc =3D bnge_hwrm_func_reset(bd); + if (rc) { + dev_err(bd->dev, "Failed to reset function rc: %d\n", rc); + return rc; + } + + bnge_hwrm_fw_set_time(bd); + + rc =3D bnge_hwrm_func_drv_rgtr(bd); + if (rc) { + dev_err(bd->dev, "Failed to rgtr with firmware rc: %d\n", rc); + return rc; + } + + return 0; +} + static void bnge_pci_disable(struct pci_dev *pdev) { pci_release_regions(pdev); @@ -126,10 +173,28 @@ static int bnge_probe_one(struct pci_dev *pdev, const= struct pci_device_id *ent) goto err_devl_free; } =20 + rc =3D bnge_init_hwrm_resources(bd); + if (rc) + goto err_bar_unmap; + + rc =3D bnge_fw_register_dev(bd); + if (rc) { + dev_err(&pdev->dev, "Failed to register with firmware rc =3D %d\n", rc); + goto err_hwrm_cleanup; + } + + bnge_devlink_register(bd); + pci_save_state(pdev); =20 return 0; =20 +err_hwrm_cleanup: + bnge_cleanup_hwrm_resources(bd); + +err_bar_unmap: + bnge_unmap_bars(pdev); + err_devl_free: bnge_devlink_free(bd); =20 @@ -142,6 +207,12 @@ static void bnge_remove_one(struct pci_dev *pdev) { struct bnge_dev *bd =3D pci_get_drvdata(pdev); =20 + bnge_devlink_unregister(bd); + + bnge_fw_unregister_dev(bd); + + bnge_cleanup_hwrm_resources(bd); + bnge_unmap_bars(pdev); =20 bnge_devlink_free(bd); diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_devlink.c b/drivers/ne= t/ethernet/broadcom/bnge/bnge_devlink.c index d01cc32ce241..a987afebd64d 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_devlink.c +++ b/drivers/net/ethernet/broadcom/bnge/bnge_devlink.c @@ -8,6 +8,7 @@ =20 #include "bnge.h" #include "bnge_devlink.h" +#include "bnge_hwrm_lib.h" =20 static int bnge_dl_info_put(struct bnge_dev *bd, struct devlink_info_req *= req, enum bnge_dl_version_type type, const char *key, @@ -16,6 +17,10 @@ static int bnge_dl_info_put(struct bnge_dev *bd, struct = devlink_info_req *req, if (!strlen(buf)) return 0; =20 + if (!strcmp(key, DEVLINK_INFO_VERSION_GENERIC_FW_NCSI) || + !strcmp(key, DEVLINK_INFO_VERSION_GENERIC_FW_ROCE)) + return 0; + switch (type) { case BNGE_VERSION_FIXED: return devlink_info_version_fixed_put(req, key, buf); @@ -63,11 +68,20 @@ static void bnge_vpd_read_info(struct bnge_dev *bd) kfree(vpd_data); } =20 +#define HWRM_FW_VER_STR_LEN 16 + static int bnge_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, struct netlink_ext_ack *extack) { + struct hwrm_nvm_get_dev_info_output nvm_dev_info; struct bnge_dev *bd =3D devlink_priv(devlink); + struct hwrm_ver_get_output *ver_resp; + char mgmt_ver[FW_VER_STR_LEN]; + char roce_ver[FW_VER_STR_LEN]; + char ncsi_ver[FW_VER_STR_LEN]; + char buf[32]; + int rc; =20 if (bd->dsn) { @@ -104,6 +118,144 @@ static int bnge_devlink_info_get(struct devlink *devl= ink, return rc; } =20 + /* More information from HWRM ver get command */ + sprintf(buf, "%X", bd->chip_num); + rc =3D bnge_dl_info_put(bd, req, BNGE_VERSION_FIXED, + DEVLINK_INFO_VERSION_GENERIC_ASIC_ID, buf); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, "Failed to set asic id"); + return rc; + } + + ver_resp =3D &bd->ver_resp; + sprintf(buf, "%c%d", 'A' + ver_resp->chip_rev, ver_resp->chip_metal); + rc =3D bnge_dl_info_put(bd, req, BNGE_VERSION_FIXED, + DEVLINK_INFO_VERSION_GENERIC_ASIC_REV, buf); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, "Failed to set asic info"); + return rc; + } + + rc =3D bnge_dl_info_put(bd, req, BNGE_VERSION_RUNNING, + DEVLINK_INFO_VERSION_GENERIC_FW_PSID, + bd->nvm_cfg_ver); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, "Failed to set firmware version"); + return rc; + } + + buf[0] =3D 0; + strncat(buf, ver_resp->active_pkg_name, HWRM_FW_VER_STR_LEN); + rc =3D bnge_dl_info_put(bd, req, BNGE_VERSION_RUNNING, + DEVLINK_INFO_VERSION_GENERIC_FW, buf); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to set firmware generic version"); + return rc; + } + + if (ver_resp->flags & VER_GET_RESP_FLAGS_EXT_VER_AVAIL) { + snprintf(mgmt_ver, FW_VER_STR_LEN, "%d.%d.%d.%d", + ver_resp->hwrm_fw_major, ver_resp->hwrm_fw_minor, + ver_resp->hwrm_fw_build, ver_resp->hwrm_fw_patch); + + snprintf(ncsi_ver, FW_VER_STR_LEN, "%d.%d.%d.%d", + ver_resp->mgmt_fw_major, ver_resp->mgmt_fw_minor, + ver_resp->mgmt_fw_build, ver_resp->mgmt_fw_patch); + + snprintf(roce_ver, FW_VER_STR_LEN, "%d.%d.%d.%d", + ver_resp->roce_fw_major, ver_resp->roce_fw_minor, + ver_resp->roce_fw_build, ver_resp->roce_fw_patch); + } else { + snprintf(mgmt_ver, FW_VER_STR_LEN, "%d.%d.%d.%d", + ver_resp->hwrm_fw_maj_8b, ver_resp->hwrm_fw_min_8b, + ver_resp->hwrm_fw_bld_8b, ver_resp->hwrm_fw_rsvd_8b); + + snprintf(ncsi_ver, FW_VER_STR_LEN, "%d.%d.%d.%d", + ver_resp->mgmt_fw_maj_8b, ver_resp->mgmt_fw_min_8b, + ver_resp->mgmt_fw_bld_8b, ver_resp->mgmt_fw_rsvd_8b); + + snprintf(roce_ver, FW_VER_STR_LEN, "%d.%d.%d.%d", + ver_resp->roce_fw_maj_8b, ver_resp->roce_fw_min_8b, + ver_resp->roce_fw_bld_8b, ver_resp->roce_fw_rsvd_8b); + } + rc =3D bnge_dl_info_put(bd, req, BNGE_VERSION_RUNNING, + DEVLINK_INFO_VERSION_GENERIC_FW_MGMT, mgmt_ver); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to set firmware mgmt version"); + return rc; + } + + rc =3D bnge_dl_info_put(bd, req, BNGE_VERSION_RUNNING, + DEVLINK_INFO_VERSION_GENERIC_FW_MGMT_API, + bd->hwrm_ver_supp); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to set firmware mgmt api version"); + return rc; + } + + rc =3D bnge_dl_info_put(bd, req, BNGE_VERSION_RUNNING, + DEVLINK_INFO_VERSION_GENERIC_FW_NCSI, ncsi_ver); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to set ncsi firmware version"); + return rc; + } + + rc =3D bnge_dl_info_put(bd, req, BNGE_VERSION_RUNNING, + DEVLINK_INFO_VERSION_GENERIC_FW_ROCE, roce_ver); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, "Failed to set roce firmware version"); + return rc; + } + + rc =3D bnge_hwrm_nvm_dev_info(bd, &nvm_dev_info); + if (!(nvm_dev_info.flags & NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID)) + return 0; + + buf[0] =3D 0; + strncat(buf, nvm_dev_info.pkg_name, HWRM_FW_VER_STR_LEN); + rc =3D bnge_dl_info_put(bd, req, BNGE_VERSION_STORED, + DEVLINK_INFO_VERSION_GENERIC_FW, buf); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to set roce firmware version"); + return rc; + } + + snprintf(mgmt_ver, FW_VER_STR_LEN, "%d.%d.%d.%d", + nvm_dev_info.hwrm_fw_major, nvm_dev_info.hwrm_fw_minor, + nvm_dev_info.hwrm_fw_build, nvm_dev_info.hwrm_fw_patch); + rc =3D bnge_dl_info_put(bd, req, BNGE_VERSION_STORED, + DEVLINK_INFO_VERSION_GENERIC_FW_MGMT, mgmt_ver); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to set stored firmware version"); + return rc; + } + + snprintf(ncsi_ver, FW_VER_STR_LEN, "%d.%d.%d.%d", + nvm_dev_info.mgmt_fw_major, nvm_dev_info.mgmt_fw_minor, + nvm_dev_info.mgmt_fw_build, nvm_dev_info.mgmt_fw_patch); + rc =3D bnge_dl_info_put(bd, req, BNGE_VERSION_STORED, + DEVLINK_INFO_VERSION_GENERIC_FW_NCSI, ncsi_ver); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to set stored ncsi firmware version"); + return rc; + } + + snprintf(roce_ver, FW_VER_STR_LEN, "%d.%d.%d.%d", + nvm_dev_info.roce_fw_major, nvm_dev_info.roce_fw_minor, + nvm_dev_info.roce_fw_build, nvm_dev_info.roce_fw_patch); + rc =3D bnge_dl_info_put(bd, req, BNGE_VERSION_STORED, + DEVLINK_INFO_VERSION_GENERIC_FW_ROCE, roce_ver); + if (rc) + NL_SET_ERR_MSG_MOD(extack, + "Failed to set stored roce firmware version"); + return rc; } =20 @@ -140,3 +292,15 @@ struct bnge_dev *bnge_devlink_alloc(struct pci_dev *pd= ev) =20 return bd; } + +void bnge_devlink_register(struct bnge_dev *bd) +{ + struct devlink *devlink =3D priv_to_devlink(bd); + devlink_register(devlink); +} + +void bnge_devlink_unregister(struct bnge_dev *bd) +{ + struct devlink *devlink =3D priv_to_devlink(bd); + devlink_unregister(devlink); +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_devlink.h b/drivers/ne= t/ethernet/broadcom/bnge/bnge_devlink.h index 497543918741..c6575255e650 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_devlink.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge_devlink.h @@ -12,5 +12,7 @@ enum bnge_dl_version_type { =20 void bnge_devlink_free(struct bnge_dev *bd); struct bnge_dev *bnge_devlink_alloc(struct pci_dev *pdev); +void bnge_devlink_register(struct bnge_dev *bd); +void bnge_devlink_unregister(struct bnge_dev *bd); =20 #endif /* _BNGE_DEVLINK_H_ */ diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c b/drivers/n= et/ethernet/broadcom/bnge/bnge_hwrm_lib.c new file mode 100644 index 000000000000..25ac73ac37ba --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2025 Broadcom. + +#include +#include +#include +#include + +#include "bnge.h" +#include "../bnxt/bnxt_hsi.h" +#include "bnge_hwrm.h" +#include "bnge_hwrm_lib.h" + +int bnge_hwrm_ver_get(struct bnge_dev *bd) +{ + u32 dev_caps_cfg, hwrm_ver, hwrm_spec_code; + u16 fw_maj, fw_min, fw_bld, fw_rsv; + struct hwrm_ver_get_output *resp; + struct hwrm_ver_get_input *req; + int rc; + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_VER_GET); + if (rc) + return rc; + + bnge_hwrm_req_flags(bd, req, BNGE_HWRM_FULL_WAIT); + bd->hwrm_max_req_len =3D HWRM_MAX_REQ_LEN; + req->hwrm_intf_maj =3D HWRM_VERSION_MAJOR; + req->hwrm_intf_min =3D HWRM_VERSION_MINOR; + req->hwrm_intf_upd =3D HWRM_VERSION_UPDATE; + + resp =3D bnge_hwrm_req_hold(bd, req); + rc =3D bnge_hwrm_req_send(bd, req); + if (rc) + goto hwrm_ver_get_exit; + + memcpy(&bd->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); + + hwrm_spec_code =3D resp->hwrm_intf_maj_8b << 16 | + resp->hwrm_intf_min_8b << 8 | + resp->hwrm_intf_upd_8b; + hwrm_ver =3D HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 | + HWRM_VERSION_UPDATE; + + if (hwrm_spec_code > hwrm_ver) + snprintf(bd->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", + HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, + HWRM_VERSION_UPDATE); + else + snprintf(bd->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", + resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, + resp->hwrm_intf_upd_8b); + + fw_maj =3D le16_to_cpu(resp->hwrm_fw_major); + fw_min =3D le16_to_cpu(resp->hwrm_fw_minor); + fw_bld =3D le16_to_cpu(resp->hwrm_fw_build); + fw_rsv =3D le16_to_cpu(resp->hwrm_fw_patch); + + bd->fw_ver_code =3D BNGE_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv); + snprintf(bd->fw_ver_str, FW_VER_STR_LEN, "%d.%d.%d.%d", + fw_maj, fw_min, fw_bld, fw_rsv); + + if (strlen(resp->active_pkg_name)) { + int fw_ver_len =3D strlen(bd->fw_ver_str); + + snprintf(bd->fw_ver_str + fw_ver_len, + FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", + resp->active_pkg_name); + bd->fw_cap |=3D BNGE_FW_CAP_PKG_VER; + } + + bd->hwrm_cmd_timeout =3D le16_to_cpu(resp->def_req_timeout); + if (!bd->hwrm_cmd_timeout) + bd->hwrm_cmd_timeout =3D BNGE_DFLT_HWRM_CMD_TIMEOUT; + bd->hwrm_cmd_max_timeout =3D le16_to_cpu(resp->max_req_timeout) * 1000; + if (!bd->hwrm_cmd_max_timeout) + bd->hwrm_cmd_max_timeout =3D BNGE_HWRM_CMD_MAX_TIMEOUT; + else if (bd->hwrm_cmd_max_timeout > BNGE_HWRM_CMD_MAX_TIMEOUT) + dev_warn(bd->dev, "Default HWRM commands max timeout increased to %d sec= onds\n", + bd->hwrm_cmd_max_timeout / 1000); + + bd->hwrm_max_req_len =3D le16_to_cpu(resp->max_req_win_len); + bd->hwrm_max_ext_req_len =3D le16_to_cpu(resp->max_ext_req_len); + + if (bd->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) + bd->hwrm_max_ext_req_len =3D HWRM_MAX_REQ_LEN; + + bd->chip_num =3D le16_to_cpu(resp->chip_num); + bd->chip_rev =3D resp->chip_rev; + + dev_caps_cfg =3D le32_to_cpu(resp->dev_caps_cfg); + if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && + (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) + bd->fw_cap |=3D BNGE_FW_CAP_SHORT_CMD; + + if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) + bd->fw_cap |=3D BNGE_FW_CAP_KONG_MB_CHNL; + + if (dev_caps_cfg & + VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) + bd->fw_cap |=3D BNGE_FW_CAP_CFA_ADV_FLOW; + +hwrm_ver_get_exit: + bnge_hwrm_req_drop(bd, req); + return rc; +} + +int +bnge_hwrm_nvm_dev_info(struct bnge_dev *bd, + struct hwrm_nvm_get_dev_info_output *nvm_info) +{ + struct hwrm_nvm_get_dev_info_output *resp; + struct hwrm_nvm_get_dev_info_input *req; + int rc; + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_NVM_GET_DEV_INFO); + if (rc) + return rc; + + resp =3D bnge_hwrm_req_hold(bd, req); + rc =3D bnge_hwrm_req_send(bd, req); + if (!rc) + memcpy(nvm_info, resp, sizeof(*resp)); + bnge_hwrm_req_drop(bd, req); + return rc; +} + +int bnge_hwrm_func_reset(struct bnge_dev *bd) +{ + struct hwrm_func_reset_input *req; + int rc; + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_FUNC_RESET); + if (rc) + return rc; + + req->enables =3D 0; + bnge_hwrm_req_timeout(bd, req, BNGE_HWRM_RESET_TIMEOUT); + return bnge_hwrm_req_send(bd, req); +} + +int bnge_hwrm_fw_set_time(struct bnge_dev *bd) +{ + struct hwrm_fw_set_time_input *req; + struct tm tm; + int rc; + + time64_to_tm(ktime_get_real_seconds(), 0, &tm); + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_FW_SET_TIME); + if (rc) + return rc; + + req->year =3D cpu_to_le16(1900 + tm.tm_year); + req->month =3D 1 + tm.tm_mon; + req->day =3D tm.tm_mday; + req->hour =3D tm.tm_hour; + req->minute =3D tm.tm_min; + req->second =3D tm.tm_sec; + return bnge_hwrm_req_send(bd, req); +} + +int bnge_hwrm_func_drv_rgtr(struct bnge_dev *bd) +{ + struct hwrm_func_drv_rgtr_output *resp; + struct hwrm_func_drv_rgtr_input *req; + u32 flags; + int rc; + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_FUNC_DRV_RGTR); + if (rc) + return rc; + + req->enables =3D cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | + FUNC_DRV_RGTR_REQ_ENABLES_VER | + FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); + + req->os_type =3D cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); + flags =3D FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE; + + req->flags =3D cpu_to_le32(flags); + req->ver_maj_8b =3D DRV_VER_MAJ; + req->ver_min_8b =3D DRV_VER_MIN; + req->ver_upd_8b =3D DRV_VER_UPD; + req->ver_maj =3D cpu_to_le16(DRV_VER_MAJ); + req->ver_min =3D cpu_to_le16(DRV_VER_MIN); + req->ver_upd =3D cpu_to_le16(DRV_VER_UPD); + + resp =3D bnge_hwrm_req_hold(bd, req); + rc =3D bnge_hwrm_req_send(bd, req); + if (!rc) { + set_bit(BNGE_STATE_DRV_REGISTERED, &bd->state); + if (resp->flags & + cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) + bd->fw_cap |=3D BNGE_FW_CAP_IF_CHANGE; + } + bnge_hwrm_req_drop(bd, req); + return rc; +} + +int bnge_hwrm_func_drv_unrgtr(struct bnge_dev *bd) +{ + struct hwrm_func_drv_unrgtr_input *req; + int rc; + + if (!test_and_clear_bit(BNGE_STATE_DRV_REGISTERED, &bd->state)) + return 0; + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_FUNC_DRV_UNRGTR); + if (rc) + return rc; + return bnge_hwrm_req_send(bd, req); +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.h b/drivers/n= et/ethernet/broadcom/bnge/bnge_hwrm_lib.h new file mode 100644 index 000000000000..9308d4fe64d2 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2025 Broadcom */ + +#ifndef _BNGE_HWRM_LIB_H_ +#define _BNGE_HWRM_LIB_H_ + +int bnge_hwrm_ver_get(struct bnge_dev *bd); +int bnge_hwrm_func_reset(struct bnge_dev *bd); +int bnge_hwrm_fw_set_time(struct bnge_dev *bd); +int bnge_hwrm_func_drv_rgtr(struct bnge_dev *bd); +int bnge_hwrm_func_drv_unrgtr(struct bnge_dev *bd); +int bnge_hwrm_vnic_qcaps(struct bnge_dev *bd); +int bnge_hwrm_nvm_dev_info(struct bnge_dev *bd, + struct hwrm_nvm_get_dev_info_output *nvm_dev_info); + +#endif /* _BNGE_HWRM_LIB_H_ */ --=20 2.47.1 From nobody Wed Oct 8 05:39:37 2025 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98D792701BB for ; Tue, 1 Jul 2025 09:12:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361130; cv=none; b=bmuy+eTw/0fnegGpSPuxSZgCdCgGqttr6pka7OfNFNCAPKWyJfyIoU/ETh0zPqIg6V2M5PbUqDXoexa47zxGHypDY70q5m918LkYCWsLFNDwvxb6PxuOW1zVKlOW2Db4uwR589qodZyLWF0axPT6QRFYNzbsJkSzlvknmEg9BlQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361130; c=relaxed/simple; bh=3vl6QDP6/oKInQpbUd/mwtNJqKOcafNUpwPOeaBo8Z0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AbNKzMz7I+PSMPHcNkWYbh+27UOs50EbWsm31qlVX/lKaF/FIL9YI/GjaQjirwtDZaV6kGkCThcUOG01DB82LrNh3C0alThdUPdQDyrpibA29lb1Q11vZsLUTeUBPzHOhhryd+47jMl9X8Fjr2ay3zg2P9zntsCoXT49a/8X4OE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=PI7AfAzz; arc=none smtp.client-ip=209.85.210.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="PI7AfAzz" Received: by mail-pf1-f178.google.com with SMTP id d2e1a72fcca58-74af4af04fdso3912521b3a.1 for ; Tue, 01 Jul 2025 02:12:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1751361128; x=1751965928; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jZ8ourLzAapYlWvSPc5AJIM32EfKtOVtF0mK8gd87tE=; b=PI7AfAzz7fq9zRTgqLiIi8TAbmlI+txTvPgvW1Ou2iU//a6m6O8tsrQehC0fKmKooI 8IWq5w+s8qQSooui53wSx8udBhakHnFKTddwjrD7USBizQZfnXiERQK8/J2F+56RwLZT JywDGl3T2HzIUpj+IO8u+zHD6e2acJ8+mcJYs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751361128; x=1751965928; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jZ8ourLzAapYlWvSPc5AJIM32EfKtOVtF0mK8gd87tE=; b=KVS2g9i6hwYcTK9ZNOL60ojTsbkHsSYh61eBD/OYUfTAPOG4jrm8FqkZgC2A3lq3Fe 9GOpoTGoobutXZ0rkqSI5xmApZoN0mbtOiKG2ftOgP5GPVTbnKCukfnfn1NFzAPWjU2Q KN8AZKg3wcC7z8m6lczILVRLPJQdbC2Jjil1j6pzlev1hZa0P4RAOnj1qHL0cnQt49eR LKCyA1WeABHnlglIjMenSy3PfwBHKrHdv6jYF1WpDIPqcMKNMf77za8jQKmTWWp+Ad+j YP6I/qsB8qkOjfJekbqmm5bSQkNa+MiBnkl2+YWImiwrBOo6pG5P6cCBh9DvMC6020Dq 5Tgw== X-Forwarded-Encrypted: i=1; AJvYcCVfgu5nxTOQxIdtdnuVyVB+8ydwYUKvZZvGPsF5g4/wlupwE2NdRBFxaZ3HnNe3/2FyOfyq1f2V2XZhaSs=@vger.kernel.org X-Gm-Message-State: AOJu0YxctmJef8xeJfPM2+4+kXZ5Rl90yfIn02yIwxO2/YPEzRpVLL+v lNjhFcftrV2Y1W0EWUoWFLv/hzHTLrmNL22220/aW3lV+FI+Y4vxPe2BjBEPodbozg== X-Gm-Gg: ASbGnctJQsLVLXyoYuGHzZA1wtCtT9OKmPyHjybTc3GH0fMlkUCsXanVMwn1cMSg6Hf +I/TnpabdXLaGMMabj9DPQo49hO3AJ0CdsrEv9bZoJplcdPgYVpK2QiRpDRhXADNiztYfwg3rW8 xoaqACHLVIG6aIOSiTaEQAaEDLmbQAe6TZPhEznRWA093bZ/XxldKtcBQLjAEcuoFIRdFu2HLLV Pdil+RxThmXNxRRdtK487HE02reH0RAoHkOj08ybAYjcwqjuVCuAsvQgbaaFG6e73eBSOjsNJ6a 8FXmOzJ7Zpa6j0+hMUoFlVqHoMMqCyBtzzJmqPpJIlOnDPiiOz5qErOC1BWe0XAhQtKueug1FAo JHTWdNg1TTOjo/P4kKCWOGXtlxiZN X-Google-Smtp-Source: AGHT+IGD+PMyQWbgggCcfUfqdisjXVNVVZ/j0kgFtp8pFRi3WYkkhSlUmFf0Uco8sWkPny3WcokBDQ== X-Received: by 2002:a05:6a21:e89:b0:21f:54f0:3b6a with SMTP id adf61e73a8af0-222c9a481fcmr5501225637.12.1751361127733; Tue, 01 Jul 2025 02:12:07 -0700 (PDT) Received: from localhost.localdomain ([192.19.203.250]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b34e30201c1sm8893603a12.22.2025.07.01.02.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 02:12:07 -0700 (PDT) From: Vikas Gupta To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, andrew+netdev@lunn.ch, horms@kernel.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, michael.chan@broadcom.com, pavan.chebbi@broadcom.com, vsrama-krishna.nemani@broadcom.com, Vikas Gupta , Bhargava Chenna Marreddy , Rajashekar Hudumula Subject: [net-next, v3 05/10] bng_en: Add ring memory allocation support Date: Tue, 1 Jul 2025 14:35:03 +0000 Message-ID: <20250701143511.280702-6-vikas.gupta@broadcom.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250701143511.280702-1-vikas.gupta@broadcom.com> References: <20250701143511.280702-1-vikas.gupta@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ring allocation/free mechanism which help to allocate rings (TX/RX/Completion) and backing stores memory on the host for the device. Future patches will use these functions. Signed-off-by: Vikas Gupta Reviewed-by: Bhargava Chenna Marreddy Reviewed-by: Rajashekar Hudumula --- drivers/net/ethernet/broadcom/bnge/Makefile | 3 +- .../net/ethernet/broadcom/bnge/bnge_rmem.c | 101 ++++++++++++++++++ .../net/ethernet/broadcom/bnge/bnge_rmem.h | 35 ++++++ 3 files changed, 138 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_rmem.c create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_rmem.h diff --git a/drivers/net/ethernet/broadcom/bnge/Makefile b/drivers/net/ethe= rnet/broadcom/bnge/Makefile index b8dbbc2d5972..1144594fc3f6 100644 --- a/drivers/net/ethernet/broadcom/bnge/Makefile +++ b/drivers/net/ethernet/broadcom/bnge/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_BNGE) +=3D bng_en.o bng_en-y :=3D bnge_core.o \ bnge_devlink.o \ bnge_hwrm.o \ - bnge_hwrm_lib.o + bnge_hwrm_lib.o \ + bnge_rmem.o diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_rmem.c b/drivers/net/e= thernet/broadcom/bnge/bnge_rmem.c new file mode 100644 index 000000000000..ef232c4217bc --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_rmem.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2025 Broadcom. + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bnge.h" +#include "../bnxt/bnxt_hsi.h" +#include "bnge_hwrm_lib.h" +#include "bnge_rmem.h" + +void bnge_free_ring(struct bnge_dev *bd, struct bnge_ring_mem_info *rmem) +{ + struct pci_dev *pdev =3D bd->pdev; + int i; + + if (!rmem->pg_arr) + goto skip_pages; + + for (i =3D 0; i < rmem->nr_pages; i++) { + if (!rmem->pg_arr[i]) + continue; + + dma_free_coherent(&pdev->dev, rmem->page_size, + rmem->pg_arr[i], rmem->dma_arr[i]); + + rmem->pg_arr[i] =3D NULL; + } +skip_pages: + if (rmem->pg_tbl) { + size_t pg_tbl_size =3D rmem->nr_pages * 8; + + if (rmem->flags & BNGE_RMEM_USE_FULL_PAGE_FLAG) + pg_tbl_size =3D rmem->page_size; + dma_free_coherent(&pdev->dev, pg_tbl_size, + rmem->pg_tbl, rmem->dma_pg_tbl); + rmem->pg_tbl =3D NULL; + } + if (rmem->vmem_size && *rmem->vmem) { + vfree(*rmem->vmem); + *rmem->vmem =3D NULL; + } +} + +int bnge_alloc_ring(struct bnge_dev *bd, struct bnge_ring_mem_info *rmem) +{ + struct pci_dev *pdev =3D bd->pdev; + u64 valid_bit =3D 0; + int i; + + if (rmem->flags & (BNGE_RMEM_VALID_PTE_FLAG | BNGE_RMEM_RING_PTE_FLAG)) + valid_bit =3D PTU_PTE_VALID; + + if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { + size_t pg_tbl_size =3D rmem->nr_pages * 8; + + if (rmem->flags & BNGE_RMEM_USE_FULL_PAGE_FLAG) + pg_tbl_size =3D rmem->page_size; + rmem->pg_tbl =3D dma_alloc_coherent(&pdev->dev, pg_tbl_size, + &rmem->dma_pg_tbl, + GFP_KERNEL); + if (!rmem->pg_tbl) + return -ENOMEM; + } + + for (i =3D 0; i < rmem->nr_pages; i++) { + u64 extra_bits =3D valid_bit; + + rmem->pg_arr[i] =3D dma_alloc_coherent(&pdev->dev, + rmem->page_size, + &rmem->dma_arr[i], + GFP_KERNEL); + if (!rmem->pg_arr[i]) + return -ENOMEM; + + if (rmem->nr_pages > 1 || rmem->depth > 0) { + if (i =3D=3D rmem->nr_pages - 2 && + (rmem->flags & BNGE_RMEM_RING_PTE_FLAG)) + extra_bits |=3D PTU_PTE_NEXT_TO_LAST; + else if (i =3D=3D rmem->nr_pages - 1 && + (rmem->flags & BNGE_RMEM_RING_PTE_FLAG)) + extra_bits |=3D PTU_PTE_LAST; + rmem->pg_tbl[i] =3D + cpu_to_le64(rmem->dma_arr[i] | extra_bits); + } + } + + if (rmem->vmem_size) { + *rmem->vmem =3D vzalloc(rmem->vmem_size); + if (!(*rmem->vmem)) + return -ENOMEM; + } + + return 0; +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_rmem.h b/drivers/net/e= thernet/broadcom/bnge/bnge_rmem.h new file mode 100644 index 000000000000..56de31ed6613 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_rmem.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2025 Broadcom */ + +#ifndef _BNGE_RMEM_H_ +#define _BNGE_RMEM_H_ + +#define PTU_PTE_VALID 0x1UL +#define PTU_PTE_LAST 0x2UL +#define PTU_PTE_NEXT_TO_LAST 0x4UL + +struct bnge_ring_mem_info { + /* Number of pages to next level */ + int nr_pages; + int page_size; + u16 flags; +#define BNGE_RMEM_VALID_PTE_FLAG 1 +#define BNGE_RMEM_RING_PTE_FLAG 2 +#define BNGE_RMEM_USE_FULL_PAGE_FLAG 4 + + u16 depth; + + void **pg_arr; + dma_addr_t *dma_arr; + + __le64 *pg_tbl; + dma_addr_t dma_pg_tbl; + + int vmem_size; + void **vmem; +}; + +int bnge_alloc_ring(struct bnge_dev *bd, struct bnge_ring_mem_info *rmem); +void bnge_free_ring(struct bnge_dev *bd, struct bnge_ring_mem_info *rmem); + +#endif /* _BNGE_RMEM_H_ */ --=20 2.47.1 From nobody Wed Oct 8 05:39:37 2025 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9F3A270EA2 for ; Tue, 1 Jul 2025 09:12:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361134; cv=none; b=mvPkzD/pK+xqKW2dDV9XTjAsDQRUotZT66TONlSC3hBWwksfxCJaFmq/I62ffwE1uIMoCE7hHNNYu71+DcfybcCHzwRAw/eslwMsC03MNfP7oEKCwTpPdKy3cfoFctEeSB2LKLfOEng+Fu0q0f4tFd3woyu6ysRFxkpB4gupKIg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361134; c=relaxed/simple; bh=aRvvfwgn4muU07e9mCsSPE6zLsYVdRsN+X5I7zRhPYc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KWP5LG37C8pmRevLspSdz6KNGxjm3t5meIQ+r+tHUUyj27MsPCPsrm74+0tHyUQLTrRwwzH7ObL6lM4hOGne0ixYCFQG0NoImg6M9i2kzoVhoUi41jtjAtUf4y3YAMPXZTfnxQyLlJaiX3Ipvau9Bhog/P9tTy4LMjdP95CcW2I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=gfbNX6py; arc=none smtp.client-ip=209.85.210.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="gfbNX6py" Received: by mail-pf1-f173.google.com with SMTP id d2e1a72fcca58-7490cb9a892so3784509b3a.0 for ; Tue, 01 Jul 2025 02:12:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1751361132; x=1751965932; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/6zldlB+51cDZUFEJG/JbyeLDVSusfY0mmn3+U6svIM=; b=gfbNX6pyQ4XEv5n+RxWfPLujsSamx1we7I5nbXWZhgVIK1cbPlxpvq3j6kOCbofAMN 6ECHKrYlNIqxwvuntp5iKNZlxUNw4ZjXE5AERVm8MTShk2PAGj0qKHtalIQJ1Y3C6J0f ncpqTdU7SYO0ummt6p4LtUGZZVdEPTxdiGIgk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751361132; x=1751965932; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/6zldlB+51cDZUFEJG/JbyeLDVSusfY0mmn3+U6svIM=; b=D3yf5X2Rscm1r9kmqtjJI/ehRCdu7T8BBmUUvA9xm/SV3/0I6r3KRPvld4H/8GxmdT ByMuYH7qbLQKLsVXuZ+Pu2S+aT6U+PA5lIt1NeBubVKtKqagBj5pRsDN3zwQOnEYl2xi R8Ve8OMgbCmMsHMPLVIPAdf+KL7k9kdqNfiwh6tI2LuBH/wElNe+oxLvTWj1OXClHbSR ZFD1d+ZHLNI4M81J31pSa6xckaWR17HHVaKo+9AQ/3S5xs/57ZvfXLeumNZ+CosIzsvI oj6QfVirPWP83igGX2wbUf3/Wo1NkFUjs6SETQFmQfCPhARzCcfqRR7WlpDzDWi6Go2B mZQQ== X-Forwarded-Encrypted: i=1; AJvYcCUQCjgbdBzL1Psj7yVQmNMHjHI7HFomFRvXJJmnUyYaB/9Lwm/0kRbeD6tz5NAl7Fw96x95o+P65GjLV0Y=@vger.kernel.org X-Gm-Message-State: AOJu0Yxw3bphpSfg0PqanCtg85pogR7i+jiXWuPJ16xPG50CsIZG4Yis mufHy7VvLHKvsi8sZwwiQonXhrSceXxwwWYmYJgG5wS7gFbG+XWeQMm4XUv0xB6ZhA== X-Gm-Gg: ASbGnct5CaVKpWnJPF1GBhR9uDhcGn6Audc7M7XBdmhl+KPMRXZOmPROONuq5KCp56Q bqZaBxkVEbFUu/gYY8pN6Ba50yZdJZWx4AaSplh9P5wn51TpF5U4LjP2zio0Spg7cvYb0od5HSH wz4PHjhAKLx4KVoTWqUG5RHTCkqQLG1HWFjhlXzFVA9OwkvYOhZz3pl/wdrwTdIkxkczindMN1V 1hWnuKPv14tJjwFQKLxMtNScSuMY6MEpcYKfALrAZ4dpsPyaAw+XrFw7kQJEniIA0+ZhiPOY/hi 0zI6dNgygcsDcmS//K3CX8tUghQtUuf4Bjr3hGJhli01vurYQACTD+21YV/TsLE9GS3PkmTMwBu t5SjJhZD7JbddW6aYM2rKtmr1zRJz X-Google-Smtp-Source: AGHT+IEmFrim4m8HzIx/dDKhQE0eNzJ2PKjTiX5hMhAupM2SzxuRWwlqR6PSFSlIngBlrRzJdBQTNw== X-Received: by 2002:a05:6a21:999c:b0:220:879d:5648 with SMTP id adf61e73a8af0-220a16b8ed1mr25166934637.21.1751361131980; Tue, 01 Jul 2025 02:12:11 -0700 (PDT) Received: from localhost.localdomain ([192.19.203.250]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b34e30201c1sm8893603a12.22.2025.07.01.02.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 02:12:11 -0700 (PDT) From: Vikas Gupta To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, andrew+netdev@lunn.ch, horms@kernel.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, michael.chan@broadcom.com, pavan.chebbi@broadcom.com, vsrama-krishna.nemani@broadcom.com, Vikas Gupta , Bhargava Chenna Marreddy , Rajashekar Hudumula Subject: [net-next, v3 06/10] bng_en: Add backing store support Date: Tue, 1 Jul 2025 14:35:04 +0000 Message-ID: <20250701143511.280702-7-vikas.gupta@broadcom.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250701143511.280702-1-vikas.gupta@broadcom.com> References: <20250701143511.280702-1-vikas.gupta@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Backing store or context memory on the host helps the device to manage rings, stats and other resources. Context memory is allocated with the help of ring alloc/free functions. Signed-off-by: Vikas Gupta Reviewed-by: Bhargava Chenna Marreddy Reviewed-by: Rajashekar Hudumula --- drivers/net/ethernet/broadcom/bnge/bnge.h | 18 + .../ethernet/broadcom/bnge/bnge_hwrm_lib.c | 168 +++++++++ .../ethernet/broadcom/bnge/bnge_hwrm_lib.h | 4 + .../net/ethernet/broadcom/bnge/bnge_rmem.c | 337 ++++++++++++++++++ .../net/ethernet/broadcom/bnge/bnge_rmem.h | 153 ++++++++ 5 files changed, 680 insertions(+) diff --git a/drivers/net/ethernet/broadcom/bnge/bnge.h b/drivers/net/ethern= et/broadcom/bnge/bnge.h index 60af0517c45e..01f64a10729c 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge.h @@ -9,6 +9,7 @@ =20 #include #include "../bnxt/bnxt_hsi.h" +#include "bnge_rmem.h" =20 #define DRV_VER_MAJ 1 #define DRV_VER_MIN 15 @@ -52,6 +53,13 @@ enum { BNGE_FW_CAP_VNIC_RE_FLUSH =3D BIT_ULL(26), }; =20 +enum { + BNGE_EN_ROCE_V1 =3D BIT_ULL(0), + BNGE_EN_ROCE_V2 =3D BIT_ULL(1), +}; + +#define BNGE_EN_ROCE (BNGE_EN_ROCE_V1 | BNGE_EN_ROCE_V2) + struct bnge_dev { struct device *dev; struct pci_dev *pdev; @@ -89,6 +97,16 @@ struct bnge_dev { #define BNGE_STATE_DRV_REGISTERED 0 =20 u64 fw_cap; + + /* Backing stores */ + struct bnge_ctx_mem_info *ctx; + + u64 flags; }; =20 +static inline bool bnge_is_roce_en(struct bnge_dev *bd) +{ + return bd->flags & BNGE_EN_ROCE; +} + #endif /* _BNGE_H_ */ diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c b/drivers/n= et/ethernet/broadcom/bnge/bnge_hwrm_lib.c index 25ac73ac37ba..dc69bd1461f9 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c +++ b/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c @@ -10,6 +10,7 @@ #include "../bnxt/bnxt_hsi.h" #include "bnge_hwrm.h" #include "bnge_hwrm_lib.h" +#include "bnge_rmem.h" =20 int bnge_hwrm_ver_get(struct bnge_dev *bd) { @@ -211,3 +212,170 @@ int bnge_hwrm_func_drv_unrgtr(struct bnge_dev *bd) return rc; return bnge_hwrm_req_send(bd, req); } + +static void bnge_init_ctx_initializer(struct bnge_ctx_mem_type *ctxm, + u8 init_val, u8 init_offset, + bool init_mask_set) +{ + ctxm->init_value =3D init_val; + ctxm->init_offset =3D BNGE_CTX_INIT_INVALID_OFFSET; + if (init_mask_set) + ctxm->init_offset =3D init_offset * 4; + else + ctxm->init_value =3D 0; +} + +static int bnge_alloc_all_ctx_pg_info(struct bnge_dev *bd, int ctx_max) +{ + struct bnge_ctx_mem_info *ctx =3D bd->ctx; + u16 type; + + for (type =3D 0; type < ctx_max; type++) { + struct bnge_ctx_mem_type *ctxm =3D &ctx->ctx_arr[type]; + int n =3D 1; + + if (!ctxm->max_entries) + continue; + + if (ctxm->instance_bmap) + n =3D hweight32(ctxm->instance_bmap); + ctxm->pg_info =3D kcalloc(n, sizeof(*ctxm->pg_info), GFP_KERNEL); + if (!ctxm->pg_info) + return -ENOMEM; + } + + return 0; +} + +#define BNGE_CTX_INIT_VALID(flags) \ + (!!((flags) & \ + FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT)) + +int bnge_hwrm_func_backing_store_qcaps(struct bnge_dev *bd) +{ + struct hwrm_func_backing_store_qcaps_v2_output *resp; + struct hwrm_func_backing_store_qcaps_v2_input *req; + struct bnge_ctx_mem_info *ctx; + u16 type; + int rc; + + if (bd->ctx) + return 0; + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_FUNC_BACKING_STORE_QCAPS_V2); + if (rc) + return rc; + + ctx =3D kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + bd->ctx =3D ctx; + + resp =3D bnge_hwrm_req_hold(bd, req); + + for (type =3D 0; type < BNGE_CTX_V2_MAX; ) { + struct bnge_ctx_mem_type *ctxm =3D &ctx->ctx_arr[type]; + u8 init_val, init_off, i; + __le32 *p; + u32 flags; + + req->type =3D cpu_to_le16(type); + rc =3D bnge_hwrm_req_send(bd, req); + if (rc) + goto ctx_done; + flags =3D le32_to_cpu(resp->flags); + type =3D le16_to_cpu(resp->next_valid_type); + if (!(flags & + FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID)) + continue; + + ctxm->type =3D le16_to_cpu(resp->type); + ctxm->entry_size =3D le16_to_cpu(resp->entry_size); + ctxm->flags =3D flags; + ctxm->instance_bmap =3D le32_to_cpu(resp->instance_bit_map); + ctxm->entry_multiple =3D resp->entry_multiple; + ctxm->max_entries =3D le32_to_cpu(resp->max_num_entries); + ctxm->min_entries =3D le32_to_cpu(resp->min_num_entries); + init_val =3D resp->ctx_init_value; + init_off =3D resp->ctx_init_offset; + bnge_init_ctx_initializer(ctxm, init_val, init_off, + BNGE_CTX_INIT_VALID(flags)); + ctxm->split_entry_cnt =3D min_t(u8, resp->subtype_valid_cnt, + BNGE_MAX_SPLIT_ENTRY); + for (i =3D 0, p =3D &resp->split_entry_0; i < ctxm->split_entry_cnt; + i++, p++) + ctxm->split[i] =3D le32_to_cpu(*p); + } + rc =3D bnge_alloc_all_ctx_pg_info(bd, BNGE_CTX_V2_MAX); + +ctx_done: + bnge_hwrm_req_drop(bd, req); + return rc; +} + +static void bnge_hwrm_set_pg_attr(struct bnge_ring_mem_info *rmem, u8 *pg_= attr, + __le64 *pg_dir) +{ + if (!rmem->nr_pages) + return; + + BNGE_SET_CTX_PAGE_ATTR(*pg_attr); + if (rmem->depth >=3D 1) { + if (rmem->depth =3D=3D 2) + *pg_attr |=3D 2; + else + *pg_attr |=3D 1; + *pg_dir =3D cpu_to_le64(rmem->dma_pg_tbl); + } else { + *pg_dir =3D cpu_to_le64(rmem->dma_arr[0]); + } +} + +int bnge_hwrm_func_backing_store(struct bnge_dev *bd, + struct bnge_ctx_mem_type *ctxm, + bool last) +{ + struct hwrm_func_backing_store_cfg_v2_input *req; + u32 instance_bmap =3D ctxm->instance_bmap; + int i, j, rc =3D 0, n =3D 1; + __le32 *p; + + if (!(ctxm->flags & BNGE_CTX_MEM_TYPE_VALID) || !ctxm->pg_info) + return 0; + + if (instance_bmap) + n =3D hweight32(ctxm->instance_bmap); + else + instance_bmap =3D 1; + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_FUNC_BACKING_STORE_CFG_V2); + if (rc) + return rc; + bnge_hwrm_req_hold(bd, req); + req->type =3D cpu_to_le16(ctxm->type); + req->entry_size =3D cpu_to_le16(ctxm->entry_size); + req->subtype_valid_cnt =3D ctxm->split_entry_cnt; + for (i =3D 0, p =3D &req->split_entry_0; i < ctxm->split_entry_cnt; i++) + p[i] =3D cpu_to_le32(ctxm->split[i]); + for (i =3D 0, j =3D 0; j < n && !rc; i++) { + struct bnge_ctx_pg_info *ctx_pg; + + if (!(instance_bmap & (1 << i))) + continue; + req->instance =3D cpu_to_le16(i); + ctx_pg =3D &ctxm->pg_info[j++]; + if (!ctx_pg->entries) + continue; + req->num_entries =3D cpu_to_le32(ctx_pg->entries); + bnge_hwrm_set_pg_attr(&ctx_pg->ring_mem, + &req->page_size_pbl_level, + &req->page_dir); + if (last && j =3D=3D n) + req->flags =3D + cpu_to_le32(BNGE_BS_CFG_ALL_DONE); + rc =3D bnge_hwrm_req_send(bd, req); + } + bnge_hwrm_req_drop(bd, req); + + return rc; +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.h b/drivers/n= et/ethernet/broadcom/bnge/bnge_hwrm_lib.h index 9308d4fe64d2..c04291d74bf0 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.h @@ -12,5 +12,9 @@ int bnge_hwrm_func_drv_unrgtr(struct bnge_dev *bd); int bnge_hwrm_vnic_qcaps(struct bnge_dev *bd); int bnge_hwrm_nvm_dev_info(struct bnge_dev *bd, struct hwrm_nvm_get_dev_info_output *nvm_dev_info); +int bnge_hwrm_func_backing_store(struct bnge_dev *bd, + struct bnge_ctx_mem_type *ctxm, + bool last); +int bnge_hwrm_func_backing_store_qcaps(struct bnge_dev *bd); =20 #endif /* _BNGE_HWRM_LIB_H_ */ diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_rmem.c b/drivers/net/e= thernet/broadcom/bnge/bnge_rmem.c index ef232c4217bc..0e935cc46da6 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_rmem.c +++ b/drivers/net/ethernet/broadcom/bnge/bnge_rmem.c @@ -15,6 +15,24 @@ #include "bnge_hwrm_lib.h" #include "bnge_rmem.h" =20 +static void bnge_init_ctx_mem(struct bnge_ctx_mem_type *ctxm, + void *p, int len) +{ + u8 init_val =3D ctxm->init_value; + u16 offset =3D ctxm->init_offset; + u8 *p2 =3D p; + int i; + + if (!init_val) + return; + if (offset =3D=3D BNGE_CTX_INIT_INVALID_OFFSET) { + memset(p, init_val, len); + return; + } + for (i =3D 0; i < len; i +=3D ctxm->entry_size) + *(p2 + i + offset) =3D init_val; +} + void bnge_free_ring(struct bnge_dev *bd, struct bnge_ring_mem_info *rmem) { struct pci_dev *pdev =3D bd->pdev; @@ -79,6 +97,10 @@ int bnge_alloc_ring(struct bnge_dev *bd, struct bnge_rin= g_mem_info *rmem) if (!rmem->pg_arr[i]) return -ENOMEM; =20 + if (rmem->ctx_mem) + bnge_init_ctx_mem(rmem->ctx_mem, rmem->pg_arr[i], + rmem->page_size); + if (rmem->nr_pages > 1 || rmem->depth > 0) { if (i =3D=3D rmem->nr_pages - 2 && (rmem->flags & BNGE_RMEM_RING_PTE_FLAG)) @@ -99,3 +121,318 @@ int bnge_alloc_ring(struct bnge_dev *bd, struct bnge_r= ing_mem_info *rmem) =20 return 0; } + +static int bnge_alloc_ctx_one_lvl(struct bnge_dev *bd, + struct bnge_ctx_pg_info *ctx_pg) +{ + struct bnge_ring_mem_info *rmem =3D &ctx_pg->ring_mem; + + rmem->page_size =3D BNGE_PAGE_SIZE; + rmem->pg_arr =3D ctx_pg->ctx_pg_arr; + rmem->dma_arr =3D ctx_pg->ctx_dma_arr; + rmem->flags =3D BNGE_RMEM_VALID_PTE_FLAG; + if (rmem->depth >=3D 1) + rmem->flags |=3D BNGE_RMEM_USE_FULL_PAGE_FLAG; + return bnge_alloc_ring(bd, rmem); +} + +static int bnge_alloc_ctx_pg_tbls(struct bnge_dev *bd, + struct bnge_ctx_pg_info *ctx_pg, u32 mem_size, + u8 depth, struct bnge_ctx_mem_type *ctxm) +{ + struct bnge_ring_mem_info *rmem =3D &ctx_pg->ring_mem; + int rc; + + if (!mem_size) + return -EINVAL; + + ctx_pg->nr_pages =3D DIV_ROUND_UP(mem_size, BNGE_PAGE_SIZE); + if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { + ctx_pg->nr_pages =3D 0; + return -EINVAL; + } + if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { + int nr_tbls, i; + + rmem->depth =3D 2; + ctx_pg->ctx_pg_tbl =3D kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), + GFP_KERNEL); + if (!ctx_pg->ctx_pg_tbl) + return -ENOMEM; + nr_tbls =3D DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); + rmem->nr_pages =3D nr_tbls; + rc =3D bnge_alloc_ctx_one_lvl(bd, ctx_pg); + if (rc) + return rc; + for (i =3D 0; i < nr_tbls; i++) { + struct bnge_ctx_pg_info *pg_tbl; + + pg_tbl =3D kzalloc(sizeof(*pg_tbl), GFP_KERNEL); + if (!pg_tbl) + return -ENOMEM; + ctx_pg->ctx_pg_tbl[i] =3D pg_tbl; + rmem =3D &pg_tbl->ring_mem; + rmem->pg_tbl =3D ctx_pg->ctx_pg_arr[i]; + rmem->dma_pg_tbl =3D ctx_pg->ctx_dma_arr[i]; + rmem->depth =3D 1; + rmem->nr_pages =3D MAX_CTX_PAGES; + rmem->ctx_mem =3D ctxm; + if (i =3D=3D (nr_tbls - 1)) { + int rem =3D ctx_pg->nr_pages % MAX_CTX_PAGES; + + if (rem) + rmem->nr_pages =3D rem; + } + rc =3D bnge_alloc_ctx_one_lvl(bd, pg_tbl); + if (rc) + break; + } + } else { + rmem->nr_pages =3D DIV_ROUND_UP(mem_size, BNGE_PAGE_SIZE); + if (rmem->nr_pages > 1 || depth) + rmem->depth =3D 1; + rmem->ctx_mem =3D ctxm; + rc =3D bnge_alloc_ctx_one_lvl(bd, ctx_pg); + } + + return rc; +} + +static void bnge_free_ctx_pg_tbls(struct bnge_dev *bd, + struct bnge_ctx_pg_info *ctx_pg) +{ + struct bnge_ring_mem_info *rmem =3D &ctx_pg->ring_mem; + + if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || + ctx_pg->ctx_pg_tbl) { + int i, nr_tbls =3D rmem->nr_pages; + + for (i =3D 0; i < nr_tbls; i++) { + struct bnge_ctx_pg_info *pg_tbl; + struct bnge_ring_mem_info *rmem2; + + pg_tbl =3D ctx_pg->ctx_pg_tbl[i]; + if (!pg_tbl) + continue; + rmem2 =3D &pg_tbl->ring_mem; + bnge_free_ring(bd, rmem2); + ctx_pg->ctx_pg_arr[i] =3D NULL; + kfree(pg_tbl); + ctx_pg->ctx_pg_tbl[i] =3D NULL; + } + kfree(ctx_pg->ctx_pg_tbl); + ctx_pg->ctx_pg_tbl =3D NULL; + } + bnge_free_ring(bd, rmem); + ctx_pg->nr_pages =3D 0; +} + +static int bnge_setup_ctxm_pg_tbls(struct bnge_dev *bd, + struct bnge_ctx_mem_type *ctxm, u32 entries, + u8 pg_lvl) +{ + struct bnge_ctx_pg_info *ctx_pg =3D ctxm->pg_info; + int i, rc =3D 0, n =3D 1; + u32 mem_size; + + if (!ctxm->entry_size || !ctx_pg) + return -EINVAL; + if (ctxm->instance_bmap) + n =3D hweight32(ctxm->instance_bmap); + if (ctxm->entry_multiple) + entries =3D roundup(entries, ctxm->entry_multiple); + entries =3D clamp_t(u32, entries, ctxm->min_entries, ctxm->max_entries); + mem_size =3D entries * ctxm->entry_size; + for (i =3D 0; i < n && !rc; i++) { + ctx_pg[i].entries =3D entries; + rc =3D bnge_alloc_ctx_pg_tbls(bd, &ctx_pg[i], mem_size, pg_lvl, + ctxm->init_value ? ctxm : NULL); + } + + return rc; +} + +static int bnge_backing_store_cfg(struct bnge_dev *bd, u32 ena) +{ + struct bnge_ctx_mem_info *ctx =3D bd->ctx; + struct bnge_ctx_mem_type *ctxm; + u16 last_type; + int rc =3D 0; + u16 type; + + if (!ena) + return 0; + else if (ena & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) + last_type =3D BNGE_CTX_MAX - 1; + else + last_type =3D BNGE_CTX_L2_MAX - 1; + ctx->ctx_arr[last_type].last =3D 1; + + for (type =3D 0 ; type < BNGE_CTX_V2_MAX; type++) { + ctxm =3D &ctx->ctx_arr[type]; + + rc =3D bnge_hwrm_func_backing_store(bd, ctxm, ctxm->last); + if (rc) + return rc; + } + + return 0; +} + +void bnge_free_ctx_mem(struct bnge_dev *bd) +{ + struct bnge_ctx_mem_info *ctx =3D bd->ctx; + u16 type; + + if (!ctx) + return; + + for (type =3D 0; type < BNGE_CTX_V2_MAX; type++) { + struct bnge_ctx_mem_type *ctxm =3D &ctx->ctx_arr[type]; + struct bnge_ctx_pg_info *ctx_pg =3D ctxm->pg_info; + int i, n =3D 1; + + if (!ctx_pg) + continue; + if (ctxm->instance_bmap) + n =3D hweight32(ctxm->instance_bmap); + for (i =3D 0; i < n; i++) + bnge_free_ctx_pg_tbls(bd, &ctx_pg[i]); + + kfree(ctx_pg); + ctxm->pg_info =3D NULL; + } + + ctx->flags &=3D ~BNGE_CTX_FLAG_INITED; + kfree(ctx); + bd->ctx =3D NULL; +} + +#define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ + (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ + FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ + FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ + FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ + FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) + +int bnge_alloc_ctx_mem(struct bnge_dev *bd) +{ + struct bnge_ctx_mem_type *ctxm; + struct bnge_ctx_mem_info *ctx; + u32 l2_qps, qp1_qps, max_qps; + u32 ena, entries_sp, entries; + u32 srqs, max_srqs, min; + u32 num_mr, num_ah; + u32 extra_srqs =3D 0; + u32 extra_qps =3D 0; + u32 fast_qpmd_qps; + u8 pg_lvl =3D 1; + int i, rc; + + rc =3D bnge_hwrm_func_backing_store_qcaps(bd); + if (rc) { + dev_err(bd->dev, "Failed querying ctx mem caps, rc: %d\n", rc); + return rc; + } + + ctx =3D bd->ctx; + if (!ctx || (ctx->flags & BNGE_CTX_FLAG_INITED)) + return 0; + + ctxm =3D &ctx->ctx_arr[BNGE_CTX_QP]; + l2_qps =3D ctxm->qp_l2_entries; + qp1_qps =3D ctxm->qp_qp1_entries; + fast_qpmd_qps =3D ctxm->qp_fast_qpmd_entries; + max_qps =3D ctxm->max_entries; + ctxm =3D &ctx->ctx_arr[BNGE_CTX_SRQ]; + srqs =3D ctxm->srq_l2_entries; + max_srqs =3D ctxm->max_entries; + ena =3D 0; + if (bnge_is_roce_en(bd) && !is_kdump_kernel()) { + pg_lvl =3D 2; + extra_qps =3D min_t(u32, 65536, max_qps - l2_qps - qp1_qps); + /* allocate extra qps if fast qp destroy feature enabled */ + extra_qps +=3D fast_qpmd_qps; + extra_srqs =3D min_t(u32, 8192, max_srqs - srqs); + if (fast_qpmd_qps) + ena |=3D FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP_FAST_QPMD; + } + + ctxm =3D &ctx->ctx_arr[BNGE_CTX_QP]; + rc =3D bnge_setup_ctxm_pg_tbls(bd, ctxm, l2_qps + qp1_qps + extra_qps, + pg_lvl); + if (rc) + return rc; + + ctxm =3D &ctx->ctx_arr[BNGE_CTX_SRQ]; + rc =3D bnge_setup_ctxm_pg_tbls(bd, ctxm, srqs + extra_srqs, pg_lvl); + if (rc) + return rc; + + ctxm =3D &ctx->ctx_arr[BNGE_CTX_CQ]; + rc =3D bnge_setup_ctxm_pg_tbls(bd, ctxm, ctxm->cq_l2_entries + + extra_qps * 2, pg_lvl); + if (rc) + return rc; + + ctxm =3D &ctx->ctx_arr[BNGE_CTX_VNIC]; + rc =3D bnge_setup_ctxm_pg_tbls(bd, ctxm, ctxm->max_entries, 1); + if (rc) + return rc; + + ctxm =3D &ctx->ctx_arr[BNGE_CTX_STAT]; + rc =3D bnge_setup_ctxm_pg_tbls(bd, ctxm, ctxm->max_entries, 1); + if (rc) + return rc; + + if (!bnge_is_roce_en(bd)) + goto skip_rdma; + + ctxm =3D &ctx->ctx_arr[BNGE_CTX_MRAV]; + /* 128K extra is needed to accommodate static AH context + * allocation by f/w. + */ + num_mr =3D min_t(u32, ctxm->max_entries / 2, 1024 * 256); + num_ah =3D min_t(u32, num_mr, 1024 * 128); + ctxm->split_entry_cnt =3D BNGE_CTX_MRAV_AV_SPLIT_ENTRY + 1; + if (!ctxm->mrav_av_entries || ctxm->mrav_av_entries > num_ah) + ctxm->mrav_av_entries =3D num_ah; + + rc =3D bnge_setup_ctxm_pg_tbls(bd, ctxm, num_mr + num_ah, 2); + if (rc) + return rc; + ena |=3D FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; + + ctxm =3D &ctx->ctx_arr[BNGE_CTX_TIM]; + rc =3D bnge_setup_ctxm_pg_tbls(bd, ctxm, l2_qps + qp1_qps + extra_qps, 1); + if (rc) + return rc; + ena |=3D FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; + +skip_rdma: + ctxm =3D &ctx->ctx_arr[BNGE_CTX_STQM]; + min =3D ctxm->min_entries; + entries_sp =3D ctx->ctx_arr[BNGE_CTX_VNIC].vnic_entries + l2_qps + + 2 * (extra_qps + qp1_qps) + min; + rc =3D bnge_setup_ctxm_pg_tbls(bd, ctxm, entries_sp, 2); + if (rc) + return rc; + + ctxm =3D &ctx->ctx_arr[BNGE_CTX_FTQM]; + entries =3D l2_qps + 2 * (extra_qps + qp1_qps); + rc =3D bnge_setup_ctxm_pg_tbls(bd, ctxm, entries, 2); + if (rc) + return rc; + for (i =3D 0; i < ctx->tqm_fp_rings_count + 1; i++) + ena |=3D FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; + ena |=3D FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; + + rc =3D bnge_backing_store_cfg(bd, ena); + if (rc) { + dev_err(bd->dev, "Failed configuring ctx mem, rc: %d\n", rc); + return rc; + } + ctx->flags |=3D BNGE_CTX_FLAG_INITED; + + return 0; +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_rmem.h b/drivers/net/e= thernet/broadcom/bnge/bnge_rmem.h index 56de31ed6613..300f1d8268ef 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_rmem.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge_rmem.h @@ -4,6 +4,9 @@ #ifndef _BNGE_RMEM_H_ #define _BNGE_RMEM_H_ =20 +struct bnge_ctx_mem_type; +struct bnge_dev; + #define PTU_PTE_VALID 0x1UL #define PTU_PTE_LAST 0x2UL #define PTU_PTE_NEXT_TO_LAST 0x4UL @@ -27,9 +30,159 @@ struct bnge_ring_mem_info { =20 int vmem_size; void **vmem; + + struct bnge_ctx_mem_type *ctx_mem; +}; + +/* The hardware supports certain page sizes. + * Use the supported page sizes to allocate the rings. + */ +#if (PAGE_SHIFT < 12) +#define BNGE_PAGE_SHIFT 12 +#elif (PAGE_SHIFT <=3D 13) +#define BNGE_PAGE_SHIFT PAGE_SHIFT +#elif (PAGE_SHIFT < 16) +#define BNGE_PAGE_SHIFT 13 +#else +#define BNGE_PAGE_SHIFT 16 +#endif +#define BNGE_PAGE_SIZE (1 << BNGE_PAGE_SHIFT) +/* The RXBD length is 16-bit so we can only support page sizes < 64K */ +#if (PAGE_SHIFT > 15) +#define BNGE_RX_PAGE_SHIFT 15 +#else +#define BNGE_RX_PAGE_SHIFT PAGE_SHIFT +#endif +#define MAX_CTX_PAGES (BNGE_PAGE_SIZE / 8) +#define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES) + +struct bnge_ctx_pg_info { + u32 entries; + u32 nr_pages; + void *ctx_pg_arr[MAX_CTX_PAGES]; + dma_addr_t ctx_dma_arr[MAX_CTX_PAGES]; + struct bnge_ring_mem_info ring_mem; + struct bnge_ctx_pg_info **ctx_pg_tbl; +}; + +#define BNGE_MAX_TQM_SP_RINGS 1 +#define BNGE_MAX_TQM_FP_RINGS 8 +#define BNGE_MAX_TQM_RINGS \ + (BNGE_MAX_TQM_SP_RINGS + BNGE_MAX_TQM_FP_RINGS) +#define BNGE_BACKING_STORE_CFG_LEGACY_LEN 256 +#define BNGE_SET_CTX_PAGE_ATTR(attr) \ +do { \ + if (BNGE_PAGE_SIZE =3D=3D 0x2000) \ + attr =3D FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \ + else if (BNGE_PAGE_SIZE =3D=3D 0x10000) \ + attr =3D FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \ + else \ + attr =3D FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \ +} while (0) + +#define BNGE_CTX_MRAV_AV_SPLIT_ENTRY 0 + +#define BNGE_CTX_QP \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP +#define BNGE_CTX_SRQ \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ +#define BNGE_CTX_CQ \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ +#define BNGE_CTX_VNIC \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC +#define BNGE_CTX_STAT \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT +#define BNGE_CTX_STQM \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING +#define BNGE_CTX_FTQM \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING +#define BNGE_CTX_MRAV \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV +#define BNGE_CTX_TIM \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM +#define BNGE_CTX_TCK \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK +#define BNGE_CTX_RCK \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK +#define BNGE_CTX_MTQM \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING +#define BNGE_CTX_SQDBS \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW +#define BNGE_CTX_RQDBS \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW +#define BNGE_CTX_SRQDBS \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW +#define BNGE_CTX_CQDBS \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW +#define BNGE_CTX_SRT_TRACE \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE +#define BNGE_CTX_SRT2_TRACE \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE +#define BNGE_CTX_CRT_TRACE \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE +#define BNGE_CTX_CRT2_TRACE \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE +#define BNGE_CTX_RIGP0_TRACE \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE +#define BNGE_CTX_L2_HWRM_TRACE \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE +#define BNGE_CTX_ROCE_HWRM_TRACE \ + FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE + +#define BNGE_CTX_MAX (BNGE_CTX_TIM + 1) +#define BNGE_CTX_L2_MAX (BNGE_CTX_FTQM + 1) +#define BNGE_CTX_INV ((u16)-1) + +#define BNGE_CTX_V2_MAX \ + (FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE + 1) + +#define BNGE_BS_CFG_ALL_DONE \ + FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE + +struct bnge_ctx_mem_type { + u16 type; + u16 entry_size; + u32 flags; +#define BNGE_CTX_MEM_TYPE_VALID \ + FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID + u32 instance_bmap; + u8 init_value; + u8 entry_multiple; + u16 init_offset; +#define BNGE_CTX_INIT_INVALID_OFFSET 0xffff + u32 max_entries; + u32 min_entries; + u8 last:1; + u8 split_entry_cnt; +#define BNGE_MAX_SPLIT_ENTRY 4 + union { + struct { + u32 qp_l2_entries; + u32 qp_qp1_entries; + u32 qp_fast_qpmd_entries; + }; + u32 srq_l2_entries; + u32 cq_l2_entries; + u32 vnic_entries; + struct { + u32 mrav_av_entries; + u32 mrav_num_entries_units; + }; + u32 split[BNGE_MAX_SPLIT_ENTRY]; + }; + struct bnge_ctx_pg_info *pg_info; +}; + +struct bnge_ctx_mem_info { + u8 tqm_fp_rings_count; + u32 flags; +#define BNGE_CTX_FLAG_INITED 0x01 + struct bnge_ctx_mem_type ctx_arr[BNGE_CTX_V2_MAX]; }; =20 int bnge_alloc_ring(struct bnge_dev *bd, struct bnge_ring_mem_info *rmem); void bnge_free_ring(struct bnge_dev *bd, struct bnge_ring_mem_info *rmem); +int bnge_alloc_ctx_mem(struct bnge_dev *bd); +void bnge_free_ctx_mem(struct bnge_dev *bd); =20 #endif /* _BNGE_RMEM_H_ */ --=20 2.47.1 From nobody Wed Oct 8 05:39:37 2025 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34E80270EDE for ; Tue, 1 Jul 2025 09:12:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361139; cv=none; b=FwD/bDESLAmdu+JIGe/RufWCPaPtaXavI6akK1FKV+2v7uqSB/U3bWe45h6PeQWWI5Jm90HQYIAEEnBtL/XJRz9sb4uAwKcVpyQ1p9oEDEKavIms2qZ+he5MZFg4rhN54LsANdXNydbRpjO7N7eEIYJwPQbv+5mOIbTQ4oGbuG8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361139; c=relaxed/simple; bh=EmQtwDqSFOHslEHXQVIdDtRSMPY6xZ0ALdbLqObh8mI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ia6O9SgSQCfKhgisPJ8Bm7tBdzmQF2hEZdSW100mQ1NoY3K0wx7K04QzzrPJ25Vu+VreTFC1mdrm61N4KmqDSoX0WidKybugxPeTXdhW/aEDSKUOylYLtdK5KPdpka4xu1fhv4xV3qiF+hsc/b2GFxtzYIfQoX3opmTuX4OfIFg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=bkM/Owna; arc=none smtp.client-ip=209.85.216.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="bkM/Owna" Received: by mail-pj1-f53.google.com with SMTP id 98e67ed59e1d1-315f6b20cf9so3212579a91.2 for ; Tue, 01 Jul 2025 02:12:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1751361136; x=1751965936; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UDIJ0qNrkTguLLdHm/mSdkZQ4U3GcQdOpDQHe5oD26c=; b=bkM/OwnaZSurw80rK5AQQgxPYBhRGrMUKgsmy9RUgHrqfyK3X6+s/LPrHtErdqHI+5 BlWvbmlj8prFa5H68AcleCxVjCypjqImkiIWf9t8tKbAaQEpCI/sTwdmOff+sI09GGjZ j7XlW1D7VuetyaeFd8Wgy3AkAGMpNWPjVPzrE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751361136; x=1751965936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UDIJ0qNrkTguLLdHm/mSdkZQ4U3GcQdOpDQHe5oD26c=; b=nQq5sbKZ3w1gv8tujDedFMaAQfpPQxxK9m/8X5BgtDsl+mdi4HFBdbZcn4F2aRLr1E +HuoCVk+teGiKdI+8F+FJBnfzHzUreOrAVHk7oM5v4MRt1pL9aGKQLXmSOqRq31Cp8sz iUnauJ9g/L/zBLj8cHHZXq8ilxG9SCH2TOTNeECzk2MFd5xwW32pJ8FrTGFuA7fA5/UQ y609wi2RsntbYeSebY/YaPu4AFb8YNeeIjYb2VXec8j4gIla9/U9iD5+JlMxR/+VuE7u z86J56gxmJ/J/eO6K4MVjPJhebkczMxKuAQwMcRsXjbKuaPpOioeXdc3MNN8Wunhj9Lt 5lhg== X-Forwarded-Encrypted: i=1; AJvYcCU7G+2QRJIlil1VZ4RcOmFUI/I1hiO9J1yKOwFEubyVCVKa6cW9UV1xY9g0vEhnUomeRNqN4V02LTymeuw=@vger.kernel.org X-Gm-Message-State: AOJu0YwcczTxHqBD8JY27tXsKm5bqdum/FM6ZlyX+LxQJN8brGDWuyWp 1TRx4mHTSrDbi9OIfjFjImZJJz+7qzr5jcfZ+vza4HMADP+lTpHJUnJYpBd7QJEc9A== X-Gm-Gg: ASbGncu5Qxx0cudStMSw3QQi6j2dGq26prkq5BPjbhHifJEj0fK5AuCYFTCG9WuWC66 HIwsznk7CbZv9YhYkiA0wF0mf5NmOTNWa3+NCLFFmaNVEy5yYddaKb49qqpQiIF61X/wTi3/HjS WGqX+ZPwbqYaGbAUCzQqyZ29kna3Ka0Z/BSwHOCqKP9HvfIe4HXmABKhn7JgQngZ17vMr2Ps1DP cLsHp8Wfq50IGJXmv5OPPuBT/2hSOObS/DEDEDWQAAeGD+DEnv6m3NV7B/k04T8q0Duh0tZ1ps1 EvMOXTNxWEA5deYGlJYxAJUuNVNeWPtaiOemif+u0gfDw1OdzXfwe4oIsw+MCiOznZjTT4ngidj Ob8xdEfYB+pw+LYxG2aZcDdOUftjY X-Google-Smtp-Source: AGHT+IEQGaS9zljtcZSdu3RuaPx9wQrbswQ+AoTelK0x3KTJrN4mAZmtwFV1I6gRjRVo0wpqecMg8g== X-Received: by 2002:a17:90b:4b0d:b0:313:62ee:45a with SMTP id 98e67ed59e1d1-318c910a9d1mr23907155a91.13.1751361136292; Tue, 01 Jul 2025 02:12:16 -0700 (PDT) Received: from localhost.localdomain ([192.19.203.250]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b34e30201c1sm8893603a12.22.2025.07.01.02.12.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 02:12:15 -0700 (PDT) From: Vikas Gupta To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, andrew+netdev@lunn.ch, horms@kernel.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, michael.chan@broadcom.com, pavan.chebbi@broadcom.com, vsrama-krishna.nemani@broadcom.com, Vikas Gupta , Bhargava Chenna Marreddy , Rajashekar Hudumula Subject: [net-next, v3 07/10] bng_en: Add resource management support Date: Tue, 1 Jul 2025 14:35:05 +0000 Message-ID: <20250701143511.280702-8-vikas.gupta@broadcom.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250701143511.280702-1-vikas.gupta@broadcom.com> References: <20250701143511.280702-1-vikas.gupta@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Get the resources and capabilities from the firmware. Add functions to manage the resources with the firmware. These functions will help netdev reserve the resources with the firmware before registering the device in future patches. The resources and their information, such as the maximum available and reserved, are part of the members present in the bnge_hw_resc struct. The bnge_reserve_rings() function also populates the RSS table entries once the RX rings are reserved with the firmware. Signed-off-by: Vikas Gupta Reviewed-by: Bhargava Chenna Marreddy Reviewed-by: Rajashekar Hudumula --- drivers/net/ethernet/broadcom/bnge/Makefile | 3 +- drivers/net/ethernet/broadcom/bnge/bnge.h | 77 ++++ .../net/ethernet/broadcom/bnge/bnge_core.c | 5 + .../net/ethernet/broadcom/bnge/bnge_hwrm.h | 1 - .../ethernet/broadcom/bnge/bnge_hwrm_lib.c | 268 ++++++++++++++ .../ethernet/broadcom/bnge/bnge_hwrm_lib.h | 6 + .../net/ethernet/broadcom/bnge/bnge_resc.c | 328 ++++++++++++++++++ .../net/ethernet/broadcom/bnge/bnge_resc.h | 75 ++++ 8 files changed, 761 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_resc.c create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_resc.h diff --git a/drivers/net/ethernet/broadcom/bnge/Makefile b/drivers/net/ethe= rnet/broadcom/bnge/Makefile index 1144594fc3f6..10df05b6695e 100644 --- a/drivers/net/ethernet/broadcom/bnge/Makefile +++ b/drivers/net/ethernet/broadcom/bnge/Makefile @@ -6,4 +6,5 @@ bng_en-y :=3D bnge_core.o \ bnge_devlink.o \ bnge_hwrm.o \ bnge_hwrm_lib.o \ - bnge_rmem.o + bnge_rmem.o \ + bnge_resc.o diff --git a/drivers/net/ethernet/broadcom/bnge/bnge.h b/drivers/net/ethern= et/broadcom/bnge/bnge.h index 01f64a10729c..b58d8fc6f258 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge.h @@ -10,6 +10,7 @@ #include #include "../bnxt/bnxt_hsi.h" #include "bnge_rmem.h" +#include "bnge_resc.h" =20 #define DRV_VER_MAJ 1 #define DRV_VER_MIN 15 @@ -21,6 +22,12 @@ enum board_idx { BCM57708, }; =20 +struct bnge_pf_info { + u16 fw_fid; + u16 port_id; + u8 mac_addr[ETH_ALEN]; +}; + #define INVALID_HW_RING_ID ((u16)-1) =20 enum { @@ -56,10 +63,23 @@ enum { enum { BNGE_EN_ROCE_V1 =3D BIT_ULL(0), BNGE_EN_ROCE_V2 =3D BIT_ULL(1), + BNGE_EN_STRIP_VLAN =3D BIT_ULL(2), + BNGE_EN_SHARED_CHNL =3D BIT_ULL(3), }; =20 #define BNGE_EN_ROCE (BNGE_EN_ROCE_V1 | BNGE_EN_ROCE_V2) =20 +enum { + BNGE_RSS_CAP_RSS_HASH_TYPE_DELTA =3D BIT(0), + BNGE_RSS_CAP_UDP_RSS_CAP =3D BIT(1), + BNGE_RSS_CAP_NEW_RSS_CAP =3D BIT(2), + BNGE_RSS_CAP_RSS_TCAM =3D BIT(3), + BNGE_RSS_CAP_AH_V4_RSS_CAP =3D BIT(4), + BNGE_RSS_CAP_AH_V6_RSS_CAP =3D BIT(5), + BNGE_RSS_CAP_ESP_V4_RSS_CAP =3D BIT(6), + BNGE_RSS_CAP_ESP_V6_RSS_CAP =3D BIT(7), +}; + struct bnge_dev { struct device *dev; struct pci_dev *pdev; @@ -73,6 +93,9 @@ struct bnge_dev { u16 chip_num; u8 chip_rev; =20 + int db_offset; /* db_offset within db_size */ + int db_size; + /* HWRM members */ u16 hwrm_cmd_seq; u16 hwrm_cmd_kong_seq; @@ -93,6 +116,8 @@ struct bnge_dev { #define BNGE_FW_VER_CODE(maj, min, bld, rsv) \ ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv)) =20 + struct bnge_pf_info pf; + unsigned long state; #define BNGE_STATE_DRV_REGISTERED 0 =20 @@ -102,6 +127,51 @@ struct bnge_dev { struct bnge_ctx_mem_info *ctx; =20 u64 flags; + + struct bnge_hw_resc hw_resc; + + u16 tso_max_segs; + + int max_fltr; +#define BNGE_L2_FLTR_MAX_FLTR 1024 + + u32 *rss_indir_tbl; +#define BNGE_RSS_TABLE_ENTRIES 64 +#define BNGE_RSS_TABLE_SIZE (BNGE_RSS_TABLE_ENTRIES * 4) +#define BNGE_RSS_TABLE_MAX_TBL 8 +#define BNGE_MAX_RSS_TABLE_SIZE \ + (BNGE_RSS_TABLE_SIZE * BNGE_RSS_TABLE_MAX_TBL) +#define BNGE_MAX_RSS_TABLE_ENTRIES \ + (BNGE_RSS_TABLE_ENTRIES * BNGE_RSS_TABLE_MAX_TBL) + u16 rss_indir_tbl_entries; + + u32 rss_cap; + + u16 rx_nr_rings; + u16 tx_nr_rings; + u16 tx_nr_rings_per_tc; + /* Number of NQs */ + u16 nq_nr_rings; + + /* Aux device resources */ + u16 aux_num_msix; + u16 aux_num_stat_ctxs; + + u16 max_mtu; +#define BNGE_MAX_MTU 9500 + + u16 hw_ring_stats_size; +#define BNGE_NUM_RX_RING_STATS 8 +#define BNGE_NUM_TX_RING_STATS 8 +#define BNGE_NUM_TPA_RING_STATS 6 +#define BNGE_RING_STATS_SIZE \ + ((BNGE_NUM_RX_RING_STATS + BNGE_NUM_TX_RING_STATS + \ + BNGE_NUM_TPA_RING_STATS) * 8) + + u16 max_tpa_v2; +#define BNGE_SUPPORTS_TPA(bd) ((bd)->max_tpa_v2) + + u8 num_tc; }; =20 static inline bool bnge_is_roce_en(struct bnge_dev *bd) @@ -109,4 +179,11 @@ static inline bool bnge_is_roce_en(struct bnge_dev *bd) return bd->flags & BNGE_EN_ROCE; } =20 +static inline bool bnge_is_agg_reqd(struct bnge_dev *bd) +{ + return true; +} + +bool bnge_aux_registered(struct bnge_dev *bd); + #endif /* _BNGE_H_ */ diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_core.c b/drivers/net/e= thernet/broadcom/bnge/bnge_core.c index 4d7b4ef1c466..f5c3e8a061e5 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_core.c +++ b/drivers/net/ethernet/broadcom/bnge/bnge_core.c @@ -39,6 +39,11 @@ static void bnge_print_device_info(struct pci_dev *pdev,= enum board_idx idx) pcie_print_link_status(pdev); } =20 +bool bnge_aux_registered(struct bnge_dev *bd) +{ + return false; +} + static void bnge_nvm_cfg_ver_get(struct bnge_dev *bd) { struct hwrm_nvm_get_dev_info_output nvm_info; diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm.h b/drivers/net/e= thernet/broadcom/bnge/bnge_hwrm.h index c99aa8406b14..012aa4fa5aa9 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge_hwrm.h @@ -107,5 +107,4 @@ int bnge_hwrm_req_send_silent(struct bnge_dev *bd, void= *req); void bnge_hwrm_req_alloc_flags(struct bnge_dev *bd, void *req, gfp_t flags= ); void *bnge_hwrm_req_dma_slice(struct bnge_dev *bd, void *req, u32 size, dma_addr_t *dma); - #endif /* _BNGE_HWRM_H_ */ diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c b/drivers/n= et/ethernet/broadcom/bnge/bnge_hwrm_lib.c index dc69bd1461f9..ee2675776c14 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c +++ b/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c @@ -11,6 +11,7 @@ #include "bnge_hwrm.h" #include "bnge_hwrm_lib.h" #include "bnge_rmem.h" +#include "bnge_resc.h" =20 int bnge_hwrm_ver_get(struct bnge_dev *bd) { @@ -379,3 +380,270 @@ int bnge_hwrm_func_backing_store(struct bnge_dev *bd, =20 return rc; } + +static int bnge_hwrm_get_rings(struct bnge_dev *bd) +{ + struct bnge_hw_resc *hw_resc =3D &bd->hw_resc; + struct hwrm_func_qcfg_output *resp; + struct hwrm_func_qcfg_input *req; + u16 cp, stats; + u16 rx, tx; + int rc; + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_FUNC_QCFG); + if (rc) + return rc; + + req->fid =3D cpu_to_le16(0xffff); + resp =3D bnge_hwrm_req_hold(bd, req); + rc =3D bnge_hwrm_req_send(bd, req); + if (rc) { + bnge_hwrm_req_drop(bd, req); + return rc; + } + + hw_resc->resv_tx_rings =3D le16_to_cpu(resp->alloc_tx_rings); + hw_resc->resv_rx_rings =3D le16_to_cpu(resp->alloc_rx_rings); + hw_resc->resv_hw_ring_grps =3D + le32_to_cpu(resp->alloc_hw_ring_grps); + hw_resc->resv_vnics =3D le16_to_cpu(resp->alloc_vnics); + hw_resc->resv_rsscos_ctxs =3D le16_to_cpu(resp->alloc_rsscos_ctx); + cp =3D le16_to_cpu(resp->alloc_cmpl_rings); + stats =3D le16_to_cpu(resp->alloc_stat_ctx); + hw_resc->resv_irqs =3D cp; + rx =3D hw_resc->resv_rx_rings; + tx =3D hw_resc->resv_tx_rings; + if (bnge_is_agg_reqd(bd)) + rx >>=3D 1; + if (cp < (rx + tx)) { + rc =3D bnge_fix_rings_count(&rx, &tx, cp, false); + if (rc) + goto get_rings_exit; + if (bnge_is_agg_reqd(bd)) + rx <<=3D 1; + hw_resc->resv_rx_rings =3D rx; + hw_resc->resv_tx_rings =3D tx; + } + hw_resc->resv_irqs =3D le16_to_cpu(resp->alloc_msix); + hw_resc->resv_hw_ring_grps =3D rx; + hw_resc->resv_cp_rings =3D cp; + hw_resc->resv_stat_ctxs =3D stats; + +get_rings_exit: + bnge_hwrm_req_drop(bd, req); + return rc; +} + +static struct hwrm_func_cfg_input * +__bnge_hwrm_reserve_pf_rings(struct bnge_dev *bd, struct bnge_hw_rings *hw= r) +{ + struct hwrm_func_cfg_input *req; + u32 enables =3D 0; + + if (bnge_hwrm_req_init(bd, req, HWRM_FUNC_QCFG)) + return NULL; + + req->fid =3D cpu_to_le16(0xffff); + enables |=3D hwr->tx ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; + req->num_tx_rings =3D cpu_to_le16(hwr->tx); + + enables |=3D hwr->rx ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; + enables |=3D hwr->stat ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; + enables |=3D hwr->nq ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; + enables |=3D hwr->cmpl ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; + enables |=3D hwr->vnic ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; + enables |=3D hwr->rss_ctx ? FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; + + req->num_rx_rings =3D cpu_to_le16(hwr->rx); + req->num_rsscos_ctxs =3D cpu_to_le16(hwr->rss_ctx); + req->num_cmpl_rings =3D cpu_to_le16(hwr->cmpl); + req->num_msix =3D cpu_to_le16(hwr->nq); + req->num_stat_ctxs =3D cpu_to_le16(hwr->stat); + req->num_vnics =3D cpu_to_le16(hwr->vnic); + req->enables =3D cpu_to_le32(enables); + + return req; +} + +static int +bnge_hwrm_reserve_pf_rings(struct bnge_dev *bd, struct bnge_hw_rings *hwr) +{ + struct hwrm_func_cfg_input *req; + int rc; + + req =3D __bnge_hwrm_reserve_pf_rings(bd, hwr); + if (!req) + return -ENOMEM; + + if (!req->enables) { + bnge_hwrm_req_drop(bd, req); + return 0; + } + + rc =3D bnge_hwrm_req_send(bd, req); + if (rc) + return rc; + + return bnge_hwrm_get_rings(bd); +} + +int bnge_hwrm_reserve_rings(struct bnge_dev *bd, struct bnge_hw_rings *hwr) +{ + return bnge_hwrm_reserve_pf_rings(bd, hwr); +} + +int bnge_hwrm_func_qcfg(struct bnge_dev *bd) +{ + struct hwrm_func_qcfg_output *resp; + struct hwrm_func_qcfg_input *req; + int rc; + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_FUNC_QCFG); + if (rc) + return rc; + + req->fid =3D cpu_to_le16(0xffff); + resp =3D bnge_hwrm_req_hold(bd, req); + rc =3D bnge_hwrm_req_send(bd, req); + if (rc) + goto func_qcfg_exit; + + bd->max_mtu =3D le16_to_cpu(resp->max_mtu_configured); + if (!bd->max_mtu) + bd->max_mtu =3D BNGE_MAX_MTU; + + if (bd->db_size) + goto func_qcfg_exit; + + bd->db_offset =3D le16_to_cpu(resp->legacy_l2_db_size_kb) * 1024; + bd->db_size =3D PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) * + 1024); + if (!bd->db_size || bd->db_size > pci_resource_len(bd->pdev, 2) || + bd->db_size <=3D bd->db_offset) + bd->db_size =3D pci_resource_len(bd->pdev, 2); + +func_qcfg_exit: + bnge_hwrm_req_drop(bd, req); + return rc; +} + +int bnge_hwrm_func_resc_qcaps(struct bnge_dev *bd) +{ + struct hwrm_func_resource_qcaps_output *resp; + struct bnge_hw_resc *hw_resc =3D &bd->hw_resc; + struct hwrm_func_resource_qcaps_input *req; + int rc; + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_FUNC_RESOURCE_QCAPS); + if (rc) + return rc; + + req->fid =3D cpu_to_le16(0xffff); + resp =3D bnge_hwrm_req_hold(bd, req); + rc =3D bnge_hwrm_req_send_silent(bd, req); + if (rc) + goto hwrm_func_resc_qcaps_exit; + + hw_resc->max_tx_sch_inputs =3D le16_to_cpu(resp->max_tx_scheduler_inputs); + hw_resc->min_rsscos_ctxs =3D le16_to_cpu(resp->min_rsscos_ctx); + hw_resc->max_rsscos_ctxs =3D le16_to_cpu(resp->max_rsscos_ctx); + hw_resc->min_cp_rings =3D le16_to_cpu(resp->min_cmpl_rings); + hw_resc->max_cp_rings =3D le16_to_cpu(resp->max_cmpl_rings); + hw_resc->min_tx_rings =3D le16_to_cpu(resp->min_tx_rings); + hw_resc->max_tx_rings =3D le16_to_cpu(resp->max_tx_rings); + hw_resc->min_rx_rings =3D le16_to_cpu(resp->min_rx_rings); + hw_resc->max_rx_rings =3D le16_to_cpu(resp->max_rx_rings); + hw_resc->min_hw_ring_grps =3D le16_to_cpu(resp->min_hw_ring_grps); + hw_resc->max_hw_ring_grps =3D le16_to_cpu(resp->max_hw_ring_grps); + hw_resc->min_l2_ctxs =3D le16_to_cpu(resp->min_l2_ctxs); + hw_resc->max_l2_ctxs =3D le16_to_cpu(resp->max_l2_ctxs); + hw_resc->min_vnics =3D le16_to_cpu(resp->min_vnics); + hw_resc->max_vnics =3D le16_to_cpu(resp->max_vnics); + hw_resc->min_stat_ctxs =3D le16_to_cpu(resp->min_stat_ctx); + hw_resc->max_stat_ctxs =3D le16_to_cpu(resp->max_stat_ctx); + + hw_resc->max_nqs =3D le16_to_cpu(resp->max_msix); + hw_resc->max_hw_ring_grps =3D hw_resc->max_rx_rings; + +hwrm_func_resc_qcaps_exit: + bnge_hwrm_req_drop(bd, req); + return rc; +} + +int bnge_hwrm_func_qcaps(struct bnge_dev *bd) +{ + struct hwrm_func_qcaps_output *resp; + struct hwrm_func_qcaps_input *req; + struct bnge_pf_info *pf =3D &bd->pf; + u32 flags; + int rc; + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_FUNC_QCAPS); + if (rc) + return rc; + + req->fid =3D cpu_to_le16(0xffff); + resp =3D bnge_hwrm_req_hold(bd, req); + rc =3D bnge_hwrm_req_send(bd, req); + if (rc) + goto hwrm_func_qcaps_exit; + + flags =3D le32_to_cpu(resp->flags); + if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) + bd->flags |=3D BNGE_EN_ROCE_V1; + if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) + bd->flags |=3D BNGE_EN_ROCE_V2; + + pf->fw_fid =3D le16_to_cpu(resp->fid); + pf->port_id =3D le16_to_cpu(resp->port_id); + memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); + + bd->tso_max_segs =3D le16_to_cpu(resp->max_tso_segs); + +hwrm_func_qcaps_exit: + bnge_hwrm_req_drop(bd, req); + return rc; +} + +int bnge_hwrm_vnic_qcaps(struct bnge_dev *bd) +{ + struct hwrm_vnic_qcaps_output *resp; + struct hwrm_vnic_qcaps_input *req; + int rc; + + bd->hw_ring_stats_size =3D sizeof(struct ctx_hw_stats); + bd->rss_cap &=3D ~BNGE_RSS_CAP_NEW_RSS_CAP; + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_VNIC_QCAPS); + if (rc) + return rc; + + resp =3D bnge_hwrm_req_hold(bd, req); + rc =3D bnge_hwrm_req_send(bd, req); + if (!rc) { + u32 flags =3D le32_to_cpu(resp->flags); + + if (flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) + bd->fw_cap |=3D BNGE_FW_CAP_VLAN_RX_STRIP; + if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP) + bd->rss_cap |=3D BNGE_RSS_CAP_RSS_HASH_TYPE_DELTA; + if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_PROF_TCAM_MODE_ENABLED) + bd->rss_cap |=3D BNGE_RSS_CAP_RSS_TCAM; + bd->max_tpa_v2 =3D le16_to_cpu(resp->max_aggs_supported); + if (bd->max_tpa_v2) + bd->hw_ring_stats_size =3D BNGE_RING_STATS_SIZE; + if (flags & VNIC_QCAPS_RESP_FLAGS_HW_TUNNEL_TPA_CAP) + bd->fw_cap |=3D BNGE_FW_CAP_VNIC_TUNNEL_TPA; + if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP) + bd->rss_cap |=3D BNGE_RSS_CAP_AH_V4_RSS_CAP; + if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP) + bd->rss_cap |=3D BNGE_RSS_CAP_AH_V6_RSS_CAP; + if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP) + bd->rss_cap |=3D BNGE_RSS_CAP_ESP_V4_RSS_CAP; + if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP) + bd->rss_cap |=3D BNGE_RSS_CAP_ESP_V6_RSS_CAP; + } + bnge_hwrm_req_drop(bd, req); + + return rc; +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.h b/drivers/n= et/ethernet/broadcom/bnge/bnge_hwrm_lib.h index c04291d74bf0..59ec1899879a 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.h @@ -16,5 +16,11 @@ int bnge_hwrm_func_backing_store(struct bnge_dev *bd, struct bnge_ctx_mem_type *ctxm, bool last); int bnge_hwrm_func_backing_store_qcaps(struct bnge_dev *bd); +int bnge_hwrm_reserve_rings(struct bnge_dev *bd, + struct bnge_hw_rings *hwr); +int bnge_hwrm_func_qcaps(struct bnge_dev *bd); +int bnge_hwrm_vnic_qcaps(struct bnge_dev *bd); +int bnge_hwrm_func_qcfg(struct bnge_dev *bd); +int bnge_hwrm_func_resc_qcaps(struct bnge_dev *bd); =20 #endif /* _BNGE_HWRM_LIB_H_ */ diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_resc.c b/drivers/net/e= thernet/broadcom/bnge/bnge_resc.c new file mode 100644 index 000000000000..68e094474822 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_resc.c @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2025 Broadcom. + +#include +#include +#include +#include + +#include "bnge.h" +#include "bnge_hwrm.h" +#include "bnge_hwrm_lib.h" +#include "bnge_resc.h" + +static u16 bnge_num_tx_to_cp(struct bnge_dev *bd, u16 tx) +{ + u16 tcs =3D bd->num_tc; + + if (!tcs) + tcs =3D 1; + + return tx / tcs; +} + +static u16 bnge_get_max_func_irqs(struct bnge_dev *bd) +{ + struct bnge_hw_resc *hw_resc =3D &bd->hw_resc; + + return min_t(u16, hw_resc->max_irqs, hw_resc->max_nqs); +} + +static int bnge_aux_get_dflt_msix(struct bnge_dev *bd) +{ + int roce_msix =3D BNGE_MAX_ROCE_MSIX; + + return min_t(int, roce_msix, num_online_cpus() + 1); +} + +static u16 bnge_aux_get_msix(struct bnge_dev *bd) +{ + if (bnge_is_roce_en(bd)) + return bd->aux_num_msix; + + return 0; +} + +static void bnge_aux_set_msix_num(struct bnge_dev *bd, u16 num) +{ + if (bnge_is_roce_en(bd)) + bd->aux_num_msix =3D num; +} + +static u16 bnge_aux_get_stat_ctxs(struct bnge_dev *bd) +{ + if (bnge_is_roce_en(bd)) + return bd->aux_num_stat_ctxs; + + return 0; +} + +static void bnge_aux_set_stat_ctxs(struct bnge_dev *bd, u16 num_aux_ctx) +{ + if (bnge_is_roce_en(bd)) + bd->aux_num_stat_ctxs =3D num_aux_ctx; +} + +static u16 bnge_func_stat_ctxs_demand(struct bnge_dev *bd) +{ + return bd->nq_nr_rings + bnge_aux_get_stat_ctxs(bd); +} + +static u16 bnge_nqs_demand(struct bnge_dev *bd) +{ + return bd->nq_nr_rings + bnge_aux_get_msix(bd); +} + +static u16 bnge_cprs_demand(struct bnge_dev *bd) +{ + return bd->tx_nr_rings + bd->rx_nr_rings; +} + +static u16 bnge_get_avail_msix(struct bnge_dev *bd, int num) +{ + u16 max_irq =3D bnge_get_max_func_irqs(bd); + u16 total_demand =3D bd->nq_nr_rings + num; + + if (max_irq < total_demand) { + num =3D max_irq - bd->nq_nr_rings; + if (num <=3D 0) + return 0; + } + + return num; +} + +static u16 bnge_num_cp_to_tx(struct bnge_dev *bd, u16 tx_chunks) +{ + return tx_chunks * bd->num_tc; +} + +int bnge_fix_rings_count(u16 *rx, u16 *tx, u16 max, bool shared) +{ + u16 _rx =3D *rx, _tx =3D *tx; + + if (shared) { + *rx =3D min_t(u16, _rx, max); + *tx =3D min_t(u16, _tx, max); + } else { + if (max < 2) + return -ENOMEM; + while (_rx + _tx > max) { + if (_rx > _tx && _rx > 1) + _rx--; + else if (_tx > 1) + _tx--; + } + *rx =3D _rx; + *tx =3D _tx; + } + + return 0; +} + +static int bnge_adjust_rings(struct bnge_dev *bd, u16 *rx, + u16 *tx, u16 max_nq, bool sh) +{ + u16 tx_chunks =3D bnge_num_tx_to_cp(bd, *tx); + + if (tx_chunks !=3D *tx) { + u16 tx_saved =3D tx_chunks, rc; + + rc =3D bnge_fix_rings_count(rx, &tx_chunks, max_nq, sh); + if (rc) + return rc; + if (tx_chunks !=3D tx_saved) + *tx =3D bnge_num_cp_to_tx(bd, tx_chunks); + return 0; + } + + return bnge_fix_rings_count(rx, tx, max_nq, sh); +} + +static int bnge_cal_nr_rss_ctxs(u16 rx_rings) +{ + if (!rx_rings) + return 0; + + return bnge_adjust_pow_two(rx_rings - 1, + BNGE_RSS_TABLE_ENTRIES); +} + +static u16 bnge_rss_ctxs_in_use(struct bnge_dev *bd, + struct bnge_hw_rings *hwr) +{ + return bnge_cal_nr_rss_ctxs(hwr->grp); +} + +static u16 bnge_get_total_vnics(struct bnge_dev *bd, u16 rx_rings) +{ + return 1; +} + +static u32 bnge_get_rxfh_indir_size(struct bnge_dev *bd) +{ + return bnge_cal_nr_rss_ctxs(bd->rx_nr_rings) * + BNGE_RSS_TABLE_ENTRIES; +} + +static void bnge_set_dflt_rss_indir_tbl(struct bnge_dev *bd) +{ + u16 max_entries, pad; + u32 *rss_indir_tbl; + int i; + + max_entries =3D bnge_get_rxfh_indir_size(bd); + rss_indir_tbl =3D &bd->rss_indir_tbl[0]; + + for (i =3D 0; i < max_entries; i++) + rss_indir_tbl[i] =3D ethtool_rxfh_indir_default(i, + bd->rx_nr_rings); + + pad =3D bd->rss_indir_tbl_entries - max_entries; + if (pad) + memset(&rss_indir_tbl[i], 0, pad * sizeof(*rss_indir_tbl)); +} + +static void bnge_copy_reserved_rings(struct bnge_dev *bd, + struct bnge_hw_rings *hwr) +{ + struct bnge_hw_resc *hw_resc =3D &bd->hw_resc; + + hwr->tx =3D hw_resc->resv_tx_rings; + hwr->rx =3D hw_resc->resv_rx_rings; + hwr->nq =3D hw_resc->resv_irqs; + hwr->cmpl =3D hw_resc->resv_cp_rings; + hwr->grp =3D hw_resc->resv_hw_ring_grps; + hwr->vnic =3D hw_resc->resv_vnics; + hwr->stat =3D hw_resc->resv_stat_ctxs; + hwr->rss_ctx =3D hw_resc->resv_rsscos_ctxs; +} + +static bool bnge_rings_ok(struct bnge_hw_rings *hwr) +{ + return hwr->tx && hwr->rx && hwr->nq && hwr->grp && hwr->vnic && + hwr->stat && hwr->cmpl; +} + +static bool bnge_need_reserve_rings(struct bnge_dev *bd) +{ + struct bnge_hw_resc *hw_resc =3D &bd->hw_resc; + u16 cprs =3D bnge_cprs_demand(bd); + u16 rx =3D bd->rx_nr_rings, stat; + u16 nqs =3D bnge_nqs_demand(bd); + u16 vnic; + + if (hw_resc->resv_tx_rings !=3D bd->tx_nr_rings) + return true; + + vnic =3D bnge_get_total_vnics(bd, rx); + + if (bnge_is_agg_reqd(bd)) + rx <<=3D 1; + stat =3D bnge_func_stat_ctxs_demand(bd); + if (hw_resc->resv_rx_rings !=3D rx || hw_resc->resv_cp_rings !=3D cprs || + hw_resc->resv_vnics !=3D vnic || hw_resc->resv_stat_ctxs !=3D stat) + return true; + if (hw_resc->resv_irqs !=3D nqs) + return true; + + return false; +} + +int bnge_reserve_rings(struct bnge_dev *bd) +{ + u16 aux_dflt_msix =3D bnge_aux_get_dflt_msix(bd); + struct bnge_hw_rings hwr =3D {0}; + u16 rx_rings, old_rx_rings; + u16 nq =3D bd->nq_nr_rings; + u16 aux_msix =3D 0; + bool sh =3D false; + u16 tx_cp; + int rc; + + if (!bnge_need_reserve_rings(bd)) + return 0; + + if (!bnge_aux_registered(bd)) { + aux_msix =3D bnge_get_avail_msix(bd, aux_dflt_msix); + if (!aux_msix) + bnge_aux_set_stat_ctxs(bd, 0); + + if (aux_msix > aux_dflt_msix) + aux_msix =3D aux_dflt_msix; + hwr.nq =3D nq + aux_msix; + } else { + hwr.nq =3D bnge_nqs_demand(bd); + } + + hwr.tx =3D bd->tx_nr_rings; + hwr.rx =3D bd->rx_nr_rings; + if (bd->flags & BNGE_EN_SHARED_CHNL) + sh =3D true; + hwr.cmpl =3D hwr.rx + hwr.tx; + + hwr.vnic =3D bnge_get_total_vnics(bd, hwr.rx); + + if (bnge_is_agg_reqd(bd)) + hwr.rx <<=3D 1; + hwr.grp =3D bd->rx_nr_rings; + hwr.rss_ctx =3D bnge_rss_ctxs_in_use(bd, &hwr); + hwr.stat =3D bnge_func_stat_ctxs_demand(bd); + old_rx_rings =3D bd->hw_resc.resv_rx_rings; + + rc =3D bnge_hwrm_reserve_rings(bd, &hwr); + if (rc) + return rc; + + bnge_copy_reserved_rings(bd, &hwr); + + rx_rings =3D hwr.rx; + if (bnge_is_agg_reqd(bd)) { + if (hwr.rx >=3D 2) + rx_rings =3D hwr.rx >> 1; + else + return -ENOMEM; + } + + rx_rings =3D min_t(u16, rx_rings, hwr.grp); + hwr.nq =3D min_t(u16, hwr.nq, bd->nq_nr_rings); + if (hwr.stat > bnge_aux_get_stat_ctxs(bd)) + hwr.stat -=3D bnge_aux_get_stat_ctxs(bd); + hwr.nq =3D min_t(u16, hwr.nq, hwr.stat); + + /* Adjust the rings */ + rc =3D bnge_adjust_rings(bd, &rx_rings, &hwr.tx, hwr.nq, sh); + if (bnge_is_agg_reqd(bd)) + hwr.rx =3D rx_rings << 1; + tx_cp =3D hwr.tx; + hwr.nq =3D sh ? max_t(u16, tx_cp, rx_rings) : tx_cp + rx_rings; + bd->tx_nr_rings =3D hwr.tx; + + if (rx_rings !=3D bd->rx_nr_rings) + dev_warn(bd->dev, "RX rings resv reduced to %d than earlier %d requested= \n", + rx_rings, bd->rx_nr_rings); + + bd->rx_nr_rings =3D rx_rings; + bd->nq_nr_rings =3D hwr.nq; + + if (!bnge_rings_ok(&hwr)) + return -ENOMEM; + + if (old_rx_rings !=3D bd->hw_resc.resv_rx_rings) + bnge_set_dflt_rss_indir_tbl(bd); + + if (!bnge_aux_registered(bd)) { + u16 resv_msix, resv_ctx, aux_ctxs; + struct bnge_hw_resc *hw_resc; + + hw_resc =3D &bd->hw_resc; + resv_msix =3D hw_resc->resv_irqs - bd->nq_nr_rings; + aux_msix =3D min_t(u16, resv_msix, aux_msix); + bnge_aux_set_msix_num(bd, aux_msix); + resv_ctx =3D hw_resc->resv_stat_ctxs - bd->nq_nr_rings; + aux_ctxs =3D min(resv_ctx, bnge_aux_get_stat_ctxs(bd)); + bnge_aux_set_stat_ctxs(bd, aux_ctxs); + } + + return rc; +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_resc.h b/drivers/net/e= thernet/broadcom/bnge/bnge_resc.h new file mode 100644 index 000000000000..c6cef514588f --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_resc.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2025 Broadcom */ + +#ifndef _BNGE_RESC_H_ +#define _BNGE_RESC_H_ + +struct bnge_hw_resc { + u16 min_rsscos_ctxs; + u16 max_rsscos_ctxs; + u16 resv_rsscos_ctxs; + u16 min_cp_rings; + u16 max_cp_rings; + u16 resv_cp_rings; + u16 min_tx_rings; + u16 max_tx_rings; + u16 resv_tx_rings; + u16 max_tx_sch_inputs; + u16 min_rx_rings; + u16 max_rx_rings; + u16 resv_rx_rings; + u16 min_hw_ring_grps; + u16 max_hw_ring_grps; + u16 resv_hw_ring_grps; + u16 min_l2_ctxs; + u16 max_l2_ctxs; + u16 min_vnics; + u16 max_vnics; + u16 resv_vnics; + u16 min_stat_ctxs; + u16 max_stat_ctxs; + u16 resv_stat_ctxs; + u16 max_nqs; + u16 max_irqs; + u16 resv_irqs; + u32 max_encap_records; + u32 max_decap_records; + u32 max_tx_em_flows; + u32 max_tx_wm_flows; + u32 max_rx_em_flows; + u32 max_rx_wm_flows; +}; + +struct bnge_hw_rings { + u16 tx; + u16 rx; + u16 grp; + u16 nq; + u16 cmpl; + u16 stat; + u16 vnic; + u16 rss_ctx; +}; + +int bnge_reserve_rings(struct bnge_dev *bd); +int bnge_fix_rings_count(u16 *rx, u16 *tx, u16 max, bool shared); + +static inline u32 +bnge_adjust_pow_two(u32 total_ent, u16 ent_per_blk) +{ + u32 blks =3D total_ent / ent_per_blk; + + if (blks =3D=3D 0 || blks =3D=3D 1) + return ++blks; + + if (!is_power_of_2(blks)) + blks =3D roundup_pow_of_two(blks); + + return blks; +} + +#define BNGE_MAX_ROCE_MSIX 64 +#define BNGE_MIN_ROCE_CP_RINGS 2 +#define BNGE_MIN_ROCE_STAT_CTXS 1 + +#endif /* _BNGE_RESC_H_ */ --=20 2.47.1 From nobody Wed Oct 8 05:39:37 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 570E026D4E8 for ; Tue, 1 Jul 2025 09:12:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361142; cv=none; b=jyJx72KI1qUsFbTvCi0+TZy5Pp3e727jiZMxMGx8+xHjt2B/vF0gnkTL7TQVol2zW0WS8dfDS7aveEnP2YIX/8An6Usrx2mV08XiWoyhEUxBaFc2dBD4j1b+pm7xhbYjkDWorsZo7vCQd2BmhoBJN/rwkmhQjh+bvob3APwlig4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361142; c=relaxed/simple; bh=mpzqWhT1I+6uw/XL0NOgYZhIQ3NUjVGpw47BxenLilM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eeAriDFw6/IJuFVE8Ii/U+Rlmj2UDxF0e5rUY5sUJuPqQgOXxMB+/cnGL2Leisn3NfNdRJA3MMUJXUIm+4RqatWPFXQN95U8hnoKv2x0s7Chk61YwivNAMZ2o/bALQAI0odc1hyD9/qeyzrSL8fmYIgkkH0/Cdf7tptpB8/cLdE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=IhqVGaLU; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="IhqVGaLU" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-2366e5e4dbaso53502435ad.1 for ; Tue, 01 Jul 2025 02:12:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1751361141; x=1751965941; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gz5DxFLcNcY/JgVYAsCkaQXBb/kJxxrffxVb/EKMKLE=; b=IhqVGaLUgPXpL8g1T3MZxH8WXmv5o0OyaGG4mOI/lSSJFV2n2GpKEdGIDW2YPzYtFx 1Unczt5BjPiWnKzdZYk23GOMt0tvmVhnupAwZtfyoGpNfFICpIWhXBjTy06Jf8+U8pbs Gki5GC8HqKvT6GCGFCx83axLZgnmpDhOn7liM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751361141; x=1751965941; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gz5DxFLcNcY/JgVYAsCkaQXBb/kJxxrffxVb/EKMKLE=; b=L7epkHQb4Y4EYJfgYVSV+gKDX45IlsjMdsuiBXr1cdFEt4SndpHRJbBtPoiiJvEmve xPQ7fmixKST2ADomiYbiOvWzedEF0XDTkHZZCRGaux2zivaAbBmQJiGWrBE+O1sS0VFL NCt7cF5IFyUZY17yybBTtePTvEGJ1vn9CmCTCxkLHh9ikw7YSsrIh9oX+LyFFIeR2or9 lF468YLXQ7DGX7Jc2v7TNPYb4TJir3dR87Xp/O9NClbsgDtrc0dL/dQBeNGQQBn3+bsn s7loFXIBPKUKuTHD1glx6a2BfW2QyNJhxehPkVuHDoBahAlZ8Jqt+MN+DJhc943rJV1S QJ6w== X-Forwarded-Encrypted: i=1; AJvYcCXcxwiiHVz/pzhaO7JUDRXd3poJmoLavdXKGo95l1tZ4ZTfbVS5QJk8IdFeLK5BwmZ1kl1ppHFNp4WhlQs=@vger.kernel.org X-Gm-Message-State: AOJu0YzeKr1NUDu75fVc7UC3xqWfyISCLZwuY6lYYsUTxmGtgg9fdCSO gYddoHquuG8liuMKxzMfnF4NoqeeqwIaV/xW0/jrG7+bxbaW66sphTVsU/U2zIg1Kw== X-Gm-Gg: ASbGncvvXjrj97QcV63sGaZ3ujzZuvybgSe9oQsTw/lW8c56V6xHOjjGGHNhZjbKPxf WV5p6JP5nqKJ7QJEDrbYwsXEO4IpvHnl+R3rk6sDAFUyV/w2DIebO/jeeIYxzTfyT0u4Q1k4kc0 Ag1jz2UYGoUUKDZ2JaTjvaF/B3nFLj4lY9Y/Fzh4f/OqWPvZFfO2RZeJTL4sAkpzAZXMqWTOFig luI1cascGTfmmgZTv/8zJxzHP1IIdmmJhkvEC/9vyQEoK/zI/RxAzBOkEFSLSDRNV03+oj33LOe CksODoPYrXELxL+yj3VaXHMoj4aL/CocK7qiQTLYklbOM/fnHvZA4GcRcR3lOqTItpuVb5WXw8I zmZoCMCDBfwIBku1SSRbe2zLHnyghjMG1lRkWzT4= X-Google-Smtp-Source: AGHT+IGYBGgecd8dWYPIr5lPRMgzOqoHDpBa6fI9mi67gnjdbRnBBRPCFnVNS888pXR+GeNceSOnog== X-Received: by 2002:a17:903:3a83:b0:234:5ea1:6041 with SMTP id d9443c01a7336-23b354bb8b8mr47396115ad.10.1751361140627; Tue, 01 Jul 2025 02:12:20 -0700 (PDT) Received: from localhost.localdomain ([192.19.203.250]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b34e30201c1sm8893603a12.22.2025.07.01.02.12.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 02:12:20 -0700 (PDT) From: Vikas Gupta To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, andrew+netdev@lunn.ch, horms@kernel.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, michael.chan@broadcom.com, pavan.chebbi@broadcom.com, vsrama-krishna.nemani@broadcom.com, Vikas Gupta , Bhargava Chenna Marreddy , Rajashekar Hudumula Subject: [net-next, v3 08/10] bng_en: Add irq allocation support Date: Tue, 1 Jul 2025 14:35:06 +0000 Message-ID: <20250701143511.280702-9-vikas.gupta@broadcom.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250701143511.280702-1-vikas.gupta@broadcom.com> References: <20250701143511.280702-1-vikas.gupta@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add irq allocation functions. This will help to allocate IRQs to both netdev and RoCE aux devices. Signed-off-by: Vikas Gupta Reviewed-by: Bhargava Chenna Marreddy Reviewed-by: Rajashekar Hudumula --- drivers/net/ethernet/broadcom/bnge/bnge.h | 3 + .../net/ethernet/broadcom/bnge/bnge_resc.c | 69 +++++++++++++++++++ .../net/ethernet/broadcom/bnge/bnge_resc.h | 13 ++++ 3 files changed, 85 insertions(+) diff --git a/drivers/net/ethernet/broadcom/bnge/bnge.h b/drivers/net/ethern= et/broadcom/bnge/bnge.h index b58d8fc6f258..3c161b1a9b62 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge.h @@ -172,6 +172,9 @@ struct bnge_dev { #define BNGE_SUPPORTS_TPA(bd) ((bd)->max_tpa_v2) =20 u8 num_tc; + + struct bnge_irq *irq_tbl; + u16 irqs_acquired; }; =20 static inline bool bnge_is_roce_en(struct bnge_dev *bd) diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_resc.c b/drivers/net/e= thernet/broadcom/bnge/bnge_resc.c index 68e094474822..0e67a0001677 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_resc.c +++ b/drivers/net/ethernet/broadcom/bnge/bnge_resc.c @@ -326,3 +326,72 @@ int bnge_reserve_rings(struct bnge_dev *bd) =20 return rc; } + +int bnge_alloc_irqs(struct bnge_dev *bd) +{ + u16 aux_msix, tx_cp, num_entries; + int i, irqs_demand, rc; + u16 max, min =3D 1; + + irqs_demand =3D bnge_nqs_demand(bd); + max =3D bnge_get_max_func_irqs(bd); + if (irqs_demand > max) + irqs_demand =3D max; + + if (!(bd->flags & BNGE_EN_SHARED_CHNL)) + min =3D 2; + + irqs_demand =3D pci_alloc_irq_vectors(bd->pdev, min, irqs_demand, + PCI_IRQ_MSIX); + aux_msix =3D bnge_aux_get_msix(bd); + if (irqs_demand < 0 || irqs_demand < aux_msix) { + rc =3D -ENODEV; + goto err_free_irqs; + } + + num_entries =3D irqs_demand; + if (pci_msix_can_alloc_dyn(bd->pdev)) + num_entries =3D max; + bd->irq_tbl =3D kcalloc(num_entries, sizeof(*bd->irq_tbl), GFP_KERNEL); + if (!bd->irq_tbl) { + rc =3D -ENOMEM; + goto err_free_irqs; + } + + for (i =3D 0; i < irqs_demand; i++) + bd->irq_tbl[i].vector =3D pci_irq_vector(bd->pdev, i); + + bd->irqs_acquired =3D irqs_demand; + /* Reduce rings based upon num of vectors allocated. + * We dont need to consider NQs as they have been calculated + * and must be more than irqs_demand. + */ + rc =3D bnge_adjust_rings(bd, &bd->rx_nr_rings, + &bd->tx_nr_rings, + irqs_demand - aux_msix, min =3D=3D 1); + if (rc) + goto err_free_irqs; + + tx_cp =3D bnge_num_tx_to_cp(bd, bd->tx_nr_rings); + bd->nq_nr_rings =3D (min =3D=3D 1) ? + max_t(u16, tx_cp, bd->rx_nr_rings) : + tx_cp + bd->rx_nr_rings; + + /* Readjust tx_nr_rings_per_tc */ + if (!bd->num_tc) + bd->tx_nr_rings_per_tc =3D bd->tx_nr_rings; + + return 0; + +err_free_irqs: + dev_err(bd->dev, "Failed to allocate IRQs err =3D %d\n", rc); + bnge_free_irqs(bd); + return rc; +} + +void bnge_free_irqs(struct bnge_dev *bd) +{ + pci_free_irq_vectors(bd->pdev); + kfree(bd->irq_tbl); + bd->irq_tbl =3D NULL; +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_resc.h b/drivers/net/e= thernet/broadcom/bnge/bnge_resc.h index c6cef514588f..23db93e03787 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_resc.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge_resc.h @@ -51,8 +51,21 @@ struct bnge_hw_rings { u16 rss_ctx; }; =20 +/* "TXRX", 2 hypens, plus maximum integer */ +#define BNGE_IRQ_NAME_EXTRA 17 +struct bnge_irq { + irq_handler_t handler; + unsigned int vector; + u8 requested:1; + u8 have_cpumask:1; + char name[IFNAMSIZ + BNGE_IRQ_NAME_EXTRA]; + cpumask_var_t cpu_mask; +}; + int bnge_reserve_rings(struct bnge_dev *bd); int bnge_fix_rings_count(u16 *rx, u16 *tx, u16 max, bool shared); +int bnge_alloc_irqs(struct bnge_dev *bd); +void bnge_free_irqs(struct bnge_dev *bd); =20 static inline u32 bnge_adjust_pow_two(u32 total_ent, u16 ent_per_blk) --=20 2.47.1 From nobody Wed Oct 8 05:39:37 2025 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E1772727EB for ; Tue, 1 Jul 2025 09:12:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361147; cv=none; b=fp9JrGx79ArpIxmrJcASlYai50cUGlE+ePsxGHVTCYQCevdRKW2SYjy9D1qT4J/D6VAqQtgMizwOSDqa/9zWbN/SFNRwJ+YVC4oDVESmR0rfiwD5Z85yEJJudnc35MYEmDifu9+cvKJRCHS3ydgxYBYJ8g5AzzpsSOy796pyvqI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361147; c=relaxed/simple; bh=c2sVCcXckcXgO+k0SV0iQuABkheQADIwPm0F+1Rlm6A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oXW7MOkGFRCeb6gJjdH15gjcvSjyT7eHS8Hlv3OTuIPAOsSGHDZxCES/mlVh3Gd8C5Qoob1dYMU8cXghMBhNUsQJZ8L5lSTXld94eVSqsr/JMnVn3spYl/7YiDI6XAR+d0BYo+4409e61Kb+/R3mecsWLrKUkUP4JjVOxjYfzVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=JED2epyY; arc=none smtp.client-ip=209.85.210.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="JED2epyY" Received: by mail-pf1-f169.google.com with SMTP id d2e1a72fcca58-7399a2dc13fso3650555b3a.2 for ; Tue, 01 Jul 2025 02:12:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1751361145; x=1751965945; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E3eT99weMxmyOdnkqjbt0/sw5f3/m7CyQJ070y3n9BI=; b=JED2epyYujgCgQZ4rsEONRN0u4FEsEJQ4ffL4LU84+7dyFtGWqhAfzeiABbS0U+QT4 AJtU1kHuzTqOL1Pwf5e65HAv9OtiZXryDFyhulRtEhsqCtHKw4r4Yf0esIfNYyLqqXS2 Udr092cl6y9NBext1DLf7qGI7bH0H338OCv/8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751361145; x=1751965945; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E3eT99weMxmyOdnkqjbt0/sw5f3/m7CyQJ070y3n9BI=; b=uCxFWbc4YDQhHnJnT0C/A3B/f7nzJoj+dzy3fB5cS8ZSeio1Anob70sognrd4D0GuC ybsdIq3gPTnsYUD15cUlseAbXTsWmiOCcxFgwcpHSPN1QUaxzkl60DDHtxH4RaqEi6AK MeJ9544StPbmifixQGV1qYPuTtdDjfFptXFK+oCL2GP+hpqDlPCSYhTcU5n47FdyiCGp sC0qKQ99OGQkRPVLNPb4bsT3HDCb7KQCtx8BZpi82OrNRuOMi2W4Oo0Y4VGua0Ih6Dlh +nJfGnFpVk8lchY+pZZVntsj6eCEMRbtXpBUuNHRvQ+QY3ZgVmTscidd4NBrSeZedtWi fzKQ== X-Forwarded-Encrypted: i=1; AJvYcCX3AJLn9wli7tjTPBfUA0ituYpAsDiL5YGmBJulGkpCH3lmGnvnSWV6wKWyaJAWLt5vYKQUwqymql6kuYc=@vger.kernel.org X-Gm-Message-State: AOJu0Ywq/vUthA0gOKeaybu2a2XB3v75Bb1x79VRGOqGwEkpeKcu9sLC JxPak1S1JMK2JUUSS89NQ7wcw/9x9FgevWtJdk0+c9TCAWX9au2IUr+pPsldbl+gVA== X-Gm-Gg: ASbGncvcVNdeq/wFDaO7yF+5OnYn1ZWX6I++duknumkQeud2dbX556pkTH323710lxu jnAmyFqHtlRix+i9/C6Ha+iIaikKF+wsfR+Zz62slGRDKzYSYiZti4oOAy84CI0kibJhO3rWfJH KvMTpuNkWtGl+mub8XGDX6e4wvg0QPWMqcxRA/c12ia7iDNx9xdv+CvByyJu2EgGHge6aXmCYM1 aEpqnwGZR66DLJPpcBlow8EIKtPJwC+wGF6Xe0ZlC5YMYTaWLYZ6fUMIkTyqfA080qZaW6s8M9T bbbV2ynWwMDvLRVStl4l5AhmZvGdjvCv3uMuPGFgVj4Uwzrj1pR56aiUFp3tCyD85cGJwcAlX/p MJp1j5kwF+cUa4QhXxb3Em87U5Xufy93FC00LFH4= X-Google-Smtp-Source: AGHT+IGRUJfZZduPHTagR4volcDuewrfzuCvht7FohXzYsq8zmvBaf7+ZxLZc69FfGzm613sRSSX/w== X-Received: by 2002:a05:6a21:6711:b0:215:e60b:3bcf with SMTP id adf61e73a8af0-220a169c953mr28069483637.30.1751361144857; Tue, 01 Jul 2025 02:12:24 -0700 (PDT) Received: from localhost.localdomain ([192.19.203.250]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b34e30201c1sm8893603a12.22.2025.07.01.02.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 02:12:24 -0700 (PDT) From: Vikas Gupta To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, andrew+netdev@lunn.ch, horms@kernel.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, michael.chan@broadcom.com, pavan.chebbi@broadcom.com, vsrama-krishna.nemani@broadcom.com, Vikas Gupta , Bhargava Chenna Marreddy , Rajashekar Hudumula Subject: [net-next, v3 09/10] bng_en: Initialize default configuration Date: Tue, 1 Jul 2025 14:35:07 +0000 Message-ID: <20250701143511.280702-10-vikas.gupta@broadcom.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250701143511.280702-1-vikas.gupta@broadcom.com> References: <20250701143511.280702-1-vikas.gupta@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Query resources from the firmware and, based on the availability of resources, initialize the default settings. The default settings include: 1. Rings and other resource reservations with the firmware. This ensures that resources are reserved before network and auxiliary devices are created. 2. Mapping the BAR, which helps access doorbells since its size is known after querying the firmware. 3. Retrieving the TCs and hardware CoS queue mappings. Signed-off-by: Vikas Gupta Reviewed-by: Bhargava Chenna Marreddy Reviewed-by: Rajashekar Hudumula --- drivers/net/ethernet/broadcom/bnge/bnge.h | 14 ++ .../net/ethernet/broadcom/bnge/bnge_core.c | 123 +++++++++++ .../ethernet/broadcom/bnge/bnge_hwrm_lib.c | 54 +++++ .../ethernet/broadcom/bnge/bnge_hwrm_lib.h | 1 + .../net/ethernet/broadcom/bnge/bnge_resc.c | 208 ++++++++++++++++++ .../net/ethernet/broadcom/bnge/bnge_resc.h | 3 + 6 files changed, 403 insertions(+) diff --git a/drivers/net/ethernet/broadcom/bnge/bnge.h b/drivers/net/ethern= et/broadcom/bnge/bnge.h index 3c161b1a9b62..cef66c1e9006 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge.h @@ -80,6 +80,12 @@ enum { BNGE_RSS_CAP_ESP_V6_RSS_CAP =3D BIT(7), }; =20 +#define BNGE_MAX_QUEUE 8 +struct bnge_queue_info { + u8 queue_id; + u8 queue_profile; +}; + struct bnge_dev { struct device *dev; struct pci_dev *pdev; @@ -89,6 +95,7 @@ struct bnge_dev { char board_serialno[BNGE_VPD_FLD_LEN]; =20 void __iomem *bar0; + void __iomem *bar1; =20 u16 chip_num; u8 chip_rev; @@ -172,6 +179,13 @@ struct bnge_dev { #define BNGE_SUPPORTS_TPA(bd) ((bd)->max_tpa_v2) =20 u8 num_tc; + u8 max_tc; + u8 max_lltc; /* lossless TCs */ + struct bnge_queue_info q_info[BNGE_MAX_QUEUE]; + u8 tc_to_qidx[BNGE_MAX_QUEUE]; + u8 q_ids[BNGE_MAX_QUEUE]; + u8 max_q; + u8 port_count; =20 struct bnge_irq *irq_tbl; u16 irqs_acquired; diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_core.c b/drivers/net/e= thernet/broadcom/bnge/bnge_core.c index f5c3e8a061e5..24babc8b9d35 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_core.c +++ b/drivers/net/ethernet/broadcom/bnge/bnge_core.c @@ -54,9 +54,46 @@ static void bnge_nvm_cfg_ver_get(struct bnge_dev *bd) nvm_info.nvm_cfg_ver_upd); } =20 +static int bnge_func_qcaps(struct bnge_dev *bd) +{ + int rc; + + rc =3D bnge_hwrm_func_qcaps(bd); + if (rc) + return rc; + + rc =3D bnge_hwrm_queue_qportcfg(bd); + if (rc) { + dev_err(bd->dev, "query qportcfg failure rc: %d\n", rc); + return rc; + } + + rc =3D bnge_hwrm_func_resc_qcaps(bd); + if (rc) { + dev_err(bd->dev, "query resc caps failure rc: %d\n", rc); + return rc; + } + + rc =3D bnge_hwrm_func_qcfg(bd); + if (rc) { + dev_err(bd->dev, "query config failure rc: %d\n", rc); + return rc; + } + + rc =3D bnge_hwrm_vnic_qcaps(bd); + if (rc) { + dev_err(bd->dev, "vnic caps failure rc: %d\n", rc); + return rc; + } + + return 0; +} + static void bnge_fw_unregister_dev(struct bnge_dev *bd) { + /* ctx mem free after unrgtr only */ bnge_hwrm_func_drv_unrgtr(bd); + bnge_free_ctx_mem(bd); } =20 static int bnge_fw_register_dev(struct bnge_dev *bd) @@ -86,7 +123,25 @@ static int bnge_fw_register_dev(struct bnge_dev *bd) return rc; } =20 + rc =3D bnge_alloc_ctx_mem(bd); + if (rc) { + dev_err(bd->dev, "Failed to allocate ctx mem rc: %d\n", rc); + goto err_func_unrgtr; + } + + /* Get the resources and configuration from firmware */ + rc =3D bnge_func_qcaps(bd); + if (rc) { + dev_err(bd->dev, "Failed initial configuration rc: %d\n", rc); + rc =3D -ENODEV; + goto err_func_unrgtr; + } + return 0; + +err_func_unrgtr: + bnge_fw_unregister_dev(bd); + return rc; } =20 static void bnge_pci_disable(struct pci_dev *pdev) @@ -134,14 +189,46 @@ static void bnge_unmap_bars(struct pci_dev *pdev) { struct bnge_dev *bd =3D pci_get_drvdata(pdev); =20 + if (bd->bar1) { + pci_iounmap(pdev, bd->bar1); + bd->bar1 =3D NULL; + } + if (bd->bar0) { pci_iounmap(pdev, bd->bar0); bd->bar0 =3D NULL; } } =20 +static void bnge_set_max_func_irqs(struct bnge_dev *bd, + unsigned int max_irqs) +{ + bd->hw_resc.max_irqs =3D max_irqs; +} + +static int bnge_get_max_irq(struct pci_dev *pdev) +{ + u16 ctrl; + + pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); + return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; +} + +static int bnge_map_db_bar(struct bnge_dev *bd) +{ + if (!bd->db_size) + return -ENODEV; + + bd->bar1 =3D pci_iomap(bd->pdev, 2, bd->db_size); + if (!bd->bar1) + return -ENOMEM; + + return 0; +} + static int bnge_probe_one(struct pci_dev *pdev, const struct pci_device_id= *ent) { + unsigned int max_irqs; struct bnge_dev *bd; int rc; =20 @@ -190,10 +277,42 @@ static int bnge_probe_one(struct pci_dev *pdev, const= struct pci_device_id *ent) =20 bnge_devlink_register(bd); =20 + max_irqs =3D bnge_get_max_irq(pdev); + bnge_set_max_func_irqs(bd, max_irqs); + + bnge_aux_init_dflt_config(bd); + + rc =3D bnge_net_init_dflt_config(bd); + if (rc) { + dev_err(&pdev->dev, "Error setting up default cfg to netdev rc =3D %d\n", + rc); + goto err_fw_reg; + } + + rc =3D bnge_map_db_bar(bd); + if (rc) { + dev_err(&pdev->dev, "Failed mapping doorbell BAR rc =3D %d, aborting\n", + rc); + goto err_config_uninit; + } + + rc =3D bnge_alloc_irqs(bd); + if (rc) { + dev_err(&pdev->dev, "Error IRQ allocation rc =3D %d\n", rc); + goto err_config_uninit; + } + pci_save_state(pdev); =20 return 0; =20 +err_config_uninit: + bnge_net_uninit_dflt_config(bd); + +err_fw_reg: + bnge_devlink_unregister(bd); + bnge_fw_unregister_dev(bd); + err_hwrm_cleanup: bnge_cleanup_hwrm_resources(bd); =20 @@ -212,6 +331,10 @@ static void bnge_remove_one(struct pci_dev *pdev) { struct bnge_dev *bd =3D pci_get_drvdata(pdev); =20 + bnge_free_irqs(bd); + + bnge_net_uninit_dflt_config(bd); + bnge_devlink_unregister(bd); =20 bnge_fw_unregister_dev(bd); diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c b/drivers/n= et/ethernet/broadcom/bnge/bnge_hwrm_lib.c index ee2675776c14..19091318cfdd 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c +++ b/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c @@ -647,3 +647,57 @@ int bnge_hwrm_vnic_qcaps(struct bnge_dev *bd) =20 return rc; } + +#define BNGE_CNPQ(q_profile) \ + ((q_profile) =3D=3D \ + QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP) + +int bnge_hwrm_queue_qportcfg(struct bnge_dev *bd) +{ + struct hwrm_queue_qportcfg_output *resp; + struct hwrm_queue_qportcfg_input *req; + u8 i, j, *qptr; + bool no_rdma; + int rc; + + rc =3D bnge_hwrm_req_init(bd, req, HWRM_QUEUE_QPORTCFG); + if (rc) + return rc; + + resp =3D bnge_hwrm_req_hold(bd, req); + rc =3D bnge_hwrm_req_send(bd, req); + if (rc) + goto qportcfg_exit; + + if (!resp->max_configurable_queues) { + rc =3D -EINVAL; + goto qportcfg_exit; + } + bd->max_tc =3D resp->max_configurable_queues; + bd->max_lltc =3D resp->max_configurable_lossless_queues; + if (bd->max_tc > BNGE_MAX_QUEUE) + bd->max_tc =3D BNGE_MAX_QUEUE; + + no_rdma =3D !bnge_is_roce_en(bd); + qptr =3D &resp->queue_id0; + for (i =3D 0, j =3D 0; i < bd->max_tc; i++) { + bd->q_info[j].queue_id =3D *qptr; + bd->q_ids[i] =3D *qptr++; + bd->q_info[j].queue_profile =3D *qptr++; + bd->tc_to_qidx[j] =3D j; + if (!BNGE_CNPQ(bd->q_info[j].queue_profile) || no_rdma) + j++; + } + bd->max_q =3D bd->max_tc; + bd->max_tc =3D max_t(u8, j, 1); + + if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) + bd->max_tc =3D 1; + + if (bd->max_lltc > bd->max_tc) + bd->max_lltc =3D bd->max_tc; + +qportcfg_exit: + bnge_hwrm_req_drop(bd, req); + return rc; +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.h b/drivers/n= et/ethernet/broadcom/bnge/bnge_hwrm_lib.h index 59ec1899879a..6c03923eb559 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.h @@ -22,5 +22,6 @@ int bnge_hwrm_func_qcaps(struct bnge_dev *bd); int bnge_hwrm_vnic_qcaps(struct bnge_dev *bd); int bnge_hwrm_func_qcfg(struct bnge_dev *bd); int bnge_hwrm_func_resc_qcaps(struct bnge_dev *bd); +int bnge_hwrm_queue_qportcfg(struct bnge_dev *bd); =20 #endif /* _BNGE_HWRM_LIB_H_ */ diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_resc.c b/drivers/net/e= thernet/broadcom/bnge/bnge_resc.c index 0e67a0001677..c79a3607a1b7 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_resc.c +++ b/drivers/net/ethernet/broadcom/bnge/bnge_resc.c @@ -5,6 +5,7 @@ #include #include #include +#include =20 #include "bnge.h" #include "bnge_hwrm.h" @@ -28,6 +29,16 @@ static u16 bnge_get_max_func_irqs(struct bnge_dev *bd) return min_t(u16, hw_resc->max_irqs, hw_resc->max_nqs); } =20 +static unsigned int bnge_get_max_func_stat_ctxs(struct bnge_dev *bd) +{ + return bd->hw_resc.max_stat_ctxs; +} + +static unsigned int bnge_get_max_func_cp_rings(struct bnge_dev *bd) +{ + return bd->hw_resc.max_cp_rings; +} + static int bnge_aux_get_dflt_msix(struct bnge_dev *bd) { int roce_msix =3D BNGE_MAX_ROCE_MSIX; @@ -68,6 +79,20 @@ static u16 bnge_func_stat_ctxs_demand(struct bnge_dev *b= d) return bd->nq_nr_rings + bnge_aux_get_stat_ctxs(bd); } =20 +static int bnge_get_dflt_aux_stat_ctxs(struct bnge_dev *bd) +{ + int stat_ctx =3D 0; + + if (bnge_is_roce_en(bd)) { + stat_ctx =3D BNGE_MIN_ROCE_STAT_CTXS; + + if (!bd->pf.port_id && bd->port_count > 1) + stat_ctx++; + } + + return stat_ctx; +} + static u16 bnge_nqs_demand(struct bnge_dev *bd) { return bd->nq_nr_rings + bnge_aux_get_msix(bd); @@ -395,3 +420,186 @@ void bnge_free_irqs(struct bnge_dev *bd) kfree(bd->irq_tbl); bd->irq_tbl =3D NULL; } + +static void _bnge_get_max_rings(struct bnge_dev *bd, u16 *max_rx, + u16 *max_tx, u16 *max_nq) +{ + struct bnge_hw_resc *hw_resc =3D &bd->hw_resc; + u16 max_ring_grps =3D 0, max_cp; + int rc; + + *max_tx =3D hw_resc->max_tx_rings; + *max_rx =3D hw_resc->max_rx_rings; + *max_nq =3D min_t(int, bnge_get_max_func_irqs(bd), + hw_resc->max_stat_ctxs); + max_ring_grps =3D hw_resc->max_hw_ring_grps; + if (bnge_is_agg_reqd(bd)) + *max_rx >>=3D 1; + + max_cp =3D bnge_get_max_func_cp_rings(bd); + + /* Fix RX and TX rings according to number of CPs available */ + rc =3D bnge_fix_rings_count(max_rx, max_tx, max_cp, false); + if (rc) { + *max_rx =3D 0; + *max_tx =3D 0; + } + + *max_rx =3D min_t(int, *max_rx, max_ring_grps); +} + +static int bnge_get_max_rings(struct bnge_dev *bd, u16 *max_rx, + u16 *max_tx, bool shared) +{ + u16 rx, tx, nq; + + _bnge_get_max_rings(bd, &rx, &tx, &nq); + *max_rx =3D rx; + *max_tx =3D tx; + if (!rx || !tx || !nq) + return -ENOMEM; + + return bnge_fix_rings_count(max_rx, max_tx, nq, shared); +} + +static int bnge_get_dflt_rings(struct bnge_dev *bd, u16 *max_rx, u16 *max_= tx, + bool shared) +{ + int rc; + + rc =3D bnge_get_max_rings(bd, max_rx, max_tx, shared); + if (rc) { + dev_info(bd->dev, "Not enough rings available\n"); + return rc; + } + + if (bnge_is_roce_en(bd)) { + int max_cp, max_stat, max_irq; + + /* Reserve minimum resources for RoCE */ + max_cp =3D bnge_get_max_func_cp_rings(bd); + max_stat =3D bnge_get_max_func_stat_ctxs(bd); + max_irq =3D bnge_get_max_func_irqs(bd); + if (max_cp <=3D BNGE_MIN_ROCE_CP_RINGS || + max_irq <=3D BNGE_MIN_ROCE_CP_RINGS || + max_stat <=3D BNGE_MIN_ROCE_STAT_CTXS) + return 0; + + max_cp -=3D BNGE_MIN_ROCE_CP_RINGS; + max_irq -=3D BNGE_MIN_ROCE_CP_RINGS; + max_stat -=3D BNGE_MIN_ROCE_STAT_CTXS; + max_cp =3D min_t(u16, max_cp, max_irq); + max_cp =3D min_t(u16, max_cp, max_stat); + rc =3D bnge_adjust_rings(bd, max_rx, max_tx, max_cp, shared); + if (rc) + rc =3D 0; + } + + return rc; +} + +/* In initial default shared ring setting, each shared ring must have a + * RX/TX ring pair. + */ +static void bnge_trim_dflt_sh_rings(struct bnge_dev *bd) +{ + bd->nq_nr_rings =3D min_t(u16, bd->tx_nr_rings_per_tc, bd->rx_nr_rings); + bd->rx_nr_rings =3D bd->nq_nr_rings; + bd->tx_nr_rings_per_tc =3D bd->nq_nr_rings; + bd->tx_nr_rings =3D bd->tx_nr_rings_per_tc; +} + +static int bnge_net_init_dflt_rings(struct bnge_dev *bd, bool sh) +{ + u16 dflt_rings, max_rx_rings, max_tx_rings; + int rc; + + if (sh) + bd->flags |=3D BNGE_EN_SHARED_CHNL; + + dflt_rings =3D netif_get_num_default_rss_queues(); + + rc =3D bnge_get_dflt_rings(bd, &max_rx_rings, &max_tx_rings, sh); + if (rc) + return rc; + bd->rx_nr_rings =3D min_t(u16, dflt_rings, max_rx_rings); + bd->tx_nr_rings_per_tc =3D min_t(u16, dflt_rings, max_tx_rings); + if (sh) + bnge_trim_dflt_sh_rings(bd); + else + bd->nq_nr_rings =3D bd->tx_nr_rings_per_tc + bd->rx_nr_rings; + bd->tx_nr_rings =3D bd->tx_nr_rings_per_tc; + + rc =3D bnge_reserve_rings(bd); + if (rc && rc !=3D -ENODEV) + dev_warn(bd->dev, "Unable to reserve tx rings\n"); + bd->tx_nr_rings_per_tc =3D bd->tx_nr_rings; + if (sh) + bnge_trim_dflt_sh_rings(bd); + + /* Rings may have been reduced, re-reserve them again */ + if (bnge_need_reserve_rings(bd)) { + rc =3D bnge_reserve_rings(bd); + if (rc && rc !=3D -ENODEV) + dev_warn(bd->dev, "Fewer rings reservation failed\n"); + bd->tx_nr_rings_per_tc =3D bd->tx_nr_rings; + } + if (rc) { + bd->tx_nr_rings =3D 0; + bd->rx_nr_rings =3D 0; + } + + return rc; +} + +static int bnge_alloc_rss_indir_tbl(struct bnge_dev *bd) +{ + u16 entries; + + entries =3D BNGE_MAX_RSS_TABLE_ENTRIES; + + bd->rss_indir_tbl_entries =3D entries; + bd->rss_indir_tbl =3D + kmalloc_array(entries, sizeof(*bd->rss_indir_tbl), GFP_KERNEL); + if (!bd->rss_indir_tbl) + return -ENOMEM; + + return 0; +} + +int bnge_net_init_dflt_config(struct bnge_dev *bd) +{ + struct bnge_hw_resc *hw_resc; + int rc; + + rc =3D bnge_alloc_rss_indir_tbl(bd); + if (rc) + return rc; + + rc =3D bnge_net_init_dflt_rings(bd, true); + if (rc) + goto err_free_tbl; + + hw_resc =3D &bd->hw_resc; + bd->max_fltr =3D hw_resc->max_rx_em_flows + hw_resc->max_rx_wm_flows + + BNGE_L2_FLTR_MAX_FLTR; + + return 0; + +err_free_tbl: + kfree(bd->rss_indir_tbl); + bd->rss_indir_tbl =3D NULL; + return rc; +} + +void bnge_net_uninit_dflt_config(struct bnge_dev *bd) +{ + kfree(bd->rss_indir_tbl); + bd->rss_indir_tbl =3D NULL; +} + +void bnge_aux_init_dflt_config(struct bnge_dev *bd) +{ + bd->aux_num_msix =3D bnge_aux_get_dflt_msix(bd); + bd->aux_num_stat_ctxs =3D bnge_get_dflt_aux_stat_ctxs(bd); +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_resc.h b/drivers/net/e= thernet/broadcom/bnge/bnge_resc.h index 23db93e03787..b39fd1a7a81b 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_resc.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge_resc.h @@ -66,6 +66,9 @@ int bnge_reserve_rings(struct bnge_dev *bd); int bnge_fix_rings_count(u16 *rx, u16 *tx, u16 max, bool shared); int bnge_alloc_irqs(struct bnge_dev *bd); void bnge_free_irqs(struct bnge_dev *bd); +int bnge_net_init_dflt_config(struct bnge_dev *bd); +void bnge_net_uninit_dflt_config(struct bnge_dev *bd); +void bnge_aux_init_dflt_config(struct bnge_dev *bd); =20 static inline u32 bnge_adjust_pow_two(u32 total_ent, u16 ent_per_blk) --=20 2.47.1 From nobody Wed Oct 8 05:39:37 2025 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38927272818 for ; Tue, 1 Jul 2025 09:12:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361152; cv=none; b=Zf37OW0O3XGKEvPnjBYa+tSETd8NoY0w9fa0Wg1BPbOL9nZABxoyhXkup+N/EOz6lbyQg2cVlXBRZplv2sHTMA6q5VctOAd51zm9nRJnztO641GZqOHm3T3IkpjxZh0gPbGZ3WROtpfmO8aQFboAQVEs2TZVrmsovEopyuOtbBw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751361152; c=relaxed/simple; bh=yHKDJoD7laWufs1kIc14KN/Zp/spSV8pLZwN0NdHLNs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tZ7A7Kg7Z0kQd63aHU1o7VnZrhM5yh5JqHgBUGnVDbhNcAqftSHbO7Kr71kAYBHj4jKHCiUsDNXPwfQAC+9VqilES5Xc/brqFkCg/c5ZF4I9bH1k5CydPLXZ1oU8alvMriIMNOQQKuGB21IIUMwCq/4/QszS+xvhKOSsk2egbYQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=T0TUCdNy; arc=none smtp.client-ip=209.85.210.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="T0TUCdNy" Received: by mail-pf1-f169.google.com with SMTP id d2e1a72fcca58-747fc7506d4so2636978b3a.0 for ; Tue, 01 Jul 2025 02:12:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1751361149; x=1751965949; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gPXzUgP2yhw1ayDkGwHNnqS4B/QCSTyOWqjyZ1UF5ww=; b=T0TUCdNyfm/70h1P0GQfYm/He70/EqmYy8C1zqnHRM0/qCZ/ZjFVSQCZO0kTAQYGue C3WQ06QSOytVfZ0YWs2NNggiOqwtyQMDfZrPy1racTXF0EKH28Cg5kkkxIBX4J7VRxBm FP1XmAP5bFqyCRbEt1j/lBHCuTM0vw4ZaqtiY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751361149; x=1751965949; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gPXzUgP2yhw1ayDkGwHNnqS4B/QCSTyOWqjyZ1UF5ww=; b=Xv5upjAJdfsckyb89EgwJ/6DsTRn/K5VXpDW+gvp/HnCMzWucP1SQpaym2eT2TYKwB p2zMx+lTBE/f5kWQTvnDNv8yeFX1dAdk7pgfdh2IFDhVK3hcO6GoHU1MUWP+AYVxL49a AIy/+hbc7mKQBSq4qw8srHwdyk66gUXRrUUt4hbwM+1HTK4gIhsHuAG02iPjZdr2EhQs IUq6qcc/IwbD9OfDZrnLbVDNKZ0+bCSwZr/UiTSP5r2YT+XxI5rRnz9s3jKI67abm+Ai 1XWadX1qxnkTBMliJDxr3bk9N6UBzhlRqb/bi21bg4IolV1qCRGacQAX/sUccx86/ynn fbgA== X-Forwarded-Encrypted: i=1; AJvYcCWxshtOC0GWBpRoWHsZ5UMZq8q48gwW2WlxDP3JFYg34z99r3o7QtOx5zkkCuFUu/i51wwsorQZV+9Ok88=@vger.kernel.org X-Gm-Message-State: AOJu0YzBLmrjlakOkrOWoKIpQNokzQyviL4t0US2U1RwwGhm1i7Ln9CC EvauUc5MuJBM9tiQAAe6Ve/pRZf/ptF11zdXMYds9WvG2PRuTfneJLqmFMi5f4DaiQ== X-Gm-Gg: ASbGncvnRgM4IdRDofowwy7ebP6Uom7WcizED1EGyiAH87x2bqYF+sgyqXIY2TqTduy jfG7qzlPRn3GUENz4YW99eoRMTuAE4qPdMriVLvqiX6rTvu/tghkDJeUq4a/QOgP0sFHkoTEOrn /zNk+TVJ8WBfplU16MT3AzKN8zfidbWBpzQ6u8qJFdJ4AVl4DpuMPnsGsp2rr7X3D94f0idxlZF PcwwnDzTQiwOOuGQx0dEcktpJcWVoHZkusmcSBcm/WNACh4nRDFlueQAsUhzItbi/ZxTjvNmSkM /zbMhTJItZp5bXusKM+sgqMjh0c4/5q9MsXg2NcB1S7DeRmd6TqD00w4IfkKkKiP+z0ITgGe1KJ EuduITdKrZ7xrCS51jYkTOy3p5uKKrnug7usxRWs= X-Google-Smtp-Source: AGHT+IEDcE4RLNQAWy6wq7+wguO/7/Ck2/SP9eTCWAzVaV1zsDTPAJC4yUUzFNzrHGQJ7+x/8ECTKw== X-Received: by 2002:a05:6a21:7316:b0:220:82c7:309c with SMTP id adf61e73a8af0-220a129c4a9mr28272547637.7.1751361149297; Tue, 01 Jul 2025 02:12:29 -0700 (PDT) Received: from localhost.localdomain ([192.19.203.250]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b34e30201c1sm8893603a12.22.2025.07.01.02.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 02:12:28 -0700 (PDT) From: Vikas Gupta To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, andrew+netdev@lunn.ch, horms@kernel.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, michael.chan@broadcom.com, pavan.chebbi@broadcom.com, vsrama-krishna.nemani@broadcom.com, Vikas Gupta , Bhargava Chenna Marreddy , Rajashekar Hudumula Subject: [net-next, v3 10/10] bng_en: Add a network device Date: Tue, 1 Jul 2025 14:35:08 +0000 Message-ID: <20250701143511.280702-11-vikas.gupta@broadcom.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250701143511.280702-1-vikas.gupta@broadcom.com> References: <20250701143511.280702-1-vikas.gupta@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a network device with netdev features enabled. Some features are enabled based on the capabilities advertised by the firmware. Add the skeleton of minimal netdev operations. Additionally, initialize the parameters for rings (TX/RX/Completion). Signed-off-by: Vikas Gupta Reviewed-by: Bhargava Chenna Marreddy Reviewed-by: Rajashekar Hudumula --- drivers/net/ethernet/broadcom/bnge/Makefile | 4 +- drivers/net/ethernet/broadcom/bnge/bnge.h | 12 + .../net/ethernet/broadcom/bnge/bnge_core.c | 9 + .../net/ethernet/broadcom/bnge/bnge_ethtool.c | 33 +++ .../net/ethernet/broadcom/bnge/bnge_ethtool.h | 9 + .../net/ethernet/broadcom/bnge/bnge_netdev.c | 268 ++++++++++++++++++ .../net/ethernet/broadcom/bnge/bnge_netdev.h | 206 ++++++++++++++ .../net/ethernet/broadcom/bnge/bnge_resc.h | 3 + 8 files changed, 543 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_ethtool.c create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_ethtool.h create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_netdev.c create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_netdev.h diff --git a/drivers/net/ethernet/broadcom/bnge/Makefile b/drivers/net/ethe= rnet/broadcom/bnge/Makefile index 10df05b6695e..6142d9c57f49 100644 --- a/drivers/net/ethernet/broadcom/bnge/Makefile +++ b/drivers/net/ethernet/broadcom/bnge/Makefile @@ -7,4 +7,6 @@ bng_en-y :=3D bnge_core.o \ bnge_hwrm.o \ bnge_hwrm_lib.o \ bnge_rmem.o \ - bnge_resc.o + bnge_resc.o \ + bnge_netdev.o \ + bnge_ethtool.o diff --git a/drivers/net/ethernet/broadcom/bnge/bnge.h b/drivers/net/ethern= et/broadcom/bnge/bnge.h index cef66c1e9006..a1795302c15a 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge.h @@ -65,6 +65,7 @@ enum { BNGE_EN_ROCE_V2 =3D BIT_ULL(1), BNGE_EN_STRIP_VLAN =3D BIT_ULL(2), BNGE_EN_SHARED_CHNL =3D BIT_ULL(3), + BNGE_EN_UDP_GSO_SUPP =3D BIT_ULL(4), }; =20 #define BNGE_EN_ROCE (BNGE_EN_ROCE_V1 | BNGE_EN_ROCE_V2) @@ -89,6 +90,7 @@ struct bnge_queue_info { struct bnge_dev { struct device *dev; struct pci_dev *pdev; + struct net_device *netdev; u64 dsn; #define BNGE_VPD_FLD_LEN 32 char board_partno[BNGE_VPD_FLD_LEN]; @@ -198,6 +200,16 @@ static inline bool bnge_is_roce_en(struct bnge_dev *bd) =20 static inline bool bnge_is_agg_reqd(struct bnge_dev *bd) { + if (bd->netdev) { + struct bnge_net *bn =3D netdev_priv(bd->netdev); + + if (bn->priv_flags & BNGE_NET_EN_TPA || + bn->priv_flags & BNGE_NET_EN_JUMBO) + return true; + else + return false; + } + return true; } =20 diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_core.c b/drivers/net/e= thernet/broadcom/bnge/bnge_core.c index 24babc8b9d35..68da656f2894 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_core.c +++ b/drivers/net/ethernet/broadcom/bnge/bnge_core.c @@ -302,10 +302,17 @@ static int bnge_probe_one(struct pci_dev *pdev, const= struct pci_device_id *ent) goto err_config_uninit; } =20 + rc =3D bnge_netdev_alloc(bd, max_irqs); + if (rc) + goto err_free_irq; + pci_save_state(pdev); =20 return 0; =20 +err_free_irq: + bnge_free_irqs(bd); + err_config_uninit: bnge_net_uninit_dflt_config(bd); =20 @@ -331,6 +338,8 @@ static void bnge_remove_one(struct pci_dev *pdev) { struct bnge_dev *bd =3D pci_get_drvdata(pdev); =20 + bnge_netdev_free(bd); + bnge_free_irqs(bd); =20 bnge_net_uninit_dflt_config(bd); diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_ethtool.c b/drivers/ne= t/ethernet/broadcom/bnge/bnge_ethtool.c new file mode 100644 index 000000000000..569371c1b4f2 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_ethtool.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2025 Broadcom. + +#include +#include +#include +#include +#include +#include +#include + +#include "bnge.h" +#include "bnge_ethtool.h" + +static void bnge_get_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + struct bnge_net *bn =3D netdev_priv(dev); + struct bnge_dev *bd =3D bn->bd; + + strscpy(info->driver, DRV_NAME, sizeof(info->driver)); + strscpy(info->fw_version, bd->fw_ver_str, sizeof(info->fw_version)); + strscpy(info->bus_info, pci_name(bd->pdev), sizeof(info->bus_info)); +} + +static const struct ethtool_ops bnge_ethtool_ops =3D { + .get_drvinfo =3D bnge_get_drvinfo, +}; + +void bnge_set_ethtool_ops(struct net_device *dev) +{ + dev->ethtool_ops =3D &bnge_ethtool_ops; +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_ethtool.h b/drivers/ne= t/ethernet/broadcom/bnge/bnge_ethtool.h new file mode 100644 index 000000000000..21e96a0976d5 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_ethtool.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2025 Broadcom */ + +#ifndef _BNGE_ETHTOOL_H_ +#define _BNGE_ETHTOOL_H_ + +void bnge_set_ethtool_ops(struct net_device *dev); + +#endif /* _BNGE_ETHTOOL_H_ */ diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_netdev.c b/drivers/net= /ethernet/broadcom/bnge/bnge_netdev.c new file mode 100644 index 000000000000..02254934f3d0 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_netdev.c @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2025 Broadcom. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bnge.h" +#include "bnge_hwrm_lib.h" +#include "bnge_ethtool.h" + +static netdev_tx_t bnge_start_xmit(struct sk_buff *skb, struct net_device = *dev) +{ + dev_kfree_skb_any(skb); + + return NETDEV_TX_OK; +} + +static int bnge_open(struct net_device *dev) +{ + return 0; +} + +static int bnge_close(struct net_device *dev) +{ + return 0; +} + +static const struct net_device_ops bnge_netdev_ops =3D { + .ndo_open =3D bnge_open, + .ndo_stop =3D bnge_close, + .ndo_start_xmit =3D bnge_start_xmit, +}; + +static void bnge_init_mac_addr(struct bnge_dev *bd) +{ + eth_hw_addr_set(bd->netdev, bd->pf.mac_addr); +} + +static void bnge_set_tpa_flags(struct bnge_dev *bd) +{ + struct bnge_net *bn =3D netdev_priv(bd->netdev); + + bn->priv_flags &=3D ~BNGE_NET_EN_TPA; + + if (bd->netdev->features & NETIF_F_LRO) + bn->priv_flags |=3D BNGE_NET_EN_LRO; + else if (bd->netdev->features & NETIF_F_GRO_HW) + bn->priv_flags |=3D BNGE_NET_EN_GRO; +} + +static void bnge_init_l2_fltr_tbl(struct bnge_net *bn) +{ + int i; + + for (i =3D 0; i < BNGE_L2_FLTR_HASH_SIZE; i++) + INIT_HLIST_HEAD(&bn->l2_fltr_hash_tbl[i]); + get_random_bytes(&bn->hash_seed, sizeof(bn->hash_seed)); +} + +void bnge_set_ring_params(struct bnge_dev *bd) +{ + struct bnge_net *bn =3D netdev_priv(bd->netdev); + u32 ring_size, rx_size, rx_space, max_rx_cmpl; + u32 agg_factor =3D 0, agg_ring_size =3D 0; + + /* 8 for CRC and VLAN */ + rx_size =3D SKB_DATA_ALIGN(bn->netdev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); + + rx_space =3D rx_size + ALIGN(NET_SKB_PAD, 8) + + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); + + bn->rx_copy_thresh =3D BNGE_RX_COPY_THRESH; + ring_size =3D bn->rx_ring_size; + bn->rx_agg_ring_size =3D 0; + bn->rx_agg_nr_pages =3D 0; + + if (bn->priv_flags & BNGE_NET_EN_TPA) + agg_factor =3D min_t(u32, 4, 65536 / BNGE_RX_PAGE_SIZE); + + bn->priv_flags &=3D ~BNGE_NET_EN_JUMBO; + if (rx_space > PAGE_SIZE) { + u32 jumbo_factor; + + bn->priv_flags |=3D BNGE_NET_EN_JUMBO; + jumbo_factor =3D PAGE_ALIGN(bn->netdev->mtu - 40) >> PAGE_SHIFT; + if (jumbo_factor > agg_factor) + agg_factor =3D jumbo_factor; + } + if (agg_factor) { + if (ring_size > BNGE_MAX_RX_DESC_CNT_JUM_ENA) { + ring_size =3D BNGE_MAX_RX_DESC_CNT_JUM_ENA; + netdev_warn(bn->netdev, "RX ring size reduced from %d to %d due to jumb= o ring\n", + bn->rx_ring_size, ring_size); + bn->rx_ring_size =3D ring_size; + } + agg_ring_size =3D ring_size * agg_factor; + + bn->rx_agg_nr_pages =3D bnge_adjust_pow_two(agg_ring_size, + RX_DESC_CNT); + if (bn->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { + u32 tmp =3D agg_ring_size; + + bn->rx_agg_nr_pages =3D MAX_RX_AGG_PAGES; + agg_ring_size =3D MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; + netdev_warn(bn->netdev, "RX agg ring size %d reduced to %d.\n", + tmp, agg_ring_size); + } + bn->rx_agg_ring_size =3D agg_ring_size; + bn->rx_agg_ring_mask =3D (bn->rx_agg_nr_pages * RX_DESC_CNT) - 1; + + rx_size =3D SKB_DATA_ALIGN(BNGE_RX_COPY_THRESH + NET_IP_ALIGN); + rx_space =3D rx_size + NET_SKB_PAD + + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); + } + + bn->rx_buf_use_size =3D rx_size; + bn->rx_buf_size =3D rx_space; + + bn->rx_nr_pages =3D bnge_adjust_pow_two(ring_size, RX_DESC_CNT); + bn->rx_ring_mask =3D (bn->rx_nr_pages * RX_DESC_CNT) - 1; + + ring_size =3D bn->tx_ring_size; + bn->tx_nr_pages =3D bnge_adjust_pow_two(ring_size, TX_DESC_CNT); + bn->tx_ring_mask =3D (bn->tx_nr_pages * TX_DESC_CNT) - 1; + + max_rx_cmpl =3D bn->rx_ring_size; + + if (bn->priv_flags & BNGE_NET_EN_TPA) + max_rx_cmpl +=3D bd->max_tpa_v2; + ring_size =3D max_rx_cmpl * 2 + agg_ring_size + bn->tx_ring_size; + bn->cp_ring_size =3D ring_size; + + bn->cp_nr_pages =3D bnge_adjust_pow_two(ring_size, CP_DESC_CNT); + if (bn->cp_nr_pages > MAX_CP_PAGES) { + bn->cp_nr_pages =3D MAX_CP_PAGES; + bn->cp_ring_size =3D MAX_CP_PAGES * CP_DESC_CNT - 1; + netdev_warn(bn->netdev, "completion ring size %d reduced to %d.\n", + ring_size, bn->cp_ring_size); + } + bn->cp_bit =3D bn->cp_nr_pages * CP_DESC_CNT; + bn->cp_ring_mask =3D bn->cp_bit - 1; +} + +int bnge_netdev_alloc(struct bnge_dev *bd, int max_irqs) +{ + struct net_device *netdev; + struct bnge_net *bn; + int rc; + + netdev =3D alloc_etherdev_mqs(sizeof(*bn), max_irqs * BNGE_MAX_QUEUE, + max_irqs); + if (!netdev) + return -ENOMEM; + + SET_NETDEV_DEV(netdev, bd->dev); + bd->netdev =3D netdev; + + netdev->netdev_ops =3D &bnge_netdev_ops; + + bnge_set_ethtool_ops(netdev); + + bn =3D netdev_priv(netdev); + bn->netdev =3D netdev; + bn->bd =3D bd; + + netdev->min_mtu =3D ETH_ZLEN; + netdev->max_mtu =3D bd->max_mtu; + + netdev->hw_features =3D NETIF_F_IP_CSUM | + NETIF_F_IPV6_CSUM | + NETIF_F_SG | + NETIF_F_TSO | + NETIF_F_TSO6 | + NETIF_F_GSO_UDP_TUNNEL | + NETIF_F_GSO_GRE | + NETIF_F_GSO_IPXIP4 | + NETIF_F_GSO_UDP_TUNNEL_CSUM | + NETIF_F_GSO_GRE_CSUM | + NETIF_F_GSO_PARTIAL | + NETIF_F_RXHASH | + NETIF_F_RXCSUM | + NETIF_F_GRO; + + if (bd->flags & BNGE_EN_UDP_GSO_SUPP) + netdev->hw_features |=3D NETIF_F_GSO_UDP_L4; + + if (BNGE_SUPPORTS_TPA(bd)) + netdev->hw_features |=3D NETIF_F_LRO; + + netdev->hw_enc_features =3D NETIF_F_IP_CSUM | + NETIF_F_IPV6_CSUM | + NETIF_F_SG | + NETIF_F_TSO | + NETIF_F_TSO6 | + NETIF_F_GSO_UDP_TUNNEL | + NETIF_F_GSO_GRE | + NETIF_F_GSO_UDP_TUNNEL_CSUM | + NETIF_F_GSO_GRE_CSUM | + NETIF_F_GSO_IPXIP4 | + NETIF_F_GSO_PARTIAL; + + if (bd->flags & BNGE_EN_UDP_GSO_SUPP) + netdev->hw_enc_features |=3D NETIF_F_GSO_UDP_L4; + + netdev->gso_partial_features =3D NETIF_F_GSO_UDP_TUNNEL_CSUM | + NETIF_F_GSO_GRE_CSUM; + + netdev->vlan_features =3D netdev->hw_features | NETIF_F_HIGHDMA; + if (bd->fw_cap & BNGE_FW_CAP_VLAN_RX_STRIP) + netdev->hw_features |=3D BNGE_HW_FEATURE_VLAN_ALL_RX; + if (bd->fw_cap & BNGE_FW_CAP_VLAN_TX_INSERT) + netdev->hw_features |=3D BNGE_HW_FEATURE_VLAN_ALL_TX; + + if (BNGE_SUPPORTS_TPA(bd)) + netdev->hw_features |=3D NETIF_F_GRO_HW; + + netdev->features |=3D netdev->hw_features | NETIF_F_HIGHDMA; + + if (netdev->features & NETIF_F_GRO_HW) + netdev->features &=3D ~NETIF_F_LRO; + + netdev->priv_flags |=3D IFF_UNICAST_FLT; + + netif_set_tso_max_size(netdev, GSO_MAX_SIZE); + if (bd->tso_max_segs) + netif_set_tso_max_segs(netdev, bd->tso_max_segs); + + bn->rx_ring_size =3D BNGE_DEFAULT_RX_RING_SIZE; + bn->tx_ring_size =3D BNGE_DEFAULT_TX_RING_SIZE; + + bnge_set_tpa_flags(bd); + bnge_set_ring_params(bd); + + bnge_init_l2_fltr_tbl(bn); + bnge_init_mac_addr(bd); + + rc =3D register_netdev(netdev); + if (rc) { + dev_err(bd->dev, "Register netdev failed rc: %d\n", rc); + goto err_netdev; + } + + return 0; + +err_netdev: + free_netdev(netdev); + return rc; +} + +void bnge_netdev_free(struct bnge_dev *bd) +{ + struct net_device *netdev =3D bd->netdev; + + unregister_netdev(netdev); + free_netdev(netdev); + bd->netdev =3D NULL; +} diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_netdev.h b/drivers/net= /ethernet/broadcom/bnge/bnge_netdev.h new file mode 100644 index 000000000000..96b77e44b552 --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnge/bnge_netdev.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2025 Broadcom */ + +#ifndef _BNGE_NETDEV_H_ +#define _BNGE_NETDEV_H_ + +#include "../bnxt/bnxt_hsi.h" + +struct tx_bd { + __le32 tx_bd_len_flags_type; + #define TX_BD_TYPE (0x3f << 0) + #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0) + #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0) + #define TX_BD_FLAGS_PACKET_END (1 << 6) + #define TX_BD_FLAGS_NO_CMPL (1 << 7) + #define TX_BD_FLAGS_BD_CNT (0x1f << 8) + #define TX_BD_FLAGS_BD_CNT_SHIFT 8 + #define TX_BD_FLAGS_LHINT (3 << 13) + #define TX_BD_FLAGS_LHINT_SHIFT 13 + #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13) + #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13) + #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13) + #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13) + #define TX_BD_FLAGS_COAL_NOW (1 << 15) + #define TX_BD_LEN (0xffff << 16) + #define TX_BD_LEN_SHIFT 16 + u32 tx_bd_opaque; + __le64 tx_bd_haddr; +} __packed; + +struct rx_bd { + __le32 rx_bd_len_flags_type; + #define RX_BD_TYPE (0x3f << 0) + #define RX_BD_TYPE_RX_PACKET_BD 0x4 + #define RX_BD_TYPE_RX_BUFFER_BD 0x5 + #define RX_BD_TYPE_RX_AGG_BD 0x6 + #define RX_BD_TYPE_16B_BD_SIZE (0 << 4) + #define RX_BD_TYPE_32B_BD_SIZE (1 << 4) + #define RX_BD_TYPE_48B_BD_SIZE (2 << 4) + #define RX_BD_TYPE_64B_BD_SIZE (3 << 4) + #define RX_BD_FLAGS_SOP (1 << 6) + #define RX_BD_FLAGS_EOP (1 << 7) + #define RX_BD_FLAGS_BUFFERS (3 << 8) + #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8) + #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8) + #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8) + #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8) + #define RX_BD_LEN (0xffff << 16) + #define RX_BD_LEN_SHIFT 16 + u32 rx_bd_opaque; + __le64 rx_bd_haddr; +}; + +struct tx_cmp { + __le32 tx_cmp_flags_type; + #define CMP_TYPE (0x3f << 0) + #define CMP_TYPE_TX_L2_CMP 0 + #define CMP_TYPE_TX_L2_COAL_CMP 2 + #define CMP_TYPE_TX_L2_PKT_TS_CMP 4 + #define CMP_TYPE_RX_L2_CMP 17 + #define CMP_TYPE_RX_AGG_CMP 18 + #define CMP_TYPE_RX_L2_TPA_START_CMP 19 + #define CMP_TYPE_RX_L2_TPA_END_CMP 21 + #define CMP_TYPE_RX_TPA_AGG_CMP 22 + #define CMP_TYPE_RX_L2_V3_CMP 23 + #define CMP_TYPE_RX_L2_TPA_START_V3_CMP 25 + #define CMP_TYPE_STATUS_CMP 32 + #define CMP_TYPE_REMOTE_DRIVER_REQ 34 + #define CMP_TYPE_REMOTE_DRIVER_RESP 36 + #define CMP_TYPE_ERROR_STATUS 48 + #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL + #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL + #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL + #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL + #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL + #define TX_CMP_FLAGS_ERROR (1 << 6) + #define TX_CMP_FLAGS_PUSH (1 << 7) + u32 tx_cmp_opaque; + __le32 tx_cmp_errors_v; + #define TX_CMP_V (1 << 0) + #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1) + #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0 + #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2 + #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4 + #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5 + #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4) + #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5) + #define TX_CMP_ERRORS_DMA_ERROR (1 << 6) + #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7) + __le32 sq_cons_idx; + #define TX_CMP_SQ_CONS_IDX_MASK 0x00ffffff +}; + +struct bnge_sw_tx_bd { + struct sk_buff *skb; + DEFINE_DMA_UNMAP_ADDR(mapping); + DEFINE_DMA_UNMAP_LEN(len); + struct page *page; + u8 is_ts_pkt; + u8 is_push; + u8 action; + unsigned short nr_frags; + union { + u16 rx_prod; + u16 txts_prod; + }; +}; + +struct bnge_sw_rx_bd { + void *data; + u8 *data_ptr; + dma_addr_t mapping; +}; + +struct bnge_sw_rx_agg_bd { + struct page *page; + unsigned int offset; + dma_addr_t mapping; +}; + +#define BNGE_RX_COPY_THRESH 256 + +#define BNGE_HW_FEATURE_VLAN_ALL_RX \ + (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX) +#define BNGE_HW_FEATURE_VLAN_ALL_TX \ + (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX) + +enum { + BNGE_NET_EN_GRO =3D BIT(0), + BNGE_NET_EN_LRO =3D BIT(1), + BNGE_NET_EN_JUMBO =3D BIT(2), +}; + +#define BNGE_NET_EN_TPA (BNGE_NET_EN_GRO | BNGE_NET_EN_LRO) + +struct bnge_net { + struct bnge_dev *bd; + struct net_device *netdev; + + u32 priv_flags; + + u32 rx_ring_size; + u32 rx_buf_size; + u32 rx_buf_use_size; /* usable size */ + u32 rx_agg_ring_size; + u32 rx_copy_thresh; + u32 rx_ring_mask; + u32 rx_agg_ring_mask; + u16 rx_nr_pages; + u16 rx_agg_nr_pages; + + u32 tx_ring_size; + u32 tx_ring_mask; + u16 tx_nr_pages; + + /* NQs and Completion rings */ + u32 cp_ring_size; + u32 cp_ring_mask; + u32 cp_bit; + u16 cp_nr_pages; + +#define BNGE_L2_FLTR_HASH_SIZE 32 +#define BNGE_L2_FLTR_HASH_MASK (BNGE_L2_FLTR_HASH_SIZE - 1) + struct hlist_head l2_fltr_hash_tbl[BNGE_L2_FLTR_HASH_SIZE]; + u32 hash_seed; + u64 toeplitz_prefix; +}; + +#define BNGE_DEFAULT_RX_RING_SIZE 511 +#define BNGE_DEFAULT_TX_RING_SIZE 511 + +int bnge_netdev_alloc(struct bnge_dev *bd, int max_irqs); +void bnge_netdev_free(struct bnge_dev *bd); +void bnge_set_ring_params(struct bnge_dev *bd); + +#if (BNGE_PAGE_SHIFT =3D=3D 16) +#define MAX_RX_PAGES_AGG_ENA 1 +#define MAX_RX_PAGES 4 +#define MAX_RX_AGG_PAGES 4 +#define MAX_TX_PAGES 1 +#define MAX_CP_PAGES 16 +#else +#define MAX_RX_PAGES_AGG_ENA 8 +#define MAX_RX_PAGES 32 +#define MAX_RX_AGG_PAGES 32 +#define MAX_TX_PAGES 8 +#define MAX_CP_PAGES 128 +#endif + +#define BNGE_RX_PAGE_SIZE (1 << BNGE_RX_PAGE_SHIFT) + +#define RX_DESC_CNT (BNGE_PAGE_SIZE / sizeof(struct rx_bd)) +#define TX_DESC_CNT (BNGE_PAGE_SIZE / sizeof(struct tx_bd)) +#define CP_DESC_CNT (BNGE_PAGE_SIZE / sizeof(struct tx_cmp)) +#define SW_RXBD_RING_SIZE (sizeof(struct bnge_sw_rx_bd) * RX_DESC_CNT) +#define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) +#define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnge_sw_rx_agg_bd) * RX_DESC= _CNT) +#define SW_TXBD_RING_SIZE (sizeof(struct bnge_sw_tx_bd) * TX_DESC_CNT) +#define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) +#define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT) +#define BNGE_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1) +#define BNGE_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA -= 1) +#define BNGE_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1) +#define BNGE_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1) + +#endif /* _BNGE_NETDEV_H_ */ diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_resc.h b/drivers/net/e= thernet/broadcom/bnge/bnge_resc.h index b39fd1a7a81b..54ef1c7d8822 100644 --- a/drivers/net/ethernet/broadcom/bnge/bnge_resc.h +++ b/drivers/net/ethernet/broadcom/bnge/bnge_resc.h @@ -4,6 +4,9 @@ #ifndef _BNGE_RESC_H_ #define _BNGE_RESC_H_ =20 +#include "bnge_netdev.h" +#include "bnge_rmem.h" + struct bnge_hw_resc { u16 min_rsscos_ctxs; u16 max_rsscos_ctxs; --=20 2.47.1