From nobody Wed Oct 8 08:35:12 2025 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5497C2749CB for ; Tue, 1 Jul 2025 13:08:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751375287; cv=none; b=mQUPNnnxQMisw0Fj41bW9TgLkeGwJ1tgr9/y6LL9MQ/q4+n9+dTTRHoyABi0HZv0WNqkff1WgCZv7h1PIx1+VEtmkjQanG8qKYLsn0X+k29rU2ZZzAdbfKDu2OumIe9K8ozAMmWeL/ATTaYAJWilreJjkuJFWZvy7V+TJf37DLE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751375287; c=relaxed/simple; bh=2gZY7Acfhkay75+KSoYtQAw+ivQxiGgR9g9578HYzG0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=FTG9shblN9kJ3drrdcp+0DbzjVGMgpnUhKnLsRxwNO9L34HpEVCp/mhx/VJW9tJxJ+UcBoYFyTSsgqRHvstkDRnW/+Idz83vBzwic03XmCumb7MFChXD5fA1d+SaMF9IVGUeTYBw48/vVUYyTRCcUoIDJOkvbCSfdPAexxCcHtQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=UFlp1ZHA; arc=none smtp.client-ip=203.254.224.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="UFlp1ZHA" Received: from epcas5p3.samsung.com (unknown [182.195.41.41]) by mailout3.samsung.com (KnoxPortal) with ESMTP id 20250701130803epoutp03acf68e210f0fb6f99b6c7a8574b4b5b5~OIoqCWcUW1262312623epoutp03G for ; Tue, 1 Jul 2025 13:08:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout3.samsung.com 20250701130803epoutp03acf68e210f0fb6f99b6c7a8574b4b5b5~OIoqCWcUW1262312623epoutp03G DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1751375283; bh=I75Ks8WoTjVRhBjGREqmgMHMQs8DiCAyjM7jzwXjn2M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UFlp1ZHAtPwD/N228WA+9c9+2Hf/pPSkgnuK4wh69lSY88VZj9vEyu14Jobnfk3WN eyMaIDOJIam5ILmt2Lk4SPN/RNXIQhVT+mR+/PdNCuLqeuyRFx4kDKBwfvZCGj/h6t wXZm2h2ElVXlrKfm7HyJ+a/yTZ/ar8S36zCHR29Y= Received: from epsnrtp02.localdomain (unknown [182.195.42.154]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPS id 20250701130802epcas5p126d498a02a08cdfb95c3c941e11bb750~OIopYeCuN1091810918epcas5p15; Tue, 1 Jul 2025 13:08:02 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.174]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4bWjxr4kfbz2SSKY; Tue, 1 Jul 2025 13:08:00 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250701115959epcas5p40f28954777a620b018251301eea13873~OHtOXVtHF2133421334epcas5p44; Tue, 1 Jul 2025 11:59:59 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250701115956epsmtip1bf43d7f7886a0107ac300806328c6f3a~OHtLf3odZ1547115471epsmtip1J; Tue, 1 Jul 2025 11:59:56 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, neil.armstrong@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v4 2/6] phy: exynos5-usbdrd: support HS phy for ExynosAutov920 Date: Tue, 1 Jul 2025 17:37:02 +0530 Message-Id: <20250701120706.2219355-3-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250701120706.2219355-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250701115959epcas5p40f28954777a620b018251301eea13873 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250701115959epcas5p40f28954777a620b018251301eea13873 References: <20250701120706.2219355-1-pritam.sutar@samsung.com> This SoC has a single USB 3.1 DRD combo phy that supports both UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD HS phy controllers those only support the UTMI+ (HS) interface. Support only UTMI+ port for this SoC which is very similar to what the existing Exynos850 supports. This SoC shares phy isol between USBs. Bypass PHY isol when first USB is powered on and enable it when all of then are powered off. Add required change in phy driver to support HS phy for this SoC. Reviewed-by: Neil Armstrong Signed-off-by: Pritam Manohar Sutar --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 131 ++++++++++++++++++++ include/linux/soc/samsung/exynos-regs-pmu.h | 2 + 2 files changed, 133 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index dd660ebe8045..64f3316f6ad4 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -480,6 +480,8 @@ struct exynos5_usbdrd_phy { enum typec_orientation orientation; }; =20 +static atomic_t usage_count =3D ATOMIC_INIT(0); + static inline struct exynos5_usbdrd_phy *to_usbdrd_phy(struct phy_usb_instance *inst) { @@ -2054,6 +2056,132 @@ static const struct exynos5_usbdrd_phy_drvdata exyn= os990_usbdrd_phy =3D { .n_regulators =3D ARRAY_SIZE(exynos5_regulator_names), }; =20 +static int exynosautov920_usbdrd_phy_init(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_UTMI) { + /* Bypass PHY isol when first USB is powered on */ + if ((atomic_inc_return(&usage_count) =3D=3D 1)) + inst->phy_cfg->phy_isol(inst, false); + } + + /* UTMI or PIPE3 specific init */ + inst->phy_cfg->phy_init(phy_drd); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static int exynosautov920_usbdrd_phy_exit(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret =3D 0; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_UTMI) { + exynos850_usbdrd_phy_exit(phy); + + /* enable PHY isol when all USBs are powered off */ + if (atomic_dec_and_test(&usage_count)) + inst->phy_cfg->phy_isol(inst, true); + } + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static int exynosautov920_usbdrd_phy_power_on(struct phy *phy) +{ + int ret; + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + + dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n"); + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + if (ret) + return ret; + + /* Enable supply */ + ret =3D regulator_bulk_enable(phy_drd->drv_data->n_regulators, + phy_drd->regulators); + if (ret) { + dev_err(phy_drd->dev, "Failed to enable PHY regulator(s)\n"); + goto fail_supply; + } + + return 0; + +fail_supply: + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + + return ret; +} + +static int exynosautov920_usbdrd_phy_power_off(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + + dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n"); + + /* Disable supply */ + regulator_bulk_disable(phy_drd->drv_data->n_regulators, + phy_drd->regulators); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + + return 0; +} + +static const char * const exynosautov920_regulator_names[] =3D { + "avdd075_usb", "avdd18_usb20", "avdd33_usb20", +}; + +static const struct phy_ops exynosautov920_usbdrd_phy_ops =3D { + .init =3D exynosautov920_usbdrd_phy_init, + .exit =3D exynosautov920_usbdrd_phy_exit, + .power_on =3D exynosautov920_usbdrd_phy_power_on, + .power_off =3D exynosautov920_usbdrd_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static const struct exynos5_usbdrd_phy_config phy_cfg_exynosautov920[] =3D= { + { + .id =3D EXYNOS5_DRDPHY_UTMI, + .phy_isol =3D exynos5_usbdrd_phy_isol, + .phy_init =3D exynos850_usbdrd_utmi_init, + }, +}; + +static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_phy = =3D { + .phy_cfg =3D phy_cfg_exynosautov920, + .phy_ops =3D &exynosautov920_usbdrd_phy_ops, + .pmu_offset_usbdrd0_phy =3D EXYNOSAUTOV920_PHY_CTRL_USB20, + .clk_names =3D exynos5_clk_names, + .n_clks =3D ARRAY_SIZE(exynos5_clk_names), + .core_clk_names =3D exynos5_core_clk_names, + .n_core_clks =3D ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names =3D exynosautov920_regulator_names, + .n_regulators =3D ARRAY_SIZE(exynosautov920_regulator_names), +}; + static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] =3D { { .id =3D EXYNOS5_DRDPHY_UTMI, @@ -2260,6 +2388,9 @@ static const struct of_device_id exynos5_usbdrd_phy_o= f_match[] =3D { }, { .compatible =3D "samsung,exynos990-usbdrd-phy", .data =3D &exynos990_usbdrd_phy + }, { + .compatible =3D "samsung,exynosautov920-usbdrd-phy", + .data =3D &exynosautov920_usbdrd_phy }, { }, }; diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/so= c/samsung/exynos-regs-pmu.h index 71e0c09a49eb..4923f9be3d1f 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -688,4 +688,6 @@ #define GS101_GRP2_INTR_BID_UPEND (0x0208) #define GS101_GRP2_INTR_BID_CLEAR (0x020c) =20 +/* exynosautov920 */ +#define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ --=20 2.34.1