From nobody Wed Oct 8 07:02:22 2025 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76D29264A73 for ; Tue, 1 Jul 2025 13:07:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751375280; cv=none; b=EgBw/VdYwJJ4Gwm6W8UdMNdNvoa9tex2xDRsaZrbEoh8fSlXxer49cK/PTc+9uzbu+E7ddm7u+0YKRgL3PVC1Dhsr+k+jMKYLAHkOhHv2dAS+mieXebgM+e/e2Y9SZAJ4xZtcygUbBRPf+cE5UsJDdoujOb3wnEliWsOG5HXmag= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751375280; c=relaxed/simple; bh=sfo18rhjx+MnvjGPYwSwlFPsNtPEB9rKrlyHRga8FKk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=JcqlykTzoH/3Sx25OPdiL+ICgzTHtymVX8EX6pXNREsMJFJT4mmThEYMf0hcWQad8fP1QruKu+jkLFF1JiWmI5t5lIJbGPyw7CuUtVpIGsYx1lWUSwsYZaQini0/dGMTyRH0UQldkTqkdy1Stt4oSWhqGX4curnULKfMZIwWYyo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=lL8Z+9An; arc=none smtp.client-ip=203.254.224.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="lL8Z+9An" Received: from epcas5p1.samsung.com (unknown [182.195.41.39]) by mailout3.samsung.com (KnoxPortal) with ESMTP id 20250701130756epoutp03db12f37cff7e32826deb2e8e1017a3cb~OIoj1lJ2h1262112621epoutp03Q for ; Tue, 1 Jul 2025 13:07:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout3.samsung.com 20250701130756epoutp03db12f37cff7e32826deb2e8e1017a3cb~OIoj1lJ2h1262112621epoutp03Q DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1751375276; bh=JgnhviKDwcEkzqEavBNjnoGVBk5ClTzXwbk+ec1DARo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lL8Z+9AnRIqdhnPclPzn0hzkfWvFh0y0Ofq0QFj/4FFqb7bQa0mMBAmfjgdJfj7GX TK1GOjyHDjl6m44ShEyA0fJL9EKowiPEXX5uWcI19iifi7itbgupXTLfj8ThQgPWYc 9U2sPadATskrHV3QX2TuTyNcHei8eZBlpQHgMzLM= Received: from epsnrtp01.localdomain (unknown [182.195.42.153]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPS id 20250701130755epcas5p22ab68adeef6288e7c8cc5a7e48343b8a~OIojEhiQA2000520005epcas5p2p; Tue, 1 Jul 2025 13:07:55 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.174]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4bWjxk0DJmz6B9m6; Tue, 1 Jul 2025 13:07:54 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20250701115955epcas5p320cfe73ca33522cd2f9f7970cfde1c63~OHtLRTmHW3228232282epcas5p3d; Tue, 1 Jul 2025 11:59:55 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250701115952epsmtip1c46584c57e4a72ad1d06026394084dbd~OHtITE5Zt1373113731epsmtip1r; Tue, 1 Jul 2025 11:59:52 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, neil.armstrong@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com, Krzysztof Kozlowski Subject: [PATCH v4 1/6] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 HS phy compatible Date: Tue, 1 Jul 2025 17:37:01 +0530 Message-Id: <20250701120706.2219355-2-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250701120706.2219355-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250701115955epcas5p320cfe73ca33522cd2f9f7970cfde1c63 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250701115955epcas5p320cfe73ca33522cd2f9f7970cfde1c63 References: <20250701120706.2219355-1-pritam.sutar@samsung.com> Add a dedicated compatible string for USB HS phy found in this SoC. The SoC requires two clocks, named "phy" and "ref" (same as clocks required by Exynos850). It also requires various power supplies (regulators) for the internal circuitry to work. The required voltages are: * avdd075_usb - 0.75v * avdd18_usb20 - 1.8v * avdd33_usb20 - 3.3v Reviewed-by: Krzysztof Kozlowski Signed-off-by: Pritam Manohar Sutar --- .../bindings/phy/samsung,usb3-drd-phy.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yam= l b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index e906403208c0..2e29ff749bba 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -34,6 +34,7 @@ properties: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usbdrd-phy =20 clocks: minItems: 1 @@ -110,6 +111,15 @@ properties: vddh-usbdp-supply: description: VDDh power supply for the USB DP phy. =20 + avdd075_usb-supply: + description: 0.75V power supply for USB phy + + avdd18_usb20-supply: + description: 1.8V power supply for USB phy + + avdd33_usb20-supply: + description: 3.3V power supply for USB phy + required: - compatible - clocks @@ -235,6 +245,33 @@ allOf: =20 reg-names: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-usbdrd-phy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: phy + - const: ref + + reg: + maxItems: 1 + + reg-names: + maxItems: 1 + + required: + - avdd075_usb-supply + - avdd18_usb20-supply + - avdd33_usb20-supply =20 unevaluatedProperties: false =20 --=20 2.34.1 From nobody Wed Oct 8 07:02:22 2025 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5497C2749CB for ; Tue, 1 Jul 2025 13:08:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751375287; cv=none; b=mQUPNnnxQMisw0Fj41bW9TgLkeGwJ1tgr9/y6LL9MQ/q4+n9+dTTRHoyABi0HZv0WNqkff1WgCZv7h1PIx1+VEtmkjQanG8qKYLsn0X+k29rU2ZZzAdbfKDu2OumIe9K8ozAMmWeL/ATTaYAJWilreJjkuJFWZvy7V+TJf37DLE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751375287; c=relaxed/simple; bh=2gZY7Acfhkay75+KSoYtQAw+ivQxiGgR9g9578HYzG0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=FTG9shblN9kJ3drrdcp+0DbzjVGMgpnUhKnLsRxwNO9L34HpEVCp/mhx/VJW9tJxJ+UcBoYFyTSsgqRHvstkDRnW/+Idz83vBzwic03XmCumb7MFChXD5fA1d+SaMF9IVGUeTYBw48/vVUYyTRCcUoIDJOkvbCSfdPAexxCcHtQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=UFlp1ZHA; arc=none smtp.client-ip=203.254.224.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="UFlp1ZHA" Received: from epcas5p3.samsung.com (unknown [182.195.41.41]) by mailout3.samsung.com (KnoxPortal) with ESMTP id 20250701130803epoutp03acf68e210f0fb6f99b6c7a8574b4b5b5~OIoqCWcUW1262312623epoutp03G for ; Tue, 1 Jul 2025 13:08:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout3.samsung.com 20250701130803epoutp03acf68e210f0fb6f99b6c7a8574b4b5b5~OIoqCWcUW1262312623epoutp03G DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1751375283; bh=I75Ks8WoTjVRhBjGREqmgMHMQs8DiCAyjM7jzwXjn2M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UFlp1ZHAtPwD/N228WA+9c9+2Hf/pPSkgnuK4wh69lSY88VZj9vEyu14Jobnfk3WN eyMaIDOJIam5ILmt2Lk4SPN/RNXIQhVT+mR+/PdNCuLqeuyRFx4kDKBwfvZCGj/h6t wXZm2h2ElVXlrKfm7HyJ+a/yTZ/ar8S36zCHR29Y= Received: from epsnrtp02.localdomain (unknown [182.195.42.154]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPS id 20250701130802epcas5p126d498a02a08cdfb95c3c941e11bb750~OIopYeCuN1091810918epcas5p15; Tue, 1 Jul 2025 13:08:02 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.174]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4bWjxr4kfbz2SSKY; Tue, 1 Jul 2025 13:08:00 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250701115959epcas5p40f28954777a620b018251301eea13873~OHtOXVtHF2133421334epcas5p44; Tue, 1 Jul 2025 11:59:59 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250701115956epsmtip1bf43d7f7886a0107ac300806328c6f3a~OHtLf3odZ1547115471epsmtip1J; Tue, 1 Jul 2025 11:59:56 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, neil.armstrong@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v4 2/6] phy: exynos5-usbdrd: support HS phy for ExynosAutov920 Date: Tue, 1 Jul 2025 17:37:02 +0530 Message-Id: <20250701120706.2219355-3-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250701120706.2219355-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250701115959epcas5p40f28954777a620b018251301eea13873 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250701115959epcas5p40f28954777a620b018251301eea13873 References: <20250701120706.2219355-1-pritam.sutar@samsung.com> This SoC has a single USB 3.1 DRD combo phy that supports both UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD HS phy controllers those only support the UTMI+ (HS) interface. Support only UTMI+ port for this SoC which is very similar to what the existing Exynos850 supports. This SoC shares phy isol between USBs. Bypass PHY isol when first USB is powered on and enable it when all of then are powered off. Add required change in phy driver to support HS phy for this SoC. Reviewed-by: Neil Armstrong Signed-off-by: Pritam Manohar Sutar --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 131 ++++++++++++++++++++ include/linux/soc/samsung/exynos-regs-pmu.h | 2 + 2 files changed, 133 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index dd660ebe8045..64f3316f6ad4 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -480,6 +480,8 @@ struct exynos5_usbdrd_phy { enum typec_orientation orientation; }; =20 +static atomic_t usage_count =3D ATOMIC_INIT(0); + static inline struct exynos5_usbdrd_phy *to_usbdrd_phy(struct phy_usb_instance *inst) { @@ -2054,6 +2056,132 @@ static const struct exynos5_usbdrd_phy_drvdata exyn= os990_usbdrd_phy =3D { .n_regulators =3D ARRAY_SIZE(exynos5_regulator_names), }; =20 +static int exynosautov920_usbdrd_phy_init(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_UTMI) { + /* Bypass PHY isol when first USB is powered on */ + if ((atomic_inc_return(&usage_count) =3D=3D 1)) + inst->phy_cfg->phy_isol(inst, false); + } + + /* UTMI or PIPE3 specific init */ + inst->phy_cfg->phy_init(phy_drd); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static int exynosautov920_usbdrd_phy_exit(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret =3D 0; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_UTMI) { + exynos850_usbdrd_phy_exit(phy); + + /* enable PHY isol when all USBs are powered off */ + if (atomic_dec_and_test(&usage_count)) + inst->phy_cfg->phy_isol(inst, true); + } + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static int exynosautov920_usbdrd_phy_power_on(struct phy *phy) +{ + int ret; + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + + dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n"); + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + if (ret) + return ret; + + /* Enable supply */ + ret =3D regulator_bulk_enable(phy_drd->drv_data->n_regulators, + phy_drd->regulators); + if (ret) { + dev_err(phy_drd->dev, "Failed to enable PHY regulator(s)\n"); + goto fail_supply; + } + + return 0; + +fail_supply: + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + + return ret; +} + +static int exynosautov920_usbdrd_phy_power_off(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + + dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n"); + + /* Disable supply */ + regulator_bulk_disable(phy_drd->drv_data->n_regulators, + phy_drd->regulators); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + + return 0; +} + +static const char * const exynosautov920_regulator_names[] =3D { + "avdd075_usb", "avdd18_usb20", "avdd33_usb20", +}; + +static const struct phy_ops exynosautov920_usbdrd_phy_ops =3D { + .init =3D exynosautov920_usbdrd_phy_init, + .exit =3D exynosautov920_usbdrd_phy_exit, + .power_on =3D exynosautov920_usbdrd_phy_power_on, + .power_off =3D exynosautov920_usbdrd_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static const struct exynos5_usbdrd_phy_config phy_cfg_exynosautov920[] =3D= { + { + .id =3D EXYNOS5_DRDPHY_UTMI, + .phy_isol =3D exynos5_usbdrd_phy_isol, + .phy_init =3D exynos850_usbdrd_utmi_init, + }, +}; + +static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_phy = =3D { + .phy_cfg =3D phy_cfg_exynosautov920, + .phy_ops =3D &exynosautov920_usbdrd_phy_ops, + .pmu_offset_usbdrd0_phy =3D EXYNOSAUTOV920_PHY_CTRL_USB20, + .clk_names =3D exynos5_clk_names, + .n_clks =3D ARRAY_SIZE(exynos5_clk_names), + .core_clk_names =3D exynos5_core_clk_names, + .n_core_clks =3D ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names =3D exynosautov920_regulator_names, + .n_regulators =3D ARRAY_SIZE(exynosautov920_regulator_names), +}; + static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] =3D { { .id =3D EXYNOS5_DRDPHY_UTMI, @@ -2260,6 +2388,9 @@ static const struct of_device_id exynos5_usbdrd_phy_o= f_match[] =3D { }, { .compatible =3D "samsung,exynos990-usbdrd-phy", .data =3D &exynos990_usbdrd_phy + }, { + .compatible =3D "samsung,exynosautov920-usbdrd-phy", + .data =3D &exynosautov920_usbdrd_phy }, { }, }; diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/so= c/samsung/exynos-regs-pmu.h index 71e0c09a49eb..4923f9be3d1f 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -688,4 +688,6 @@ #define GS101_GRP2_INTR_BID_UPEND (0x0208) #define GS101_GRP2_INTR_BID_CLEAR (0x020c) =20 +/* exynosautov920 */ +#define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ --=20 2.34.1 From nobody Wed Oct 8 07:02:22 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A8C010F9 for ; Wed, 2 Jul 2025 04:15:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.24 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751429733; cv=none; b=F0j49QfqKB4rlFQcQUJ3brVkLjUrU1x9wbVttu92wm4D1oGawvyOiLlwuefjNFaZsJLevG8fGJpcpyOq0zXT+bBUpNrYbMNUGv7yhhgTLzfVx3wAEDhrnKvyFJkG4LA4lJHEXUnMfz7Q2W6Y0iPQSKRw0aM6qzGoqIt3UtzcbGQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751429733; c=relaxed/simple; bh=jE20g9Zox0XFvzxD2FICODTEPEej0WovQVF70Jz/RPo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=kX7UfBsgkShpoCqM7jXzSMJn63r501ax07Xp09fePn5IwkXKqyus2HpTPt2UzWgrKQXH/tnxR2SWg4KZGYcoQ2g9+J8frr9C/oNSlIpwmV9F2+FlDKvJKXI9MfLEq0DjpX3G5En9Ku4qUY0i4gvL0E8QXjJZpPV3InWgURXNoXs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=CW7cJ8lN; arc=none smtp.client-ip=203.254.224.24 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="CW7cJ8lN" Received: from epcas5p1.samsung.com (unknown [182.195.41.39]) by mailout1.samsung.com (KnoxPortal) with ESMTP id 20250702041529epoutp0198b7ed6c59cdfb3f46d067d73787bc84~OVA89aygD0993409934epoutp01E for ; Wed, 2 Jul 2025 04:15:29 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20250702041529epoutp0198b7ed6c59cdfb3f46d067d73787bc84~OVA89aygD0993409934epoutp01E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1751429729; bh=dzSOjmVG/qviZa0J9qW06zNK9D7hAaYltgUrXMSHzgY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CW7cJ8lNmOX7W7eKnWmaDaGdf2TsVi/E6M2NaEVnqX9+IRFo4FxbZgrFpGxBJkwSa t6ZkbEkZXeEMoLxaje1BNULjPREApZ8ZZytIFgTpxPVeXloy+e9mUCPsfDSGDrN0AY zttuqgdEnSSLevfWP3W5B02sed8ozo+YBTyecyxU= Received: from epsnrtp01.localdomain (unknown [182.195.42.153]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPS id 20250702041528epcas5p11f7b012fab5de2fb22c70089c32308d9~OVA7rT1ZB2996129961epcas5p13; Wed, 2 Jul 2025 04:15:28 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.175]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4bX64t0JyTz6B9mM; Wed, 2 Jul 2025 04:15:26 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20250701120002epcas5p2c4d728d599a819057bcc40b724881276~OHtRg2gIH0511605116epcas5p2i; Tue, 1 Jul 2025 12:00:02 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250701115959epsmtip1bb515e6078065cef456ed1ede6dc339f~OHtOlyyB_1373213732epsmtip14; Tue, 1 Jul 2025 11:59:59 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, neil.armstrong@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v4 3/6] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 combo HS phy Date: Tue, 1 Jul 2025 17:37:03 +0530 Message-Id: <20250701120706.2219355-4-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250701120706.2219355-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250701120002epcas5p2c4d728d599a819057bcc40b724881276 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250701120002epcas5p2c4d728d599a819057bcc40b724881276 References: <20250701120706.2219355-1-pritam.sutar@samsung.com> This phy supports USB3.1 SSP+(10Gbps) protocol and is backwards compatible to the USB3.0 SS(5Gbps). 'Add-on USB2.0' phy is added to support USB2.0 HS(480Mbps), FS(12Mbps) and LS(1.5Mbps) data rates. These two phys are combined to form a combo phy. Add a dedicated compatible string for USB combo HS phy found in this SoC. The SoC requires two clocks, named "phy" and "ref" and various power supplies (regulators) for the internal circuitry to work. The required voltages are: * avdd075_usb - 0.75v * avdd18_usb20 - 1.8v * avdd33_usb20 - 3.3v Add schema only for 'Add-on USB2.0' HS phy in this combo phy. Signed-off-by: Pritam Manohar Sutar --- Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yam= l b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 2e29ff749bba..b024339b5acc 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -34,6 +34,7 @@ properties: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy =20 clocks: @@ -250,6 +251,7 @@ allOf: compatible: contains: enum: + - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy then: properties: --=20 2.34.1 From nobody Wed Oct 8 07:02:22 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AA19274B3D for ; Tue, 1 Jul 2025 13:08:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751375296; cv=none; b=JHQRP4UYeIIOq/ifc6aFmJ07FcLcP5Din5FhFkmiok9F4Z1gESytx2xSWuSN6NWWYPkF06BuXgrS2avspyF5/TprIJtKz7WOeTBjwHuMGpbUt16WhtK5OTtpArbLk/q14jleZSg2Xi7Sap6z1XsP6ibuPPTLjj7bYFouvcsOxx0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751375296; c=relaxed/simple; bh=vs9W3rgstivY7xP5VrWM8hnl9oWGwLHJmx91xXqYOV4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=gSqs8yAn1MIGMmP26e4Y6rzk0aC6n8hKtZy5vMAIR+2bPRlblPXsp6RDnaM61cqlPYalCbQXTJvCYzqeEKVGjhcZMmj3tEHj5cbohWG+UZPoW+7tSrmIg1Eh6dPaRCtQAsZDEOVwelJR5pMJSmEFq3vr2RFXMWcoR0bt01a0/aU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=UFW9uTot; arc=none smtp.client-ip=203.254.224.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="UFW9uTot" Received: from epcas5p4.samsung.com (unknown [182.195.41.42]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20250701130809epoutp0425602ac4374e6b6afb558e06f5af6cc3~OIovvQ24j2179521795epoutp04X for ; Tue, 1 Jul 2025 13:08:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250701130809epoutp0425602ac4374e6b6afb558e06f5af6cc3~OIovvQ24j2179521795epoutp04X DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1751375289; bh=pvoHxXvlrlKde8j+ma+r7GZr6pK2wxjLK7jGp5m/Tr8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UFW9uTotF5JNcXZqMUxLXpPYNe2VF0PhCDzUbqiVrQleH4Fvr/e1fc9TiYt0Qx43f Lzv4Tm0/LXOmz7MH7odGsJNAHtiwFT8vQHJW/zfpkPwAJnibqrrW1h4cnvC38cAXcQ Yy4OQq/UTzcHjiJdZZvVYpWQLORVyG5oCMzp02s0= Received: from epsnrtp03.localdomain (unknown [182.195.42.155]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPS id 20250701130808epcas5p141519839fbd01223fd53a85cccefabee~OIouvWza11094810948epcas5p1p; Tue, 1 Jul 2025 13:08:08 +0000 (GMT) Received: from epcas5p3.samsung.com (unknown [182.195.38.182]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4bWjxy3lmFz3hhT7; Tue, 1 Jul 2025 13:08:06 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20250701120005epcas5p24a8cfb5037524127416756fb723ccae7~OHtUl4_WI0527505275epcas5p2u; Tue, 1 Jul 2025 12:00:05 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250701120002epsmtip1963c41750682632818c9ba20a18b8e5e~OHtRvKFrW1373213732epsmtip15; Tue, 1 Jul 2025 12:00:02 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, neil.armstrong@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v4 4/6] phy: exynos5-usbdrd: support HS combo phy for ExynosAutov920 Date: Tue, 1 Jul 2025 17:37:04 +0530 Message-Id: <20250701120706.2219355-5-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250701120706.2219355-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250701120005epcas5p24a8cfb5037524127416756fb723ccae7 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250701120005epcas5p24a8cfb5037524127416756fb723ccae7 References: <20250701120706.2219355-1-pritam.sutar@samsung.com> This SoC has a single USB 3.1 DRD combo phy that supports both UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD HS phy controllers those only support the UTMI+ (HS) interface. Support UTMI+ combo phy for this SoC which is somewhat simmilar to what the existing Exynos850 support does. The difference is that some register offsets and bit fields are defferent from Exynos850. Add required change in phy driver to support combo HS phy for this SoC. Reviewed-by: Neil Armstrong Signed-off-by: Pritam Manohar Sutar --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 212 +++++++++++++++++++++++ 1 file changed, 212 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index 64f3316f6ad4..8a1cd63b29ce 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -41,6 +41,13 @@ #define EXYNOS2200_CLKRST_LINK_PCLK_SEL BIT(1) =20 #define EXYNOS2200_DRD_UTMI 0x10 + +/* ExynosAutov920 bits */ +#define UTMICTL_FORCE_UTMI_SUSPEND BIT(13) +#define UTMICTL_FORCE_UTMI_SLEEP BIT(12) +#define UTMICTL_FORCE_DPPULLDOWN BIT(9) +#define UTMICTL_FORCE_DMPULLDOWN BIT(8) + #define EXYNOS2200_UTMI_FORCE_VBUSVALID BIT(1) #define EXYNOS2200_UTMI_FORCE_BVALID BIT(0) =20 @@ -250,6 +257,22 @@ #define EXYNOS850_DRD_HSP_TEST 0x5c #define HSP_TEST_SIDDQ BIT(24) =20 +#define EXYNOSAUTOV920_DRD_HSP_CLKRST 0x100 +#define HSPCLKRST_PHY20_SW_PORTRESET BIT(3) +#define HSPCLKRST_PHY20_SW_POR BIT(1) +#define HSPCLKRST_PHY20_SW_POR_SEL BIT(0) + +#define EXYNOSAUTOV920_DRD_HSPCTL 0x104 +#define HSPCTRL_VBUSVLDEXTSEL BIT(13) +#define HSPCTRL_VBUSVLDEXT BIT(12) +#define HSPCTRL_EN_UTMISUSPEND BIT(9) +#define HSPCTRL_COMMONONN BIT(8) + +#define EXYNOSAUTOV920_DRD_HSP_TEST 0x10c + +#define EXYNOSAUTOV920_DRD_HSPPLLTUNE 0x110 +#define HSPPLLTUNE_FSEL GENMASK(18, 16) + /* Exynos9 - GS101 */ #define EXYNOS850_DRD_SECPMACTL 0x48 #define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12) @@ -2056,6 +2079,139 @@ static const struct exynos5_usbdrd_phy_drvdata exyn= os990_usbdrd_phy =3D { .n_regulators =3D ARRAY_SIZE(exynos5_regulator_names), }; =20 +static void +exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + /* + * Disable HWACG (hardware auto clock gating control). This + * forces QACTIVE signal in Q-Channel interface to HIGH level, + * to make sure the PHY clock is not gated by the hardware. + */ + reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg |=3D LINKCTRL_FORCE_QACT; + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + /* De-assert link reset */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_CLKRST); + reg &=3D ~CLKRST_LINK_SW_RST; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); + + /* Set PHY POR High */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + reg |=3D HSPCLKRST_PHY20_SW_POR | HSPCLKRST_PHY20_SW_POR_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + + /* Enable UTMI+ */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_UTMI); + reg &=3D ~(UTMICTL_FORCE_UTMI_SUSPEND | UTMICTL_FORCE_UTMI_SLEEP | + UTMICTL_FORCE_DPPULLDOWN | UTMICTL_FORCE_DMPULLDOWN); + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI); + + /* set phy clock & control HS phy */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + reg |=3D HSPCTRL_EN_UTMISUSPEND | HSPCTRL_COMMONONN; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + + fsleep(100); + + /* Set VBUS Valid and DP-Pull up control by VBUS pad usage */ + reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg |=3D FIELD_PREP_CONST(LINKCTRL_BUS_FILTER_BYPASS, 0xf); + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + reg =3D readl(reg_phy + EXYNOS2200_DRD_UTMI); + reg |=3D EXYNOS2200_UTMI_FORCE_VBUSVALID | EXYNOS2200_UTMI_FORCE_BVALID; + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI); + + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + reg |=3D HSPCTRL_VBUSVLDEXTSEL | HSPCTRL_VBUSVLDEXT; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + + /* Setting FSEL for refference clock */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSPPLLTUNE); + reg &=3D ~HSPPLLTUNE_FSEL; + switch (phy_drd->extrefclk) { + case EXYNOS5_FSEL_50MHZ: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 7); + break; + case EXYNOS5_FSEL_26MHZ: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 6); + break; + case EXYNOS5_FSEL_24MHZ: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 2); + break; + case EXYNOS5_FSEL_20MHZ: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 1); + break; + case EXYNOS5_FSEL_19MHZ2: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 0); + break; + default: + dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", + phy_drd->extrefclk); + break; + } + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPPLLTUNE); + + /* Enable PHY Power Mode */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + reg &=3D ~HSP_TEST_SIDDQ; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + + /* before POR low, 10us delay is needed to Finish PHY reset */ + fsleep(10); + + /* Set PHY POR Low */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + reg |=3D HSPCLKRST_PHY20_SW_POR_SEL; + reg &=3D ~(HSPCLKRST_PHY20_SW_POR | HSPCLKRST_PHY20_SW_PORTRESET); + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + + /* after POR low and delay 75us, PHYCLOCK is guaranteed. */ + fsleep(75); + + /* force pipe3 signal for link */ + reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg |=3D LINKCTRL_FORCE_PIPE_EN; + reg &=3D ~LINKCTRL_FORCE_PHYSTATUS; + reg |=3D LINKCTRL_FORCE_RXELECIDLE; + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); +} + +static void +exynosautov920_usbdrd_hsphy_disable(struct exynos5_usbdrd_phy *phy_drd) +{ + u32 reg; + void __iomem *reg_phy =3D phy_drd->reg_phy; + + /* set phy clock & control HS phy */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_UTMI); + reg |=3D UTMICTL_FORCE_UTMI_SUSPEND | UTMICTL_FORCE_UTMI_SLEEP; + reg &=3D ~(UTMICTL_FORCE_DPPULLDOWN | UTMICTL_FORCE_DMPULLDOWN); + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI); + + /* Disable PHY Power Mode */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + reg |=3D HSP_TEST_SIDDQ; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + + /* clear force q-channel */ + reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg &=3D ~LINKCTRL_FORCE_QACT; + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + /* link sw reset is need for USB_DP/DM high-z in host mode */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_CLKRST); + reg |=3D CLKRST_LINK_SW_RST; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); + fsleep(10); + reg &=3D ~CLKRST_LINK_SW_RST; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); +} + static int exynosautov920_usbdrd_phy_init(struct phy *phy) { struct phy_usb_instance *inst =3D phy_get_drvdata(phy); @@ -2103,6 +2259,29 @@ static int exynosautov920_usbdrd_phy_exit(struct phy= *phy) return 0; } =20 +static int exynosautov920_usbdrd_combo_phy_exit(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret =3D 0; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_UTMI) { + exynosautov920_usbdrd_hsphy_disable(phy_drd); + + /* enable PHY isol when all USBs are powered off */ + if (atomic_dec_and_test(&usage_count)) + inst->phy_cfg->phy_isol(inst, true); + } + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + static int exynosautov920_usbdrd_phy_power_on(struct phy *phy) { int ret; @@ -2154,6 +2333,36 @@ static const char * const exynosautov920_regulator_n= ames[] =3D { "avdd075_usb", "avdd18_usb20", "avdd33_usb20", }; =20 +static const struct phy_ops exynosautov920_usbdrd_combo_hsphy_ops =3D { + .init =3D exynosautov920_usbdrd_phy_init, + .exit =3D exynosautov920_usbdrd_combo_phy_exit, + .power_on =3D exynosautov920_usbdrd_phy_power_on, + .power_off =3D exynosautov920_usbdrd_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static const struct +exynos5_usbdrd_phy_config usbdrd_hsphy_cfg_exynosautov920[] =3D { + { + .id =3D EXYNOS5_DRDPHY_UTMI, + .phy_isol =3D exynos5_usbdrd_phy_isol, + .phy_init =3D exynosautov920_usbdrd_utmi_init, + }, +}; + +static const +struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_combo_hsphy =3D { + .phy_cfg =3D usbdrd_hsphy_cfg_exynosautov920, + .phy_ops =3D &exynosautov920_usbdrd_combo_hsphy_ops, + .pmu_offset_usbdrd0_phy =3D EXYNOSAUTOV920_PHY_CTRL_USB20, + .clk_names =3D exynos5_clk_names, + .n_clks =3D ARRAY_SIZE(exynos5_clk_names), + .core_clk_names =3D exynos5_core_clk_names, + .n_core_clks =3D ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names =3D exynosautov920_regulator_names, + .n_regulators =3D ARRAY_SIZE(exynosautov920_regulator_names), +}; + static const struct phy_ops exynosautov920_usbdrd_phy_ops =3D { .init =3D exynosautov920_usbdrd_phy_init, .exit =3D exynosautov920_usbdrd_phy_exit, @@ -2388,6 +2597,9 @@ static const struct of_device_id exynos5_usbdrd_phy_o= f_match[] =3D { }, { .compatible =3D "samsung,exynos990-usbdrd-phy", .data =3D &exynos990_usbdrd_phy + }, { + .compatible =3D "samsung,exynosautov920-usbdrd-combo-hsphy", + .data =3D &exynosautov920_usbdrd_combo_hsphy }, { .compatible =3D "samsung,exynosautov920-usbdrd-phy", .data =3D &exynosautov920_usbdrd_phy --=20 2.34.1 From nobody Wed Oct 8 07:02:22 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C51D2274FF0 for ; Tue, 1 Jul 2025 13:08:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751375300; cv=none; b=ZGK/RMLx89JrmLmelwD49NB/dqVpEGX+wAQDtD2cC0WjbOzbX220ykKxS1J6a9U0TQvxwlPQlo4R2KoGSXq3LnGl3Bk3sSVld/X0wuZ0TJqpPdAL1h1AM7MHKIIIdsNar1bzrkDytieXaBEm6RTE79re2eVLGlw649mOpvyhCU8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751375300; c=relaxed/simple; bh=fwEXZ2vcv3xXMfBBmX94hX1enBc8ZaZug3xf8S/Vpzc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=SZmTh7+S20QR0oMWsgRNbGeJNcprqhaH8LjwBMq6l+Ac8fSJZ/NGpTyhBAINJhwZGRvPT1Ycgp+pNuMzXSb418G4iabDn7yPUjf2itxnx+jon2K/9Bf5OFetMP5hHx/UF5bEJRBQbU90qSrY3J67c4veZGwoYlyyPpAFX+pGovI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=mA2tEYM+; arc=none smtp.client-ip=203.254.224.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="mA2tEYM+" Received: from epcas5p2.samsung.com (unknown [182.195.41.40]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20250701130816epoutp043aadccc8353775d930bc5c2e41c0967a~OIo14BF3Q2171121711epoutp04Y for ; Tue, 1 Jul 2025 13:08:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250701130816epoutp043aadccc8353775d930bc5c2e41c0967a~OIo14BF3Q2171121711epoutp04Y DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1751375296; bh=RSiRk+FOT4DNKqboAFamlYzH4Uom4Urrgp6xmTmHgRM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mA2tEYM+jXhlIO9Hc0oizFlLK21VASQmoBBzkUAjKz97MZXEFK4rpqphQR8t8zrzi 1VjGcpIFbyA2PybuW7awaRmQBB7fHdvoT4T8EJLqqMcz4Kks7NkLk/zptObhu+ABhb dAvR1wEWVtS/XW1e9GXYKmoYl1xVn2BRCqX0Fpxc= Received: from epsnrtp03.localdomain (unknown [182.195.42.155]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPS id 20250701130815epcas5p2a6c34c804d9dc216064f6315c128ff85~OIo03E2Xk2226922269epcas5p2X; Tue, 1 Jul 2025 13:08:15 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.178]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4bWjy50DQ9z3hhT4; Tue, 1 Jul 2025 13:08:13 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250701120009epcas5p46bc2870446c499f9c0008c1d396650bb~OHtXw9dpn2412624126epcas5p4R; Tue, 1 Jul 2025 12:00:09 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250701120006epsmtip18b4477dd17fd0b164ffd5e6b5429271b~OHtU0vI6c1563115631epsmtip1i; Tue, 1 Jul 2025 12:00:06 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, neil.armstrong@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v4 5/6] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 combo SS phy Date: Tue, 1 Jul 2025 17:37:05 +0530 Message-Id: <20250701120706.2219355-6-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250701120706.2219355-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250701120009epcas5p46bc2870446c499f9c0008c1d396650bb X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250701120009epcas5p46bc2870446c499f9c0008c1d396650bb References: <20250701120706.2219355-1-pritam.sutar@samsung.com> This phy supports USB3.1 SSP+(10Gbps) protocol and is backwards compatible to the USB3.0 SS(5Gbps). 'Add-on USB2.0' phy is required to support USB2.0 HS(480Mbps), FS(12Mbps) and LS(1.5Mbps) data rates. These two phys are combined to form a combo phy. Add a dedicated compatible string for USB combo SS phy found in this SoC. The SoC requires two clocks, named "phy" and "ref" and various power supplies (regulators) for the internal circuitry to work. The required voltages are: * avdd075_usb - 0.75v * avdd18_usb20 - 1.8v * avdd33_usb20 - 3.3v Add schema only for 'USB3.1 SSP+' SS phy in this commit. Signed-off-by: Pritam Manohar Sutar --- Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yam= l b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index b024339b5acc..b43b2ecbc132 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -34,6 +34,7 @@ properties: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usb31drd-combo-ssphy - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy =20 @@ -251,6 +252,7 @@ allOf: compatible: contains: enum: + - samsung,exynosautov920-usb31drd-combo-ssphy - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy then: --=20 2.34.1 From nobody Wed Oct 8 07:02:22 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5D43274FD0 for ; Tue, 1 Jul 2025 13:08:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.24 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751375306; cv=none; b=Q4NO003FQ/AELIWlRFA2tBjRkpoEpxZD/CexIo/wbm8wriISnLCOYyDoy+HFYcUaPIIuYyLEGA2kYC9tN6q0wYCM74F5lsq9UWZwTrnQHhSJ8jlgtgfuzjLGlb0yaFsI0LlcUnFv6G0905QzjJibg58Guq5uP9OQen83X6MxSl4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751375306; c=relaxed/simple; bh=GsIDiGM4SIKLy61S3XbEaiNxOnRQgy88hSTIDk7bJas=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=c8nYXFL7saGgQZamOX315DaBQemd4czzJQIdnvXaqiGdGWQRWLIMpMsZvaR0vLy1eQSyDkHFyOr4L5akeSCx5Ew1LWYNcEkMPS/Thc+c7rIsTvQlkLvV8WnRUJHe58k+t+9VeRzg6wjUplyvbB2w+hlhSYtIraTIm+D2ck3XmmU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=BOTAPZNn; arc=none smtp.client-ip=203.254.224.24 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="BOTAPZNn" Received: from epcas5p1.samsung.com (unknown [182.195.41.39]) by mailout1.samsung.com (KnoxPortal) with ESMTP id 20250701130822epoutp01a5d4710b5afee0bb336aa06f146712d3~OIo8TqqU11119711197epoutp010 for ; Tue, 1 Jul 2025 13:08:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20250701130822epoutp01a5d4710b5afee0bb336aa06f146712d3~OIo8TqqU11119711197epoutp010 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1751375303; bh=jJ167illKN1TO8G0fjABg4r+eK06fCfby4plELWDkek=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BOTAPZNn5LylCo+g0S/V2Sz21ViRc9Bw0sq6CZSTPAjWQSzx2OhKguFIF7nrPMlkI Tpo/9y3VXibQz9Si40ZCx4+W00s9zgR/LyaOtsmKur1EIpbm5JXhrwakNlAxnUBo+4 KTtHj9sNpu25vu6m+FjWOQhKPj1SjZfMj+aeJkRo= Received: from epsnrtp03.localdomain (unknown [182.195.42.155]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPS id 20250701130822epcas5p30fdd35c885c18e2142f3b6e3e8c81add~OIo7yr9vY0162201622epcas5p3n; Tue, 1 Jul 2025 13:08:22 +0000 (GMT) Received: from epcas5p1.samsung.com (unknown [182.195.38.180]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4bWjyD4nc9z3hhT7; Tue, 1 Jul 2025 13:08:20 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250701120012epcas5p4def7f4d718241407b598ad961d32c1f8~OHtaxgs2v2655426554epcas5p4F; Tue, 1 Jul 2025 12:00:12 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250701120009epsmtip1f9012c673877687574ad3fd991ebdd62~OHtX5xkLN1547115471epsmtip1o; Tue, 1 Jul 2025 12:00:09 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, neil.armstrong@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v4 6/6] phy: exynos5-usbdrd: support SS combo phy for ExynosAutov920 Date: Tue, 1 Jul 2025 17:37:06 +0530 Message-Id: <20250701120706.2219355-7-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250701120706.2219355-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250701120012epcas5p4def7f4d718241407b598ad961d32c1f8 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250701120012epcas5p4def7f4d718241407b598ad961d32c1f8 References: <20250701120706.2219355-1-pritam.sutar@samsung.com> This SoC has a DWC3 compatible link controller and single USB 3.1 DRD combo phy that supports both UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD HS phy controllers those only support the UTMI+ (HS) interface. Combo phy is combination of two phys. Among these phys, one supports USB3.1 SSP+(10Gbps) protocol and is backwards compatible to the USB3.0 SS(5Gbps). 'Add-on USB2.0' phy is required to support USB2.0 HS(480Mbps), FS(12Mbps) and LS(1.5Mbps) data rates. Add required change in phy driver to support combo SS phy for this SoC. Reviewed-by: Neil Armstrong Signed-off-by: Pritam Manohar Sutar --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 327 +++++++++++++++++++- include/linux/soc/samsung/exynos-regs-pmu.h | 1 + 2 files changed, 324 insertions(+), 4 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index 8a1cd63b29ce..9e70bc815937 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -273,6 +273,36 @@ #define EXYNOSAUTOV920_DRD_HSPPLLTUNE 0x110 #define HSPPLLTUNE_FSEL GENMASK(18, 16) =20 +/* ExynosAutov920 phy usb31drd port reg */ +#define EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL 0x000 +#define PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN BIT(5) +#define PHY_RST_CTRL_PIPE_LANE0_RESET_N BIT(4) +#define PHY_RST_CTRL_PHY_RESET_OVRD_EN BIT(1) +#define PHY_RST_CTRL_PHY_RESET BIT(0) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0 0x0004 +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR GENMASK(31, 16) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK BIT(8) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK BIT(4) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL BIT(0) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1 0x0008 + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2 0x000c +#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN BIT(0) +#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA GENMASK(31, 16) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0 0x100 +#define PHY_CONFIG0_PHY0_PMA_PWR_STABLE BIT(14) +#define PHY_CONFIG0_PHY0_PCS_PWR_STABLE BIT(13) +#define PHY_CONFIG0_PHY0_ANA_PWR_EN BIT(1) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7 0x11c +#define PHY_CONFIG7_PHY_TEST_POWERDOWN BIT(24) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4 0x110 +#define PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN BIT(2) + /* Exynos9 - GS101 */ #define EXYNOS850_DRD_SECPMACTL 0x48 #define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12) @@ -2079,6 +2109,253 @@ static const struct exynos5_usbdrd_phy_drvdata exyn= os990_usbdrd_phy =3D { .n_regulators =3D ARRAY_SIZE(exynos5_regulator_names), }; =20 +static void +exynosautov920_usb31drd_cr_clk(struct exynos5_usbdrd_phy *phy_drd, bool hi= gh) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg =3D 0; + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + if (high) + reg |=3D PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + else + reg &=3D ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + fsleep(1); +} + +static void +exynosautov920_usb31drd_port_phy_ready(struct exynos5_usbdrd_phy *phy_drd) +{ + struct device *dev =3D phy_drd->dev; + void __iomem *reg_phy =3D phy_drd->reg_phy; + static const unsigned int timeout_us =3D 20000; + static const unsigned int sleep_us =3D 40; + u32 reg =3D 0; + int err; + + /* Clear cr_para_con */ + reg &=3D ~(PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK | + PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR); + reg |=3D PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1); + writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + + exynosautov920_usb31drd_cr_clk(phy_drd, true); + exynosautov920_usb31drd_cr_clk(phy_drd, false); + + /* + * The maximum time from phy reset de-assertion to de-assertion of + * tx/rx_ack can be as high as 5ms in fast simulation mode. + * Time to phy ready is < 20ms + */ + err =3D readl_poll_timeout(reg_phy + + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0, + reg, !(reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK), + sleep_us, timeout_us); + if (err) + dev_err(dev, "timed out waiting for rx/tx_ack: %#.8x\n", reg); + + reg &=3D ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); +} + +static void +exynosautov920_usb31drd_cr_write(struct exynos5_usbdrd_phy *phy_drd, + u16 addr, u16 data) +{ + struct device *dev =3D phy_drd->dev; + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 cnt =3D 0; + u32 reg =3D 0; + + /* Pre Clocking */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + reg |=3D PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* + * tx clks must be available prior to assertion of tx req. + * tx pstate p2 to p0 transition directly is not permitted. + * tx clk ready must be asserted synchronously on tx clk prior + * to internal transmit clk alignment sequence in the phy + * when entering from p2 to p1 to p0. + */ + do { + exynosautov920_usb31drd_cr_clk(phy_drd, true); + exynosautov920_usb31drd_cr_clk(phy_drd, false); + cnt++; + } while (cnt < 15); + + reg &=3D ~PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* + * tx data path is active when tx lane is in p0 state + * and tx data en asserted. enable cr_para_wr_en. + */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + reg &=3D ~PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA; + reg |=3D FIELD_PREP(PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA, data) | + PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + + /* write addr */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + reg &=3D ~PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR; + reg |=3D FIELD_PREP(PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR, addr) | + PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK | + PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* check cr_para_ack*/ + cnt =3D 0; + do { + /* + * data symbols are captured by phy on rising edge of the + * tx_clk when tx data enabled. + * completion of the write cycle is acknowledged by assertion + * of the cr_para_ack. + */ + exynosautov920_usb31drd_cr_clk(phy_drd, true); + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + if ((reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK)) + break; + + exynosautov920_usb31drd_cr_clk(phy_drd, false); + + /* + * wait for minimum of 10 cr_para_clk cycles after phy reset + * is negated, before accessing control regs to allow for + * internal resets. + */ + cnt++; + } while (cnt < 10); + + if (cnt =3D=3D 10) + dev_dbg(dev, "CR write failed to 0x%04x\n", addr); + else + exynosautov920_usb31drd_cr_clk(phy_drd, false); +} + +static void +exynosautov920_usb31drd_phy_reset(struct exynos5_usbdrd_phy *phy_drd, int = val) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + reg &=3D ~PHY_RST_CTRL_PHY_RESET_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + if (val) + reg |=3D PHY_RST_CTRL_PHY_RESET; + else + reg &=3D ~PHY_RST_CTRL_PHY_RESET; + + reg |=3D PHY_RST_CTRL_PHY_RESET_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); +} + +static void +exynosautov920_usb31drd_lane0_reset(struct exynos5_usbdrd_phy *phy_drd, in= t val) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + reg |=3D PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + if (val) + reg &=3D ~PHY_RST_CTRL_PIPE_LANE0_RESET_N; + else + reg |=3D PHY_RST_CTRL_PIPE_LANE0_RESET_N; + + reg &=3D ~PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); +} + +static void +exynosautov920_usb31drd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + /* + * Phy and Pipe Lane reset assert. + * assert reset (phy_reset =3D 1). + * The lane-ack outputs are asserted during reset (tx_ack =3D rx_ack =3D = 1) + */ + exynosautov920_usb31drd_phy_reset(phy_drd, 1); + exynosautov920_usb31drd_lane0_reset(phy_drd, 1); + + /* + * ANA Power En, PCS & PMA PWR Stable Set + * ramp-up power suppiles + */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0); + reg |=3D PHY_CONFIG0_PHY0_ANA_PWR_EN | PHY_CONFIG0_PHY0_PCS_PWR_STABLE | + PHY_CONFIG0_PHY0_PMA_PWR_STABLE; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0); + + fsleep(10); + + /* + * phy is not functional in test_powerdown mode, test_powerdown to be + * de-asserted for normal operation + */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + reg &=3D ~PHY_CONFIG7_PHY_TEST_POWERDOWN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + + /* + * phy reset signal be asserted for minimum 10us after power + * supplies are ramped-up + */ + fsleep(10); + + /* + * Phy and Pipe Lane reset assert de-assert + */ + exynosautov920_usb31drd_phy_reset(phy_drd, 0); + exynosautov920_usb31drd_lane0_reset(phy_drd, 0); + + /* Pipe_rx0_sris_mode_en =3D 1 */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4); + reg |=3D PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4); + + /* + * wait for lane ack outputs to de-assert (tx_ack =3D rx_ack =3D 0) + * Exit from the reset state is indicated by de-assertion of *_ack + */ + exynosautov920_usb31drd_port_phy_ready(phy_drd); + + /* override values for level settings */ + exynosautov920_usb31drd_cr_write(phy_drd, 0x22, 0x00F5); +} + +static void +exynosautov920_usb31drd_ssphy_disable(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + /* 1. Assert reset (phy_reset =3D 1) */ + exynosautov920_usb31drd_lane0_reset(phy_drd, 1); + exynosautov920_usb31drd_phy_reset(phy_drd, 1); + + /* phy test power down */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + reg |=3D PHY_CONFIG7_PHY_TEST_POWERDOWN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); +} + static void exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) { @@ -2173,12 +2450,15 @@ exynosautov920_usbdrd_utmi_init(struct exynos5_usbd= rd_phy *phy_drd) /* after POR low and delay 75us, PHYCLOCK is guaranteed. */ fsleep(75); =20 - /* force pipe3 signal for link */ + /* Disable forcing pipe interface */ reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); - reg |=3D LINKCTRL_FORCE_PIPE_EN; - reg &=3D ~LINKCTRL_FORCE_PHYSTATUS; - reg |=3D LINKCTRL_FORCE_RXELECIDLE; + reg &=3D ~LINKCTRL_FORCE_PIPE_EN; writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + /* Pclk to pipe_clk */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_CLKRST); + reg |=3D EXYNOS2200_CLKRST_LINK_PCLK_SEL; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); } =20 static void @@ -2226,6 +2506,8 @@ static int exynosautov920_usbdrd_phy_init(struct phy = *phy) /* Bypass PHY isol when first USB is powered on */ if ((atomic_inc_return(&usage_count) =3D=3D 1)) inst->phy_cfg->phy_isol(inst, false); + } else if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_PIPE3) { + inst->phy_cfg->phy_isol(inst, false); } =20 /* UTMI or PIPE3 specific init */ @@ -2275,6 +2557,10 @@ static int exynosautov920_usbdrd_combo_phy_exit(stru= ct phy *phy) /* enable PHY isol when all USBs are powered off */ if (atomic_dec_and_test(&usage_count)) inst->phy_cfg->phy_isol(inst, true); + } else if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_PIPE3) { + exynosautov920_usb31drd_ssphy_disable(phy_drd); + + inst->phy_cfg->phy_isol(inst, true); } =20 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); @@ -2333,6 +2619,36 @@ static const char * const exynosautov920_regulator_n= ames[] =3D { "avdd075_usb", "avdd18_usb20", "avdd33_usb20", }; =20 +static const struct +exynos5_usbdrd_phy_config usb31drd_phy_cfg_exynosautov920[] =3D { + { + .id =3D EXYNOS5_DRDPHY_PIPE3, + .phy_isol =3D exynos5_usbdrd_phy_isol, + .phy_init =3D exynosautov920_usb31drd_pipe3_init, + }, +}; + +static const struct phy_ops exynosautov920_usb31drd_combo_ssphy_ops =3D { + .init =3D exynosautov920_usbdrd_phy_init, + .exit =3D exynosautov920_usbdrd_combo_phy_exit, + .power_on =3D exynosautov920_usbdrd_phy_power_on, + .power_off =3D exynosautov920_usbdrd_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static const +struct exynos5_usbdrd_phy_drvdata exynosautov920_usb31drd_combo_ssphy =3D { + .phy_cfg =3D usb31drd_phy_cfg_exynosautov920, + .phy_ops =3D &exynosautov920_usb31drd_combo_ssphy_ops, + .pmu_offset_usbdrd0_phy =3D EXYNOSAUTOV920_PHY_CTRL_USB31, + .clk_names =3D exynos5_clk_names, + .n_clks =3D ARRAY_SIZE(exynos5_clk_names), + .core_clk_names =3D exynos5_core_clk_names, + .n_core_clks =3D ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names =3D exynosautov920_regulator_names, + .n_regulators =3D ARRAY_SIZE(exynosautov920_regulator_names), +}; + static const struct phy_ops exynosautov920_usbdrd_combo_hsphy_ops =3D { .init =3D exynosautov920_usbdrd_phy_init, .exit =3D exynosautov920_usbdrd_combo_phy_exit, @@ -2597,6 +2913,9 @@ static const struct of_device_id exynos5_usbdrd_phy_o= f_match[] =3D { }, { .compatible =3D "samsung,exynos990-usbdrd-phy", .data =3D &exynos990_usbdrd_phy + }, { + .compatible =3D "samsung,exynosautov920-usb31drd-combo-ssphy", + .data =3D &exynosautov920_usb31drd_combo_ssphy }, { .compatible =3D "samsung,exynosautov920-usbdrd-combo-hsphy", .data =3D &exynosautov920_usbdrd_combo_hsphy diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/so= c/samsung/exynos-regs-pmu.h index 4923f9be3d1f..f96c773b85c9 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -690,4 +690,5 @@ =20 /* exynosautov920 */ #define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) +#define EXYNOSAUTOV920_PHY_CTRL_USB31 (0x0714) #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ --=20 2.34.1