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charset="utf-8" Add device tree bindings for the Qualcomm I3C controller. This includes the necessary documentation and properties required to describe the hardware in the device tree. Signed-off-by: Mukesh Kumar Savaliya Reviewed-by: Rob Herring (Arm) --- .../bindings/i3c/qcom,geni-i3c.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/i3c/qcom,geni-i3c.yaml diff --git a/Documentation/devicetree/bindings/i3c/qcom,geni-i3c.yaml b/Doc= umentation/devicetree/bindings/i3c/qcom,geni-i3c.yaml new file mode 100644 index 000000000000..45022327aee7 --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/qcom,geni-i3c.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i3c/qcom,geni-i3c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Geni based QUP I3C Controller + +maintainers: + - Mukesh Kumar Savaliya + +description: + I3C in master mode supports up to 12.5MHz, SDR mode data transfer in mix= ed + bus mode (I2C and I3C target devices on same i3c bus). It also supports + hotjoin, IBI mechanism. + + I3C Controller nodes must be child of GENI based Qualcomm Universal + Peripharal. Please refer GENI based QUP wrapper controller node bindings + described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yam= l. + +allOf: + - $ref: i3c.yaml# + +properties: + compatible: + const: qcom,geni-i3c + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i3c@884000 { + compatible =3D "qcom,geni-i3c"; + reg =3D <0x00884000 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <3>; + #size-cells =3D <0>; + }; +... --=20 2.25.1