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Tue, 01 Jul 2025 08:32:58 -0700 (PDT) From: James Clark Date: Tue, 01 Jul 2025 16:31:57 +0100 Subject: [PATCH 1/3] perf: arm_spe: Add barrier before enabling profiling buffer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250701-james-spe-vm-interface-v1-1-52a2cd223d00@linaro.org> References: <20250701-james-spe-vm-interface-v1-0-52a2cd223d00@linaro.org> In-Reply-To: <20250701-james-spe-vm-interface-v1-0-52a2cd223d00@linaro.org> To: Will Deacon , Mark Rutland , Catalin Marinas , Alexandru Elisei , Anshuman Khandual , Rob Herring , Suzuki Poulose , Robin Murphy Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 DEN0154 states that PMBPTR_EL1 must not be modified while the profiling buffer is enabled. Ensure that enabling the buffer comes after setting PMBPTR_EL1 by inserting an isb(). This only applies to guests for now, but in future versions of the architecture the PE will be allowed to behave in the same way. Fixes: d5d9696b0380 ("drivers/perf: Add support for ARMv8.2 Statistical Pro= filing Extension") Signed-off-by: James Clark Reviewed-by: Alexandru Elisei Tested-by: Alexandru Elisei --- drivers/perf/arm_spe_pmu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 3efed8839a4e..6235ca7ecd48 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -537,6 +537,7 @@ static void arm_spe_perf_aux_output_begin(struct perf_o= utput_handle *handle, limit +=3D (u64)buf->base; base =3D (u64)buf->base + PERF_IDX2OFF(handle->head, buf); write_sysreg_s(base, SYS_PMBPTR_EL1); + isb(); =20 out_write_limit: write_sysreg_s(limit, SYS_PMBLIMITR_EL1); --=20 2.34.1 From nobody Wed Oct 8 05:55:36 2025 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30BE72797AC for ; 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Tue, 01 Jul 2025 08:33:00 -0700 (PDT) Received: from ho-tower-lan.lan ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80b5a3sm13435002f8f.40.2025.07.01.08.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 08:33:00 -0700 (PDT) From: James Clark Date: Tue, 01 Jul 2025 16:31:58 +0100 Subject: [PATCH 2/3] perf: arm_spe: Disable buffer before writing to PMBPTR_EL1 or PMBSR_EL1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250701-james-spe-vm-interface-v1-2-52a2cd223d00@linaro.org> References: <20250701-james-spe-vm-interface-v1-0-52a2cd223d00@linaro.org> In-Reply-To: <20250701-james-spe-vm-interface-v1-0-52a2cd223d00@linaro.org> To: Will Deacon , Mark Rutland , Catalin Marinas , Alexandru Elisei , Anshuman Khandual , Rob Herring , Suzuki Poulose , Robin Murphy Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 DEN0154 states that writes to PMBPTR_EL1 or PMBSR_EL1 must be done while the buffer is disabled (PMBLIMITR_EL1.E =3D=3D 0). Re-arrange the interrupt handler to always disable the buffer for non-spurious interrupts before doing either. Most of arm_spe_pmu_disable_and_drain_local() is now always done, so for faults the only thing left to do is clear PMSCR_EL1. Elaborate the comment in arm_spe_pmu_disable_and_drain_local() to explain the ramifications of not doing it in the right order. Fixes: d5d9696b0380 ("drivers/perf: Add support for ARMv8.2 Statistical Pro= filing Extension") Signed-off-by: James Clark Reviewed-by: Alexandru Elisei Tested-by: Alexandru Elisei --- drivers/perf/arm_spe_pmu.c | 33 +++++++++++++++++++++------------ 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 6235ca7ecd48..5829947c8871 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -559,7 +559,12 @@ static void arm_spe_perf_aux_output_end(struct perf_ou= tput_handle *handle) =20 static void arm_spe_pmu_disable_and_drain_local(void) { - /* Disable profiling at EL0 and EL1 */ + /* + * To prevent the CONSTRAINED UNPREDICTABLE behavior of either writing + * to memory after the buffer is disabled, or SPE reporting an access + * not allowed event, we must disable sampling before draining the + * buffer. + */ write_sysreg_s(0, SYS_PMSCR_EL1); isb(); =20 @@ -661,16 +666,24 @@ static irqreturn_t arm_spe_pmu_irq_handler(int irq, v= oid *dev) */ irq_work_run(); =20 + /* + * arm_spe_pmu_buf_get_fault_act() already drained, and PMBSR_EL1.S =3D= =3D 1 + * means that StatisticalProfilingEnabled() =3D=3D false. So now we can + * safely disable the buffer. + */ + write_sysreg_s(0, SYS_PMBLIMITR_EL1); + isb(); + + /* Status can be cleared now that PMBLIMITR_EL1.E =3D=3D 0 */ + write_sysreg_s(0, SYS_PMBSR_EL1); + switch (act) { case SPE_PMU_BUF_FAULT_ACT_FATAL: /* - * If a fatal exception occurred then leaving the profiling - * buffer enabled is a recipe waiting to happen. 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Tue, 01 Jul 2025 08:33:01 -0700 (PDT) Received: from ho-tower-lan.lan ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80b5a3sm13435002f8f.40.2025.07.01.08.33.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 08:33:01 -0700 (PDT) From: James Clark Date: Tue, 01 Jul 2025 16:31:59 +0100 Subject: [PATCH 3/3] perf: arm_spe: Add support for SPE VM interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250701-james-spe-vm-interface-v1-3-52a2cd223d00@linaro.org> References: <20250701-james-spe-vm-interface-v1-0-52a2cd223d00@linaro.org> In-Reply-To: <20250701-james-spe-vm-interface-v1-0-52a2cd223d00@linaro.org> To: Will Deacon , Mark Rutland , Catalin Marinas , Alexandru Elisei , Anshuman Khandual , Rob Herring , Suzuki Poulose , Robin Murphy Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 DEN0154 describes the new SPE VM interface, which allows the hypervisor to define a max buffer size hint and to raise a new buffer management error for exceeding it. Report the size as a capability to userspace, and prevent larger buffers from being allocated in the driver. Although it's a only a hint and smaller buffers may also be disallowed in some scenarios, a larger buffer is never expected to work so we can fail early. Failures after arm_spe_pmu_setup_aux() have to happen asynchronously through the buffer management event. Signed-off-by: James Clark Reviewed-by: Alexandru Elisei Tested-by: Alexandru Elisei --- arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/tools/sysreg | 6 +++++- drivers/perf/arm_spe_pmu.c | 26 ++++++++++++++++++++++++++ 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index f1bb0d10c39a..9c48a7119aa7 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -367,6 +367,7 @@ #define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK =20 #define PMBSR_EL1_BUF_BSC_FULL 0x1UL +#define PMBSR_EL1_BUF_BSC_SIZE 0x4UL =20 /*** End of Statistical Profiling Extension ***/ =20 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8a8cf6874298..d6bb1736f554 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2976,7 +2976,11 @@ Field 7:0 Attr EndSysreg =20 Sysreg PMBIDR_EL1 3 0 9 10 7 -Res0 63:12 +Res0 63:48 +Field 47:46 MaxBuffSize_RES +Field 45:41 MaxBuffSize_E +Field 40:32 MaxBuffSize_M +Res0 31:12 Enum 11:8 EA 0b0000 NotDescribed 0b0001 Ignored diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 5829947c8871..23f18dc2890c 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -92,6 +92,7 @@ struct arm_spe_pmu { u16 max_record_sz; u16 align; struct perf_output_handle __percpu *handle; + u64 max_buff_size; }; =20 #define to_spe_pmu(p) (container_of(p, struct arm_spe_pmu, pmu)) @@ -115,6 +116,7 @@ enum arm_spe_pmu_capabilities { SPE_PMU_CAP_FEAT_MAX, SPE_PMU_CAP_CNT_SZ =3D SPE_PMU_CAP_FEAT_MAX, SPE_PMU_CAP_MIN_IVAL, + SPE_PMU_CAP_MAX_BUFF_SIZE, }; =20 static int arm_spe_pmu_feat_caps[SPE_PMU_CAP_FEAT_MAX] =3D { @@ -132,6 +134,8 @@ static u32 arm_spe_pmu_cap_get(struct arm_spe_pmu *spe_= pmu, int cap) return spe_pmu->counter_sz; case SPE_PMU_CAP_MIN_IVAL: return spe_pmu->min_period; + case SPE_PMU_CAP_MAX_BUFF_SIZE: + return spe_pmu->max_buff_size; default: WARN(1, "unknown cap %d\n", cap); } @@ -164,6 +168,7 @@ static struct attribute *arm_spe_pmu_cap_attr[] =3D { SPE_CAP_EXT_ATTR_ENTRY(ernd, SPE_PMU_CAP_ERND), SPE_CAP_EXT_ATTR_ENTRY(count_size, SPE_PMU_CAP_CNT_SZ), SPE_CAP_EXT_ATTR_ENTRY(min_interval, SPE_PMU_CAP_MIN_IVAL), + SPE_CAP_EXT_ATTR_ENTRY(max_buff_size, SPE_PMU_CAP_MAX_BUFF_SIZE), NULL, }; =20 @@ -631,6 +636,9 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_handle= *handle) case PMBSR_EL1_BUF_BSC_FULL: ret =3D SPE_PMU_BUF_FAULT_ACT_OK; goto out_stop; + case PMBSR_EL1_BUF_BSC_SIZE: + err_str =3D "Buffer size too large"; + goto out_err; default: err_str =3D "Unknown buffer status code"; } @@ -896,6 +904,7 @@ static void *arm_spe_pmu_setup_aux(struct perf_event *e= vent, void **pages, int i, cpu =3D event->cpu; struct page **pglist; struct arm_spe_pmu_buf *buf; + struct arm_spe_pmu *spe_pmu =3D to_spe_pmu(event->pmu); =20 /* We need at least two pages for this to work. */ if (nr_pages < 2) @@ -910,6 +919,10 @@ static void *arm_spe_pmu_setup_aux(struct perf_event *= event, void **pages, if (snapshot && (nr_pages & 1)) return NULL; =20 + if (spe_pmu->max_buff_size && + nr_pages * PAGE_SIZE > spe_pmu->max_buff_size) + return NULL; + if (cpu =3D=3D -1) cpu =3D raw_smp_processor_id(); =20 @@ -999,6 +1012,17 @@ static void arm_spe_pmu_perf_destroy(struct arm_spe_p= mu *spe_pmu) perf_pmu_unregister(&spe_pmu->pmu); } =20 +static u64 arm_spe_decode_buf_size(u64 pmbidr) +{ + u64 mantissa =3D FIELD_GET(PMBIDR_EL1_MaxBuffSize_M, pmbidr); + u8 exp =3D FIELD_GET(PMBIDR_EL1_MaxBuffSize_E, pmbidr); + + if (exp =3D=3D 0) + return mantissa << 12; + + return (mantissa | 0b1000000000) << (exp + 11); +} + static void __arm_spe_pmu_dev_probe(void *info) { int fld; @@ -1033,6 +1057,8 @@ static void __arm_spe_pmu_dev_probe(void *info) return; } =20 + spe_pmu->max_buff_size =3D arm_spe_decode_buf_size(reg); + /* It's now safe to read PMSIDR and figure out what we've got */ reg =3D read_sysreg_s(SYS_PMSIDR_EL1); if (FIELD_GET(PMSIDR_EL1_FE, reg)) --=20 2.34.1