From nobody Wed Oct 8 07:27:04 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CA419277CA4 for ; Tue, 1 Jul 2025 14:53:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751381634; cv=none; b=m/KXpcIox3rJzCAPm5/kLvyCUm37YRuxMz5J/g5sP5R9Zzz+QARguPwhXO+lkFZDnZhVOcdxGOAOyYD98OpbszU6nZzARIMP4Y7ZPCFbAFWRkF3yx744stg+4DjFBTwodkiPhFmGjGt2jknNoWQlTp4wQY+90H3ijA6E3M9SzSw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751381634; c=relaxed/simple; bh=xHj8VpMyNgGZKJjTVl7tHeMB6vi0clNQ6rHiVOCFt18=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MYqxOYXTMfkIbGVxhys3NmjSIZfBjOCx/ZzOFWHGj5wAndgoVB5G8E8FSOKvVfzAFrgKGFXA6y6N9vKOSMKr9x2MssLSZcGcTbZl4utdUfW/uQ8cdjBwywKiFuZ/xiyV0l4C2QwUYkxE3RU3qtklhjWgDwcrlMWuz66ZEVkZzWE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CCEF6236D; Tue, 1 Jul 2025 07:53:36 -0700 (PDT) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1DB683F66E; Tue, 1 Jul 2025 07:53:49 -0700 (PDT) From: Leo Yan Date: Tue, 01 Jul 2025 15:53:26 +0100 Subject: [PATCH v2 01/28] coresight: Change device mode to atomic type Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250701-arm_cs_pm_fix_v3-v2-1-23ebb864fcc1@arm.com> References: <20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.com> In-Reply-To: <20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Levi Yun , Greg Kroah-Hartman , Alexander Shishkin , Yabin Cui , Keita Morisaki , Yuanfang Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751381627; l=3351; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=xHj8VpMyNgGZKJjTVl7tHeMB6vi0clNQ6rHiVOCFt18=; b=WeDAwQGUCWVxvDF3qX3ZM+cZ5MT4bdoKZiIMzHifUhXkdA/NyWH4lEuqMgd8esL2YFs0hm6Uk AsQATQ2DENXC87csZiEx2JCybRt4fPG9o6NeXfaeeLqlW/0YpDUEn9N X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= The device mode is defined as local type. This type cannot promise SMP-safe access. Change to atomic type and impose relax ordering, which ensures the SMP-safe synchronisation and the ordering between the mode setting and relevant operations. Fixes: 22fd532eaa0c ("coresight: etm3x: adding operation mode for etm_enabl= e()") Signed-off-by: Leo Yan --- include/linux/coresight.h | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 4ac65c68bbf44b98db22c3dad2d83a224ce5278e..5fd3d08824e5a91a197aa01daf0= fc392392f3e55 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -251,15 +251,11 @@ struct coresight_trace_id_map { * by @coresight_ops. * @access: Device i/o access abstraction for this device. * @dev: The device entity associated to this component. - * @mode: This tracer's mode, i.e sysFS, Perf or disabled. This is - * actually an 'enum cs_mode', but is stored in an atomic type. - * This is always accessed through local_read() and local_set(), - * but wherever it's done from within the Coresight device's lock, - * a non-atomic read would also work. This is the main point of - * synchronisation between code happening inside the sysfs mode's - * coresight_mutex and outside when running in Perf mode. A compare - * and exchange swap is done to atomically claim one mode or the - * other. + * @mode: The device mode, i.e sysFS, Perf or disabled. This is actually + * an 'enum cs_mode' but stored in an atomic type. Access is always + * through atomic APIs, ensuring SMP-safe synchronisation between + * racing from sysFS and Perf mode. A compare-and-exchange + * operation is done to atomically claim one mode or the other. * @refcnt: keep track of what is in use. Only access this outside of the * device's spinlock when the coresight_mutex held and mode =3D=3D * CS_MODE_SYSFS. Otherwise it must be accessed from inside the @@ -288,7 +284,7 @@ struct coresight_device { const struct coresight_ops *ops; struct csdev_access access; struct device dev; - local_t mode; + atomic_t mode; int refcnt; bool orphan; /* sink specific fields */ @@ -650,13 +646,14 @@ static inline bool coresight_is_percpu_sink(struct co= resight_device *csdev) static inline bool coresight_take_mode(struct coresight_device *csdev, enum cs_mode new_mode) { - return local_cmpxchg(&csdev->mode, CS_MODE_DISABLED, new_mode) =3D=3D - CS_MODE_DISABLED; + int curr =3D CS_MODE_DISABLED; + + return atomic_try_cmpxchg_acquire(&csdev->mode, &curr, new_mode); } =20 static inline enum cs_mode coresight_get_mode(struct coresight_device *csd= ev) { - return local_read(&csdev->mode); + return atomic_read_acquire(&csdev->mode); } =20 static inline void coresight_set_mode(struct coresight_device *csdev, @@ -672,7 +669,7 @@ static inline void coresight_set_mode(struct coresight_= device *csdev, WARN(new_mode !=3D CS_MODE_DISABLED && current_mode !=3D CS_MODE_DISABLED= && current_mode !=3D new_mode, "Device already in use\n"); =20 - local_set(&csdev->mode, new_mode); + atomic_set_release(&csdev->mode, new_mode); } =20 struct coresight_device *coresight_register(struct coresight_desc *desc); --=20 2.34.1