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Mon, 30 Jun 2025 04:02:04 -0700 From: Kartik Rajput To: , , , , , CC: Subject: [PATCH] clocksource: timer-tegra186: Enable WDT at probe Date: Mon, 30 Jun 2025 16:31:35 +0530 Message-ID: <20250630110135.201930-1-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A1:EE_|LV3PR12MB9265:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ec17698-d152-417e-cfa9-08ddb7c59509 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?NnpzUG50dkhsekRybE1ZTlZ6SUlSUS9GK2lSbXMzcVM3czhDSmk1V3VnQzJD?= =?utf-8?B?N2V5Z3NkR1hXV2xCVzF3SmcrWXU2NURCMGZObDdmY1lLWHFaWjJ1QVB5V25P?= =?utf-8?B?MjhOKzk3ajFTWEdzeUdBNjh2Z0dEcEhLVjI3MEg0ZTEyc2xXbG9pRWxoZ0Jz?= =?utf-8?B?TEg5UGIzREJJZ3liNUFpaTFqWWRLSng3NFZtdzF3andwcVRTd2FhTndjMTlm?= =?utf-8?B?VCtMTWxNVUpOb0dNRVJrK0p6aUVBWUp5YUZIVGlCV2RBYkFmaC9XaEJyS1Rj?= =?utf-8?B?Nk5KMm5TNGNiMXdadERCWm9lZi8wbTZwaWVIR3N3dkFLKzNKcWh1YnFkcTBC?= =?utf-8?B?Zks5eVI1MVpaMTAxNmc4VzRtb3B1a21NY3UwQjk3czBHUldMZGxGMVRTL1Rn?= =?utf-8?B?S2tOem4vSkoyaTlHcHJzYUVLaUV6M2pSajRHVnQ0eDRaQmFOVmp0QVNMRlhO?= =?utf-8?B?WVdwcG9lQUQ2UnZiM3ZQZDFNMW9sb2llemlQTCtLMmZEd3U4NjJxcDBSTjV2?= =?utf-8?B?RlVUeFA1cDNIVGtMc20xZEZPSy80ekxBVDZXYml0RkVyc3pGOXRuY3hqOFpu?= =?utf-8?B?SlFGWWpYbWEwdkdJL2ltTjlrZGVzRTBXandVaFM1UU1OREJBQ2JuSVBPeC9W?= =?utf-8?B?YitIek1ZVks4TmFTU2prdUNlY2c5MWtPdjVIRkRvL1NJVCtSQzJRS3Z2NENH?= =?utf-8?B?V3Ryd0tVWDhZK0RVRkpaZ0l0Y1pUN1kxS3IyaXpaaXE3QmlhcnFyVFFOQy9P?= =?utf-8?B?YVN1SkM0dGVPY2MzSXFxU09HdHBaanZ5Q3NGS0N4Z2g4U2xuaUJ3NytNUStX?= =?utf-8?B?MnlOUld2QkI4eWh4MGJ1RDlqVHh2QUI1SVRrTTZjbm9GZGJhcmw3b1RTcndE?= =?utf-8?B?aTFxam1HUmJOcG5kYjdkV2VmUmJaUklweHF3Sml6TDVpZkVFN1RiOUR3Vk9X?= =?utf-8?B?aVZOSjNJNTRVSmxCdnlnYXNhanZmZDM3eDhSVHZqVlpIdXl5NnZmQWFUWG5B?= =?utf-8?B?ZWluSjBnckNaQ1hYOVFTejBHd29rYWVJTWpaV3hjZDZxVytkZGg5aVoyNmk4?= =?utf-8?B?VDY4WnJpbjBWWFIwMU1YdWFpTk1RU3phTllOVktvdnJLTHFSNzFqK3dwOWwx?= =?utf-8?B?QTJaUU52bnhqV2EzdThqUkI5dkExNWdabWxPZ2FUVW5KMDVBNWZyZlJydmtJ?= =?utf-8?B?bTZISjVlSVdYbVBlLy9OWGZCNkR1UzhSbGswVTdaY1l1RXhzdGVTRVJpbzZs?= =?utf-8?B?MUw5a1ZoTUNrc1dmdVArMWhaVklvUFErK29DWUpNRWcyRzNIVnRYR3lXOW1V?= =?utf-8?B?S0xrYzNsZzBtUTV0N2hpcnhqMlJIVFE5N3A5VUF0cnZyMzRQZHMxd2NNeUZz?= =?utf-8?B?aEtpeXp5K2d0T0JibGdQK2hGM2V4bFlrNVFob1RSMG9IT2ZOeGQ2Uk83RkY4?= =?utf-8?B?cEtrbS95SWJMQVFhTiszendnZDRmTUlDRnhKSTR3RGEvNk5mWklNRTVXQU1w?= =?utf-8?B?T0l3aDdpZ0o2Zm90RnFGWjBwbGFrMTg2WGg3OHJxUnVMRDZWN3RzbVFuZ09x?= =?utf-8?B?Nmo0Yk9nb0xJdWE4RWFxTWpOWkZFUnhEMEp2WmpBK1ZIS1A5YXBMeG5EQXV1?= =?utf-8?B?REl6ckFnZ040b0RsVzhXUk1ZTk56cGNxTHhXdk1nMkxVSUZMQys3TGRZaXNK?= =?utf-8?B?MVFiMWRhOVBSOUpqR2FBT2Fsa2taTkROYzRVaXJGTWUwa1BlTkZIWGswb1g3?= =?utf-8?B?MHVRTVlFQUU5UFY3ZnB0akEraWg3NjJWdHVidHBvWU9EZmU3bnNCRnQ3YVVi?= =?utf-8?B?SVJoTU52YVBnRzJ5NGtwQkRqSTlTZFpSQ29MZEY3TFNhdEMyV0tpQjFwVmRo?= =?utf-8?B?Z04xZElaMjYzZzh0c000Y2J6bm1QNkJmNklwa3NVYW93Mjh4em1uRHZIMEFY?= =?utf-8?B?K1pJOWRqVENheWFhNGNGQllIa1k3V01pQlR1UVh0Uy9hZ2ZBTzFMZzkxeHdI?= =?utf-8?B?c012MEZYVmdTYmFrWG9tNmE5cFZ5Zm4veWgxZlpHUTV2MkNsNDBSWnI1RVNC?= =?utf-8?Q?yfWhQR?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 11:02:19.2079 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ec17698-d152-417e-cfa9-08ddb7c59509 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9265 Currently, if the system crashes or hangs during kernel boot before userspace initializes and configures the watchdog timer, then the watchdog won=E2=80=99t be able to recover the system as it=E2=80=99s not ru= nning. This becomes crucial during an over-the-air update, where if the newly updated kernel crashes on boot, the watchdog is needed to reset the device and boot into an alternative system partition. If the watchdog is disabled in such scenarios, it can lead to the system getting bricked. Enable the WDT during driver probe to allow recovery from any crash/hang seen during early kernel boot. Also, disable interrupts once userspace starts pinging the watchdog. Signed-off-by: Kartik Rajput --- drivers/clocksource/timer-tegra186.c | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/tim= er-tegra186.c index e5394f98a02e..59abb5dab8f1 100644 --- a/drivers/clocksource/timer-tegra186.c +++ b/drivers/clocksource/timer-tegra186.c @@ -57,6 +57,8 @@ #define WDTUR 0x00c #define WDTUR_UNLOCK_PATTERN 0x0000c45a =20 +#define WDT_DEFAULT_TIMEOUT 120 + struct tegra186_timer_soc { unsigned int num_timers; unsigned int num_wdts; @@ -74,6 +76,7 @@ struct tegra186_wdt { =20 void __iomem *regs; unsigned int index; + bool enable_irq; bool locked; =20 struct tegra186_tmr *tmr; @@ -174,6 +177,12 @@ static void tegra186_wdt_enable(struct tegra186_wdt *w= dt) value &=3D ~WDTCR_PERIOD_MASK; value |=3D WDTCR_PERIOD(1); =20 + /* configure local interrupt for WDT petting */ + if (wdt->enable_irq) + value |=3D WDTCR_LOCAL_INT_ENABLE; + else + value &=3D ~WDTCR_LOCAL_INT_ENABLE; + /* enable system POR reset */ value |=3D WDTCR_SYSTEM_POR_RESET_ENABLE; =20 @@ -205,6 +214,10 @@ static int tegra186_wdt_ping(struct watchdog_device *w= dd) { struct tegra186_wdt *wdt =3D to_tegra186_wdt(wdd); =20 + /* Disable WDT interrupt once userspace takes over. */ + if (wdt->enable_irq) + wdt->enable_irq =3D false; + tegra186_wdt_disable(wdt); tegra186_wdt_enable(wdt); =20 @@ -315,6 +328,8 @@ static struct tegra186_wdt *tegra186_wdt_create(struct = tegra186_timer *tegra, if (value & WDTCR_LOCAL_INT_ENABLE) wdt->locked =3D true; =20 + wdt->enable_irq =3D true; + source =3D value & WDTCR_TIMER_SOURCE_MASK; =20 wdt->tmr =3D tegra186_tmr_create(tegra, source); @@ -339,6 +354,13 @@ static struct tegra186_wdt *tegra186_wdt_create(struct= tegra186_timer *tegra, return ERR_PTR(err); } =20 + /* + * Start the watchdog to recover the system if it crashes before + * userspace initialize the WDT. + */ + tegra186_wdt_set_timeout(&wdt->base, WDT_DEFAULT_TIMEOUT); + tegra186_wdt_start(&wdt->base); + return wdt; } =20 @@ -415,10 +437,21 @@ static int tegra186_timer_usec_init(struct tegra186_t= imer *tegra) return clocksource_register_hz(&tegra->usec, USEC_PER_SEC); } =20 +static irqreturn_t tegra186_timer_irq(int irq, void *data) +{ + struct tegra186_timer *tegra =3D data; + + tegra186_wdt_disable(tegra->wdt); + tegra186_wdt_enable(tegra->wdt); + + return IRQ_HANDLED; +} + static int tegra186_timer_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct tegra186_timer *tegra; + unsigned int irq; int err; =20 tegra =3D devm_kzalloc(dev, sizeof(*tegra), GFP_KERNEL); @@ -437,6 +470,15 @@ static int tegra186_timer_probe(struct platform_device= *pdev) if (err < 0) return err; =20 + irq =3D err; + + err =3D devm_request_irq(dev, irq, tegra186_timer_irq, 0, + "tegra186-timer", tegra); + if (err < 0) { + dev_err(dev, "failed to request IRQ#%u: %d\n", irq, err); + return err; + } + /* create a watchdog using a preconfigured timer */ tegra->wdt =3D tegra186_wdt_create(tegra, 0); if (IS_ERR(tegra->wdt)) { --=20 2.43.0