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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 04B194160504; Mon, 30 Jun 2025 12:16:07 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v5 13/14] arm64: dts: cix: Add PCIe Root Complex on sky1 Date: Mon, 30 Jun 2025 12:16:00 +0800 Message-ID: <20250630041601.399921-14-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250630041601.399921-1-hans.zhang@cixtech.com> References: <20250630041601.399921-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CA:EE_|PUZPR06MB5604:EE_ X-MS-Office365-Filtering-Correlation-Id: 17a1cb8c-1f71-4136-24f9-08ddb78cd848 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?HtnqClRmrUmxbcx45BCTgBDK6k8/37zx8VDOzTUO3dx8PllR2x4+/BGHHKl0?= =?us-ascii?Q?3FsYYY5GVoZq6FgpecqbhfqBmFKNCaWmr1hBHJb+8mL4Q3y/nn1sP5LQltah?= =?us-ascii?Q?pa68qHH1kQzgr43VPex0g1uW57vovOTsWACxNTrimUfLe/TzsToPMFxOZ+TS?= =?us-ascii?Q?g7chaNKX4MJMTVpb6gd36MczsTnp47Yhelz5bYOK6TcLjllzalHd/+7VqAF5?= =?us-ascii?Q?eOkjOCK8jwCxdM0nJGwBW28Znf4ak1i0lqo2/YVnC4bAr6lj2c6VXPKSdN5b?= =?us-ascii?Q?Mnvp2w7igSHq6qpCfVQeT1r6/XA1yjz7Hzc7e5tQP3bROiMWyo0kQfqXIT8b?= =?us-ascii?Q?fLC70ujtOeCBwawHtlateizaQBMJbfnuWbAK/wUj4UpfF3pDsS4l1BZS6Eal?= =?us-ascii?Q?351VRjtDpAXTKeu67x6+xvLlz+cPoXBCeZBuqZNWvfiaJwaxOzWhw63X211C?= =?us-ascii?Q?5LGwxAmoxZCuIdo5lGZCAtPHD2XmnDa1UP/3JZXQTwe+/x4Un1MlpFBwS9p9?= =?us-ascii?Q?m4KFVz3+kkekaFCDYhXrrCCBn0szUp5Xse7eT1cwKSJDpNYOLpvcWBqKD8+w?= =?us-ascii?Q?TqDYuU4SytbFAtN/Q/LMFPanpffAB/Y31TgUlGSKRBKd6+bymv6etX/bsX34?= =?us-ascii?Q?IQ1+VKHuWJXwAyb1pZkUb4s5IVlszQXmymU17cKQzqhARuhnQIxCdq6Bo5ns?= =?us-ascii?Q?BLwlCrAMsBLhAXh7vBBAil4p09GCGzrhBUZX2XQ+Ox7OKzAVC3/TQA8FLlyn?= =?us-ascii?Q?aTqIP312zhWae6hjUuirTO3/5QuletMXYgEc0mGRvKoUyAkR66TzUX6aqARs?= =?us-ascii?Q?+QAzEDmMEuYOdEA03ThDwQ2gkq8bK2ysp1cTueTNK4ZHs//sBxFeenYB0JFU?= =?us-ascii?Q?P/3Y5888IBEv9eUFOHQi7nEMsv9zCLqifliX/XK2O8Om+vgnoGk9E8g0fKaV?= =?us-ascii?Q?/3L/L3iVXTt58TTWHCuYANXgjm4ObD3RT9Dh61Qex+vYQrumtvVRg7lhdbDX?= =?us-ascii?Q?UL4GAoAtvjHAQ+MuzVeeTK4Gd3ElpxhPPmMKMZHB0x580PLkNKUYSMlatx17?= =?us-ascii?Q?Cn5922P+DE1lTTlXz1AiH4yVvSBoC9TZmaZPQxUNqzN+xCYMR6zOcZF6ML40?= =?us-ascii?Q?5krYtbp0xdi7LI2JxYBebK9bk7zYlf2FVBNHdhQh2q6hkf2AVx/Sfk6Za/Wc?= =?us-ascii?Q?hQXT15HusCTNJqQDyY5s2vnvf9RieZhtuKJSxjZrGIX45TzSi83z5rME+Bjt?= =?us-ascii?Q?u1C/QmObS+eQEBuYBxXvHuNba6Xp2pLocfPWDSsJsarUHMJMBn6UJSuziaQN?= =?us-ascii?Q?IOHGVWAiMPUl78DnfoSDoUQDZovpCDcvCZElsqRV2FepCFikCb456cOpg8O3?= =?us-ascii?Q?DoEkuBBturNIg32rZgNuRcIlwNA47k9msKGqtn2iLn+87R0CSWhMXTXZcX0B?= =?us-ascii?Q?4s03HZG9AV5Un6PzTv/HiHsYBZh92EaGlHSIFZ+7M68I330eIiozPzPLGx78?= =?us-ascii?Q?SFLIH+u9q6CQzNaTgCKD7yzeVs8N9PM6D2gd?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7416014)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 04:16:10.6284 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17a1cb8c-1f71-4136-24f9-08ddb78cd848 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CA.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PUZPR06MB5604 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add pcie_x*_rc node to support Sky1 PCIe driver based on the Cadence PCIe core. Supports Gen1/Gen2/Gen3/Gen4, 1/2/4/8 lane, MSI/MSI-x interrupts using the ARM GICv3. Signed-off-by: Hans Zhang Reviewed-by: Peter Chen Reviewed-by: Manikandan K Pillai --- arch/arm64/boot/dts/cix/sky1.dtsi | 150 ++++++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi index 9c723917d8ca..1dac0e8d5fc1 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -289,6 +289,156 @@ mbox_ap2sfh: mailbox@80a0000 { cix,mbox-dir =3D "tx"; }; =20 + pcie_x8_rc: pcie@a010000 { /* X8 */ + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a010000 0x00 0x10000>, + <0x00 0x0a000000 0x00 0x10000>, + <0x00 0x2c000000 0x00 0x4000000>, + <0x00 0x60000000 0x00 0x00100000>; + reg-names =3D "reg", "rcsu", "cfg", "msg"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>; + max-link-speed =3D <4>; + num-lanes =3D <8>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0xc0 0xff>; + device_type =3D "pci"; + ranges =3D <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>, + <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>; + msi-map =3D <0xc000 &gic_its 0xc000 0x4000>; + vendor-id =3D <0x1f6c>; + device-id =3D <0x0001>; + cdns,no-inbound-bar; + sky1,pcie-ctrl-id =3D <0x0>; + status =3D "disabled"; + }; + + pcie_x4_rc: pcie@a070000 { /* X4 */ + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a070000 0x00 0x10000>, + <0x00 0x0a060000 0x00 0x10000>, + <0x00 0x29000000 0x00 0x3000000>, + <0x00 0x50000000 0x00 0x00100000>; + reg-names =3D "reg", "rcsu", "cfg", "msg"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>; + max-link-speed =3D <4>; + num-lanes =3D <4>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x90 0xbf>; + device_type =3D "pci"; + ranges =3D <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>, + <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>, + <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>; + msi-map =3D <0x9000 &gic_its 0x9000 0x3000>; + vendor-id =3D <0x1f6c>; + device-id =3D <0x0001>; + cdns,no-inbound-bar; + sky1,pcie-ctrl-id =3D <0x1>; + status =3D "disabled"; + }; + + pcie_x2_rc: pcie@a0c0000 { /* X2 */ + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0c0000 0x00 0x10000>, + <0x00 0x0a060000 0x00 0x10000>, + <0x00 0x26000000 0x00 0x3000000>, + <0x00 0x40000000 0x00 0x00100000>; + reg-names =3D "reg", "rcsu", "cfg", "msg"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>; + max-link-speed =3D <4>; + num-lanes =3D <2>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x60 0x8f>; + device_type =3D "pci"; + ranges =3D <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>, + <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>; + msi-map =3D <0x6000 &gic_its 0x6000 0x3000>; + vendor-id =3D <0x1f6c>; + device-id =3D <0x0001>; + cdns,no-inbound-bar; + sky1,pcie-ctrl-id =3D <0x2>; + status =3D "disabled"; + }; + + pcie_x1_0_rc: pcie@a0d0000 { /* X1_0 */ + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0d0000 0x00 0x10000>, + <0x00 0x0a060000 0x00 0x10000>, + <0x00 0x20000000 0x00 0x3000000>, + <0x00 0x30000000 0x00 0x00100000>; + reg-names =3D "reg", "rcsu", "cfg", "msg"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; + max-link-speed =3D <4>; + num-lanes =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x00 0x2f>; + device_type =3D "pci"; + ranges =3D <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>, + <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>, + <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>; + msi-map =3D <0x0000 &gic_its 0x0000 0x3000>; + vendor-id =3D <0x1f6c>; + device-id =3D <0x0001>; + cdns,no-inbound-bar; + sky1,pcie-ctrl-id =3D <0x4>; + status =3D "disabled"; + }; + + pcie_x1_1_rc: pcie@a0e0000 { /* X1_1 */ + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0e0000 0x00 0x10000>, + <0x00 0x0a060000 0x00 0x10000>, + <0x00 0x23000000 0x00 0x3000000>, + <0x00 0x38000000 0x00 0x00100000>; + reg-names =3D "reg", "rcsu", "cfg", "msg"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>; + max-link-speed =3D <4>; + num-lanes =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x30 0x5f>; + device_type =3D "pci"; + ranges =3D <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, + <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>, + <0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000>; + msi-map =3D <0x3000 &gic_its 0x3000 0x3000>; + vendor-id =3D <0x1f6c>; + device-id =3D <0x0001>; + sky1,pcie-ctrl-id =3D <0x3>; + cdns,no-inbound-bar; + status =3D "disabled"; + }; + gic: interrupt-controller@e010000 { compatible =3D "arm,gic-v3"; reg =3D <0x0 0x0e010000 0 0x10000>, /* GICD */ --=20 2.49.0