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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id C00DA41604F7; Mon, 30 Jun 2025 12:16:06 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v5 09/14] PCI: cadence: Add support for PCIe HPA controller platform Date: Mon, 30 Jun 2025 12:15:56 +0800 Message-ID: <20250630041601.399921-10-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250630041601.399921-1-hans.zhang@cixtech.com> References: <20250630041601.399921-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CC:EE_|TYZPR06MB5528:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d8067ac-4d77-465b-a968-08ddb78cd7a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?nnlVUPCMN1r9WIYhV4k3M44aVwMjfx4sE9ARyKaIN4QKWZsTg45gZv6q0KVl?= =?us-ascii?Q?Oyx3QWUTWf8EuRelTz1MOKMu4/6iLFxu7CiAolaU+OLNTZVascGaThO+MOpo?= =?us-ascii?Q?igENxB0L6rOdYPk0KCII+Jz2/zbZ9B573AC++MefOuJxZg25xho04JUbrgso?= =?us-ascii?Q?6RRaogyQM7H4MUEob5hPxoqy0+jO/xCNY/BlQVxnb5eS0MoUW5j5mcqAtpZO?= =?us-ascii?Q?AXjNiMPac5faAOUea+TFz+VpEpnHV0Zp/tRH85YHAn9/L0FBs3PF3Mg5TUMc?= =?us-ascii?Q?Djo1jw8XqbaSRbZp32cvTkUfEoEqIGVrgN9lMXiFjcwJ/HuMP8sxYAg+0Meh?= =?us-ascii?Q?bZgSh9YQO9FgyjhaMpaaCE4W4f4ns+45CLAyWQU5LP1WTCm9A7i9+x2QCouU?= =?us-ascii?Q?KCKW2HAQVZSMOIl55Fsb1okPZoVH5smfWdRAzdyhl4Hz/gIE/iQbopD1b458?= =?us-ascii?Q?spmVNfR5H2wgawE5Pz0TfrPikShn/rks1u47gVmbUGu9KIZHK7CwSTPx5m3B?= =?us-ascii?Q?6olDv82vCFUFwO5v9vqS0YQSlP+4AjTmxjb2HqjxpCfZVzeySqb9uAo0kHOL?= =?us-ascii?Q?NMEx+TUPamDAI2sihEbiPctaGeCZH2X0Pi/KQXRzd5ddv9H65ebn9p4Au2P/?= =?us-ascii?Q?pp++Y0QG5c8detNdL2VoOgGs9Z71xdfD3QTSFUIqAdDGPFt1PLUZvrSaQVCT?= =?us-ascii?Q?87XC804P1aiJRnB0KdAz29+hwTJ1tvlt/EdmfJ5uP4r+Bb2qIeX7Mqw6yrBL?= =?us-ascii?Q?59jRCFp6ZVkc+Ftwq0fUOO+H6N81H66YR5XZiOI2nO+l24aaC5S+1dwbpjkN?= =?us-ascii?Q?naE3pV+drKROxb5A+21mX15RvWhrYXD/MFMz5DAsYsDe52zbdvNnOnnRxgS3?= =?us-ascii?Q?HYh4SavBHBz4FreE9Ua9Aq2DOHw4TnthORGnvjQW2s/FZ3mr8FqTfLc7eEny?= =?us-ascii?Q?ebh+t/1GGYguBHdLLvZoz+uTFgps8E5jP5/bgFmYGi7eATH0YuSZQi6encdB?= =?us-ascii?Q?MBFc6Jkz71mbGCFawRAs36VvXc5yCAOShfROs/UuVS6xL7MVG6hACfm7fnDm?= =?us-ascii?Q?ovbySSFrxm4vU65PyHbA2AnDJu2SO6eMvzHjAscqTc0G+wiSkIpiXIRav9JU?= =?us-ascii?Q?qdyLlxksJMoI6aHHzp4FuwCfB4rYSd6JSw01A16ZxgOWQ3IGJ4k19M8NyC/6?= =?us-ascii?Q?SPqu30DFSX8aJckx3eerKdltIqSOzhH3LUx17jWJfQiVA7m/veEEvrqlPaYD?= =?us-ascii?Q?c615hAG/Jyfawap9jr177LWlA8/2cAZlgRTAYjQfMagwytnkQcYYG7SSEFae?= =?us-ascii?Q?IL6fMb+vuchQpMdZ/KIFT78psT8WiNho5yaBpm8C+1E9YnpLXbvMhM1FxgeN?= =?us-ascii?Q?6cwNKoAnkcnYcV56+9jdbpHcco6303c9h4+RXi9E8LuhlMED4wrbyYULhCsG?= =?us-ascii?Q?2oHDI7urvBZfdrsN6Kv8UdVe5+1ozVuXIgZBHysGYKAgo9QuSqoY1JqYGgnm?= =?us-ascii?Q?dUuxyuvxWIzuzUy7hlqNk4djgYx24MK4mXTH?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700013)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 04:16:09.5985 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d8067ac-4d77-465b-a968-08ddb78cd7a4 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CC.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB5528 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add support for Cadence HPA PCIe controller based platform. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Kconfig | 5 + drivers/pci/controller/cadence/Makefile | 1 + .../cadence/pcie-cadence-plat-hpa.c | 183 ++++++++++++++++++ 3 files changed, 189 insertions(+) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-plat-hpa.c diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controlle= r/cadence/Kconfig index a1caf154888d..427aa9beca22 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -29,11 +29,15 @@ config PCIE_CADENCE_EP config PCIE_CADENCE_PLAT bool =20 +config PCIE_CADENCE_PLAT_HPA + bool + config PCIE_CADENCE_PLAT_HOST bool "Cadence platform PCIe controller (host mode)" depends on OF select PCIE_CADENCE_HOST select PCIE_CADENCE_PLAT + select PCIE_CADENCE_PLAT_HPA help Say Y here if you want to support the Cadence PCIe platform controller = in host mode. This PCIe controller may be embedded into many different @@ -45,6 +49,7 @@ config PCIE_CADENCE_PLAT_EP depends on PCI_ENDPOINT select PCIE_CADENCE_EP select PCIE_CADENCE_PLAT + select PCIE_CADENCE_PLAT_HPA help Say Y here if you want to support the Cadence PCIe platform controller = in endpoint mode. This PCIe controller may be embedded into many diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index e2df24ff4c33..f8575a0eee2d 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_PCIE_CADENCE_HOST_COMMON) +=3D pcie-cadence-ho= st-common.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o pcie-cadence-host= -hpa.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o pcie-cadence-ep-hpa.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o +obj-$(CONFIG_PCIE_CADENCE_PLAT_HPA) +=3D pcie-cadence-plat-hpa.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat-hpa.c b/drive= rs/pci/controller/cadence/pcie-cadence-plat-hpa.c new file mode 100644 index 000000000000..fb42547d47d2 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-plat-hpa.c @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cadence PCIe platform driver. + * + * Copyright (c) 2019, Cadence Design Systems + * Author: Manikandan K Pillai + */ +#include +#include +#include +#include +#include +#include "pcie-cadence.h" + +/** + * struct cdns_plat_pcie - private data for this PCIe platform driver + * @pcie: Cadence PCIe controller + */ +struct cdns_plat_pcie { + struct cdns_pcie *pcie; +}; + +static const struct cdns_pcie_ops cdns_plat_hpa_ops =3D { + .start_link =3D cdns_pcie_hpa_start_link, + .stop_link =3D cdns_pcie_hpa_stop_link, + .link_up =3D cdns_pcie_hpa_link_up, +}; + +static int cdns_plat_pcie_hpa_probe(struct platform_device *pdev) +{ + const struct cdns_plat_pcie_of_data *data; + struct cdns_plat_pcie *cdns_plat_pcie; + struct device *dev =3D &pdev->dev; + struct pci_host_bridge *bridge; + struct cdns_pcie_ep *ep; + struct cdns_pcie_rc *rc; + int phy_count; + bool is_rc; + int ret; + + data =3D of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + is_rc =3D data->is_rc; + + pr_debug(" Started %s with is_rc: %d\n", __func__, is_rc); + cdns_plat_pcie =3D devm_kzalloc(dev, sizeof(*cdns_plat_pcie), GFP_KERNEL); + if (!cdns_plat_pcie) + return -ENOMEM; + + platform_set_drvdata(pdev, cdns_plat_pcie); + if (is_rc) { + if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_HOST)) + return -ENODEV; + + bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) + return -ENOMEM; + + rc =3D pci_host_bridge_priv(bridge); + rc->pcie.dev =3D dev; + rc->pcie.ops =3D &cdns_plat_hpa_ops; + rc->pcie.is_rc =3D data->is_rc; + + /* + * Store the register bank offsets pointer + */ + rc->pcie.cdns_pcie_reg_offsets =3D data; + + cdns_plat_pcie->pcie =3D &rc->pcie; + + ret =3D cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie); + if (ret) { + dev_err(dev, "failed to init phy\n"); + return ret; + } + pm_runtime_enable(dev); + ret =3D pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync() failed\n"); + goto err_get_sync; + } + + ret =3D cdns_pcie_hpa_host_setup(rc); + if (ret) + goto err_init; + } else { + if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_EP)) + return -ENODEV; + + ep =3D devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); + if (!ep) + return -ENOMEM; + + ep->pcie.dev =3D dev; + ep->pcie.ops =3D &cdns_plat_hpa_ops; + ep->pcie.is_rc =3D data->is_rc; + + /* + * Store the register bank offset pointer + */ + ep->pcie.cdns_pcie_reg_offsets =3D data; + + cdns_plat_pcie->pcie =3D &ep->pcie; + + ret =3D cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie); + if (ret) { + dev_err(dev, "failed to init phy\n"); + return ret; + } + + pm_runtime_enable(dev); + ret =3D pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync() failed\n"); + goto err_get_sync; + } + + ret =3D cdns_pcie_hpa_ep_setup(ep); + if (ret) + goto err_init; + } + + return 0; + + err_init: + err_get_sync: + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + cdns_pcie_disable_phy(cdns_plat_pcie->pcie); + phy_count =3D cdns_plat_pcie->pcie->phy_count; + while (phy_count--) + device_link_del(cdns_plat_pcie->pcie->link[phy_count]); + + return 0; +} + +static void cdns_plat_pcie_hpa_shutdown(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct cdns_pcie *pcie =3D dev_get_drvdata(dev); + int ret; + + ret =3D pm_runtime_put_sync(dev); + if (ret < 0) + dev_dbg(dev, "pm_runtime_put_sync failed\n"); + + pm_runtime_disable(dev); + + cdns_pcie_disable_phy(pcie); +} + +static const struct cdns_plat_pcie_of_data cdns_plat_pcie_hpa_host_of_data= =3D { + .is_rc =3D true, +}; + +static const struct cdns_plat_pcie_of_data cdns_plat_pcie_hpa_ep_of_data = =3D { + .is_rc =3D false, +}; + +static const struct of_device_id cdns_plat_pcie_hpa_of_match[] =3D { + { + .compatible =3D "cdns,cdns-pcie-hpa-host", + .data =3D &cdns_plat_pcie_hpa_host_of_data, + }, + { + .compatible =3D "cdns,cdns-pcie-hpa-ep", + .data =3D &cdns_plat_pcie_hpa_ep_of_data, + }, + {}, +}; + +static struct platform_driver cdns_plat_pcie_hpa_driver =3D { + .driver =3D { + .name =3D "cdns-pcie-hpa", + .of_match_table =3D cdns_plat_pcie_hpa_of_match, + .pm =3D &cdns_pcie_pm_ops, + }, + .probe =3D cdns_plat_pcie_hpa_probe, + .shutdown =3D cdns_plat_pcie_hpa_shutdown, +}; +builtin_platform_driver(cdns_plat_pcie_hpa_driver); --=20 2.49.0