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Signed-off-by: Manikandan K Pillai --- .../devicetree/bindings/pci/cdns,cdns-pcie-host.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml= b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml index a8190d9b100f..83a33c4c008f 100644 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml @@ -7,14 +7,16 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence PCIe host controller =20 maintainers: - - Tom Joseph + - Manikandan K Pillai =20 allOf: - $ref: cdns-pcie-host.yaml# =20 properties: compatible: - const: cdns,cdns-pcie-host + enum: + - cdns,cdns-pcie-host + - cdns,cdns-pcie-hpa-host =20 reg: maxItems: 2 --=20 2.49.0 From nobody Wed Oct 8 10:00:53 2025 Received: from TYPPR03CU001.outbound.protection.outlook.com (mail-japaneastazon11022105.outbound.protection.outlook.com [52.101.126.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E311C1940A2; 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Signed-off-by: Manikandan K Pillai --- .../devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml b= /Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml index 8735293962ee..c3f0a620f1c2 100644 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml @@ -7,14 +7,16 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence PCIe EP Controller =20 maintainers: - - Tom Joseph + - Manikandan K Pillai =20 allOf: - $ref: cdns-pcie-ep.yaml# =20 properties: compatible: - const: cdns,cdns-pcie-ep + enum: + - cdns,cdns-pcie-ep + - cdns,cdns-pcie-hpa-ep =20 reg: maxItems: 2 --=20 2.49.0 From nobody Wed Oct 8 10:00:53 2025 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023092.outbound.protection.outlook.com [40.107.44.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68AD519F137; Mon, 30 Jun 2025 04:16:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.44.92 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751256977; cv=fail; b=heFN0NtnCEAmNbLpBYnTETvEvM04sRcTzFTotsJuA0VsyeiIamVHOjl8cXEN3wvdkhPGPRmzOwGJhwbic6pdM4EcvzWvbpJW8oHxtnIxSjFCQZVf03PxbO2qPR0zHJlCc1SsDR8iYs/m1ZqJqLTLL+U0vmo1WAdcrcz85cb+9WM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751256977; c=relaxed/simple; bh=7BdFoaqzczxV2qGqD2nZ0n3jXjyxa1na5Q1YyF099us=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=J4Gwik/PCh3ymfI4yovMyH6wQCArpBvNCcDuKL7CU/3zVgdWm6/rLZU+vxTOJiFkS5rLvt3dKTbcz8B4PrfqS+EjBNbdRwkTOO2v0nCGQ2vLQm2QbiNKV8xe7Clrg/QaRdTAMCYwLxArloK/qy9qK3Sk8JsvvIbgj3/hngRIWKw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=40.107.44.92 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CV5DE0hA/l0tNIDEBJQ412uJEZC/jgHbr4o/WxDEq64YnFMvhzss+DB5lwFaVB2AaxbkYdErgdR/AKJh2DveOV+kA8ZCPZCpDrtoiMNuH3zgXjhfk0L/GDZYyy7NaBMCr+7XZETQIOEZsDISoQU+rhZQBMxJRMqj6+tlecA87RCENVzaVV/u2f4VBPjPThMgJVlIX0Tw1xZK9OpUBa4VSmYoP8MTR0WwJwK1fLzyPEr16zOWeZg1axbUeX93o712fnpjQ6OPImOgBWWph6BP7E9QUiPI/ORrbIWXvCJH/kwyBD8K7tetERRnwZlTSrEPJBu2emUIr5DN0tRY+zUp5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4fLVX8pOx9Wb4y2xQ97itnfigh87l3HUPueRJ9n6Bj4=; b=syNU0rWjKw0kFIqJ3dioATA/MqxZfgGkqvnb6HdjsBNIzuajM1ozTM6nOCu6DACn5UPoaoOHLs87F8WgPXvoe77glhvwOQSCDEKmHoVXl90bFGB3/VbUIxhZd3COG2ttuSxlfY9l6ts8y3DdZYRzUV9qludZVc41MUPv5uoPfk1dwzENEL3ieWU5rtkyfe5nlK1+zcx77guJFw/6BCYUJbZfazgGfffDWUBAgKGsokkdwJupauLQPQ0Jp0DAf6zdLDhKMbN4vHvXUnZFrCroSa+mhnnsJfjVKzu8JWJ4W03cGmi6/axOSVcBu7Pr3mZyKbx738Qe8iUZq5golhWkwg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from TYCPR01CA0203.jpnprd01.prod.outlook.com (2603:1096:405:7a::12) by OSQPR06MB7277.apcprd06.prod.outlook.com (2603:1096:604:29a::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8880.29; Mon, 30 Jun 2025 04:16:08 +0000 Received: from TY2PEPF0000AB88.apcprd03.prod.outlook.com (2603:1096:405:7a:cafe::b7) by TYCPR01CA0203.outlook.office365.com (2603:1096:405:7a::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8880.28 via Frontend Transport; Mon, 30 Jun 2025 04:16:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by TY2PEPF0000AB88.mail.protection.outlook.com (10.167.253.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8901.15 via Frontend Transport; Mon, 30 Jun 2025 04:16:07 +0000 Received: from hans.. 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Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- .../cadence/pcie-cadence-lga-regs.h | 228 ++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 226 +---------------- 2 files changed, 229 insertions(+), 225 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-lga-regs.h diff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drive= rs/pci/controller/cadence/pcie-cadence-lga-regs.h new file mode 100644 index 000000000000..0e88beb77292 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver. +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_LGA_REGS_H +#define _PCIE_CADENCE_LGA_REGS_H + +#include + +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 + +/* Local Management Registers */ +#define CDNS_PCIE_LM_BASE 0x00100000 + +/* Vendor ID Register */ +#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) +#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) +#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 +#define CDNS_PCIE_LM_ID_VENDOR(vid) \ + (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) +#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) +#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 +#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ + (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) + +/* Root Port Requester ID Register */ +#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) +#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) +#define CDNS_PCIE_LM_RP_RID_SHIFT 0 +#define CDNS_PCIE_LM_RP_RID_(rid) \ + (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) + +/* Endpoint Bus and Device Number Register */ +#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022C) +#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) +#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 +#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) +#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 + +/* Endpoint Function f BAR b Configuration Registers */ +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FU= NC_BAR_CFG1(fn)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ + (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ + (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_V= FUNC_BAR_CFG1(fn)) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ + (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ + (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ + (GENMASK(4, 0) << ((b) * 8)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ + (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ + (GENMASK(7, 5) << ((b) * 8)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ + (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) + +/* Endpoint Function Configuration Register */ +#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02C0) + +/* Root Complex BAR Configuration Register */ +#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ + (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ + (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ + (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ + (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) +#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) + +/* BAR control values applicable to both Endpoint Function and Root Comple= x */ +#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 + +#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ + (((aperture) - 2) << ((bar) * 8)) + +/* PTM Control Register */ +#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0DA8) +#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) + +/* + * Endpoint Function Registers (PCI configuration space for endpoint funct= ions) + */ +#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) + +#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 +#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xB0 +#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xC0 +#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 + +/* Endpoint PF Registers */ +#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) +#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) + +/* Root Port Registers (PCI configuration space for the root port function= ) */ +#define CDNS_PCIE_RP_BASE 0x00200000 +#define CDNS_PCIE_RP_CAP_OFFSET 0xC0 + +/* Address Translation Registers */ +#define CDNS_PCIE_AT_BASE 0x00400000 + +/* Region r Outbound AXI to PCIe Address Translation Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ + (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ + (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ + (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) + +/* Region r Outbound AXI to PCIe Address Translation Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ + (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1F) * 0x0020) + +/* Region r Outbound PCIe Descriptor Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ + (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xA +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xB +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xC +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xD +/* Bit 23 MUST be set in RC mode. */ +#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ + (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) + +/* Region r Outbound PCIe Descriptor Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ + (CDNS_PCIE_AT_BASE + 0x000C + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ + ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) + +/* Region r AXI Region Base Address Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ + (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) + +/* Region r AXI Region Base Address Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ + (CDNS_PCIE_AT_BASE + 0x001C + ((r) & 0x1F) * 0x0020) + +/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ + (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ + (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) + +/* AXI link down register */ +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) + +/* LTSSM Capabilities register */ +#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ + (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ + CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) + +#define CDNS_PCIE_RP_MAX_IB 0x3 +#define CDNS_PCIE_MAX_OB 32 + +/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register = */ +#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ + (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) +#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ + (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) + +/* Normal/Vendor specific message access: offset inside some outbound regi= on */ +#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) +#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ + (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) +#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) +#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ + (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) +#define CDNS_PCIE_MSG_NO_DATA BIT(16) + +#endif /* _PCIE_CADENCE_LGA_REGS_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index a149845d341a..b87fab47f2e7 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -10,213 +10,7 @@ #include #include #include - -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - -/* - * Local Management Registers - */ -#define CDNS_PCIE_LM_BASE 0x00100000 - -/* Vendor ID Register */ -#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) -#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) -#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 -#define CDNS_PCIE_LM_ID_VENDOR(vid) \ - (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) -#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) -#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 -#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ - (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) - -/* Root Port Requester ID Register */ -#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) -#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) -#define CDNS_PCIE_LM_RP_RID_SHIFT 0 -#define CDNS_PCIE_LM_RP_RID_(rid) \ - (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) - -/* Endpoint Bus and Device Number Register */ -#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c) -#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) -#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 -#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) -#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 - -/* Endpoint Function f BAR b Configuration Registers */ -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ - (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FU= NC_BAR_CFG1(fn)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ - (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ - (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ - (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_V= FUNC_BAR_CFG1(fn)) -#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ - (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ - (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ - (GENMASK(4, 0) << ((b) * 8)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ - (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ - (GENMASK(7, 5) << ((b) * 8)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ - (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) - -/* Endpoint Function Configuration Register */ -#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0) - -/* Root Complex BAR Configuration Register */ -#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ - (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ - (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ - (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ - (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) -#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 -#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) -#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) -#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 -#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) -#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) - -/* BAR control values applicable to both Endpoint Function and Root Comple= x */ -#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 - -#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ - (((aperture) - 2) << ((bar) * 8)) - -/* PTM Control Register */ -#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8) -#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) - -/* - * Endpoint Function Registers (PCI configuration space for endpoint funct= ions) - */ -#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) - -#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 -#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 -#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 - -/* - * Endpoint PF Registers - */ -#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) -#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) - -/* - * Root Port Registers (PCI configuration space for the root port function) - */ -#define CDNS_PCIE_RP_BASE 0x00200000 -#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 - -/* - * Address Translation Registers - */ -#define CDNS_PCIE_AT_BASE 0x00400000 - -/* Region r Outbound AXI to PCIe Address Translation Register 0 */ -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ - (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ - (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ - (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ - (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) - -/* Region r Outbound AXI to PCIe Address Translation Register 1 */ -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ - (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) - -/* Region r Outbound PCIe Descriptor Register 0 */ -#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ - (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd -/* Bit 23 MUST be set in RC mode. */ -#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) -#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) -#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ - (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) - -/* Region r Outbound PCIe Descriptor Register 1 */ -#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ - (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) -#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ - ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) - -/* Region r AXI Region Base Address Register 0 */ -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ - (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ - (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) - -/* Region r AXI Region Base Address Register 1 */ -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ - (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) - -/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ - (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ - (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ - (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) - -/* AXI link down register */ -#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) - -/* LTSSM Capabilities register */ -#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x005= 4) -#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) -#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 -#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ - (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ - CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) +#include "pcie-cadence-lga-regs.h" =20 enum cdns_pcie_rp_bar { RP_BAR_UNDEFINED =3D -1, @@ -225,29 +19,11 @@ enum cdns_pcie_rp_bar { RP_NO_BAR }; =20 -#define CDNS_PCIE_RP_MAX_IB 0x3 -#define CDNS_PCIE_MAX_OB 32 - struct cdns_pcie_rp_ib_bar { u64 size; bool free; }; =20 -/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register = */ -#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ - 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 9C19641604E4; Mon, 30 Jun 2025 12:16:06 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v5 04/14] PCI: cadence: Add register definitions for HPA(High Perf Architecture) Date: Mon, 30 Jun 2025 12:15:51 +0800 Message-ID: <20250630041601.399921-5-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250630041601.399921-1-hans.zhang@cixtech.com> References: <20250630041601.399921-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66D0:EE_|TYZPR06MB7144:EE_ X-MS-Office365-Filtering-Correlation-Id: fae7522c-3890-483b-ebbc-08ddb78cd647 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?UrXFbHNsRhf52Astcksa+SyrBR+683Ce8A2lDB08hn9USr7Xhm57/Nw3YvV3?= =?us-ascii?Q?2TLVNitn9ZFEI7SovXYigqWG6FaOsQl2wk2S3ZPZcFe5HYER43dvlBMA6F3O?= =?us-ascii?Q?mJZ94hdTs5HkpqoYy2R2wgKbNNutDgx6uFXjARJ9fmmvBoyIQLsiIRyAw2bE?= =?us-ascii?Q?4X/c38FwsGelxAz/0KAmB6RjW9QmDjZ8W82MOKJAIWnKCrC2SJwFShXmodX4?= =?us-ascii?Q?La9iJVQwVv9Ie6vw5ejZ89elhjR7sJAnZQaMx083AL7/xFsC5ID/oufjMr0p?= =?us-ascii?Q?X6G2+3Er1rRmApzzw0vI7NcfuOQIzLQYcGMKJI6OHkH5Z422i3nsnX2SyinA?= =?us-ascii?Q?EEbw2GFKZK69IM4pOoSsl9y5sy3lczLRfZlA5YctaLnFyfB9Mgf8GiX4REG8?= =?us-ascii?Q?TpfGu281vK+8KB3K2VDvQC3Rzt3eOs2bTTkABRcO/mEnRxQeBoX8FBLdJPFR?= =?us-ascii?Q?zRKslbUUoXsmuHrTvBFRDNxWLB/x5QqlRwY8OoW0AldwvESS4Rawgq8L5iLr?= =?us-ascii?Q?2jWePshEFZwLlYgJ/DOcpcq7KjlGci7IpfacTFpQeVhuhDb1CGKNs3ph4nwR?= =?us-ascii?Q?h2u3ftl5t9DWLO7Ij4hfDEq5W8/OEyXAzXfZgJFbvqIrWA8G/cWVs5vxflq8?= =?us-ascii?Q?xNJXD9ur12jJ+jFX6iLa4M+QvYbpYYdZLrBKQMa5dDTnDczpZXhpzXbtsGJE?= =?us-ascii?Q?ZgFSwFDoG4ySWR4BqIBc24dUqOfmQ6ux27jczgQOvG2VecPYz0BMV2uMowVK?= =?us-ascii?Q?DpfZbTyKeNyM6HdFYP5Uep9kD8YMAbaqm2Uk9T7uwAAABn54AjuGvcm2XVPg?= =?us-ascii?Q?Eg9dOuFFJAykWj+c/g4F+vIEi217HA1N8YkB6cHEbq4ZbT3i1RUrXsFszzwA?= =?us-ascii?Q?+fj8iIYQNW/4JMihq4LY06CM1OBcZ1noZ9xMyqTTy5RC5JNa/Nl0ouoBPSVc?= =?us-ascii?Q?SkrX9oHfPX71yxZ1/gkEbNveyWeSUplSkR35G7jCUHspEjlhx1RGx+XaONBf?= =?us-ascii?Q?CNTt2eLEIP9FNVdnV4ZGmWt8dCC7vIM1D4rCJ1NUzFyqDA56zQ7bt66bpo1o?= =?us-ascii?Q?BImiLdX2TAJajYbViODyyZDazYdK7+WasPgr4W3I8BzzbYC2nkoaQXI4aZJ4?= =?us-ascii?Q?lnBGtN9E9S+UG6itYlDQFVUyESrzLdJ9cAIzZpizprlzYFQtDLqgRk1XoYQ1?= =?us-ascii?Q?3MRquk4/DC15BjseFZMd9TjVDi/begudmlzSfBX07ScXOYGzO5rB67SaRLHg?= =?us-ascii?Q?SCnXLsO52/shdmvouvED4o+wNKJfgZem5LYJAcaZ+F9bxP4AnCRO+CmUDM3j?= =?us-ascii?Q?ljQfxrxDXE2ctX2GJK8sHA4p+hUq0ftLqjDnXYZYY961idKFQ8DCJqbLzzA/?= =?us-ascii?Q?HK15Ro1OKQl58HbxU+jAf4a21OSEFsZE5pRl0BKMz6ajjxVhwuA/H7x8ULIB?= =?us-ascii?Q?rnb2CixK0LFlNTaaZ25cpxWYL/7/gZ55qfqNKxqJoy/SBMwrrCm/4VbjPXx8?= =?us-ascii?Q?iJvByHfVZf+WUjabgMi1IilHxiMe8kZtywAF?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 04:16:07.3041 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fae7522c-3890-483b-ebbc-08ddb78cd647 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66D0.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB7144 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add the register offsets and register definitions for HPA(High Performance architecture) PCIe controllers from Cadence. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- .../cadence/pcie-cadence-hpa-regs.h | 212 ++++++++++++++++++ .../controller/cadence/pcie-cadence-plat.c | 4 - drivers/pci/controller/cadence/pcie-cadence.h | 121 ++++++++-- 3 files changed, 320 insertions(+), 17 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h b/drive= rs/pci/controller/cadence/pcie-cadence-hpa-regs.h new file mode 100644 index 000000000000..016144e2df81 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h @@ -0,0 +1,212 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver. +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_HPA_REGS_H +#define _PCIE_CADENCE_HPA_REGS_H + +#include +#include +#include +#include +#include + +/* + * HPA (High Performance Architecture) PCIe controller register + */ +#define CDNS_PCIE_HPA_IP_REG_BANK 0x01000000 +#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x01003C00 +#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0x01020000 +/* + * Address Translation Registers(HPA) + */ +#define CDNS_PCIE_HPA_AXI_SLAVE 0x03000000 +#define CDNS_PCIE_HPA_AXI_MASTER 0x03002000 +/* + * Root port register base address + */ +#define CDNS_PCIE_HPA_RP_BASE 0x0 + +#define CDNS_PCIE_HPA_LM_ID 0x1420 + +/* + * Endpoint Function BARs(HPA) Configuration Registers + */ +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \ + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(fn)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) (0x4000 * (pfn)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) ((0x4000 * (pfn)) + 0x04) +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \ + CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(fn)) +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) ((0x4000 * (vfn)) + 0x08) +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(vfn) ((0x4000 * (vfn)) + 0x0C) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(f) \ + (GENMASK(9, 4) << ((f) * 10)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ + (((a) << (4 + ((b) * 10))) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTU= RE_MASK(b))) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(f) \ + (GENMASK(3, 0) << ((f) * 10)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ + (((c) << ((b) * 10)) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)= )) + +/* + * Endpoint Function Configuration Register + */ +#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG 0x02C0 + +/* + * Root Complex BAR Configuration Register + */ +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG 0x14 +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(9, 4) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK, a) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(3, 0) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(c) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK, c) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(19, 14) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK, a) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(13, 10) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(c) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK, c) + +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(20) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(21) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE BIT(22) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS BIT(23) + +/* BAR control values applicable to both Endpoint Function and Root Comple= x */ +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED 0x0 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS 0x3 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS 0x1 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x9 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS 0x5 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0xD + +#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture) \ + (((aperture) - 7) << ((bar) * 10)) + +#define CDNS_PCIE_HPA_LM_PTM_CTRL 0x0520 +#define CDNS_PCIE_HPA_LM_TPM_CTRL_PTMRSEN BIT(17) + +/* + * Root Port Registers PCI config space(HPA) for root port function + */ +#define CDNS_PCIE_HPA_RP_CAP_OFFSET 0xC0 + +/* + * Region r Outbound AXI to PCIe Address Translation Register 0 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r) (0x1010 + ((r) = & 0x1F) * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK, ((nbits) - 1)) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(23, 16) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK, devfn) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(31, 24) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK, bus) + +/* + * Region r Outbound AXI to PCIe Address Translation Register 1 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r) (0x1014 + ((r) = & 0x1F) * 0x0080) + +/* + * Region r Outbound PCIe Descriptor Register 0 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r) (0x1008 + ((r) = & 0x1F) * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(28, 24) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x0) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x2) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x4) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x5) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x10) + +/* + * Region r Outbound PCIe Descriptor Register 1 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r) (0x100C + ((r) & 0x1F) = * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK GENMASK(31, 24) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(bus) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK, bus) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK GENMASK(23, 16) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(devfn) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK, devfn) + +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r) (0x1018 + ((r) & 0x1F)= * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS BIT(26) +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN BIT(25) + +/* + * Region r AXI Region Base Address Register 0 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r) (0x1000 + ((r) & 0x1F)= * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK, ((nbits) - 1)) + +/* + * Region r AXI Region Base Address Register 1 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r) (0x1004 + ((r) & 0x1F)= * 0x0080) + +/* + * Root Port BAR Inbound PCIe to AXI Address Translation Register + */ +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar) (((bar) * 0x000= 8)) +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK, ((nbits) - 1)) +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar) (0x04 + ((bar) = * 0x0008)) + +/* + * AXI link down register + */ +#define CDNS_PCIE_HPA_AT_LINKDOWN 0x04 + +/* + * Physical Layer Configuration Register 0 + * This register contains the parameters required for functional setup + * of Physical Layer. + */ +#define CDNS_PCIE_HPA_PHY_LAYER_CFG0 0x0400 +#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK GENMASK(26, 24) +#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay) \ + FIELD_PREP(CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK, delay) +#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK GENMASK(27, 27) + +#define CDNS_PCIE_HPA_PHY_DBG_STS_REG0 0x0420 + +#define CDNS_PCIE_HPA_RP_MAX_IB 0x3 +#define CDNS_PCIE_HPA_MAX_OB 15 + +/* + * Endpoint Function BAR Inbound PCIe to AXI Address Translation Register(= HPA) + */ +#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) (((fn) * 0x0040) + = ((bar) * 0x0008)) +#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) (0x4 + ((fn) * 0x00= 40) + ((bar) * 0x0008)) + +#endif /* _PCIE_CADENCE_HPA_REGS_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/p= ci/controller/cadence/pcie-cadence-plat.c index 0456845dabb9..e09f23427313 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -22,10 +22,6 @@ struct cdns_plat_pcie { struct cdns_pcie *pcie; }; =20 -struct cdns_plat_pcie_of_data { - bool is_rc; -}; - static const struct of_device_id cdns_plat_pcie_of_match[]; =20 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index b87fab47f2e7..5c0ea49551c8 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -10,7 +10,9 @@ #include #include #include +#include #include "pcie-cadence-lga-regs.h" +#include "pcie-cadence-hpa-regs.h" =20 enum cdns_pcie_rp_bar { RP_BAR_UNDEFINED =3D -1, @@ -25,6 +27,7 @@ struct cdns_pcie_rp_ib_bar { }; =20 struct cdns_pcie; +struct cdns_pcie_rc; =20 enum cdns_pcie_msg_routing { /* Route to Root Complex */ @@ -46,6 +49,19 @@ enum cdns_pcie_msg_routing { MSG_ROUTING_GATHER, }; =20 +enum cdns_pcie_reg_bank { + REG_BANK_RP, + REG_BANK_IP_REG, + REG_BANK_IP_CFG_CTRL_REG, + REG_BANK_AXI_MASTER_COMMON, + REG_BANK_AXI_MASTER, + REG_BANK_AXI_SLAVE, + REG_BANK_AXI_HLS, + REG_BANK_AXI_RAS, + REG_BANK_AXI_DTI, + REG_BANKS_MAX, +}; + struct cdns_pcie_ops { int (*start_link)(struct cdns_pcie *pcie); void (*stop_link)(struct cdns_pcie *pcie); @@ -53,6 +69,30 @@ struct cdns_pcie_ops { u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); }; =20 +/** + * struct cdns_plat_pcie_of_data - Register bank offset for a platform + * @is_rc: controller is a RC + * @ip_reg_bank_offset: ip register bank start offset + * @ip_cfg_ctrl_reg_offset: ip config control register start offset + * @axi_mstr_common_offset: AXI master common register start offset + * @axi_slave_offset: AXI slave start offset + * @axi_master_offset: AXI master start offset + * @axi_hls_offset: AXI HLS offset start + * @axi_ras_offset: AXI RAS offset + * @axi_dti_offset: AXI DTI offset + */ +struct cdns_plat_pcie_of_data { + u32 is_rc:1; + u32 ip_reg_bank_offset; + u32 ip_cfg_ctrl_reg_offset; + u32 axi_mstr_common_offset; + u32 axi_slave_offset; + u32 axi_master_offset; + u32 axi_hls_offset; + u32 axi_ras_offset; + u32 axi_dti_offset; +}; + /** * struct cdns_pcie - private data for Cadence PCIe controller drivers * @reg_base: IO mapped register base @@ -64,16 +104,18 @@ struct cdns_pcie_ops { * @link: list of pointers to corresponding device link representations * @ops: Platform-specific ops to control various inputs from Cadence PCIe * wrapper + * @cdns_pcie_reg_offsets: Register bank offsets for different SoC */ struct cdns_pcie { - void __iomem *reg_base; - struct resource *mem_res; - struct device *dev; - bool is_rc; - int phy_count; - struct phy **phy; - struct device_link **link; - const struct cdns_pcie_ops *ops; + void __iomem *reg_base; + struct resource *mem_res; + struct device *dev; + bool is_rc; + int phy_count; + struct phy **phy; + struct device_link **link; + const struct cdns_pcie_ops *ops; + const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; }; =20 /** @@ -151,6 +193,40 @@ struct cdns_pcie_ep { unsigned int quirk_disable_flr:1; }; =20 +static inline u32 cdns_reg_bank_to_off(struct cdns_pcie *pcie, enum cdns_p= cie_reg_bank bank) +{ + u32 offset =3D 0x0; + + switch (bank) { + case REG_BANK_IP_REG: + offset =3D pcie->cdns_pcie_reg_offsets->ip_reg_bank_offset; + break; + case REG_BANK_IP_CFG_CTRL_REG: + offset =3D pcie->cdns_pcie_reg_offsets->ip_cfg_ctrl_reg_offset; + break; + case REG_BANK_AXI_MASTER_COMMON: + offset =3D pcie->cdns_pcie_reg_offsets->axi_mstr_common_offset; + break; + case REG_BANK_AXI_MASTER: + offset =3D pcie->cdns_pcie_reg_offsets->axi_master_offset; + break; + case REG_BANK_AXI_SLAVE: + offset =3D pcie->cdns_pcie_reg_offsets->axi_slave_offset; + break; + case REG_BANK_AXI_HLS: + offset =3D pcie->cdns_pcie_reg_offsets->axi_hls_offset; + break; + case REG_BANK_AXI_RAS: + offset =3D pcie->cdns_pcie_reg_offsets->axi_ras_offset; + break; + case REG_BANK_AXI_DTI: + offset =3D pcie->cdns_pcie_reg_offsets->axi_dti_offset; + break; + default: + break; + }; + return offset; +} =20 /* Register access */ static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 v= alue) @@ -163,6 +239,27 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pc= ie, u32 reg) return readl(pcie->reg_base + reg); } =20 +static inline void cdns_pcie_hpa_writel(struct cdns_pcie *pcie, + enum cdns_pcie_reg_bank bank, + u32 reg, + u32 value) +{ + u32 offset =3D cdns_reg_bank_to_off(pcie, bank); + + reg +=3D offset; + writel(value, pcie->reg_base + reg); +} + +static inline u32 cdns_pcie_hpa_readl(struct cdns_pcie *pcie, + enum cdns_pcie_reg_bank bank, + u32 reg) +{ + u32 offset =3D cdns_reg_bank_to_off(pcie, bank); + + reg +=3D offset; + return readl(pcie->reg_base + reg); +} + static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) { void __iomem *aligned_addr =3D PTR_ALIGN_DOWN(addr, 0x4); @@ -333,19 +430,17 @@ static inline void cdns_pcie_ep_disable(struct cdns_p= cie_ep *ep) #endif =20 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); - 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id A3B6541604EA; Mon, 30 Jun 2025 12:16:06 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v5 05/14] PCI: cadence: Split PCIe EP support into common and specific functions Date: Mon, 30 Jun 2025 12:15:52 +0800 Message-ID: <20250630041601.399921-6-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250630041601.399921-1-hans.zhang@cixtech.com> References: <20250630041601.399921-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CA:EE_|SEZPR06MB7289:EE_ X-MS-Office365-Filtering-Correlation-Id: cd97029e-1c9d-4832-722d-08ddb78cd7fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?4KJR+iuVJV1U6+2rYkQonp8zSAt0rpJmJMnWdWh5+L+XmRIhK5nY4Vb11RC1?= =?us-ascii?Q?ZIqqOVoLLgmoBftV0w9egBK6WBrlWMVc/rAMxqU7Cd/clQ8YM3AnMEhoiMaI?= =?us-ascii?Q?J72wyJX/PldHd8F8hhsm81IT0F8CpL+Iln1A1E75yZsnncykvQrSeAXMyxD/?= =?us-ascii?Q?80OFhDDBUMrVN6sCm3+gTVJNcqgEZCJp8f4LPXWKA9+ipTcD5IEwrerrALeQ?= =?us-ascii?Q?vmdfM+h4VZdppySngBGHDn2m0V3eezumtxKCbnVNM8FnuyLaZc9hNZ7+ApnG?= =?us-ascii?Q?5gG8ZZWgG5duk6+Lg7LDZtuDczK/OWRF+N3hra0Q7U8royfIIXyD5ORT6tOJ?= =?us-ascii?Q?25DnGakGvaxeEnN5RbSXrgIrzf8/qVmDmVXaKaXvgSeBF9EfeqJ0N7hxecbB?= =?us-ascii?Q?0ob9B5bhxpFHtNN8//r+q9hHz+/KtjCMiu/3K0APkl1+YRTuBfdVWQ6JQJh9?= =?us-ascii?Q?gMhkAewRoZUna6tzR24vO5fDbypki6ztZqK0CxU70gd0zQOsapq8yuBTmWPc?= =?us-ascii?Q?EO7/Y5T1lwKOgq6KsQQpfRURg0lobrS4bLOAJJHoNngucePGkvaO1Ogb/xU9?= =?us-ascii?Q?zc8+iEsBsafKtIRHRwgbleqKhgEj1zz5OhJtiV8QzhDe3Qz34XYhSAb0D2TL?= =?us-ascii?Q?TKoM4G/buNeDtDskw/pOis1Sx3yjrps+io3/jn/vgln8yZJe6PJafLd2Mdd/?= =?us-ascii?Q?gaqfmbkNyG/AzrIdlGo3t4uixZru1bxB/suqEHMeaRZ7qavz1jQfc/4vON71?= =?us-ascii?Q?kv4iFpVInOlp3GLLDtnwgfcxg6L5jKF1XzLZ7SKVukvUOH0ahpLqUrFZguQu?= =?us-ascii?Q?6LU04gmIi/+bosienqOpryOZ7QIOKT0di6BsTiMV0v9O8t9PpkuFhh2rtmrx?= =?us-ascii?Q?/0V46EKHUHA5KqY3ZYV8OF5SpGMrMfgM0LPSM1ws3eMszrDG4pY3l6LUPe3h?= =?us-ascii?Q?bleJl2ydtBQ9dhfKnhE0c9ZJR9kG8at/zePX/ekvjwCvLBgrpJeA9+iBYXaA?= =?us-ascii?Q?58sXjjCrlrfqJTHdbz/0XLtuRWZb0zr6Y4BVQ6Wv+DQvUUpMAC9oqY6it+KT?= =?us-ascii?Q?eIiPbF5CBRjwIewg9GcJoEfHX+LZ9HywLvdWv4MfQZ+XyYjwwAKHZhWFPHtM?= =?us-ascii?Q?SwwYxkO2jzh0SwKl8uEuiQweVJdQLpdmcXHKyGtSJBjedG79IDpSOLISgtx4?= =?us-ascii?Q?4Kp1OdKq9zdPCwHMJ9YKqsdBMn0YWBhiPgv7q3LZV0uq7FwFnea8cQVLXMem?= =?us-ascii?Q?yUUpAm5AumQDJ1+arEnvf2Zd8bRpsk0Flp/DUoAO2YP3u5pCdaB4wi1+cOJ2?= =?us-ascii?Q?WjZbRdT0JzcaqYYjuJEj8H7uI/73bLmPA5sVkARXMVjXrqp57Hw63WVj0ZTi?= =?us-ascii?Q?D/iO0t24a4SNEVZQqJVEuadKLl+7dOvpwfYPJ0W80/oNF8ZLYW8AUkCKbdNY?= =?us-ascii?Q?ITWrzoGUnJuSXgI+GL/wMYl/nYkua1yVu53DcuCUU5R7iSoe9ys6bw7LGxrO?= =?us-ascii?Q?V8xV030Mbo4yQSLqbo+8S5RwB/Y1JSNl3+Hu?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(1800799024)(82310400026)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 04:16:10.0813 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd97029e-1c9d-4832-722d-08ddb78cd7fa X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CA.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEZPR06MB7289 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Split the Cadence PCIe controller EP functionality into common library functions and functions for legacy PCIe EP controller. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Kconfig | 4 + drivers/pci/controller/cadence/Makefile | 1 + .../cadence/pcie-cadence-ep-common.c | 240 +++++++++++++++++ .../cadence/pcie-cadence-ep-common.h | 36 +++ .../pci/controller/cadence/pcie-cadence-ep.c | 243 +----------------- 5 files changed, 287 insertions(+), 237 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-ep-common.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-ep-common.h diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controlle= r/cadence/Kconfig index 666e16b6367f..417f981ac8ca 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -12,11 +12,15 @@ config PCIE_CADENCE_HOST select IRQ_DOMAIN select PCIE_CADENCE =20 +config PCIE_CADENCE_COMMON + bool + config PCIE_CADENCE_EP tristate depends on OF depends on PCI_ENDPOINT select PCIE_CADENCE + select PCIE_CADENCE_COMMON =20 config PCIE_CADENCE_PLAT bool diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index 9bac5fb2f13d..918f8c924487 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o +obj-$(CONFIG_PCIE_CADENCE_COMMON) +=3D pcie-cadence-ep-common.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-common.c b/driv= ers/pci/controller/cadence/pcie-cadence-ep-common.c new file mode 100644 index 000000000000..cf5be3b3c981 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-common.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe endpoint controller driver common +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-ep-common.h" + +u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) +{ + u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; + u32 first_vf_offset, stride; + + if (vfn =3D=3D 0) + return fn; + + first_vf_offset =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OF= FSET); + stride =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); + fn =3D fn + first_vf_offset + ((vfn - 1) * stride); + + return fn; +} + +int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_header *hdr) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; + struct cdns_pcie *pcie =3D &ep->pcie; + u32 reg; + + if (vfn > 1) { + dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); + return -EINVAL; + } else if (vfn =3D=3D 1) { + reg =3D cap + PCI_SRIOV_VF_DID; + cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); + return 0; + } + + cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); + cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, + hdr->subclass_code | hdr->baseclass_code << 8); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, + hdr->cache_line_size); + cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin); + + /* + * Vendor ID can only be modified from function 0, all other functions + * use the same vendor ID as function 0. + */ + if (fn =3D=3D 0) { + /* Update the vendor IDs. */ + u32 id =3D CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) | + CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id); + + cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); + } + + return 0; +} + +int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u16 flags; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* + * Set the Multiple Message Capable bitfield into the Message Control + * register. + */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + flags =3D (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1); + flags |=3D PCI_MSI_FLAGS_64BIT; + flags &=3D ~PCI_MSI_FLAGS_MASKBIT; + cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags); + + return 0; +} + +int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u16 flags, mme; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Validate that the MSI feature is actually enabled. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* + * Get the Multiple Message Enable bitfield from the Message Control + * register. + */ + mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); + + return mme; +} + +int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 val, reg; + + func_no =3D cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); + + reg =3D cap + PCI_MSIX_FLAGS; + val =3D cdns_pcie_ep_fn_readw(pcie, func_no, reg); + if (!(val & PCI_MSIX_FLAGS_ENABLE)) + return -EINVAL; + + val &=3D PCI_MSIX_FLAGS_QSIZE; + + return val; +} + +int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, + u16 interrupts, enum pci_barno bir, + u32 offset) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 val, reg; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + reg =3D cap + PCI_MSIX_FLAGS; + val =3D cdns_pcie_ep_fn_readw(pcie, fn, reg); + val &=3D ~PCI_MSIX_FLAGS_QSIZE; + val |=3D interrupts; + cdns_pcie_ep_fn_writew(pcie, fn, reg, val); + + /* Set MSI-X BAR and offset */ + reg =3D cap + PCI_MSIX_TABLE; + val =3D offset | bir; + cdns_pcie_ep_fn_writel(pcie, fn, reg, val); + + /* Set PBA BAR and offset. BAR must match MSI-X BAR */ + reg =3D cap + PCI_MSIX_PBA; + val =3D (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; + cdns_pcie_ep_fn_writel(pcie, fn, reg, val); + + return 0; +} + +int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data, + u32 *msi_addr_offset) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + struct cdns_pcie *pcie =3D &ep->pcie; + u64 pci_addr, pci_addr_mask =3D 0xff; + u16 flags, mme, data, data_mask; + u8 msi_count; + int ret; + int i; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Check whether the MSI feature has been enabled by the PCI host. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* Get the number of enabled MSIs */ + mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); + msi_count =3D 1 << mme; + if (!interrupt_num || interrupt_num > msi_count) + return -EINVAL; + + /* Compute the data value to be written. */ + data_mask =3D msi_count - 1; + data =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); + data =3D data & ~data_mask; + + /* Get the PCI address where to write the data into. */ + pci_addr =3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); + pci_addr <<=3D 32; + pci_addr |=3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); + pci_addr &=3D GENMASK_ULL(63, 2); + + for (i =3D 0; i < interrupt_num; i++) { + ret =3D epc->ops->map_addr(epc, fn, vfn, addr, + pci_addr & ~pci_addr_mask, + entry_size); + if (ret) + return ret; + addr =3D addr + entry_size; + } + + *msi_data =3D data; + *msi_addr_offset =3D pci_addr & pci_addr_mask; + + return 0; +} + +static const struct pci_epc_features cdns_pcie_epc_vf_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D true, + .align =3D 65536, +}; + +static const struct pci_epc_features cdns_pcie_epc_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D true, + .align =3D 256, +}; + +const struct pci_epc_features* +cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + if (!vfunc_no) + return &cdns_pcie_epc_features; + + return &cdns_pcie_epc_vf_features; +} diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-common.h b/driv= ers/pci/controller/cadence/pcie-cadence-ep-common.h new file mode 100644 index 000000000000..a91084bdedd5 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-common.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe Endpoint controller driver. +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_EP_COMMON_H_ +#define _PCIE_CADENCE_EP_COMMON_H_ + +#include +#include +#include +#include +#include "../../pci.h" + +#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */ +#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1 +#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3 + +u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn); +int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_header *hdr); +int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc); +int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn); +int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no); +int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, + u16 interrupts, enum pci_barno bir, + u32 offset); +int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data, + u32 *msi_addr_offset); +const struct pci_epc_features *cdns_pcie_ep_get_features(struct pci_epc *e= pc, + u8 func_no, + u8 vfunc_no); + +#endif /* _PCIE_CADENCE_EP_COMMON_H_ */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci= /controller/cadence/pcie-cadence-ep.c index 8ab6cf70c18e..14c9ec45cc39 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -13,68 +13,7 @@ #include =20 #include "pcie-cadence.h" -#include "../../pci.h" - -#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */ -#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1 -#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3 - -static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) -{ - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; - u32 first_vf_offset, stride; - - if (vfn =3D=3D 0) - return fn; - - first_vf_offset =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OF= FSET); - stride =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); - fn =3D fn + first_vf_offset + ((vfn - 1) * stride); - - return fn; -} - -static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, - struct pci_epf_header *hdr) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; - struct cdns_pcie *pcie =3D &ep->pcie; - u32 reg; - - if (vfn > 1) { - dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); - return -EINVAL; - } else if (vfn =3D=3D 1) { - reg =3D cap + PCI_SRIOV_VF_DID; - cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); - return 0; - } - - cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); - cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, - hdr->subclass_code | hdr->baseclass_code << 8); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, - hdr->cache_line_size); - cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin); - - /* - * Vendor ID can only be modified from function 0, all other functions - * use the same vendor ID as function 0. - */ - if (fn =3D=3D 0) { - /* Update the vendor IDs. */ - u32 id =3D CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) | - CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id); - - cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); - } - - return 0; -} +#include "pcie-cadence-ep-common.h" =20 static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, struct pci_epf_bar *epf_bar) @@ -222,100 +161,6 @@ static void cdns_pcie_ep_unmap_addr(struct pci_epc *e= pc, u8 fn, u8 vfn, clear_bit(r, &ep->ob_region_map); } =20 -static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 nr_= irqs) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u8 mmc =3D order_base_2(nr_irqs); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; - u16 flags; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - /* - * Set the Multiple Message Capable bitfield into the Message Control - * register. - */ - flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); - flags =3D (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1); - flags |=3D PCI_MSI_FLAGS_64BIT; - flags &=3D ~PCI_MSI_FLAGS_MASKBIT; - cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags); - - return 0; -} - -static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; - u16 flags, mme; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - /* Validate that the MSI feature is actually enabled. */ - flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); - if (!(flags & PCI_MSI_FLAGS_ENABLE)) - return -EINVAL; - - /* - * Get the Multiple Message Enable bitfield from the Message Control - * register. - */ - mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); - - return 1 << mme; -} - -static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc= _no) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; - u32 val, reg; - - func_no =3D cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); - - reg =3D cap + PCI_MSIX_FLAGS; - val =3D cdns_pcie_ep_fn_readw(pcie, func_no, reg); - if (!(val & PCI_MSIX_FLAGS_ENABLE)) - return -EINVAL; - - val &=3D PCI_MSIX_FLAGS_QSIZE; - - return val + 1; -} - -static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, - u16 nr_irqs, enum pci_barno bir, u32 offset) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; - u32 val, reg; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - reg =3D cap + PCI_MSIX_FLAGS; - val =3D cdns_pcie_ep_fn_readw(pcie, fn, reg); - val &=3D ~PCI_MSIX_FLAGS_QSIZE; - val |=3D nr_irqs - 1; /* encoded as N-1 */ - cdns_pcie_ep_fn_writew(pcie, fn, reg, val); - - /* Set MSI-X BAR and offset */ - reg =3D cap + PCI_MSIX_TABLE; - val =3D offset | bir; - cdns_pcie_ep_fn_writel(pcie, fn, reg, val); - - /* Set PBA BAR and offset. BAR must match MSI-X BAR */ - reg =3D cap + PCI_MSIX_PBA; - val =3D (offset + (nr_irqs * PCI_MSIX_ENTRY_SIZE)) | bir; - cdns_pcie_ep_fn_writel(pcie, fn, reg, val); - - return 0; -} - static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 in= tx, bool is_asserted) { @@ -426,59 +271,6 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_= ep *ep, u8 fn, u8 vfn, return 0; } =20 -static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, - phys_addr_t addr, u8 interrupt_num, - u32 entry_size, u32 *msi_data, - u32 *msi_addr_offset) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; - struct cdns_pcie *pcie =3D &ep->pcie; - u64 pci_addr, pci_addr_mask =3D 0xff; - u16 flags, mme, data, data_mask; - u8 msi_count; - int ret; - int i; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - /* Check whether the MSI feature has been enabled by the PCI host. */ - flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); - if (!(flags & PCI_MSI_FLAGS_ENABLE)) - return -EINVAL; - - /* Get the number of enabled MSIs */ - mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); - msi_count =3D 1 << mme; - if (!interrupt_num || interrupt_num > msi_count) - return -EINVAL; - - /* Compute the data value to be written. */ - data_mask =3D msi_count - 1; - data =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); - data =3D data & ~data_mask; - - /* Get the PCI address where to write the data into. */ - pci_addr =3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); - pci_addr <<=3D 32; - pci_addr |=3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); - pci_addr &=3D GENMASK_ULL(63, 2); - - for (i =3D 0; i < interrupt_num; i++) { - ret =3D cdns_pcie_ep_map_addr(epc, fn, vfn, addr, - pci_addr & ~pci_addr_mask, - entry_size); - if (ret) - return ret; - addr =3D addr + entry_size; - } - - *msi_data =3D data; - *msi_addr_offset =3D pci_addr & pci_addr_mask; - - return 0; -} - static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 v= fn, u16 interrupt_num) { @@ -589,12 +381,12 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) continue; =20 value =3D cdns_pcie_ep_fn_readl(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP); + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP); value &=3D ~PCI_EXP_DEVCAP_FLR; cdns_pcie_ep_fn_writel(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP, value); + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP, value); } } =20 @@ -607,29 +399,6 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) return 0; } =20 -static const struct pci_epc_features cdns_pcie_epc_vf_features =3D { - .linkup_notifier =3D false, - .msi_capable =3D true, - .msix_capable =3D true, - .align =3D 65536, -}; - -static const struct pci_epc_features cdns_pcie_epc_features =3D { - .linkup_notifier =3D false, - .msi_capable =3D true, - .msix_capable =3D true, - .align =3D 256, -}; - -static const struct pci_epc_features* -cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) -{ - if (!vfunc_no) - return &cdns_pcie_epc_features; - - return &cdns_pcie_epc_vf_features; -} - static const struct pci_epc_ops cdns_pcie_epc_ops =3D { .write_header =3D cdns_pcie_ep_write_header, .set_bar =3D cdns_pcie_ep_set_bar, @@ -759,7 +528,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) =20 return 0; =20 - free_epc_mem: +free_epc_mem: pci_epc_mem_exit(epc); =20 return ret; --=20 2.49.0 From nobody Wed Oct 8 10:00:53 2025 Received: from OS8PR02CU002.outbound.protection.outlook.com (mail-japanwestazon11022085.outbound.protection.outlook.com [40.107.75.85]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ABC41A23B9; Mon, 30 Jun 2025 04:16:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.75.85 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751256978; cv=fail; b=o67vkhYNQRXvJgz1yJD1RWeP+GEnX6eW8QZnpWrUui2JspJK87IOmnuB5LEgae6xx3pC6mSyAoMJqFQvDL6i4b+OYxEJeTAx3Tpia594W6T983bVSt5aR9Xtre/jUU87e5lwVYGKcLNqHozg+jpd4R0PLqNhXevWpMC+ktKfXSU= ARC-Message-Signature: i=2; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id AA8C741604EE; Mon, 30 Jun 2025 12:16:06 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v5 06/14] PCI: cadence: Split PCIe RP support into common and specific functions Date: Mon, 30 Jun 2025 12:15:53 +0800 Message-ID: <20250630041601.399921-7-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250630041601.399921-1-hans.zhang@cixtech.com> References: <20250630041601.399921-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB88:EE_|PUZPR06MB6007:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d5c41ee-b9f1-4772-f769-08ddb78cd7d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?JJoHkR3ES/dR6pPVEUqhPhA0pUnIusPtWO2JkweqfElQgc0HkJXzygumdsSI?= =?us-ascii?Q?qWW6x9jYX8OC818BG3CPYqwlDO/qq9znOsIlpsOg/Wg95zaFhCWgMYxjfkTE?= =?us-ascii?Q?J6su5pkBmzfbntsD2/66QvLYc7F/Esh+NctWyo62kRY2s6NbKnvqks9D1z6e?= =?us-ascii?Q?R6jyJ0T+p4N3znttVVFp6KsEjR/FkuvJWqah0P/3sUS4mted49XawqrFl3Sx?= =?us-ascii?Q?bCm/h7cIrvNO2sgZN/DwQHkeVtr/dLh6xskzyYjB0h9DX7pbHZeV/DpKiUWh?= =?us-ascii?Q?BE3LSIq1ltW+lVLBqhGUHa8FcaI6rFn3THhnL6nxNmYZ0OzYa8y/iD+7cHP/?= =?us-ascii?Q?nL7Vq9Ml2//WS5qopvgRwyAXUEXJAafP2VK4qGl5IBhSgTs0+CbZegT8HisL?= =?us-ascii?Q?yUmsUZ/7kMRYpnovugtK1uWtQp0rlJxQAijE4V2RYBVUA6R0HDmAcZJPR6yd?= =?us-ascii?Q?qpJUr7+Wv82zhnVvitNhUbT4cCVbxKNYbPCarbIymUQURCrfr5YffxHA+fs/?= =?us-ascii?Q?sFX2dTHqLejRw1jdPAcNboA27R9POu8eyUNbIH7kU+BnT3MvMZamroSlBqu6?= =?us-ascii?Q?NT1Pkopy4wI2VthaHoUY4xnjannk1SXjWVjku74ZOvJ1Y8EfirPkzuA82/2s?= =?us-ascii?Q?L7pIz33AhOtnCyQguSxo95rUvem2RfcrwPvysdr3pu2d/fj0thYLc9n+/DSN?= =?us-ascii?Q?4cvg33ISFxQJX5ZtVeWTTQJyfV56Ez4c4N0I6PFSfQNamcDQ53iCHk2fjvov?= =?us-ascii?Q?WNFL2kcvATWC2+Xysx0Ugj+xDjw/F9U7wFG53/JICgqajJQZwz52cWQFnGrP?= =?us-ascii?Q?49a+2AgdgTmsq+zJHa6nZbb9WvEEptxR5D52T7RPBGtFoQx+MB6DfjMklvam?= =?us-ascii?Q?JH+ZRI5K+q9BOmhkBe5lWuuTQxzq43AJaskZ0h0Fm4nGsTLJmztQhQ0NaGXA?= =?us-ascii?Q?UFd7RT+O/FeEvqR9jmwHxCAtOg1qlheqqoQQQsk+tFA0ABQk9gjWKjJH+uoe?= =?us-ascii?Q?yKR7z4Jqx42CSOqXpvvr8fRhut+9qPFVniMhfGo2nNj9hCP7siUJKu2Ngi02?= =?us-ascii?Q?p/1V5Lj6KRtIOiEOm6sr4RolBO8BLKzKJjLaloziD1UiLJCJ2MwVXLI4n61o?= =?us-ascii?Q?ByIeHvFs4SU2wAOYckb4F7/VMHqT653QPkaOeumaSZq5zJ56q7XEjIIQoYy7?= =?us-ascii?Q?20qMMTShgSj7eXNdS0airtV67hzXuk3rqYk5QzNgbcY9eoP/FiwdOlfCHrPl?= =?us-ascii?Q?7VspLWCOKG72Z3FIweyBNvnM1JrulgNftdiGvsidgaFM2RrR/LnHxlNKODoY?= =?us-ascii?Q?aEV9HfBYygs6ALNWMr5OWnFw9tBPi5zh95MY1s88k4ztpLEamLjUxQ5OlPC/?= =?us-ascii?Q?d6WypMr1/VAd/smmKCz+15mDJ+73D1z5ECkLdEYNnpvN9fQKsty2DO+pUQiJ?= =?us-ascii?Q?yh2RmqzjCl6Xff1W/yboUERW4LQbAzU1AYPZM2FW7kdxwknQ8PXcorCguHBs?= =?us-ascii?Q?uoartO+zzxrQKWpgwusxtVrJrlBFZZU8kwN0?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7416014)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 04:16:09.8568 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d5c41ee-b9f1-4772-f769-08ddb78cd7d6 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB88.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PUZPR06MB6007 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Split the Cadence PCIe controller RP functionality into common functions and functions for legacy PCIe RP controller. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Kconfig | 12 +- drivers/pci/controller/cadence/Makefile | 3 +- .../cadence/pcie-cadence-ep-common.h | 8 +- .../cadence/pcie-cadence-host-common.c | 169 ++++++++++++++++++ .../cadence/pcie-cadence-host-common.h | 25 +++ .../controller/cadence/pcie-cadence-host.c | 156 +--------------- 6 files changed, 209 insertions(+), 164 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common= .c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common= .h diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controlle= r/cadence/Kconfig index 417f981ac8ca..a1caf154888d 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -6,21 +6,25 @@ menu "Cadence-based PCIe controllers" config PCIE_CADENCE tristate =20 +config PCIE_CADENCE_EP_COMMON + bool + +config PCIE_CADENCE_HOST_COMMON + bool + config PCIE_CADENCE_HOST tristate depends on OF select IRQ_DOMAIN select PCIE_CADENCE - -config PCIE_CADENCE_COMMON - bool + select PCIE_CADENCE_HOST_COMMON =20 config PCIE_CADENCE_EP tristate depends on OF depends on PCI_ENDPOINT select PCIE_CADENCE - select PCIE_CADENCE_COMMON + select PCIE_CADENCE_EP_COMMON =20 config PCIE_CADENCE_PLAT bool diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index 918f8c924487..0440ac6aba5d 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o -obj-$(CONFIG_PCIE_CADENCE_COMMON) +=3D pcie-cadence-ep-common.o +obj-$(CONFIG_PCIE_CADENCE_EP_COMMON) +=3D pcie-cadence-ep-common.o +obj-$(CONFIG_PCIE_CADENCE_HOST_COMMON) +=3D pcie-cadence-host-common.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-common.h b/driv= ers/pci/controller/cadence/pcie-cadence-ep-common.h index a91084bdedd5..9cfd0cfa7459 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep-common.h +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-common.h @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0 */ // Copyright (c) 2017 Cadence -// Cadence PCIe Endpoint controller driver. +// Cadence PCIe Endpoint controller driver // Author: Manikandan K Pillai =20 -#ifndef _PCIE_CADENCE_EP_COMMON_H_ -#define _PCIE_CADENCE_EP_COMMON_H_ +#ifndef _PCIE_CADENCE_EP_COMMON_H +#define _PCIE_CADENCE_EP_COMMON_H =20 #include #include @@ -33,4 +33,4 @@ const struct pci_epc_features *cdns_pcie_ep_get_features(= struct pci_epc *epc, u8 func_no, u8 vfunc_no); =20 -#endif /* _PCIE_CADENCE_EP_COMMON_H_ */ +#endif /* _PCIE_CADENCE_EP_COMMON_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.c new file mode 100644 index 000000000000..21264247951e --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe host controller driver. +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-host-common.h" + +#define LINK_RETRAIN_TIMEOUT HZ + +u64 bar_max_size[] =3D { + [RP_BAR0] =3D _ULL(128 * SZ_2G), + [RP_BAR1] =3D SZ_2G, + [RP_NO_BAR] =3D _BITULL(63), +}; + +int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) +{ + u32 pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; + unsigned long end_jiffies; + u16 lnk_stat; + + /* Wait for link training to complete. Exit after timeout. */ + end_jiffies =3D jiffies + LINK_RETRAIN_TIMEOUT; + do { + lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) + break; + usleep_range(0, 1000); + } while (time_before(jiffies, end_jiffies)); + + if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) + return 0; + + return -ETIMEDOUT; +} + +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + + return -ETIMEDOUT; +} + +int cdns_pcie_retrain(struct cdns_pcie *pcie) +{ + u32 lnk_cap_sls, pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; + u16 lnk_stat, lnk_ctl; + int ret =3D 0; + + /* + * Set retrain bit if current speed is 2.5 GB/s, + * but the PCIe root port support is > 2.5 GB/s. + */ + + lnk_cap_sls =3D cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + + PCI_EXP_LNKCAP)); + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <=3D PCI_EXP_LNKCAP_SLS_2_5GB) + return ret; + + lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) =3D=3D PCI_EXP_LNKSTA_CLS_2_5GB) { + lnk_ctl =3D cdns_pcie_rp_readw(pcie, + pcie_cap_off + PCI_EXP_LNKCTL); + lnk_ctl |=3D PCI_EXP_LNKCTL_RL; + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, + lnk_ctl); + + ret =3D cdns_pcie_host_training_complete(pcie); + if (ret) + return ret; + + ret =3D cdns_pcie_host_wait_for_link(pcie); + } + return ret; +} + +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + int ret; + + ret =3D cdns_pcie_host_wait_for_link(pcie); + + /* + * Retrain link for Gen2 training defect + * if quirk flag is set. + */ + if (!ret && rc->quirk_retrain_flag) + ret =3D cdns_pcie_retrain(pcie); + + return ret; +} + +enum cdns_pcie_rp_bar +cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) +{ + enum cdns_pcie_rp_bar bar, sel_bar; + + sel_bar =3D RP_BAR_UNDEFINED; + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { + if (!rc->avail_ib_bar[bar]) + continue; + + if (size <=3D bar_max_size[bar]) { + if (sel_bar =3D=3D RP_BAR_UNDEFINED) { + sel_bar =3D bar; + continue; + } + + if (bar_max_size[bar] < bar_max_size[sel_bar]) + sel_bar =3D bar; + } + } + + return sel_bar; +} + +enum cdns_pcie_rp_bar +cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) +{ + enum cdns_pcie_rp_bar bar, sel_bar; + + sel_bar =3D RP_BAR_UNDEFINED; + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { + if (!rc->avail_ib_bar[bar]) + continue; + + if (size >=3D bar_max_size[bar]) { + if (sel_bar =3D=3D RP_BAR_UNDEFINED) { + sel_bar =3D bar; + continue; + } + + if (bar_max_size[bar] > bar_max_size[sel_bar]) + sel_bar =3D bar; + } + } + + return sel_bar; +} + +int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, + const struct list_head *b) +{ + struct resource_entry *entry1, *entry2; + + entry1 =3D container_of(a, struct resource_entry, node); + entry2 =3D container_of(b, struct resource_entry, node); + + return resource_size(entry2->res) - resource_size(entry1->res); +} diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.h b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.h new file mode 100644 index 000000000000..f8eae2e963d8 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe Endpoint controller driver +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_HOST_COMMON_H +#define _PCIE_CADENCE_HOST_COMMON_H + +#include +#include + +extern u64 bar_max_size[]; + +int cdns_pcie_host_training_complete(struct cdns_pcie *pcie); +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie); +int cdns_pcie_retrain(struct cdns_pcie *pcie); +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc); +enum cdns_pcie_rp_bar +cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size); +enum cdns_pcie_rp_bar +cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size); +int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, + const struct list_head *b); + +#endif /* _PCIE_CADENCE_HOST_COMMON_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/p= ci/controller/cadence/pcie-cadence-host.c index 59a4631de79f..bfdd0f200cfb 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -12,14 +12,7 @@ #include =20 #include "pcie-cadence.h" - -#define LINK_RETRAIN_TIMEOUT HZ - -static u64 bar_max_size[] =3D { - [RP_BAR0] =3D _ULL(128 * SZ_2G), - [RP_BAR1] =3D SZ_2G, - [RP_NO_BAR] =3D _BITULL(63), -}; +#include "pcie-cadence-host-common.h" =20 static u8 bar_aperture_mask[] =3D { [RP_BAR0] =3D 0x1F, @@ -81,77 +74,6 @@ static struct pci_ops cdns_pcie_host_ops =3D { .write =3D pci_generic_config_write, }; =20 -static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) -{ - u32 pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; - unsigned long end_jiffies; - u16 lnk_stat; - - /* Wait for link training to complete. Exit after timeout. */ - end_jiffies =3D jiffies + LINK_RETRAIN_TIMEOUT; - do { - lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); - if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) - break; - usleep_range(0, 1000); - } while (time_before(jiffies, end_jiffies)); - - if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) - return 0; - - return -ETIMEDOUT; -} - -static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) -{ - struct device *dev =3D pcie->dev; - int retries; - - /* Check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { - if (cdns_pcie_link_up(pcie)) { - dev_info(dev, "Link up\n"); - return 0; - } - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); - } - - return -ETIMEDOUT; -} - -static int cdns_pcie_retrain(struct cdns_pcie *pcie) -{ - u32 lnk_cap_sls, pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; - u16 lnk_stat, lnk_ctl; - int ret =3D 0; - - /* - * Set retrain bit if current speed is 2.5 GB/s, - * but the PCIe root port support is > 2.5 GB/s. - */ - - lnk_cap_sls =3D cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + - PCI_EXP_LNKCAP)); - if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <=3D PCI_EXP_LNKCAP_SLS_2_5GB) - return ret; - - lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); - if ((lnk_stat & PCI_EXP_LNKSTA_CLS) =3D=3D PCI_EXP_LNKSTA_CLS_2_5GB) { - lnk_ctl =3D cdns_pcie_rp_readw(pcie, - pcie_cap_off + PCI_EXP_LNKCTL); - lnk_ctl |=3D PCI_EXP_LNKCTL_RL; - cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, - lnk_ctl); - - ret =3D cdns_pcie_host_training_complete(pcie); - if (ret) - return ret; - - ret =3D cdns_pcie_host_wait_for_link(pcie); - } - return ret; -} - static void cdns_pcie_host_disable_ptm_response(struct cdns_pcie *pcie) { u32 val; @@ -168,23 +90,6 @@ static void cdns_pcie_host_enable_ptm_response(struct c= dns_pcie *pcie) cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL= _PTMRSEN); } =20 -static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) -{ - struct cdns_pcie *pcie =3D &rc->pcie; - int ret; - - ret =3D cdns_pcie_host_wait_for_link(pcie); - - /* - * Retrain link for Gen2 training defect - * if quirk flag is set. - */ - if (!ret && rc->quirk_retrain_flag) - ret =3D cdns_pcie_retrain(pcie); - - return ret; -} - static void cdns_pcie_host_deinit_root_port(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie =3D &rc->pcie; @@ -290,54 +195,6 @@ static int cdns_pcie_host_bar_ib_config(struct cdns_pc= ie_rc *rc, return 0; } =20 -static enum cdns_pcie_rp_bar -cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) -{ - enum cdns_pcie_rp_bar bar, sel_bar; - - sel_bar =3D RP_BAR_UNDEFINED; - for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { - if (!rc->avail_ib_bar[bar]) - continue; - - if (size <=3D bar_max_size[bar]) { - if (sel_bar =3D=3D RP_BAR_UNDEFINED) { - sel_bar =3D bar; - continue; - } - - if (bar_max_size[bar] < bar_max_size[sel_bar]) - sel_bar =3D bar; - } - } - - return sel_bar; -} - -static enum cdns_pcie_rp_bar -cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) -{ - enum cdns_pcie_rp_bar bar, sel_bar; - - sel_bar =3D RP_BAR_UNDEFINED; - for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { - if (!rc->avail_ib_bar[bar]) - continue; - - if (size >=3D bar_max_size[bar]) { - if (sel_bar =3D=3D RP_BAR_UNDEFINED) { - sel_bar =3D bar; - continue; - } - - if (bar_max_size[bar] > bar_max_size[sel_bar]) - sel_bar =3D bar; - } - } - - return sel_bar; -} - static int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, struct resource_entry *entry) { @@ -410,17 +267,6 @@ static int cdns_pcie_host_bar_config(struct cdns_pcie_= rc *rc, return 0; } =20 -static int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_hea= d *a, - const struct list_head *b) -{ - struct resource_entry *entry1, *entry2; - - entry1 =3D container_of(a, struct resource_entry, node); - entry2 =3D container_of(b, struct resource_entry, node); - - return resource_size(entry2->res) - resource_size(entry1->res); -} - static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie =3D &rc->pcie; --=20 2.49.0 From nobody Wed Oct 8 10:00:53 2025 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023099.outbound.protection.outlook.com [40.107.44.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E0B319E82A; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id B0DFA41604F2; Mon, 30 Jun 2025 12:16:06 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v5 07/14] PCI: cadence: Split the common functions for PCIE controller support Date: Mon, 30 Jun 2025 12:15:54 +0800 Message-ID: <20250630041601.399921-8-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250630041601.399921-1-hans.zhang@cixtech.com> References: <20250630041601.399921-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66D0:EE_|JH0PR06MB7268:EE_ X-MS-Office365-Filtering-Correlation-Id: 6e12ee99-e2a1-401c-065e-08ddb78cd7b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|7416014|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?r0G42MHP+BXv01Q3uot8fojNBh64B9VywpwSKIxW8yy/J8mYgsYKJez0O5Xk?= =?us-ascii?Q?h6QHdPHNz62gFePW0fg5MhAR4Nw3N2gbwqBMVmSG3hc97pcPj6T3qLkbWNAM?= =?us-ascii?Q?Ikc0FMOh9f424h2ZKgsVebiPjn2SzQCHtn5oaTNpoaYG5SvAKeCrW/UMMGUm?= =?us-ascii?Q?X7QHekxPqIEoOGWf1g3ihkgFxeizTG6xfX8e23ya40Ls4kCMAlnj86rgoISJ?= =?us-ascii?Q?EMLGsOnVxZhcnN/WwKZAAtDPaCqwTvsEV0Dd2lILXD9jVVeRtLSPzYn1rZmu?= =?us-ascii?Q?5U3Q5Dvjqpg7phBEMGkjzXNe6trMMfE0JVg73+zjHvBUjx6nNOxyBW5AqY/M?= =?us-ascii?Q?1n1hMEm2m3EegyTvJsoS5ijseCOxDlgaBdjf/zgmYwtTcTyHYmIoeEabZVIQ?= =?us-ascii?Q?+2WcLxPCE7ZTySas8KEkifnx/Q5tzyU9VlFQJUxebvLPkMlU34XEpzfm4T36?= =?us-ascii?Q?KmEjv9J33lWGm9IxtZ6T7tk3dVOL09C8RB9xNwNPxnBet33VPQiY/kaWYVcC?= =?us-ascii?Q?+nqIydp/ZgRw4ts7Wvo4K9Z6o1GKSAx0LULt4LROxW7KZAwkZd2VG8uSmmjz?= =?us-ascii?Q?mTry+pR2RqOANz2N530okmV7eE3LwGwIoG4/Fb/BiuwUwoinqPyVr2pqLyoA?= =?us-ascii?Q?U80S1j1fQDkqt20+MqPiJYBrq8X7YXh7ojxc8IRxCQZK1s7IScukAe5fgKaI?= =?us-ascii?Q?CN3PNGfpUPlf9AUEJQEEsvrtFTLPWsAPWBHrkeRTBMHAiVUFmM7ZOittt9sp?= =?us-ascii?Q?81XO716RsxUWsQLqYx0dqxW6k/xEJMShTLIUksDgJhre5Sli+HG5iNK/qyj5?= =?us-ascii?Q?CDkzeF7SBbn3Dm1UzKbVrlLptWnwe6N7e82V4VpnkXIZvmRZdKIBCBY2mox9?= =?us-ascii?Q?fW5G8EPm4gk7QFErINdw4k1yvS85xxtZ8A80l0ZsFr1wFGEVfkMwlC3ovU2U?= =?us-ascii?Q?K3vmUWdJ3DZazSvesnvP6/p2bQQXPI2yXLyopdJh+f0+piKxtloru4CD8IL8?= =?us-ascii?Q?OoU8PDAiB0ncsmiFfvqh8Yi/zX6I2JeK2Dh+cHheH0a8ORUV1nR3h2Z97Q7U?= =?us-ascii?Q?8SNyUcGvmJlLHGnK/ONbI0PMkv4pjKZG0DvWyTk01N5QVn0dCWYBjODU1bFD?= =?us-ascii?Q?N1dXWhhcNtUAtNMKfw52Igm+SRmHRIUaCi7e9G9uCT/1CvlDCw6oZlci8lS5?= =?us-ascii?Q?Si3ALlU1GbBgCq5Vk/RYY0Kgi9nnjXaB8wLj+Zloa9NnQb7UbjUIKI/x2lkP?= =?us-ascii?Q?lhYv8tiDC1EikSdkYKELxl96A3nmHnrXCyzRYwwvX5IhBQjF6vr9B6iYU7xP?= =?us-ascii?Q?H1+BNTA3XRct8xQj0iAZKrJBkp7F6GN/Oee8199myxOygpIhVlh5iF5M3Z0D?= =?us-ascii?Q?38f3KE9848VGqkkgkUu6SCHgufRojjLDi7DK9EpNOVJRUKDfvRw18E/uysiT?= =?us-ascii?Q?gEZ0IZPuWlV1xZPNq4darMYpfqjSa/gfisso/sjXqaB5/pw1jnMER2Bt7iRu?= =?us-ascii?Q?P7k24XbQ6ByBQBylFsVDmYw6hIFUXSeuwSFn?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(7416014)(36860700013)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 04:16:09.6011 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e12ee99-e2a1-401c-065e-08ddb78cd7b7 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66D0.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: JH0PR06MB7268 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Separate the functions to platform specific functions and common library functions. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 2 +- .../controller/cadence/pcie-cadence-common.c | 134 ++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.c | 128 ----------------- 3 files changed, 135 insertions(+), 129 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-common.c diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index 0440ac6aba5d..3fe5dd2bbd5b 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o +obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence-common.o pcie-cadence.o obj-$(CONFIG_PCIE_CADENCE_EP_COMMON) +=3D pcie-cadence-ep-common.o obj-$(CONFIG_PCIE_CADENCE_HOST_COMMON) +=3D pcie-cadence-host-common.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-common.c b/drivers= /pci/controller/cadence/pcie-cadence-common.c new file mode 100644 index 000000000000..8399a73b3a4d --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-common.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver. +// Author: Manikandan K Pillai + +#include +#include + +#include "pcie-cadence.h" + +void cdns_pcie_disable_phy(struct cdns_pcie *pcie) +{ + int i =3D pcie->phy_count; + + while (i--) { + phy_power_off(pcie->phy[i]); + phy_exit(pcie->phy[i]); + } +} + +int cdns_pcie_enable_phy(struct cdns_pcie *pcie) +{ + int ret; + int i; + + for (i =3D 0; i < pcie->phy_count; i++) { + ret =3D phy_init(pcie->phy[i]); + if (ret < 0) + goto err_phy; + + ret =3D phy_power_on(pcie->phy[i]); + if (ret < 0) { + phy_exit(pcie->phy[i]); + goto err_phy; + } + } + + return 0; + +err_phy: + while (--i >=3D 0) { + phy_power_off(pcie->phy[i]); + phy_exit(pcie->phy[i]); + } + + return ret; +} + +int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) +{ + struct device_node *np =3D dev->of_node; + int phy_count; + struct phy **phy; + struct device_link **link; + int i; + int ret; + const char *name; + + phy_count =3D of_property_count_strings(np, "phy-names"); + if (phy_count < 1) { + dev_info(dev, "no \"phy-names\" property found; PHY will not be initiali= zed\n"); + pcie->phy_count =3D 0; + return 0; + } + + phy =3D devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + link =3D devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); + if (!link) + return -ENOMEM; + + for (i =3D 0; i < phy_count; i++) { + of_property_read_string_index(np, "phy-names", i, &name); + phy[i] =3D devm_phy_get(dev, name); + if (IS_ERR(phy[i])) { + ret =3D PTR_ERR(phy[i]); + goto err_phy; + } + link[i] =3D device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); + if (!link[i]) { + devm_phy_put(dev, phy[i]); + ret =3D -EINVAL; + goto err_phy; + } + } + + pcie->phy_count =3D phy_count; + pcie->phy =3D phy; + pcie->link =3D link; + + ret =3D cdns_pcie_enable_phy(pcie); + if (ret) + goto err_phy; + + return 0; + +err_phy: + while (--i >=3D 0) { + device_link_del(link[i]); + devm_phy_put(dev, phy[i]); + } + + return ret; +} + +static int cdns_pcie_suspend_noirq(struct device *dev) +{ + struct cdns_pcie *pcie =3D dev_get_drvdata(dev); + + cdns_pcie_disable_phy(pcie); + + return 0; +} + +static int cdns_pcie_resume_noirq(struct device *dev) +{ + struct cdns_pcie *pcie =3D dev_get_drvdata(dev); + int ret; + + ret =3D cdns_pcie_enable_phy(pcie); + if (ret) { + dev_err(dev, "failed to enable PHY\n"); + return ret; + } + + return 0; +} + +const struct dev_pm_ops cdns_pcie_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, + cdns_pcie_resume_noirq) +}; diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/co= ntroller/cadence/pcie-cadence.c index 70a19573440e..51c9bc4eb174 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -152,134 +152,6 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie= *pcie, u32 r) } EXPORT_SYMBOL_GPL(cdns_pcie_reset_outbound_region); =20 -void cdns_pcie_disable_phy(struct cdns_pcie *pcie) -{ - int i =3D pcie->phy_count; - - while (i--) { - phy_power_off(pcie->phy[i]); - phy_exit(pcie->phy[i]); - } -} -EXPORT_SYMBOL_GPL(cdns_pcie_disable_phy); - -int cdns_pcie_enable_phy(struct cdns_pcie *pcie) -{ - int ret; - int i; - - for (i =3D 0; i < pcie->phy_count; i++) { - ret =3D phy_init(pcie->phy[i]); - if (ret < 0) - goto err_phy; - - ret =3D phy_power_on(pcie->phy[i]); - if (ret < 0) { - phy_exit(pcie->phy[i]); - goto err_phy; - } - } - - return 0; - -err_phy: - while (--i >=3D 0) { - phy_power_off(pcie->phy[i]); - phy_exit(pcie->phy[i]); - } - - return ret; -} -EXPORT_SYMBOL_GPL(cdns_pcie_enable_phy); - -int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) -{ - struct device_node *np =3D dev->of_node; - int phy_count; - struct phy **phy; - struct device_link **link; - int i; - int ret; - const char *name; - - phy_count =3D of_property_count_strings(np, "phy-names"); - if (phy_count < 1) { - dev_info(dev, "no \"phy-names\" property found; PHY will not be initiali= zed\n"); - pcie->phy_count =3D 0; - return 0; - } - - phy =3D devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - - link =3D devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); - if (!link) - return -ENOMEM; - - for (i =3D 0; i < phy_count; i++) { - of_property_read_string_index(np, "phy-names", i, &name); - phy[i] =3D devm_phy_get(dev, name); - if (IS_ERR(phy[i])) { - ret =3D PTR_ERR(phy[i]); - goto err_phy; - } - link[i] =3D device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); - if (!link[i]) { - devm_phy_put(dev, phy[i]); - ret =3D -EINVAL; - goto err_phy; - } - } - - pcie->phy_count =3D phy_count; - pcie->phy =3D phy; - pcie->link =3D link; - - ret =3D cdns_pcie_enable_phy(pcie); - if (ret) - goto err_phy; - - return 0; - -err_phy: - while (--i >=3D 0) { - device_link_del(link[i]); - devm_phy_put(dev, phy[i]); - } - - return ret; -} -EXPORT_SYMBOL_GPL(cdns_pcie_init_phy); - -static int cdns_pcie_suspend_noirq(struct device *dev) -{ - struct cdns_pcie *pcie =3D dev_get_drvdata(dev); - - cdns_pcie_disable_phy(pcie); - - return 0; -} - -static int cdns_pcie_resume_noirq(struct device *dev) -{ - struct cdns_pcie *pcie =3D dev_get_drvdata(dev); - int ret; - - ret =3D cdns_pcie_enable_phy(pcie); - if (ret) { - dev_err(dev, "failed to enable PHY\n"); - return ret; - } - - return 0; -} - -const struct dev_pm_ops cdns_pcie_pm_ops =3D { - NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, - cdns_pcie_resume_noirq) -}; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id B965D41604F5; Mon, 30 Jun 2025 12:16:06 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v5 08/14] PCI: cadence: Add support for High Performance Arch(HPA) controller Date: Mon, 30 Jun 2025 12:15:55 +0800 Message-ID: <20250630041601.399921-9-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250630041601.399921-1-hans.zhang@cixtech.com> References: <20250630041601.399921-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CA:EE_|SEZPR06MB7137:EE_ X-MS-Office365-Filtering-Correlation-Id: bc684230-5e55-4fb6-2298-08ddb78cd79a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|82310400026|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?/whj6Hvevc74aPw0Gi4gK6HGe23OqAwrYmEA8oFhiqYTiORl58B0zl2Lougz?= =?us-ascii?Q?OfFBfzQgKWNJAgO4KvEkCPPrz0VYaGAEbfKh8COeOmsi4xals17d/rBGizST?= =?us-ascii?Q?7Ki7Vug75jWcMOGwa/L+296NU7oGeBPGPc7TYw4sGjFkK6um1PnCS5annoSa?= =?us-ascii?Q?hv9TbUlJaFMxcRDgvgHcRsAV/gDziKGMDWqJgF380OaAin9mgei0NJOM5o8J?= =?us-ascii?Q?6YLXkhVrc82P5i1CDIuhcYD9Pt9M6J+4OlhN1IUTUa4be97EmjYBLeF/slwy?= =?us-ascii?Q?odHsox5B//a9b6zgC9ROTTAeGhjevL1d/CwVwVSJ342nzWkYfY4Btm3fbMJc?= =?us-ascii?Q?a4iBAlHQoFoUzylAipRapXzlRH+mP7EjeVuam8RycdR0wnoGDkJWUqDgJ3Ah?= =?us-ascii?Q?k0dAFEb4b/Xf4I7ZtdZAVUsVKrTZA53mznSnxI+rowQiQ6mNJgMqlVW9B2C5?= =?us-ascii?Q?AKWTPeS/o4OzoxGGNLvyNkJimYRg/pw72TYLjssRchcsZMbDnsukic8qnb1o?= =?us-ascii?Q?5exyUKaji6T1kYHk0dazGMz+X4yO284n0gcENHkKN2w1As6uxBBY/su2MvS5?= =?us-ascii?Q?HeKQ1hzBvD0jiNZVDZCWjugGSsQeSyAT13D1P63WhLWfuFxgzdXjk3VyxJBb?= =?us-ascii?Q?oODq8mb5iEMFnwJo9tr/+aSA0K7F1fdgfOKcSGUqJhc63ikx4rhakAyWRxbA?= =?us-ascii?Q?H3N+h0FDIM5vkyxQdtGpM+ZPSJjEcU5U4gYHRDnz+dCEOs8jHEaXKULF1gPt?= =?us-ascii?Q?txJyurddULKtfzWqg/Z0K3gk2pwaVHiWByNTR6Hm1DTVYEDvxYXUWWSGB0lX?= =?us-ascii?Q?0xNpNH6MHTUgSc1pglqwiqda718nTb7xUiOZSmedFVbPQB/QRhpE0ZoVrJxP?= =?us-ascii?Q?xOZFPTZXIjCns+g+ZdNzzBM3mpIiKTyVnjAQ7byPeuRIsqEYM88cNpoprKR6?= =?us-ascii?Q?jni9Ms11+Hy3kyTIiC9OOfRNNJb6NiqYKo+bZrf4wa3cPAVixftXzTCuCiQT?= =?us-ascii?Q?upBypF2JkRKn1AlJPixh0Zpf6hPj1lrUIgfn6zXGCsu+cyXtzJKBDCHfQfVB?= =?us-ascii?Q?med9KjwVNyhP8s4sI69+vhSBJkHOsp070DgkpWDzvU00PLwP8nPcPwkzaS2L?= =?us-ascii?Q?co7xBbe6+vVN635DcuYf1iXMGr039EV/HXT7G7LLxWEcuxujkMjjNmE58Mgt?= =?us-ascii?Q?KnolPsp9F7dkGky5ZPulG4ypN4er5x8rYs5GFwo7qyyn6J9gq1zzAviZKPG8?= =?us-ascii?Q?/UwsxiT9zE5uc1v2Pi8jVLBLtlG5MSMRCS1KG0S3CAywUSniX5/HO5WxH8/R?= =?us-ascii?Q?OqU4kVglPtoqM3X/FRhmbi638y/B0o6OsuTCWzhO33Ef17eNiFVGa9tDOXKd?= =?us-ascii?Q?eOYwHBn4n2aiu2rKwPYqSLhTdATd3z+JP/KkjOyAvr44DKi4/Qn0UDrCwVwj?= =?us-ascii?Q?3Tlgr00M/cUaMs7pmYZTTlSP+/IwJvfyxZnaqNHickmQZTxJ91eUxL+4rNE8?= =?us-ascii?Q?B4M3YpUGcXQ0pzbgJLcs+Jrxtt/vYEqOfKwg?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(82310400026)(1800799024)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 04:16:09.5372 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc684230-5e55-4fb6-2298-08ddb78cd79a X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CA.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEZPR06MB7137 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add support for Cadence PCIe RP and EP configuration for High Performance Architecture(HPA) controllers. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 6 +- .../controller/cadence/pcie-cadence-ep-hpa.c | 523 ++++++++++++++++ .../cadence/pcie-cadence-host-hpa.c | 584 ++++++++++++++++++ .../pci/controller/cadence/pcie-cadence-hpa.c | 199 ++++++ .../controller/cadence/pcie-cadence-plat.c | 19 +- drivers/pci/controller/cadence/pcie-cadence.c | 10 + drivers/pci/controller/cadence/pcie-cadence.h | 69 ++- 7 files changed, 1395 insertions(+), 15 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-ep-hpa.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-hpa.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa.c diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index 3fe5dd2bbd5b..e2df24ff4c33 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence-common.o pcie-cadence.o +obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence-common.o pcie-cadence.o pcie-= cadence-hpa.o obj-$(CONFIG_PCIE_CADENCE_EP_COMMON) +=3D pcie-cadence-ep-common.o obj-$(CONFIG_PCIE_CADENCE_HOST_COMMON) +=3D pcie-cadence-host-common.o -obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o -obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o +obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o pcie-cadence-host= -hpa.o +obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o pcie-cadence-ep-hpa.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-hpa.c b/drivers= /pci/controller/cadence/pcie-cadence-ep-hpa.c new file mode 100644 index 000000000000..5d769a460d76 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-hpa.c @@ -0,0 +1,523 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe endpoint controller driver. +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-ep-common.h" + +static int cdns_pcie_hpa_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr, u64 pci_addr, size_t size) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 r; + + r =3D find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG); + if (r >=3D ep->max_regions - 1) { + dev_err(&epc->dev, "no free outbound region\n"); + return -EINVAL; + } + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + cdns_pcie_hpa_set_outbound_region(pcie, 0, fn, r, false, addr, pci_addr, = size); + + set_bit(r, &ep->ob_region_map); + ep->ob_addr[r] =3D addr; + + return 0; +} + +static void cdns_pcie_hpa_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 r; + + for (r =3D 0; r < ep->max_regions - 1; r++) + if (ep->ob_addr[r] =3D=3D addr) + break; + + if (r =3D=3D ep->max_regions - 1) + return; + + cdns_pcie_hpa_reset_outbound_region(pcie, r); + + ep->ob_addr[r] =3D 0; + clear_bit(r, &ep->ob_region_map); +} + +static void cdns_pcie_hpa_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u= 8 intx, + bool is_asserted) +{ + struct cdns_pcie *pcie =3D &ep->pcie; + unsigned long flags; + u32 offset; + u16 status; + u8 msg_code; + + intx &=3D 3; + + /* Set the outbound region if needed. */ + if (unlikely(ep->irq_pci_addr !=3D CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY || + ep->irq_pci_fn !=3D fn)) { + /* First region was reserved for IRQ writes. */ + cdns_pcie_hpa_set_outbound_region_for_normal_msg(pcie, 0, fn, 0, ep->irq= _phys_addr); + ep->irq_pci_addr =3D CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY; + ep->irq_pci_fn =3D fn; + } + + if (is_asserted) { + ep->irq_pending |=3D BIT(intx); + msg_code =3D PCIE_MSG_CODE_ASSERT_INTA + intx; + } else { + ep->irq_pending &=3D ~BIT(intx); + msg_code =3D PCIE_MSG_CODE_DEASSERT_INTA + intx; + } + + spin_lock_irqsave(&ep->lock, flags); + status =3D cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS); + if (((status & PCI_STATUS_INTERRUPT) !=3D 0) ^ (ep->irq_pending !=3D 0)) { + status ^=3D PCI_STATUS_INTERRUPT; + cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status); + } + spin_unlock_irqrestore(&ep->lock, flags); + + offset =3D CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) | + CDNS_PCIE_NORMAL_MSG_CODE(msg_code); + writel(0, ep->irq_cpu_addr + offset); +} + +static int cdns_pcie_hpa_ep_send_intx_irq(struct cdns_pcie_ep *ep, u8 fn, = u8 vfn, + u8 intx) +{ + u16 cmd; + + cmd =3D cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND); + if (cmd & PCI_COMMAND_INTX_DISABLE) + return -EINVAL; + + cdns_pcie_hpa_ep_assert_intx(ep, fn, intx, true); + + /* The mdelay() value was taken from dra7xx_pcie_raise_intx_irq() */ + mdelay(1); + cdns_pcie_hpa_ep_assert_intx(ep, fn, intx, false); + return 0; +} + +static int cdns_pcie_hpa_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u= 8 vfn, + u8 interrupt_num) +{ + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u16 flags, mme, data, data_mask; + u8 msi_count; + u64 pci_addr, pci_addr_mask =3D 0xff; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Check whether the MSI feature has been enabled by the PCI host. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* Get the number of enabled MSIs */ + mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); + msi_count =3D 1 << mme; + if (!interrupt_num || interrupt_num > msi_count) + return -EINVAL; + + /* Compute the data value to be written. */ + data_mask =3D msi_count - 1; + data =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); + data =3D (data & ~data_mask) | ((interrupt_num - 1) & data_mask); + + /* Get the PCI address where to write the data into. */ + pci_addr =3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); + pci_addr <<=3D 32; + pci_addr |=3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); + pci_addr &=3D GENMASK_ULL(63, 2); + + /* Set the outbound region if needed. */ + if (unlikely(ep->irq_pci_addr !=3D (pci_addr & ~pci_addr_mask) || + ep->irq_pci_fn !=3D fn)) { + /* First region was reserved for IRQ writes. */ + cdns_pcie_hpa_set_outbound_region(pcie, 0, fn, 0, + false, + ep->irq_phys_addr, + pci_addr & ~pci_addr_mask, + pci_addr_mask + 1); + ep->irq_pci_addr =3D (pci_addr & ~pci_addr_mask); + ep->irq_pci_fn =3D fn; + } + writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); + + return 0; +} + +static int cdns_pcie_hpa_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, = u8 vfn, + u16 interrupt_num) +{ + u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 tbl_offset, msg_data, reg; + struct cdns_pcie *pcie =3D &ep->pcie; + struct pci_epf_msix_tbl *msix_tbl; + struct cdns_pcie_epf *epf; + u64 pci_addr_mask =3D 0xff; + u64 msg_addr; + u16 flags; + u8 bir; + + epf =3D &ep->epf[fn]; + if (vfn > 0) + epf =3D &epf->epf[vfn - 1]; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Check whether the MSI-X feature has been enabled by the PCI host. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSIX_FLAGS); + if (!(flags & PCI_MSIX_FLAGS_ENABLE)) + return -EINVAL; + + reg =3D cap + PCI_MSIX_TABLE; + tbl_offset =3D cdns_pcie_ep_fn_readl(pcie, fn, reg); + bir =3D FIELD_GET(PCI_MSIX_TABLE_BIR, tbl_offset); + tbl_offset &=3D PCI_MSIX_TABLE_OFFSET; + + msix_tbl =3D epf->epf_bar[bir]->addr + tbl_offset; + msg_addr =3D msix_tbl[(interrupt_num - 1)].msg_addr; + msg_data =3D msix_tbl[(interrupt_num - 1)].msg_data; + + /* Set the outbound region if needed. */ + if (ep->irq_pci_addr !=3D (msg_addr & ~pci_addr_mask) || + ep->irq_pci_fn !=3D fn) { + /* First region was reserved for IRQ writes. */ + cdns_pcie_hpa_set_outbound_region(pcie, 0, fn, 0, + false, + ep->irq_phys_addr, + msg_addr & ~pci_addr_mask, + pci_addr_mask + 1); + ep->irq_pci_addr =3D (msg_addr & ~pci_addr_mask); + ep->irq_pci_fn =3D fn; + } + writel(msg_data, ep->irq_cpu_addr + (msg_addr & pci_addr_mask)); + + return 0; +} + +static int cdns_pcie_hpa_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn, + unsigned int type, u16 interrupt_num) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + struct device *dev =3D pcie->dev; + + switch (type) { + case PCI_IRQ_INTX: + if (vfn > 0) { + dev_err(dev, "Cannot raise INTX interrupts for VF\n"); + return -EINVAL; + } + return cdns_pcie_hpa_ep_send_intx_irq(ep, fn, vfn, 0); + + case PCI_IRQ_MSI: + return cdns_pcie_hpa_ep_send_msi_irq(ep, fn, vfn, interrupt_num); + + case PCI_IRQ_MSIX: + return cdns_pcie_hpa_ep_send_msix_irq(ep, fn, vfn, interrupt_num); + + default: + break; + } + + return -EINVAL; +} + +static int cdns_pcie_hpa_ep_start(struct pci_epc *epc) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + struct device *dev =3D pcie->dev; + int max_epfs =3D sizeof(epc->function_num_map) * 8; + int ret, epf, last_fn; + u32 reg, value; + + /* + * BIT(0) is hardwired to 1, hence function 0 is always enabled + * and can't be disabled anyway. + */ + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, + CDNS_PCIE_HPA_LM_EP_FUNC_CFG, epc->function_num_map); + + /* + * Next function field in ARI_CAP_AND_CTR register for last function + * should be 0. Clear Next Function Number field for the last + * function used. + */ + last_fn =3D find_last_bit(&epc->function_num_map, BITS_PER_LONG); + reg =3D CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(last_fn); + value =3D cdns_pcie_readl(pcie, reg); + value &=3D ~CDNS_PCIE_ARI_CAP_NFN_MASK; + cdns_pcie_writel(pcie, reg, value); + + if (ep->quirk_disable_flr) { + for (epf =3D 0; epf < max_epfs; epf++) { + if (!(epc->function_num_map & BIT(epf))) + continue; + + value =3D cdns_pcie_ep_fn_readl(pcie, epf, + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP); + value &=3D ~PCI_EXP_DEVCAP_FLR; + cdns_pcie_ep_fn_writel(pcie, epf, + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP, value); + } + } + + ret =3D cdns_pcie_start_link(pcie); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + + return 0; +} + +static int cdns_pcie_hpa_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_bar *epf_bar) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie_epf *epf =3D &ep->epf[fn]; + struct cdns_pcie *pcie =3D &ep->pcie; + dma_addr_t bar_phys =3D epf_bar->phys_addr; + enum pci_barno bar =3D epf_bar->barno; + int flags =3D epf_bar->flags; + u32 addr0, addr1, reg, cfg, b, aperture, ctrl; + u64 sz; + + /* BAR size is 2^(aperture + 7) */ + sz =3D max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE); + + /* + * roundup_pow_of_two() returns an unsigned long, which is not suited + * for 64bit values. + */ + sz =3D 1ULL << fls64(sz - 1); + + /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ + aperture =3D ilog2(sz) - 7; + + if ((flags & PCI_BASE_ADDRESS_SPACE) =3D=3D PCI_BASE_ADDRESS_SPACE_IO) { + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS; + } else { + bool is_prefetch =3D !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); + bool is_64bits =3D !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64); + + if (is_64bits && (bar & 1)) + return -EINVAL; + + if (is_64bits && is_prefetch) + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; + else if (is_prefetch) + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS; + else if (is_64bits) + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS; + else + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS; + } + + addr0 =3D lower_32_bits(bar_phys); + addr1 =3D upper_32_bits(bar_phys); + + if (vfn =3D=3D 1) + reg =3D CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn); + else + reg =3D CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn); + b =3D (bar < BAR_4) ? bar : bar - BAR_4; + + if (vfn =3D=3D 0 || vfn =3D=3D 1) { + cfg =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, reg); + cfg &=3D ~(CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); + cfg |=3D (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) | + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, reg, cfg); + } + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), addr1); + + if (vfn > 0) + epf =3D &epf->epf[vfn - 1]; + epf->epf_bar[bar] =3D epf_bar; + + return 0; +} + +static void cdns_pcie_hpa_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_bar *epf_bar) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie_epf *epf =3D &ep->epf[fn]; + struct cdns_pcie *pcie =3D &ep->pcie; + enum pci_barno bar =3D epf_bar->barno; + u32 reg, cfg, b, ctrl; + + if (vfn =3D=3D 1) + reg =3D CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn); + else + reg =3D CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn); + b =3D (bar < BAR_4) ? bar : bar - BAR_4; + + if (vfn =3D=3D 0 || vfn =3D=3D 1) { + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED; + cfg =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, reg); + cfg &=3D ~(CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); + cfg |=3D CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, reg, cfg); + } + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0); + + if (vfn > 0) + epf =3D &epf->epf[vfn - 1]; + epf->epf_bar[bar] =3D NULL; +} + +static const struct pci_epc_ops cdns_pcie_hpa_epc_ops =3D { + .write_header =3D cdns_pcie_ep_write_header, + .set_bar =3D cdns_pcie_hpa_ep_set_bar, + .clear_bar =3D cdns_pcie_hpa_ep_clear_bar, + .map_addr =3D cdns_pcie_hpa_ep_map_addr, + .unmap_addr =3D cdns_pcie_hpa_ep_unmap_addr, + .set_msi =3D cdns_pcie_ep_set_msi, + .get_msi =3D cdns_pcie_ep_get_msi, + .set_msix =3D cdns_pcie_ep_set_msix, + .get_msix =3D cdns_pcie_ep_get_msix, + .raise_irq =3D cdns_pcie_hpa_ep_raise_irq, + .map_msi_irq =3D cdns_pcie_ep_map_msi_irq, + .start =3D cdns_pcie_hpa_ep_start, + .get_features =3D cdns_pcie_ep_get_features, +}; + +int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep) +{ + struct device *dev =3D ep->pcie.dev; + struct platform_device *pdev =3D to_platform_device(dev); + struct device_node *np =3D dev->of_node; + struct cdns_pcie *pcie =3D &ep->pcie; + struct cdns_pcie_epf *epf; + struct resource *res; + struct pci_epc *epc; + int ret; + int i; + + pcie->is_rc =3D false; + + pcie->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); + if (IS_ERR(pcie->reg_base)) { + dev_err(dev, "missing \"reg\"\n"); + return PTR_ERR(pcie->reg_base); + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); + if (!res) { + dev_err(dev, "missing \"mem\"\n"); + return -EINVAL; + } + pcie->mem_res =3D res; + + ep->max_regions =3D CDNS_PCIE_MAX_OB; + of_property_read_u32(np, "cdns,max-outbound-regions", &ep->max_regions); + + ep->ob_addr =3D devm_kcalloc(dev, + ep->max_regions, sizeof(*ep->ob_addr), + GFP_KERNEL); + if (!ep->ob_addr) + return -ENOMEM; + + epc =3D devm_pci_epc_create(dev, &cdns_pcie_hpa_epc_ops); + if (IS_ERR(epc)) { + dev_err(dev, "failed to create epc device\n"); + return PTR_ERR(epc); + } + + epc_set_drvdata(epc, ep); + + if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) + epc->max_functions =3D 1; + + ep->epf =3D devm_kcalloc(dev, epc->max_functions, sizeof(*ep->epf), + GFP_KERNEL); + if (!ep->epf) + return -ENOMEM; + + epc->max_vfs =3D devm_kcalloc(dev, epc->max_functions, + sizeof(*epc->max_vfs), GFP_KERNEL); + if (!epc->max_vfs) + return -ENOMEM; + + ret =3D of_property_read_u8_array(np, "max-virtual-functions", + epc->max_vfs, epc->max_functions); + if (ret =3D=3D 0) { + for (i =3D 0; i < epc->max_functions; i++) { + epf =3D &ep->epf[i]; + if (epc->max_vfs[i] =3D=3D 0) + continue; + epf->epf =3D devm_kcalloc(dev, epc->max_vfs[i], + sizeof(*ep->epf), GFP_KERNEL); + if (!epf->epf) + return -ENOMEM; + } + } + + ret =3D pci_epc_mem_init(epc, pcie->mem_res->start, + resource_size(pcie->mem_res), PAGE_SIZE); + if (ret < 0) { + dev_err(dev, "failed to initialize the memory space\n"); + return ret; + } + + ep->irq_cpu_addr =3D pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, + SZ_128K); + if (!ep->irq_cpu_addr) { + dev_err(dev, "failed to reserve memory space for MSI\n"); + ret =3D -ENOMEM; + goto free_epc_mem; + } + ep->irq_pci_addr =3D CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE; + /* Reserve region 0 for IRQs */ + set_bit(0, &ep->ob_region_map); + + if (ep->quirk_detect_quiet_flag) + cdns_pcie_hpa_detect_quiet_min_delay_set(&ep->pcie); + + spin_lock_init(&ep->lock); + + pci_epc_init_notify(epc); + + return 0; + + free_epc_mem: + pci_epc_mem_exit(epc); + + return ret; +} diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drive= rs/pci/controller/cadence/pcie-cadence-host-hpa.c new file mode 100644 index 000000000000..94cba8ec4860 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c @@ -0,0 +1,584 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe host controller driver. +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-host-common.h" + +static u8 bar_aperture_mask[] =3D { + [RP_BAR0] =3D 0x1F, + [RP_BAR1] =3D 0xF, +}; + +void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) +{ + struct pci_host_bridge *bridge =3D pci_find_host_bridge(bus); + struct cdns_pcie_rc *rc =3D pci_host_bridge_priv(bridge); + struct cdns_pcie *pcie =3D &rc->pcie; + unsigned int busn =3D bus->number; + u32 addr0, desc0, desc1, ctrl0; + u32 regval; + + if (pci_is_root_bus(bus)) { + /* + * Only the root port (devfn =3D=3D 0) is connected to this bus. + * All other PCI devices are behind some bridge hence on another + * bus. + */ + if (devfn) + return NULL; + + return pcie->reg_base + (where & 0xfff); + } + + /* Clear AXI link-down status */ + regval =3D cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT= _LINKDOWN); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN, + (regval & ~GENMASK(0, 0))); + + desc1 =3D 0; + ctrl0 =3D 0; + + /* Update Output registers for AXI region 0. */ + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(12) | + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) | + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(busn); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), addr0); + + desc1 =3D cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0)); + desc1 &=3D ~CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK; + desc1 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); + ctrl0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; + + if (busn =3D=3D bridge->busnr + 1) + desc0 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0; + else + desc0 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1; + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), desc0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), ctrl0); + + return rc->cfg_base + (where & 0xfff); +} + +int cdns_pcie_hpa_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + return -ETIMEDOUT; +} + +int cdns_pcie_hpa_host_start_link(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + int ret; + + ret =3D cdns_pcie_host_wait_for_link(pcie); + + /* + * Retrain link for Gen2 training defect + * if quirk flag is set. + */ + if (!ret && rc->quirk_retrain_flag) + ret =3D cdns_pcie_retrain(pcie); + + return ret; +} + +static struct pci_ops cdns_pcie_hpa_host_ops =3D { + .map_bus =3D cdns_pci_hpa_map_bus, + .read =3D pci_generic_config_read, + .write =3D pci_generic_config_write, +}; + +static void cdns_pcie_hpa_host_enable_ptm_response(struct cdns_pcie *pcie) +{ + u32 val; + + val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_C= TRL); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL, + val | CDNS_PCIE_HPA_LM_TPM_CTRL_PTMRSEN); +} + +static int cdns_pcie_hpa_host_bar_ib_config(struct cdns_pcie_rc *rc, + enum cdns_pcie_rp_bar bar, + u64 cpu_addr, u64 size, + unsigned long flags) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + u32 addr0, addr1, aperture, value; + + if (!rc->avail_ib_bar[bar]) + return -EBUSY; + + rc->avail_ib_bar[bar] =3D false; + + aperture =3D ilog2(size); + addr0 =3D CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(aperture) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, + CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, + CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar), addr1); + + if (bar =3D=3D RP_NO_BAR) + return 0; + + value =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_H= PA_LM_RC_BAR_CFG); + value &=3D ~(HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) | + HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) | + HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) | + HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) | + HPA_LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 2)); + if (size + cpu_addr >=3D SZ_4G) { + if (!(flags & IORESOURCE_PREFETCH)) + value |=3D HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar); + value |=3D HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar); + } else { + if (!(flags & IORESOURCE_PREFETCH)) + value |=3D HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar); + value |=3D HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar); + } + + value |=3D HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_= BAR_CFG, value); + + return 0; +} + +static int cdns_pcie_hpa_host_bar_config(struct cdns_pcie_rc *rc, + struct resource_entry *entry) +{ + u64 cpu_addr, pci_addr, size, winsize; + struct cdns_pcie *pcie =3D &rc->pcie; + struct device *dev =3D pcie->dev; + enum cdns_pcie_rp_bar bar; + unsigned long flags; + int ret; + + cpu_addr =3D entry->res->start; + pci_addr =3D entry->res->start - entry->offset; + flags =3D entry->res->flags; + size =3D resource_size(entry->res); + + if (entry->offset) { + dev_err(dev, "PCI addr: %llx must be equal to CPU addr: %llx\n", + pci_addr, cpu_addr); + return -EINVAL; + } + + while (size > 0) { + /* + * Try to find a minimum BAR whose size is greater than + * or equal to the remaining resource_entry size. This will + * fail if the size of each of the available BARs is less than + * the remaining resource_entry size. + * If a minimum BAR is found, IB ATU will be configured and + * exited. + */ + bar =3D cdns_pcie_host_find_min_bar(rc, size); + if (bar !=3D RP_BAR_UNDEFINED) { + ret =3D cdns_pcie_hpa_host_bar_ib_config(rc, bar, cpu_addr, + size, flags); + if (ret) + dev_err(dev, "IB BAR: %d config failed\n", bar); + return ret; + } + + /* + * If the control reaches here, it would mean the remaining + * resource_entry size cannot be fitted in a single BAR. So we + * find a maximum BAR whose size is less than or equal to the + * remaining resource_entry size and split the resource entry + * so that part of resource entry is fitted inside the maximum + * BAR. The remaining size would be fitted during the next + * iteration of the loop. + * If a maximum BAR is not found, there is no way we can fit + * this resource_entry, so we error out. + */ + bar =3D cdns_pcie_host_find_max_bar(rc, size); + if (bar =3D=3D RP_BAR_UNDEFINED) { + dev_err(dev, "No free BAR to map cpu_addr %llx\n", + cpu_addr); + return -EINVAL; + } + + winsize =3D bar_max_size[bar]; + ret =3D cdns_pcie_hpa_host_bar_ib_config(rc, bar, cpu_addr, winsize, fla= gs); + if (ret) { + dev_err(dev, "IB BAR: %d config failed\n", bar); + return ret; + } + + size -=3D winsize; + cpu_addr +=3D winsize; + } + + return 0; +} + +static int cdns_pcie_hpa_host_map_dma_ranges(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct device *dev =3D pcie->dev; + struct device_node *np =3D dev->of_node; + struct pci_host_bridge *bridge; + struct resource_entry *entry; + u32 no_bar_nbits =3D 32; + int err; + + bridge =3D pci_host_bridge_from_priv(rc); + if (!bridge) + return -ENOMEM; + + if (list_empty(&bridge->dma_ranges)) { + of_property_read_u32(np, "cdns,no-bar-match-nbits", + &no_bar_nbits); + err =3D cdns_pcie_hpa_host_bar_ib_config(rc, RP_NO_BAR, 0x0, + (u64)1 << no_bar_nbits, 0); + if (err) + dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR); + return err; + } + + list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); + + resource_list_for_each_entry(entry, &bridge->dma_ranges) { + err =3D cdns_pcie_hpa_host_bar_config(rc, entry); + if (err) { + dev_err(dev, "Fail to configure IB using dma-ranges\n"); + return err; + } + } + + return 0; +} + +static int cdns_pcie_hpa_host_init_root_port(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + u32 value, ctrl; + + /* + * Set the root complex BAR configuration register: + * - disable both BAR0 and BAR1. + * - enable Prefetchable Memory Base and Limit registers in type 1 + * config space (64 bits). + * - enable IO Base and Limit registers in type 1 config + * space (32 bits). + */ + + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED; + value =3D CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS; + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, + CDNS_PCIE_HPA_LM_RC_BAR_CFG, value); + + if (rc->vendor_id !=3D 0xffff) + cdns_pcie_hpa_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id); + + if (rc->device_id !=3D 0xffff) + cdns_pcie_hpa_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); + + cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_REVISION, 0); + cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_PROG, 0); + cdns_pcie_hpa_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); + + return 0; +} + +static void cdns_pcie_hpa_create_region_for_ecam(struct cdns_pcie_rc *rc) +{ + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(rc); + struct resource *cfg_res =3D rc->cfg_res; + struct cdns_pcie *pcie =3D &rc->pcie; + u32 value, root_port_req_id_reg, pcie_bus_number_reg; + u32 ecam_addr_0, region_size_0, request_id_0; + int busnr =3D 0, secbus =3D 0, subbus =3D 0; + struct resource_entry *entry; + resource_size_t size; + u32 axi_address_low; + int nbits; + u64 sz; + + entry =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (entry) { + busnr =3D entry->res->start; + secbus =3D (busnr < 0xff) ? (busnr + 1) : 0xff; + subbus =3D entry->res->end; + } + size =3D resource_size(cfg_res); + sz =3D 1ULL << fls64(size - 1); + nbits =3D ilog2(sz); + if (nbits < 8) + nbits =3D 8; + + root_port_req_id_reg =3D ((busnr & 0xff) << 8); + pcie_bus_number_reg =3D ((subbus & 0xff) << 16) | ((secbus & 0xff) << 8) | + (busnr & 0xff); + ecam_addr_0 =3D cfg_res->start; + region_size_0 =3D nbits - 1; + request_id_0 =3D ((busnr & 0xff) << 8); + +#define CDNS_PCIE_HPA_TAG_MANAGEMENT (0x0) + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_TAG_MANAGEMENT, 0x200000); + + /* Taking slave err as OKAY */ +#define CDNS_PCIE_HPA_SLAVE_RESP (0x100) + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_SLAVE_RESP, + 0x0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_SLAVE_RESP + 0x4, 0x0); + + /* Program the register "i_root_port_req_id_reg" with RP's BDF */ +#define I_ROOT_PORT_REQ_ID_REG (0x141c) + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, I_ROOT_PORT_REQ_ID_REG, + root_port_req_id_reg); + + /** + * Program the register "i_pcie_bus_numbers" with Primary(RP's bus number= ), + * secondary and subordinate bus numbers + */ +#define I_PCIE_BUS_NUMBERS (CDNS_PCIE_HPA_RP_BASE + 0x18) + cdns_pcie_hpa_writel(pcie, REG_BANK_RP, I_PCIE_BUS_NUMBERS, + pcie_bus_number_reg); + + /* Program the register "lm_hal_sbsa_ctrl[0]" to enable the sbsa */ +#define LM_HAL_SBSA_CTRL (0x1170) + value =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, LM_HAL_SBSA_CTRL); + value |=3D BIT(0); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, LM_HAL_SBSA_CTRL, value); + + /* Program region[0] for ECAM */ + axi_address_low =3D (ecam_addr_0 & 0xfff00000) | region_size_0; + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(0), + axi_address_low); + + /* rc0-high-axi-address */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(0), 0x0); + /* Type-1 CFG */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), 0x05000000); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), + (request_id_0 << 16)); + + /* All AXI bits pass through PCIe */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), 0x1b); + /* PCIe address-high */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(0), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), 0x06000000); +} + +static void cdns_pcie_hpa_create_region_for_cfg(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(rc); + struct resource *cfg_res =3D rc->cfg_res; + struct resource_entry *entry; + u64 cpu_addr =3D cfg_res->start; + u32 addr0, addr1, desc1; + int busnr =3D 0; + + entry =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (entry) + busnr =3D entry->res->start; + + /* + * Reserve region 0 for PCI configure space accesses: + * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by + * cdns_pci_map_bus(), other region registers are set here once for all. + */ + addr1 =3D 0; + desc1 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(0), addr1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); + + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(12) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(0), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(0), addr1); +} + +static int cdns_pcie_hpa_host_init_address_translation(struct cdns_pcie_rc= *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct device *dev =3D pcie->dev; + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(rc); + struct resource_entry *entry; + int r =3D 0, busnr =3D 0; + + if (rc->ecam_support_flag) + cdns_pcie_hpa_create_region_for_ecam(rc); + else + cdns_pcie_hpa_create_region_for_cfg(rc); + + entry =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (entry) + busnr =3D entry->res->start; + + r++; + if (pcie->msg_res) + cdns_pcie_hpa_set_outbound_region_for_normal_msg(pcie, busnr, 0, r, + pcie->msg_res->start); + + r++; + resource_list_for_each_entry(entry, &bridge->windows) { + struct resource *res =3D entry->res; + u64 pci_addr =3D res->start - entry->offset; + + if (resource_type(res) =3D=3D IORESOURCE_IO) + cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, + true, + pci_pio_to_address(res->start), + pci_addr, + resource_size(res)); + else + cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, + false, + res->start, + pci_addr, + resource_size(res)); + + r++; + } + + if (device_property_read_bool(dev, "cdns,no-inbound-bar")) + return 0; + else + return cdns_pcie_hpa_host_map_dma_ranges(rc); +} + +int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc) +{ + int err; + + err =3D cdns_pcie_hpa_host_init_root_port(rc); + if (err) + return err; + + return cdns_pcie_hpa_host_init_address_translation(rc); +} + +int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct device *dev =3D rc->pcie.dev; + int ret; + + if (rc->quirk_detect_quiet_flag) + cdns_pcie_hpa_detect_quiet_min_delay_set(&rc->pcie); + + cdns_pcie_hpa_host_enable_ptm_response(pcie); + + ret =3D cdns_pcie_start_link(pcie); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + + ret =3D cdns_pcie_host_start_link(rc); + if (ret) + dev_dbg(dev, "PCIe link never came up\n"); + + return ret; +} + +int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) +{ + struct device *dev =3D rc->pcie.dev; + struct platform_device *pdev =3D to_platform_device(dev); + struct device_node *np =3D dev->of_node; + struct pci_host_bridge *bridge; + enum cdns_pcie_rp_bar bar; + struct cdns_pcie *pcie; + struct resource *res; + int ret; + + bridge =3D pci_host_bridge_from_priv(rc); + if (!bridge) + return -ENOMEM; + + pcie =3D &rc->pcie; + pcie->is_rc =3D true; + + rc->vendor_id =3D 0xffff; + of_property_read_u32(np, "vendor-id", &rc->vendor_id); + + rc->device_id =3D 0xffff; + of_property_read_u32(np, "device-id", &rc->device_id); + + if (!pcie->reg_base) { + pcie->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); + if (IS_ERR(pcie->reg_base)) { + dev_err(dev, "missing \"reg\"\n"); + return PTR_ERR(pcie->reg_base); + } + } + + /* ECAM config space is remapped at glue layer */ + if (!rc->cfg_base) { + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + rc->cfg_base =3D devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(rc->cfg_base)) + return PTR_ERR(rc->cfg_base); + rc->cfg_res =3D res; + } + + ret =3D cdns_pcie_hpa_host_link_setup(rc); + if (ret) + return ret; + + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) + rc->avail_ib_bar[bar] =3D true; + + ret =3D cdns_pcie_hpa_host_init(rc); + if (ret) + return ret; + + if (!bridge->ops) + bridge->ops =3D &cdns_pcie_hpa_host_ops; + + return pci_host_probe(bridge); +} diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa.c b/drivers/pc= i/controller/cadence/pcie-cadence-hpa.c new file mode 100644 index 000000000000..7982b40dcfe6 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-hpa.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver +// Author: Manikandan K Pillai + +#include +#include + +#include "pcie-cadence.h" + +bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_P= HY_DBG_STS_REG0); + if (pl_reg_val & GENMASK(0, 0)) + return true; + return false; +} + +int cdns_pcie_hpa_start_link(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_P= HY_LAYER_CFG0); + pl_reg_val |=3D CDNS_PCIE_HPA_LINK_TRNG_EN_MASK; + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_PHY_LAYER_CFG0,= pl_reg_val); + return 0; +} + +void cdns_pcie_hpa_stop_link(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_P= HY_LAYER_CFG0); + pl_reg_val &=3D ~CDNS_PCIE_HPA_LINK_TRNG_EN_MASK; + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_PHY_LAYER_CFG0,= pl_reg_val); +} + +void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie) +{ + u32 delay =3D 0x3; + u32 ltssm_control_cap; + + /* + * Set the LTSSM Detect Quiet state min. delay to 2ms. + */ + ltssm_control_cap =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, + CDNS_PCIE_HPA_PHY_LAYER_CFG0); + ltssm_control_cap =3D ((ltssm_control_cap & + ~CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK) | + CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay)); + + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, + CDNS_PCIE_HPA_PHY_LAYER_CFG0, ltssm_control_cap); +} + +void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u= 8 fn, + u32 r, bool is_io, + u64 cpu_addr, u64 pci_addr, size_t size) +{ + /* + * roundup_pow_of_two() returns an unsigned long, which is not suited + * for 64bit values. + */ + u64 sz =3D 1ULL << fls64(size - 1); + int nbits =3D ilog2(sz); + u32 addr0, addr1, desc0, desc1, ctrl0; + + if (nbits < 8) + nbits =3D 8; + + /* Set the PCI address */ + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) | + (lower_32_bits(pci_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(pci_addr); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), addr1); + + /* Set the PCIe header descriptor */ + if (is_io) + desc0 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO; + else + desc0 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM; + desc1 =3D 0; + ctrl0 =3D 0; + + /* + * Whether Bit [26] is set or not inside DESC0 register of the outbound + * PCIe descriptor, the PCI function number must be set into + * Bits [31:24] of DESC1 anyway. + * + * In Root Complex mode, the function number is always 0 but in Endpoint + * mode, the PCIe controller may support more than one function. This + * function number needs to be set properly into the outbound PCIe + * descriptor. + * + * Besides, setting Bit [26] is mandatory when in Root Complex mode: + * then the driver must provide the bus, resp. device, number in + * Bits [31:24] of DESC1, resp. Bits[23:16] of DESC0. Like the function + * number, the device number is always 0 in Root Complex mode. + * + * However when in Endpoint mode, we can clear Bit [26] of DESC0, hence + * the PCIe controller will use the captured values for the bus and + * device numbers. + */ + if (pcie->is_rc) { + /* The device and function numbers are always 0. */ + desc1 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | + CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); + ctrl0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; + } else { + /* + * Use captured values for bus and device numbers but still + * need to set the function number. + */ + desc1 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); + } + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); + + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); +} + +void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pc= ie, + u8 busnr, u8 fn, + u32 r, u64 cpu_addr) +{ + u32 addr0, addr1, desc0, desc1, ctrl0; + + desc0 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG; + desc1 =3D 0; + ctrl0 =3D 0; + + /* + * See cdns_pcie_set_outbound_region() comments above. + */ + if (pcie->is_rc) { + desc1 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | + CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); + ctrl0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; + } else { + desc1 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); + } + + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(17) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); +} + +void cdns_pcie_hpa_reset_outbound_region(struct cdns_pcie *pcie, u32 r) +{ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), 0); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), 0); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), 0); +} diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/p= ci/controller/cadence/pcie-cadence-plat.c index e09f23427313..882c4aef7ac5 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -12,8 +12,6 @@ #include #include "pcie-cadence.h" =20 -#define CDNS_PLAT_CPU_TO_BUS_ADDR 0x0FFFFFFF - /** * struct cdns_plat_pcie - private data for this PCIe platform driver * @pcie: Cadence PCIe controller @@ -24,13 +22,8 @@ struct cdns_plat_pcie { =20 static const struct of_device_id cdns_plat_pcie_of_match[]; =20 -static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) -{ - return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR; -} - static const struct cdns_pcie_ops cdns_plat_ops =3D { - .cpu_addr_fixup =3D cdns_plat_cpu_addr_fixup, + .link_up =3D cdns_pcie_linkup, }; =20 static int cdns_plat_pcie_probe(struct platform_device *pdev) @@ -68,6 +61,11 @@ static int cdns_plat_pcie_probe(struct platform_device *= pdev) rc =3D pci_host_bridge_priv(bridge); rc->pcie.dev =3D dev; rc->pcie.ops =3D &cdns_plat_ops; + rc->pcie.is_rc =3D data->is_rc; + + /* Store the register bank offsets pointer */ + rc->pcie.cdns_pcie_reg_offsets =3D data; + cdns_plat_pcie->pcie =3D &rc->pcie; =20 ret =3D cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie); @@ -95,6 +93,11 @@ static int cdns_plat_pcie_probe(struct platform_device *= pdev) =20 ep->pcie.dev =3D dev; ep->pcie.ops =3D &cdns_plat_ops; + ep->pcie.is_rc =3D data->is_rc; + + /* Store the register bank offset pointer */ + ep->pcie.cdns_pcie_reg_offsets =3D data; + cdns_plat_pcie->pcie =3D &ep->pcie; =20 ret =3D cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie); diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/co= ntroller/cadence/pcie-cadence.c index 51c9bc4eb174..f86a44efc510 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -9,6 +9,16 @@ =20 #include "pcie-cadence.h" =20 +bool cdns_pcie_linkup(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE); + if (pl_reg_val & GENMASK(0, 0)) + return true; + return false; +} + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) { u32 delay =3D 0x3; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 5c0ea49551c8..3215d4665d89 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -29,6 +29,8 @@ struct cdns_pcie_rp_ib_bar { struct cdns_pcie; struct cdns_pcie_rc; =20 +bool cdns_pcie_linkup(struct cdns_pcie *pcie); + enum cdns_pcie_msg_routing { /* Route to Root Complex */ MSG_ROUTING_TO_RC, @@ -63,9 +65,9 @@ enum cdns_pcie_reg_bank { }; =20 struct cdns_pcie_ops { - int (*start_link)(struct cdns_pcie *pcie); - void (*stop_link)(struct cdns_pcie *pcie); - bool (*link_up)(struct cdns_pcie *pcie); + int (*start_link)(struct cdns_pcie *pcie); + void (*stop_link)(struct cdns_pcie *pcie); + bool (*link_up)(struct cdns_pcie *pcie); u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); }; =20 @@ -97,6 +99,7 @@ struct cdns_plat_pcie_of_data { * struct cdns_pcie - private data for Cadence PCIe controller drivers * @reg_base: IO mapped register base * @mem_res: start/end offsets in the physical system memory to map PCI ac= cesses + * @msg_res: Region for send message to map PCI accesses * @dev: PCIe controller * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoi= nt. * @phy_count: number of supported PHY devices @@ -109,6 +112,7 @@ struct cdns_plat_pcie_of_data { struct cdns_pcie { void __iomem *reg_base; struct resource *mem_res; + struct resource *msg_res; struct device *dev; bool is_rc; int phy_count; @@ -131,6 +135,7 @@ struct cdns_pcie { * available * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk + * @ecam_support_flag: Whether the ECAM flag is supported */ struct cdns_pcie_rc { struct cdns_pcie pcie; @@ -141,6 +146,7 @@ struct cdns_pcie_rc { bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; unsigned int quirk_retrain_flag:1; unsigned int quirk_detect_quiet_flag:1; + unsigned int ecam_support_flag:1; }; =20 /** @@ -324,6 +330,29 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie = *pcie, u32 reg) return cdns_pcie_read_sz(addr, 0x2); } =20 +static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie, + u32 reg, u8 value) +{ + void __iomem *addr =3D pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; + + cdns_pcie_write_sz(addr, 0x1, value); +} + +static inline void cdns_pcie_hpa_rp_writew(struct cdns_pcie *pcie, + u32 reg, u16 value) +{ + void __iomem *addr =3D pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; + + cdns_pcie_write_sz(addr, 0x2, value); +} + +static inline u16 cdns_pcie_hpa_rp_readw(struct cdns_pcie *pcie, u32 reg) +{ + void __iomem *addr =3D pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; + + return cdns_pcie_read_sz(addr, 0x2); +} + /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value) @@ -388,6 +417,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); void cdns_pcie_host_disable(struct cdns_pcie_rc *rc); void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, int where); +int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc); #else static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) { @@ -404,6 +434,11 @@ static inline int cdns_pcie_host_setup(struct cdns_pci= e_rc *rc) return 0; } =20 +static inline int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) +{ + return 0; +} + static inline void cdns_pcie_host_disable(struct cdns_pcie_rc *rc) { } @@ -418,17 +453,24 @@ static inline void __iomem *cdns_pci_map_bus(struct p= ci_bus *bus, unsigned int d #if IS_ENABLED(CONFIG_PCIE_CADENCE_EP) int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep); void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep); +int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep); #else static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) { return 0; } =20 +static inline int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep) +{ + return 0; +} + static inline void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep) { } #endif - +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie); +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc); void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, u32 r, bool is_io, @@ -441,6 +483,25 @@ void cdns_pcie_disable_phy(struct cdns_pcie *pcie); int cdns_pcie_enable_phy(struct cdns_pcie *pcie); int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); =20 +void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie); +void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u= 8 fn, + u32 r, bool is_io, + u64 cpu_addr, u64 pci_addr, size_t size); +void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pc= ie, + u8 busnr, u8 fn, + u32 r, u64 cpu_addr); +void cdns_pcie_hpa_reset_outbound_region(struct cdns_pcie *pcie, u32 r); +int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc); 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id C00DA41604F7; Mon, 30 Jun 2025 12:16:06 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v5 09/14] PCI: cadence: Add support for PCIe HPA controller platform Date: Mon, 30 Jun 2025 12:15:56 +0800 Message-ID: <20250630041601.399921-10-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250630041601.399921-1-hans.zhang@cixtech.com> References: <20250630041601.399921-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CC:EE_|TYZPR06MB5528:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d8067ac-4d77-465b-a968-08ddb78cd7a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?nnlVUPCMN1r9WIYhV4k3M44aVwMjfx4sE9ARyKaIN4QKWZsTg45gZv6q0KVl?= =?us-ascii?Q?Oyx3QWUTWf8EuRelTz1MOKMu4/6iLFxu7CiAolaU+OLNTZVascGaThO+MOpo?= =?us-ascii?Q?igENxB0L6rOdYPk0KCII+Jz2/zbZ9B573AC++MefOuJxZg25xho04JUbrgso?= =?us-ascii?Q?6RRaogyQM7H4MUEob5hPxoqy0+jO/xCNY/BlQVxnb5eS0MoUW5j5mcqAtpZO?= =?us-ascii?Q?AXjNiMPac5faAOUea+TFz+VpEpnHV0Zp/tRH85YHAn9/L0FBs3PF3Mg5TUMc?= =?us-ascii?Q?Djo1jw8XqbaSRbZp32cvTkUfEoEqIGVrgN9lMXiFjcwJ/HuMP8sxYAg+0Meh?= =?us-ascii?Q?bZgSh9YQO9FgyjhaMpaaCE4W4f4ns+45CLAyWQU5LP1WTCm9A7i9+x2QCouU?= =?us-ascii?Q?KCKW2HAQVZSMOIl55Fsb1okPZoVH5smfWdRAzdyhl4Hz/gIE/iQbopD1b458?= =?us-ascii?Q?spmVNfR5H2wgawE5Pz0TfrPikShn/rks1u47gVmbUGu9KIZHK7CwSTPx5m3B?= =?us-ascii?Q?6olDv82vCFUFwO5v9vqS0YQSlP+4AjTmxjb2HqjxpCfZVzeySqb9uAo0kHOL?= =?us-ascii?Q?NMEx+TUPamDAI2sihEbiPctaGeCZH2X0Pi/KQXRzd5ddv9H65ebn9p4Au2P/?= =?us-ascii?Q?pp++Y0QG5c8detNdL2VoOgGs9Z71xdfD3QTSFUIqAdDGPFt1PLUZvrSaQVCT?= =?us-ascii?Q?87XC804P1aiJRnB0KdAz29+hwTJ1tvlt/EdmfJ5uP4r+Bb2qIeX7Mqw6yrBL?= =?us-ascii?Q?59jRCFp6ZVkc+Ftwq0fUOO+H6N81H66YR5XZiOI2nO+l24aaC5S+1dwbpjkN?= =?us-ascii?Q?naE3pV+drKROxb5A+21mX15RvWhrYXD/MFMz5DAsYsDe52zbdvNnOnnRxgS3?= =?us-ascii?Q?HYh4SavBHBz4FreE9Ua9Aq2DOHw4TnthORGnvjQW2s/FZ3mr8FqTfLc7eEny?= =?us-ascii?Q?ebh+t/1GGYguBHdLLvZoz+uTFgps8E5jP5/bgFmYGi7eATH0YuSZQi6encdB?= =?us-ascii?Q?MBFc6Jkz71mbGCFawRAs36VvXc5yCAOShfROs/UuVS6xL7MVG6hACfm7fnDm?= =?us-ascii?Q?ovbySSFrxm4vU65PyHbA2AnDJu2SO6eMvzHjAscqTc0G+wiSkIpiXIRav9JU?= =?us-ascii?Q?qdyLlxksJMoI6aHHzp4FuwCfB4rYSd6JSw01A16ZxgOWQ3IGJ4k19M8NyC/6?= =?us-ascii?Q?SPqu30DFSX8aJckx3eerKdltIqSOzhH3LUx17jWJfQiVA7m/veEEvrqlPaYD?= =?us-ascii?Q?c615hAG/Jyfawap9jr177LWlA8/2cAZlgRTAYjQfMagwytnkQcYYG7SSEFae?= =?us-ascii?Q?IL6fMb+vuchQpMdZ/KIFT78psT8WiNho5yaBpm8C+1E9YnpLXbvMhM1FxgeN?= =?us-ascii?Q?6cwNKoAnkcnYcV56+9jdbpHcco6303c9h4+RXi9E8LuhlMED4wrbyYULhCsG?= =?us-ascii?Q?2oHDI7urvBZfdrsN6Kv8UdVe5+1ozVuXIgZBHysGYKAgo9QuSqoY1JqYGgnm?= =?us-ascii?Q?dUuxyuvxWIzuzUy7hlqNk4djgYx24MK4mXTH?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700013)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 04:16:09.5985 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d8067ac-4d77-465b-a968-08ddb78cd7a4 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CC.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB5528 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add support for Cadence HPA PCIe controller based platform. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Kconfig | 5 + drivers/pci/controller/cadence/Makefile | 1 + .../cadence/pcie-cadence-plat-hpa.c | 183 ++++++++++++++++++ 3 files changed, 189 insertions(+) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-plat-hpa.c diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controlle= r/cadence/Kconfig index a1caf154888d..427aa9beca22 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -29,11 +29,15 @@ config PCIE_CADENCE_EP config PCIE_CADENCE_PLAT bool =20 +config PCIE_CADENCE_PLAT_HPA + bool + config PCIE_CADENCE_PLAT_HOST bool "Cadence platform PCIe controller (host mode)" depends on OF select PCIE_CADENCE_HOST select PCIE_CADENCE_PLAT + select PCIE_CADENCE_PLAT_HPA help Say Y here if you want to support the Cadence PCIe platform controller = in host mode. This PCIe controller may be embedded into many different @@ -45,6 +49,7 @@ config PCIE_CADENCE_PLAT_EP depends on PCI_ENDPOINT select PCIE_CADENCE_EP select PCIE_CADENCE_PLAT + select PCIE_CADENCE_PLAT_HPA help Say Y here if you want to support the Cadence PCIe platform controller = in endpoint mode. This PCIe controller may be embedded into many diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index e2df24ff4c33..f8575a0eee2d 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_PCIE_CADENCE_HOST_COMMON) +=3D pcie-cadence-ho= st-common.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o pcie-cadence-host= -hpa.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o pcie-cadence-ep-hpa.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o +obj-$(CONFIG_PCIE_CADENCE_PLAT_HPA) +=3D pcie-cadence-plat-hpa.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat-hpa.c b/drive= rs/pci/controller/cadence/pcie-cadence-plat-hpa.c new file mode 100644 index 000000000000..fb42547d47d2 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-plat-hpa.c @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cadence PCIe platform driver. + * + * Copyright (c) 2019, Cadence Design Systems + * Author: Manikandan K Pillai + */ +#include +#include +#include +#include +#include +#include "pcie-cadence.h" + +/** + * struct cdns_plat_pcie - private data for this PCIe platform driver + * @pcie: Cadence PCIe controller + */ +struct cdns_plat_pcie { + struct cdns_pcie *pcie; +}; + +static const struct cdns_pcie_ops cdns_plat_hpa_ops =3D { + .start_link =3D cdns_pcie_hpa_start_link, + .stop_link =3D cdns_pcie_hpa_stop_link, + .link_up =3D cdns_pcie_hpa_link_up, +}; + +static int cdns_plat_pcie_hpa_probe(struct platform_device *pdev) +{ + const struct cdns_plat_pcie_of_data *data; + struct cdns_plat_pcie *cdns_plat_pcie; + struct device *dev =3D &pdev->dev; + struct pci_host_bridge *bridge; + struct cdns_pcie_ep *ep; + struct cdns_pcie_rc *rc; + int phy_count; + bool is_rc; + int ret; + + data =3D of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + is_rc =3D data->is_rc; + + pr_debug(" Started %s with is_rc: %d\n", __func__, is_rc); + cdns_plat_pcie =3D devm_kzalloc(dev, sizeof(*cdns_plat_pcie), GFP_KERNEL); + if (!cdns_plat_pcie) + return -ENOMEM; + + platform_set_drvdata(pdev, cdns_plat_pcie); + if (is_rc) { + if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_HOST)) + return -ENODEV; + + bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) + return -ENOMEM; + + rc =3D pci_host_bridge_priv(bridge); + rc->pcie.dev =3D dev; + rc->pcie.ops =3D &cdns_plat_hpa_ops; + rc->pcie.is_rc =3D data->is_rc; + + /* + * Store the register bank offsets pointer + */ + rc->pcie.cdns_pcie_reg_offsets =3D data; + + cdns_plat_pcie->pcie =3D &rc->pcie; + + ret =3D cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie); + if (ret) { + dev_err(dev, "failed to init phy\n"); + return ret; + } + pm_runtime_enable(dev); + ret =3D pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync() failed\n"); + goto err_get_sync; + } + + ret =3D cdns_pcie_hpa_host_setup(rc); + if (ret) + goto err_init; + } else { + if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_EP)) + return -ENODEV; + + ep =3D devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); + if (!ep) + return -ENOMEM; + + ep->pcie.dev =3D dev; + ep->pcie.ops =3D &cdns_plat_hpa_ops; + ep->pcie.is_rc =3D data->is_rc; + + /* + * Store the register bank offset pointer + */ + ep->pcie.cdns_pcie_reg_offsets =3D data; + + cdns_plat_pcie->pcie =3D &ep->pcie; + + ret =3D cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie); + if (ret) { + dev_err(dev, "failed to init phy\n"); + return ret; + } + + pm_runtime_enable(dev); + ret =3D pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync() failed\n"); + goto err_get_sync; + } + + ret =3D cdns_pcie_hpa_ep_setup(ep); + if (ret) + goto err_init; + } + + return 0; + + err_init: + err_get_sync: + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + cdns_pcie_disable_phy(cdns_plat_pcie->pcie); + phy_count =3D cdns_plat_pcie->pcie->phy_count; + while (phy_count--) + device_link_del(cdns_plat_pcie->pcie->link[phy_count]); + + return 0; +} + +static void cdns_plat_pcie_hpa_shutdown(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct cdns_pcie *pcie =3D dev_get_drvdata(dev); + int ret; + + ret =3D pm_runtime_put_sync(dev); + if (ret < 0) + dev_dbg(dev, "pm_runtime_put_sync failed\n"); + + pm_runtime_disable(dev); + + cdns_pcie_disable_phy(pcie); +} + +static const struct cdns_plat_pcie_of_data cdns_plat_pcie_hpa_host_of_data= =3D { + .is_rc =3D true, +}; + +static const struct cdns_plat_pcie_of_data cdns_plat_pcie_hpa_ep_of_data = =3D { + .is_rc =3D false, +}; + +static const struct of_device_id cdns_plat_pcie_hpa_of_match[] =3D { + { + .compatible =3D "cdns,cdns-pcie-hpa-host", + .data =3D &cdns_plat_pcie_hpa_host_of_data, + }, + { + .compatible =3D "cdns,cdns-pcie-hpa-ep", + .data =3D &cdns_plat_pcie_hpa_ep_of_data, + }, + {}, +}; + +static struct platform_driver cdns_plat_pcie_hpa_driver =3D { + .driver =3D { + .name =3D "cdns-pcie-hpa", + .of_match_table =3D cdns_plat_pcie_hpa_of_match, + .pm =3D &cdns_pcie_pm_ops, + }, + .probe =3D cdns_plat_pcie_hpa_probe, + .shutdown =3D cdns_plat_pcie_hpa_shutdown, +}; +builtin_platform_driver(cdns_plat_pcie_hpa_driver); --=20 2.49.0 From nobody Wed Oct 8 10:00:53 2025 Received: from TYDPR03CU002.outbound.protection.outlook.com (mail-japaneastazon11023109.outbound.protection.outlook.com [52.101.127.109]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D87311BD9CE; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id C4BB041604FA; Mon, 30 Jun 2025 12:16:06 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v5 10/14] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings Date: Mon, 30 Jun 2025 12:15:57 +0800 Message-ID: <20250630041601.399921-11-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250630041601.399921-1-hans.zhang@cixtech.com> References: <20250630041601.399921-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB88:EE_|SI2PR06MB5138:EE_ X-MS-Office365-Filtering-Correlation-Id: 59c1b0e2-f303-44bd-8402-08ddb78cd86d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?e7rvxOH/vWNE6CCt4pHqPMH1iZR8GvftfG96qGuVixMj+KzWNzuZ8p8eNOV0?= =?us-ascii?Q?5WTkFSpBFujCTmmcwALM4C7HF8D87FCRA5mNbvCoTVkrfYAMbgFhhFlsadiX?= =?us-ascii?Q?WaG+hsStFQcQzN2nNXi0K5ca4iWuxR0v2nEOFAZ85e0qrcbnZ5UMxSiSGl/Z?= =?us-ascii?Q?nnyfy4HwqDLg+3F/vRP4DdIZJZmigeDbesEnAdWH46o3JQMAJhbbHQBn2ovB?= =?us-ascii?Q?ie73/+QEmjDX4bifUNeX04tE7leOw+p1Xd4kOS/zVsY/bBbSbRW5jvT6LPq4?= =?us-ascii?Q?QsJlQxA7V/DjRIr76hwteMC1JMJMMUpGFPkVFifhw9k/4PI+w4ptd9iAbUJ8?= =?us-ascii?Q?wSGCRpUIlsFqXBzRrQrGfSWs8mHXJgUnBajVI2cnNW9h4ukfPKBobU6zZlIm?= =?us-ascii?Q?tOw1l10nZNx7owqdN1byvEN2PKDFnfoIsDayitwZjCzanLcSAuf9j0mlE8IX?= =?us-ascii?Q?JYUAm5OuEgpkH930+GwD3aiDWQALurPRkspTNi8mhqMZBVyiK2qvld5npKZ9?= =?us-ascii?Q?ap18hSAB0UyxunzBNEsN8SHJ6mschX63RYDv6HumoAML/jSjfnNOYr2PsVVE?= =?us-ascii?Q?LZstKxHtH3uFa6OZQH9plQHiJDJrPJ5cBdev+0edYn0qImolcJUVTuHsyn6o?= =?us-ascii?Q?4kULIAQHUxFh/RsT+LXHljMzQfscfMyIJrJCnyDxEGm5zAfr2RVvc8DooJ53?= =?us-ascii?Q?eIRmMHM9hipNgWu0uK3zoKnKoaE7AhZJmg2zo/ezkW1VBXzDBhTHCawOG/Zw?= =?us-ascii?Q?gVLFLGKL2p7/SKFQDgqDUh3QoaOdFEpEzzd7m8A9fTQR8XTR/5ubNneR48ch?= =?us-ascii?Q?E+UAH2vudN6LiSWBuy8e3ZBzpQsUuzYkPq4bwmYERDVpSA7ctyRyYmvitY1E?= =?us-ascii?Q?cqSJ17w0Q0wwYIU6XpTb66pTKcPnhKxgcB3wZTTxJ3j/KJCQWMoMh31l50Z5?= =?us-ascii?Q?ILGIFJUiTh09dJSxvsuhqdTodbtAQQlklcWSNsBlk+RIrbHRhnOEpF/pT/pu?= =?us-ascii?Q?8KZRXmsJVs7Rz/6zFbGEbfYMzR6Mtajh6STtNwsTkxA9E6FWEP5tJosy1AvY?= =?us-ascii?Q?B+Z+XarkzTi2T9iT3Hb+RLzA3XGJzr59NIh+PRRLjAZ6Dul2sIczSwNRUXNC?= =?us-ascii?Q?OOAGMXJBsMSuhak/lTcQMSmGw1ONJA0aGdtUrfPMMmdzbK5FYwQ5wuDPe5mc?= =?us-ascii?Q?W1cXbZJmW5NRsvfCn/+Cl2CGIJjbMRJsXd7XiEItEVjoOxZg3uyvcjngO9pe?= =?us-ascii?Q?3NlotEOBQubtxAdJwZS5KTYfyR5XLG2rSKNV2rva9Yy2M/9gePQ1MxvCu4Mo?= =?us-ascii?Q?NQJOmrMMv6XkuvENwPuP9u64NDUZm83BOAd4kon1sd7X3qtRC6zbCa4FTlXp?= =?us-ascii?Q?iX79XMgXT5jvq6kd/E+5aEmSG9Ov1ezikzNMP1l3nWIxxjiXvndxiZwNuFll?= =?us-ascii?Q?PNCIGltLFUUe2Ka3mNztk6RyLO81zX78eHChUtJXOUn06uzGZpVyEg=3D=3D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700013)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 04:16:10.8727 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 59c1b0e2-f303-44bd-8402-08ddb78cd86d X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB88.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SI2PR06MB5138 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Document the bindings for CIX Sky1 PCIe Controller configured in root complex mode with five root port. Supports 4 INTx, MSI and MSI-x interrupts from the ARM GICv3 controller. Signed-off-by: Hans Zhang Reviewed-by: Peter Chen Reviewed-by: Manikandan K Pillai --- .../bindings/pci/cix,sky1-pcie-host.yaml | 133 ++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/cix,sky1-pcie-hos= t.yaml diff --git a/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml = b/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml new file mode 100644 index 000000000000..b4395bc06f2f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cix,sky1-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 PCIe Root Complex + +maintainers: + - Hans Zhang + +description: + PCIe root complex controller based on the Cadence PCIe core. + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - $ref: /schemas/pci/cdns-pcie.yaml# + +properties: + compatible: + oneOf: + - const: cix,sky1-pcie-host + + reg: + items: + - description: PCIe controller registers. + - description: Remote CIX System Unit registers. + - description: ECAM registers. + - description: Region for sending messages registers. + + reg-names: + items: + - const: reg + - const: rcsu + - const: cfg + - const: msg + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + interrupt-map: + maxItems: 4 + + max-link-speed: + maximum: 4 + + num-lanes: + maximum: 8 + + ranges: + maxItems: 3 + + msi-map: + maxItems: 1 + + vendor-id: + const: 0x1f6c + + device-id: + enum: + - 0x0001 + + cdns,no-inbound-bar: + description: | + Indicates the PCIe controller does not require an inbound BAR region. + type: boolean + + sky1,pcie-ctrl-id: + description: | + Specifies the PCIe controller instance identifier (0-4). + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 4 + +required: + - compatible + - reg + - reg-names + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + - max-link-speed + - num-lanes + - bus-range + - device_type + - ranges + - msi-map + - vendor-id + - device-id + - cdns,no-inbound-bar + - sky1,pcie-ctrl-id + +unevaluatedProperties: false + +examples: + - | + #include + + pcie_x8_rc: pcie@a010000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a010000 0x00 0x10000>, + <0x00 0x0a000000 0x00 0x10000>, + <0x00 0x2c000000 0x00 0x4000000>, + <0x00 0x60000000 0x00 0x00100000>; + reg-names =3D "reg", "rcsu", "cfg", "msg"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIG= H 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH = 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH = 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH = 0>; + max-link-speed =3D <4>; + num-lanes =3D <8>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0xc0 0xff>; + device_type =3D "pci"; + ranges =3D <0x01000000 0x00 0x60100000 0x00 0x60100000 0x00 0x0010= 0000>, + <0x02000000 0x00 0x60200000 0x00 0x60200000 0x00 0x1fe000= 00>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x000000= 00>; + msi-map =3D <0xc000 &gic_its 0xc000 0x4000>; + vendor-id =3D <0x1f6c>; + device-id =3D <0x0001>; + sky1,pcie-ctrl-id =3D <0x0>; + cdns,no-inbound-bar; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id D4D184160500; Mon, 30 Jun 2025 12:16:06 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v5 11/14] PCI: sky1: Add PCIe host support for CIX Sky1 Date: Mon, 30 Jun 2025 12:15:58 +0800 Message-ID: <20250630041601.399921-12-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250630041601.399921-1-hans.zhang@cixtech.com> References: <20250630041601.399921-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB8A:EE_|KUZPR06MB8027:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f0f57b0-c4ef-4205-c207-08ddb78cd83e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?XVubkCsTbvrO3oU/IwffK+gr4CkRiw/26o4AbQf76QSPjuVC1+OTo5hRkdK4?= =?us-ascii?Q?UkJejv9JwVRSquVWB0agIxV46OwciF5NCnwpyfPtokQKP8fdMmmazCiOtdal?= =?us-ascii?Q?6zGl/ddq7G2zFWM6XcqydnNUYxCSVgJo3EM2qFYwEqFEBNMEf4ctigkPW1bz?= =?us-ascii?Q?C73LP3vDw+AwF10GHYjFtV9aFzUsLkEFR57fIeZR+8DBc8rlxczk9obV4ueg?= =?us-ascii?Q?+K47SL39H430Kf91PSvlBWw2oHQ+bjLTzRWjLqQHKsnSt3ajGGzOfiGS69JE?= =?us-ascii?Q?kUF0vsHtXlormdKbOAedy0IgqSgGThM4WMwKoN/WJlBkOIPdeiMJA3zKjJWr?= =?us-ascii?Q?kqOFUiFBF7dgGmuUqzgGqv8uB/zmhdZAJZFHa56eMEniBkPZ1nnApDLVp2XY?= =?us-ascii?Q?0BE/F+reERSbaHFmyBILxfbnWs7pOgi1CV3EsxmvDLxa4loID/zQsWD6ONFS?= =?us-ascii?Q?heftSvdW8nBl6lUScBPXYcQXHUu7i/6a2x4X8pcxYjk5H/3zigcNjLzENBeX?= =?us-ascii?Q?qcdLGZ61GtcR2JJEZ9qGz36dbinQXoJZY1AkxCeMY55E8ze3eBSjQdUbx0uQ?= =?us-ascii?Q?v5ym7NAvpMpdXSGYJwZpNTBgc9itgBD/L6MbNjVMzHOFQI+qk4x3m1QfXIY7?= =?us-ascii?Q?HzHI6yszKMOf62gx+rBsxUahqJjGKh4I+4HP1cNqnHY85DUXdp5B+tOmHR3v?= =?us-ascii?Q?0d3acE0PWasJjFpb1wB9h7JC12MoLt1QGwooAwXEou3nKq8GXrlIfr2otGeJ?= =?us-ascii?Q?ddXrt5Y07X+8m/ZkINpuWwp200QHtnAa6rN74M29rHCLCN+8WwrA6qmbFxAC?= =?us-ascii?Q?zqHjoe6n71Qj98oAWC01fT1v5gY1yr9qUt7eUkFp9IN17Vu+m/RdI2nRKUqX?= =?us-ascii?Q?K/xyEtyEMZ9g8Tw6HIQTakHQMWAO9RBC4uZVIUj9WVHsut4Vggc5KKNumEky?= =?us-ascii?Q?ORAKU1Z0wSuqj/qHSoeC10Z+vhyCqDbhSYHeecR+pvMVrK1mdQBPVNgjpXg0?= =?us-ascii?Q?J7q0Z+SJBIHbqfKT+Db4NTQ8aS6CACFs32cvoPZkDXCtcm47VNlb9ZxZaajc?= =?us-ascii?Q?1Wkcr6tCRfcP63tv0lPTai4vfASEbK2JfbO4+tWsE6cDDarTOrs0sGoqlw59?= =?us-ascii?Q?lpIM8TEtxoguPyzHx5hGIIlnPCyJvZgVZTejkbuWFm5laNlBjMG9tORzT1J0?= =?us-ascii?Q?Oj0QwmoWMLB2U5B4nmsWb7tJQ3XkKb0Iu07Eg9bJPkLYG/QPJ1ZkMD9JIGEo?= =?us-ascii?Q?wXa79ciw8ifLvTRxxFjWFYWmq/68o32cjQhGhpmWgTsyza+TfXIgCNtpgywB?= =?us-ascii?Q?SSOVF2VT1FXhUm/UOisCjzgkSmjYxsGARzRSJXu44/3uiOAVhhyBXhuI9lHo?= =?us-ascii?Q?7uU5+2/1Y5mUV00anfhHBlTLVsRFe4B04evfqlTkeKfgMIELNrbFV2AC7D9n?= =?us-ascii?Q?CUGclyFnKqI4BohgqRcASW4pP8kUxFZP+1FQdBWNjipW2naobnmJdqGTK9Np?= =?us-ascii?Q?cB/Wu3rqJDy1gq0dVNXPrc4FFh9jqx4xRcEV?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 04:16:10.5392 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f0f57b0-c4ef-4205-c207-08ddb78cd83e X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB8A.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KUZPR06MB8027 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add driver for the CIX Sky1 SoC PCIe Gen4 16 GT/s controller based on the Cadence PCIe core. Supports MSI/MSI-x via GICv3, Single Virtual Channel, Single Function. Signed-off-by: Hans Zhang Reviewed-by: Peter Chen Reviewed-by: Manikandan K Pillai --- drivers/pci/controller/cadence/Kconfig | 16 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pci-sky1.c | 435 ++++++++++++++++++++++ 3 files changed, 452 insertions(+) create mode 100644 drivers/pci/controller/cadence/pci-sky1.c diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controlle= r/cadence/Kconfig index 427aa9beca22..63993495b20d 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -80,4 +80,20 @@ config PCI_J721E_EP Say Y here if you want to support the TI J721E PCIe platform controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe core. + +config PCI_SKY1 + bool + +config PCI_SKY1_HOST + tristate "CIX SKY1 PCIe controller (host mode)" + depends on OF + select PCIE_CADENCE_HOST + select PCI_SKY1 + help + Say Y here if you want to support the CIX SKY1 PCIe platform + controller in host mode. CIX SKY1 PCIe controller uses Cadence HPA(High + Performance Architecture IP[Second generation of cadence PCIe IP]) + + This driver requires Cadence PCIe core infrastructure (PCIE_CADENCE_HOS= T) + and hardware platform adaptation layer to function. endmenu diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index f8575a0eee2d..cfe8c89c0427 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o pcie-c= adence-ep-hpa.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCIE_CADENCE_PLAT_HPA) +=3D pcie-cadence-plat-hpa.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o +obj-$(CONFIG_PCI_SKY1) +=3D pci-sky1.o diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/contro= ller/cadence/pci-sky1.c new file mode 100644 index 000000000000..a4828b92159e --- /dev/null +++ b/drivers/pci/controller/cadence/pci-sky1.c @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * pci-sky1 - PCIe controller driver for CIX's sky1 SoCs + * + * Author: Hans Zhang + */ + +#include +#include +#include +#include + +#include "../../pci.h" +#include "pcie-cadence.h" +#include "pcie-cadence-host-common.h" + +#define STRAP_REG(n) ((n) * 0x04) +#define STATUS_REG(n) ((n) * 0x04) + +#define RCSU_STRAP_REG 0x300 +#define RCSU_STATUS_REG 0x400 + +#define RCSU_STRAP_STATUS_SUBREG_X2 0x40 +#define RCSU_STRAP_STATUS_SUBREG_X10 0x60 +#define RCSU_STRAP_STATUS_SUBREG_X11 0x80 + +#define SKY1_IP_REG_BANK_OFFSET 0x1000 +#define SKY1_IP_CFG_CTRL_REG_BANK_OFFSET 0x4c00 +#define SKY1_IP_AXI_MASTER_COMMON_OFFSET 0xf000 +#define SKY1_AXI_SLAVE_OFFSET 0x9000 +#define SKY1_AXI_MASTER_OFFSET 0xb000 +#define SKY1_AXI_HLS_REGISTERS_OFFSET 0xc000 +#define SKY1_AXI_RAS_REGISTERS_OFFSET 0xe000 +#define SKY1_DTI_REGISTERS_OFFSET 0xd000 + +#define IP_REG_I_DBG_STS_0 0x420 + +#define LINK_TRAINING_ENABLE BIT(0) +#define LINK_COMPLETE BIT(0) +#define SKY1_MAX_LANES 8 + +#define BYPASS_PHASE23_MASK BIT(26) +#define BYPASS_REMOTE_TX_EQ_MASK BIT(25) +#define DC_MAX_EVAL_ITERATION_MASK GENMASK(24, 18) +#define LANE_COUNT_IN_MASK GENMASK(17, 15) +#define PCIE_RATE_MAX_MASK GENMASK(14, 12) +#define SUPPORTED_PRESET_MASK GENMASK(10, 0) + +enum sky1_pcie_id { + PCIE_ID_x8, + PCIE_ID_x4, + PCIE_ID_x2, + PCIE_ID_x1_1, + PCIE_ID_x1_0, +}; + +struct sky1_def_speed_lane { + u32 link_speed; + u32 max_lanes; +}; + +struct sky1_pcie_data { + const struct sky1_def_speed_lane *speed_lane; + struct cdns_plat_pcie_of_data reg_off; +}; + +struct sky1_pcie { + struct device *dev; + const struct sky1_pcie_data *data; + const struct sky1_def_speed_lane *speed_lane; + struct cdns_pcie *cdns_pcie; + struct cdns_pcie_rc *cdns_pcie_rc; + + struct resource *cfg_res; + struct resource *msg_res; + struct pci_config_window *cfg; + void __iomem *rcsu_base; + void __iomem *strap_base; + void __iomem *status_base; + void __iomem *reg_base; + void __iomem *cfg_base; + void __iomem *msg_base; + + u32 id; + u32 link_speed; + u32 num_lanes; +}; + +static const struct sky1_def_speed_lane def_speed_lane[] =3D { + [PCIE_ID_x8] =3D { 4, 8 }, + [PCIE_ID_x4] =3D { 4, 4 }, + [PCIE_ID_x2] =3D { 4, 2 }, + [PCIE_ID_x1_1] =3D { 4, 1 }, + [PCIE_ID_x1_0] =3D { 4, 1 }, +}; + +static void sky1_pcie_clear_and_set_dword(void __iomem *addr, u32 clear, + u32 set) +{ + u32 val; + + val =3D readl(addr); + val &=3D ~clear; + val |=3D set; + writel(val, addr); +} + +static void sky1_pcie_init_bases(struct sky1_pcie *pcie) +{ + u32 strap =3D 0, status =3D 0; + + switch (pcie->id) { + case PCIE_ID_x1_1: + strap =3D status =3D RCSU_STRAP_STATUS_SUBREG_X11; + break; + case PCIE_ID_x1_0: + strap =3D status =3D RCSU_STRAP_STATUS_SUBREG_X10; + break; + case PCIE_ID_x2: + strap =3D status =3D RCSU_STRAP_STATUS_SUBREG_X2; + break; + case PCIE_ID_x8: + case PCIE_ID_x4: + default: + break; + } + + pcie->strap_base =3D pcie->rcsu_base + RCSU_STRAP_REG + strap; + pcie->status_base =3D pcie->rcsu_base + RCSU_STATUS_REG + status; +} + +static int sky1_pcie_parse_mem(struct sky1_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + struct platform_device *pdev =3D to_platform_device(dev); + struct resource *res; + void __iomem *base; + int ret =3D 0; + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "rcsu"); + if (!res) { + dev_err(dev, "Parse \"rcsu\" resource err\n"); + return -ENXIO; + } + pcie->rcsu_base =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!pcie->rcsu_base) { + dev_err(dev, "ioremap failed for resource %pR\n", res); + return -ENOMEM; + } + + base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); + if (IS_ERR(base)) { + dev_err(dev, "Parse \"reg\" resource err\n"); + return PTR_ERR(base); + } + pcie->reg_base =3D base; + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "msg"); + if (!res) { + dev_err(dev, "Parse \"msg\" resource err\n"); + return -ENXIO; + } + pcie->msg_res =3D res; + pcie->msg_base =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!pcie->msg_base) { + dev_err(dev, "ioremap failed for resource %pR\n", res); + return -ENOMEM; + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + if (!res) { + dev_err(dev, "Parse \"cfg\" resource err\n"); + return -ENXIO; + } + pcie->cfg_res =3D res; + + return ret; +} + +static int sky1_pcie_parse_ctrl_id(struct sky1_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + int id, ret =3D 0; + + ret =3D of_property_read_u32(dev->of_node, "sky1,pcie-ctrl-id", &id); + if (ret < 0) { + dev_err(dev, "Failed to read sky1,pcie-ctrl-id: %d\n", ret); + return ret; + } + + if ((id < PCIE_ID_x8) || (id > PCIE_ID_x1_0)) { + dev_err(dev, "get illegal pcie-ctrl-id %d\n", id); + return -EINVAL; + } + pcie->id =3D id; + pcie->speed_lane =3D &def_speed_lane[id]; + + return ret; +} + +static void sky1_pcie_parse_link_speed(struct sky1_pcie *pcie) +{ + int link_speed; + + link_speed =3D of_pci_get_max_link_speed(pcie->dev->of_node); + if (link_speed < 0) + link_speed =3D pcie->speed_lane->link_speed; + pcie->link_speed =3D link_speed; +} + +static int sky1_pcie_parse_num_lanes(struct sky1_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + int ret =3D 0; + u32 lanes; + + ret =3D of_property_read_u32(dev->of_node, "num-lanes", &lanes); + if (ret) { + dev_err(dev, "error:%x, lane number:%d\n", ret, lanes); + ret =3D -EINVAL; + return ret; + } + + if ((lanes < 1) || (lanes > pcie->speed_lane->max_lanes)) + lanes =3D pcie->speed_lane->max_lanes; + pcie->num_lanes =3D lanes; + + return ret; +} + +static int sky1_pcie_get_max_lane_count(struct sky1_pcie *pcie) +{ + if (is_power_of_2(pcie->num_lanes) && pcie->num_lanes <=3D SKY1_MAX_LANES) + return ilog2(pcie->num_lanes); + + pcie->num_lanes =3D 1; + return pcie->num_lanes; +} + +static void sky1_pcie_set_strap_pin0(struct sky1_pcie *pcie) +{ + u32 val; + + val =3D readl(pcie->strap_base + STRAP_REG(0)); + + /* clear bypass_phase23 and bypass_remote_eq */ + val &=3D ~(BYPASS_PHASE23_MASK | BYPASS_REMOTE_TX_EQ_MASK); + + /* set iteration timeout */ + val &=3D ~DC_MAX_EVAL_ITERATION_MASK; + val |=3D FIELD_PREP(DC_MAX_EVAL_ITERATION_MASK, 0x2); + + /* set support preset val */ + val &=3D ~SUPPORTED_PRESET_MASK; + val |=3D FIELD_PREP(SUPPORTED_PRESET_MASK, 0x7ff); + + /* Set link speed */ + val &=3D ~PCIE_RATE_MAX_MASK; + val |=3D FIELD_PREP(PCIE_RATE_MAX_MASK, pcie->link_speed - 1); + + /* Set lane number */ + val &=3D ~LANE_COUNT_IN_MASK; + val |=3D FIELD_PREP(LANE_COUNT_IN_MASK, + sky1_pcie_get_max_lane_count(pcie)); + + writel(val, pcie->strap_base + STRAP_REG(0)); +} + +static int sky1_pcie_parse_property(struct platform_device *pdev, + struct sky1_pcie *pcie) +{ + int ret =3D 0; + + ret =3D sky1_pcie_parse_ctrl_id(pcie); + if (ret < 0) + return ret; + + sky1_pcie_parse_link_speed(pcie); + + ret =3D sky1_pcie_parse_num_lanes(pcie); + if (ret < 0) + return ret; + + ret =3D sky1_pcie_parse_mem(pcie); + if (ret < 0) + return ret; + + sky1_pcie_init_bases(pcie); + + return ret; +} + +static int sky1_pcie_start_link(struct cdns_pcie *cdns_pcie) +{ + struct sky1_pcie *pcie =3D dev_get_drvdata(cdns_pcie->dev); + + sky1_pcie_clear_and_set_dword(pcie->strap_base + STRAP_REG(1), + 0, LINK_TRAINING_ENABLE); + + return 0; +} + +static void sky1_pcie_stop_link(struct cdns_pcie *cdns_pcie) +{ + struct sky1_pcie *pcie =3D dev_get_drvdata(cdns_pcie->dev); + + sky1_pcie_clear_and_set_dword(pcie->strap_base + STRAP_REG(1), + LINK_TRAINING_ENABLE, 0); +} + + +static bool sky1_pcie_link_up(struct cdns_pcie *cdns_pcie) +{ + u32 val; + + val =3D cdns_pcie_hpa_readl(cdns_pcie, REG_BANK_IP_REG, + IP_REG_I_DBG_STS_0); + return val & LINK_COMPLETE; +} + +static const struct cdns_pcie_ops sky1_pcie_ops =3D { + .start_link =3D sky1_pcie_start_link, + .stop_link =3D sky1_pcie_stop_link, + .link_up =3D sky1_pcie_link_up, +}; + +static int sky1_pcie_probe(struct platform_device *pdev) +{ + const struct sky1_pcie_data *data; + struct device *dev =3D &pdev->dev; + struct pci_host_bridge *bridge; + struct cdns_pcie *cdns_pcie; + struct resource_entry *bus; + struct cdns_pcie_rc *rc; + struct sky1_pcie *pcie; + int ret; + + pcie =3D devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + data =3D of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + pcie->data =3D data; + pcie->dev =3D dev; + dev_set_drvdata(dev, pcie); + + bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) + return -ENOMEM; + + bus =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (!bus) + return -ENODEV; + + ret =3D sky1_pcie_parse_property(pdev, pcie); + if (ret < 0) + return -ENXIO; + + sky1_pcie_set_strap_pin0(pcie); + + pcie->cfg =3D pci_ecam_create(dev, pcie->cfg_res, bus->res, + &pci_generic_ecam_ops); + if (IS_ERR(pcie->cfg)) + return PTR_ERR(pcie->cfg); + + bridge->ops =3D (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + rc =3D pci_host_bridge_priv(bridge); + rc->ecam_support_flag =3D 1; + rc->cfg_base =3D pcie->cfg->win; + rc->cfg_res =3D &pcie->cfg->res; + + cdns_pcie =3D &rc->pcie; + cdns_pcie->dev =3D dev; + cdns_pcie->ops =3D &sky1_pcie_ops; + cdns_pcie->reg_base =3D pcie->reg_base; + cdns_pcie->msg_res =3D pcie->msg_res; + cdns_pcie->cdns_pcie_reg_offsets =3D &data->reg_off; + cdns_pcie->is_rc =3D data->reg_off.is_rc; + + pcie->cdns_pcie =3D cdns_pcie; + pcie->cdns_pcie_rc =3D rc; + pcie->cfg_base =3D rc->cfg_base; + bridge->sysdata =3D pcie->cfg; + + ret =3D cdns_pcie_hpa_host_setup(rc); + if (ret < 0) { + pci_ecam_free(pcie->cfg); + return ret; + } + + return 0; +} + +static const struct sky1_pcie_data sky1_pcie_rc_data =3D { + .speed_lane =3D &def_speed_lane[0], + .reg_off =3D { + .is_rc =3D true, + .ip_reg_bank_offset =3D SKY1_IP_REG_BANK_OFFSET, + .ip_cfg_ctrl_reg_offset =3D SKY1_IP_CFG_CTRL_REG_BANK_OFFSET, + .axi_mstr_common_offset =3D SKY1_IP_AXI_MASTER_COMMON_OFFSET, + .axi_slave_offset =3D SKY1_AXI_SLAVE_OFFSET, + .axi_master_offset =3D SKY1_AXI_MASTER_OFFSET, + .axi_hls_offset =3D SKY1_AXI_HLS_REGISTERS_OFFSET, + .axi_ras_offset =3D SKY1_AXI_RAS_REGISTERS_OFFSET, + .axi_dti_offset =3D SKY1_DTI_REGISTERS_OFFSET, + }, +}; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id E7C3D4160503; Mon, 30 Jun 2025 12:16:06 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v5 12/14] MAINTAINERS: add entry for CIX Sky1 PCIe driver Date: Mon, 30 Jun 2025 12:15:59 +0800 Message-ID: <20250630041601.399921-13-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250630041601.399921-1-hans.zhang@cixtech.com> References: <20250630041601.399921-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000C8:EE_|SI2PR06MB5289:EE_ X-MS-Office365-Filtering-Correlation-Id: 3bb1108e-8ba7-4af9-0a36-08ddb78cd844 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700013|7053199007; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 04:16:10.5719 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3bb1108e-8ba7-4af9-0a36-08ddb78cd844 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C8.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SI2PR06MB5289 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add myself as maintainer of Sky1 PCIe host driver Signed-off-by: Hans Zhang Reviewed-by: Peter Chen Reviewed-by: Manikandan K Pillai --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7f8bee29bb8f..2972e24c7b45 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18951,6 +18951,13 @@ S: Orphan F: Documentation/devicetree/bindings/pci/cdns,* F: drivers/pci/controller/cadence/*cadence* =20 +PCI DRIVER FOR CIX Sky1 +M: Hans Zhang +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/cix,sky1-pcie-*.yaml +F: drivers/pci/controller/cadence/*sky1* + PCI DRIVER FOR FREESCALE LAYERSCAPE M: Minghuan Lian M: Mingkai Hu --=20 2.49.0 From nobody Wed Oct 8 10:00:53 2025 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023138.outbound.protection.outlook.com [40.107.44.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE5B92AF1B; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 04B194160504; Mon, 30 Jun 2025 12:16:07 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v5 13/14] arm64: dts: cix: Add PCIe Root Complex on sky1 Date: Mon, 30 Jun 2025 12:16:00 +0800 Message-ID: <20250630041601.399921-14-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250630041601.399921-1-hans.zhang@cixtech.com> References: <20250630041601.399921-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CA:EE_|PUZPR06MB5604:EE_ X-MS-Office365-Filtering-Correlation-Id: 17a1cb8c-1f71-4136-24f9-08ddb78cd848 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?HtnqClRmrUmxbcx45BCTgBDK6k8/37zx8VDOzTUO3dx8PllR2x4+/BGHHKl0?= =?us-ascii?Q?3FsYYY5GVoZq6FgpecqbhfqBmFKNCaWmr1hBHJb+8mL4Q3y/nn1sP5LQltah?= =?us-ascii?Q?pa68qHH1kQzgr43VPex0g1uW57vovOTsWACxNTrimUfLe/TzsToPMFxOZ+TS?= =?us-ascii?Q?g7chaNKX4MJMTVpb6gd36MczsTnp47Yhelz5bYOK6TcLjllzalHd/+7VqAF5?= =?us-ascii?Q?eOkjOCK8jwCxdM0nJGwBW28Znf4ak1i0lqo2/YVnC4bAr6lj2c6VXPKSdN5b?= =?us-ascii?Q?Mnvp2w7igSHq6qpCfVQeT1r6/XA1yjz7Hzc7e5tQP3bROiMWyo0kQfqXIT8b?= =?us-ascii?Q?fLC70ujtOeCBwawHtlateizaQBMJbfnuWbAK/wUj4UpfF3pDsS4l1BZS6Eal?= =?us-ascii?Q?351VRjtDpAXTKeu67x6+xvLlz+cPoXBCeZBuqZNWvfiaJwaxOzWhw63X211C?= =?us-ascii?Q?5LGwxAmoxZCuIdo5lGZCAtPHD2XmnDa1UP/3JZXQTwe+/x4Un1MlpFBwS9p9?= =?us-ascii?Q?m4KFVz3+kkekaFCDYhXrrCCBn0szUp5Xse7eT1cwKSJDpNYOLpvcWBqKD8+w?= =?us-ascii?Q?TqDYuU4SytbFAtN/Q/LMFPanpffAB/Y31TgUlGSKRBKd6+bymv6etX/bsX34?= =?us-ascii?Q?IQ1+VKHuWJXwAyb1pZkUb4s5IVlszQXmymU17cKQzqhARuhnQIxCdq6Bo5ns?= =?us-ascii?Q?BLwlCrAMsBLhAXh7vBBAil4p09GCGzrhBUZX2XQ+Ox7OKzAVC3/TQA8FLlyn?= =?us-ascii?Q?aTqIP312zhWae6hjUuirTO3/5QuletMXYgEc0mGRvKoUyAkR66TzUX6aqARs?= =?us-ascii?Q?+QAzEDmMEuYOdEA03ThDwQ2gkq8bK2ysp1cTueTNK4ZHs//sBxFeenYB0JFU?= =?us-ascii?Q?P/3Y5888IBEv9eUFOHQi7nEMsv9zCLqifliX/XK2O8Om+vgnoGk9E8g0fKaV?= =?us-ascii?Q?/3L/L3iVXTt58TTWHCuYANXgjm4ObD3RT9Dh61Qex+vYQrumtvVRg7lhdbDX?= =?us-ascii?Q?UL4GAoAtvjHAQ+MuzVeeTK4Gd3ElpxhPPmMKMZHB0x580PLkNKUYSMlatx17?= =?us-ascii?Q?Cn5922P+DE1lTTlXz1AiH4yVvSBoC9TZmaZPQxUNqzN+xCYMR6zOcZF6ML40?= =?us-ascii?Q?5krYtbp0xdi7LI2JxYBebK9bk7zYlf2FVBNHdhQh2q6hkf2AVx/Sfk6Za/Wc?= =?us-ascii?Q?hQXT15HusCTNJqQDyY5s2vnvf9RieZhtuKJSxjZrGIX45TzSi83z5rME+Bjt?= =?us-ascii?Q?u1C/QmObS+eQEBuYBxXvHuNba6Xp2pLocfPWDSsJsarUHMJMBn6UJSuziaQN?= =?us-ascii?Q?IOHGVWAiMPUl78DnfoSDoUQDZovpCDcvCZElsqRV2FepCFikCb456cOpg8O3?= =?us-ascii?Q?DoEkuBBturNIg32rZgNuRcIlwNA47k9msKGqtn2iLn+87R0CSWhMXTXZcX0B?= =?us-ascii?Q?4s03HZG9AV5Un6PzTv/HiHsYBZh92EaGlHSIFZ+7M68I330eIiozPzPLGx78?= =?us-ascii?Q?SFLIH+u9q6CQzNaTgCKD7yzeVs8N9PM6D2gd?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7416014)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2025 04:16:10.6284 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17a1cb8c-1f71-4136-24f9-08ddb78cd848 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CA.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PUZPR06MB5604 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add pcie_x*_rc node to support Sky1 PCIe driver based on the Cadence PCIe core. Supports Gen1/Gen2/Gen3/Gen4, 1/2/4/8 lane, MSI/MSI-x interrupts using the ARM GICv3. Signed-off-by: Hans Zhang Reviewed-by: Peter Chen Reviewed-by: Manikandan K Pillai --- arch/arm64/boot/dts/cix/sky1.dtsi | 150 ++++++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi index 9c723917d8ca..1dac0e8d5fc1 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -289,6 +289,156 @@ mbox_ap2sfh: mailbox@80a0000 { cix,mbox-dir =3D "tx"; }; =20 + pcie_x8_rc: pcie@a010000 { /* X8 */ + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a010000 0x00 0x10000>, + <0x00 0x0a000000 0x00 0x10000>, + <0x00 0x2c000000 0x00 0x4000000>, + <0x00 0x60000000 0x00 0x00100000>; + reg-names =3D "reg", "rcsu", "cfg", "msg"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>; + max-link-speed =3D <4>; + num-lanes =3D <8>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0xc0 0xff>; + device_type =3D "pci"; + ranges =3D <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>, + <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>; + msi-map =3D <0xc000 &gic_its 0xc000 0x4000>; + vendor-id =3D <0x1f6c>; + device-id =3D <0x0001>; + cdns,no-inbound-bar; + sky1,pcie-ctrl-id =3D <0x0>; + status =3D "disabled"; + }; + + pcie_x4_rc: pcie@a070000 { /* X4 */ + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a070000 0x00 0x10000>, + <0x00 0x0a060000 0x00 0x10000>, + <0x00 0x29000000 0x00 0x3000000>, + <0x00 0x50000000 0x00 0x00100000>; + reg-names =3D "reg", "rcsu", "cfg", "msg"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>; + max-link-speed =3D <4>; + num-lanes =3D <4>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x90 0xbf>; + device_type =3D "pci"; + ranges =3D <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>, + <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>, + <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>; + msi-map =3D <0x9000 &gic_its 0x9000 0x3000>; + vendor-id =3D <0x1f6c>; + device-id =3D <0x0001>; + cdns,no-inbound-bar; + sky1,pcie-ctrl-id =3D <0x1>; + status =3D "disabled"; + }; + + pcie_x2_rc: pcie@a0c0000 { /* X2 */ + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0c0000 0x00 0x10000>, + <0x00 0x0a060000 0x00 0x10000>, + <0x00 0x26000000 0x00 0x3000000>, + <0x00 0x40000000 0x00 0x00100000>; + reg-names =3D "reg", "rcsu", "cfg", "msg"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>; + max-link-speed =3D <4>; + num-lanes =3D <2>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x60 0x8f>; + device_type =3D "pci"; + ranges =3D <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>, + <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>; + msi-map =3D <0x6000 &gic_its 0x6000 0x3000>; + vendor-id =3D <0x1f6c>; + device-id =3D <0x0001>; + cdns,no-inbound-bar; + sky1,pcie-ctrl-id =3D <0x2>; + status =3D "disabled"; + }; + + pcie_x1_0_rc: pcie@a0d0000 { /* X1_0 */ + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0d0000 0x00 0x10000>, + <0x00 0x0a060000 0x00 0x10000>, + <0x00 0x20000000 0x00 0x3000000>, + <0x00 0x30000000 0x00 0x00100000>; + reg-names =3D "reg", "rcsu", "cfg", "msg"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; + max-link-speed =3D <4>; + num-lanes =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x00 0x2f>; + device_type =3D "pci"; + ranges =3D <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>, + <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>, + <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>; + msi-map =3D <0x0000 &gic_its 0x0000 0x3000>; + vendor-id =3D <0x1f6c>; + device-id =3D <0x0001>; + cdns,no-inbound-bar; + sky1,pcie-ctrl-id =3D <0x4>; + status =3D "disabled"; + }; + + pcie_x1_1_rc: pcie@a0e0000 { /* X1_1 */ + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0e0000 0x00 0x10000>, + <0x00 0x0a060000 0x00 0x10000>, + <0x00 0x23000000 0x00 0x3000000>, + <0x00 0x38000000 0x00 0x00100000>; + reg-names =3D "reg", "rcsu", "cfg", "msg"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>; 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Signed-off-by: Hans Zhang Reviewed-by: Peter Chen Reviewed-by: Manikandan K Pillai --- arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dt= s/cix/sky1-orion-o6.dts index d74964d53c3b..44710d54ddad 100644 --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts @@ -37,3 +37,23 @@ linux,cma { &uart2 { status =3D "okay"; }; + +&pcie_x8_rc { + status =3D "okay"; +}; + +&pcie_x4_rc { + status =3D "okay"; +}; + +&pcie_x2_rc { + status =3D "okay"; +}; + +&pcie_x1_0_rc { + status =3D "okay"; +}; + +&pcie_x1_1_rc { + status =3D "okay"; +}; --=20 2.49.0