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bh=Rl8rUhHmRFSg5ocU//+Q9pQPMUl7/usDwSblRogsAYA=; b=WAOKgty0MEGT/uDRgXN96XqJak4Tr6uCKyvxcuNzi/1+dRKU5jGkGaWQUJI/PK9eWEwSNBRiV3v5SPRmRswcb4sE5IwKbDnZHz/O8PvdOhMY5zEAQ7719kFYrmhLCUnCNPFUAvz+YsioHc+barv1Zn/YIh1fW4esWpd9ZcLqNHQ= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=os.amperecomputing.com; Received: from PH0PR01MB7975.prod.exchangelabs.com (2603:10b6:510:26d::15) by LV3PR01MB8511.prod.exchangelabs.com (2603:10b6:408:1a0::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8880.28; Mon, 30 Jun 2025 03:03:45 +0000 Received: from PH0PR01MB7975.prod.exchangelabs.com ([fe80::6926:a627:118e:8050]) by PH0PR01MB7975.prod.exchangelabs.com ([fe80::6926:a627:118e:8050%6]) with mapi id 15.20.8857.026; Mon, 30 Jun 2025 03:03:45 +0000 From: Huang Shijie To: catalin.marinas@arm.com, will@kernel.org, corbet@lwn.net Cc: patches@amperecomputing.com, cl@linux.com, yang@os.amperecomputing.com, akpm@linux-foundation.org, paulmck@kernel.org, rostedt@goodmis.org, Neeraj.Upadhyay@amd.com, bp@alien8.de, ardb@kernel.org, anshuman.khandual@arm.com, suzuki.poulose@arm.com, gshan@redhat.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Huang Shijie Subject: [PATCH V5 1/2] arm64: refactor the rodata=xxx Date: Mon, 30 Jun 2025 11:02:27 +0800 Message-Id: <20250630030228.4221-2-shijie@os.amperecomputing.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20250630030228.4221-1-shijie@os.amperecomputing.com> References: <20250630030228.4221-1-shijie@os.amperecomputing.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TPYP295CA0009.TWNP295.PROD.OUTLOOK.COM (2603:1096:7d0:9::8) To PH0PR01MB7975.prod.exchangelabs.com (2603:10b6:510:26d::15) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH0PR01MB7975:EE_|LV3PR01MB8511:EE_ X-MS-Office365-Filtering-Correlation-Id: ba751848-b050-483d-8850-08ddb782ba54 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|7416014|1800799024|366016|38350700014; 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charset="utf-8" As per admin guide documentation, "rodata=3Don" should be the default on platforms. Documentation/admin-guide/kernel-parameters.txt describes these options as rodata=3D [KNL,EARLY] on Mark read-only kernel memory as read-only (default). off Leave read-only kernel memory writable for debugging. full Mark read-only kernel memory and aliases as read-only [arm64] But on arm64 platform, "rodata=3Dfull" is the default instead. This patch implements the following changes. - Make "rodata=3Don" behaviour same as the original "rodata=3Dfull" - Make "rodata=3Dnoalias" (new) behaviour same as the original "rodata=3Do= n" - Drop the original "rodata=3Dfull" - Add comment for arch_parse_debug_rodata() - Update kernel-parameters.txt as required After this patch, the "rodata=3Don" will be the default on arm64 platform as well. Signed-off-by: Huang Shijie --- .../admin-guide/kernel-parameters.txt | 2 +- arch/arm64/include/asm/setup.h | 28 +++++++++++++++++-- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index ee0735c6b8e2..e0cd6dac26d3 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -6354,7 +6354,7 @@ rodata=3D [KNL,EARLY] on Mark read-only kernel memory as read-only (default). off Leave read-only kernel memory writable for debugging. - full Mark read-only kernel memory and aliases as read-only + noalias Use more block mappings,may have better performance. [arm64] =20 rockchip.usb_uart diff --git a/arch/arm64/include/asm/setup.h b/arch/arm64/include/asm/setup.h index ba269a7a3201..6b994d0881d1 100644 --- a/arch/arm64/include/asm/setup.h +++ b/arch/arm64/include/asm/setup.h @@ -13,6 +13,30 @@ extern phys_addr_t __fdt_pointer __initdata; extern u64 __cacheline_aligned boot_args[4]; =20 +/* + * rodata=3Don (default) + * + * This applies read-only attributes to VM areas and to the linear + * alias of the backing pages as well. This prevents code or read- + * only data from being modified (inadvertently or intentionally), + * via another mapping for the same memory page. + * + * But this might cause linear map region to be mapped down to base + * pages, which may adversely affect performance in some cases. + * + * rodata=3Doff + * + * This provides more block mappings and contiguous hints for linear + * map region which would minimize TLB footprint. This also leaves + * read-only kernel memory writable for debugging. + * + * rodata=3Dnoalias + * + * This provides more block mappings and contiguous hints for linear + * map region which would minimize TLB footprint. This leaves the linear + * alias of read-only mappings in the vmalloc space writeable, making + * them susceptible to inadvertent modification by software. + */ static inline bool arch_parse_debug_rodata(char *arg) { extern bool rodata_enabled; @@ -21,7 +45,7 @@ static inline bool arch_parse_debug_rodata(char *arg) if (!arg) return false; =20 - if (!strcmp(arg, "full")) { + if (!strcmp(arg, "on")) { rodata_enabled =3D rodata_full =3D true; return true; } @@ -31,7 +55,7 @@ static inline bool arch_parse_debug_rodata(char *arg) return true; } =20 - if (!strcmp(arg, "on")) { + if (!strcmp(arg, "noalias")) { rodata_enabled =3D true; rodata_full =3D false; return true; --=20 2.40.1