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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-315f5426be4sm13402856a91.32.2025.06.30.01.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jun 2025 01:50:19 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Mon, 30 Jun 2025 14:20:15 +0530 Subject: [PATCH v3] arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250630-ipq5424_hsuart-v3-1-fa0866b12cbc@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAMZPYmgC/13MQQrCMBCF4auUWZsSk0kWrryHiEzSiQ3Ypk3aI pTe3eBK3Dz4Fu/foXCOXODS7JB5iyWmsUKfGvA9jU8WsasGJZWRVksRp9mgwkdfVsqLkD4odIi anIN6mjKH+P4Gb/fqkNMglj4z/WQU/mc2Jc7CGms7coGR7DWV0s4rvXwahrYOHMcHgWjJYa0AA AA= X-Change-ID: 20250630-ipq5424_hsuart-0cf24b443abb To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751273416; l=2805; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=she2MK+667uF9NMpAB7wWzjENWSuCdor4U9yjFHG4lU=; b=hQhbLvr2857q6giO4da1L6gIforS6oRHZDVsJq47r/F55Zn5G9aPQO1XdjZmDMNoTgjnBdsbK UzbjKQSbg32B11Djgcj/h9X2yVfw1jwBQ/HyEF2jG9nDScEMkc//R6y X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Authority-Analysis: v=2.4 cv=ZKfXmW7b c=1 sm=1 tr=0 ts=68624fcd cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Vg8ECOsEd2VHoE4ukXAA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjMwMDA3MyBTYWx0ZWRfX8O9rENq5FxK2 2SUT14qUPPFfNF7ya19chr6jiMp9IgThIq23xnnILKFGM37481lJyYkS7kMJwHq1+jPr89vOZ9H FmG45W6+RR9CyilSPcwxHu890OfYl8lMAJhsNi93ZleO7/1cqlYMhZqNCKxM+cAxsE9o6Oop8Az ox5/XzDkfJOdI8RVhLIPu7a+u0BznhRivPAkp273vlOjoFnWEX/giB8CWosIJ5MV1wIEnDsOc64 BjV+DKL2oPgzP/H+S92WwgnSjirMIZMx2nUByO92c8OcFaAigtUWf92IfqMXldiT3n3mC7+q7/W c8ilodlOqcLQgJn9PVcX1Zm1I9emEFm71SqUgxJMdVqG5AHvG5Mdf/tL3LdGIxgmOTg+o64C4Wf t/uFYW4wyhXfEFPPeQ1FCz3tErrmXJrd2LOc60iL+KVE5kqkmo//OIVvIgjHWUND1tNbJI/D X-Proofpoint-ORIG-GUID: hLYKOjYaZ43DfosVeikq5BBJp_WmMhbg X-Proofpoint-GUID: hLYKOjYaZ43DfosVeikq5BBJp_WmMhbg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-30_02,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 mlxlogscore=929 spamscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 impostorscore=0 malwarescore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506300073 QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the first SE, which supports a 4-wire UART configuration suitable for applications such as HS-UART. Note that the required initialization for this SE is not handled by the bootloader. Therefore, add the SE node in the device tree but keep it disabled. Enable it once Linux gains support for configuring the SE, allowing to use in relevant RDPs. Signed-off-by: Kathiravan Thirumoorthy --- Changes in v3: - Add the pinctrl configuration for the SE (Konrad) - Link to v2: https://lore.kernel.org/linux-arm-msm/20250624-ipq5424_hsuart-v2-1-6566da= bfe4a6@oss.qualcomm.com/ Changes in v2: - Correct the interrupt number - Link to v1: https://lore.kernel.org/r/20250624-ipq5424_hsuart-v1-1-a4e71d00fc05@oss.q= ualcomm.com --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 12 ++++++++++++ arch/arm64/boot/dts/qcom/ipq5424.dtsi | 9 +++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/= dts/qcom/ipq5424-rdp466.dts index 1f89530cb0353898e0ac83e67dfd32721ede88f8..8dee436464cb588fdde707b06bd= 93302b2499454 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -224,6 +224,13 @@ data-pins { }; }; =20 + uart0_pins: uart0-default-state { + pins =3D "gpio10", "gpio11", "gpio12", "gpio13"; + function =3D "uart0"; + drive-strength =3D <8>; + bias-pull-down; + }; + pcie2_default_state: pcie2-default-state { pins =3D "gpio31"; function =3D "gpio"; @@ -239,6 +246,11 @@ pcie3_default_state: pcie3-default-state { }; }; =20 +&uart0 { + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; +}; + &uart1 { pinctrl-0 =3D <&uart1_pins>; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index 66bd2261eb25d79051adddef604c55f5b01e6e8b..2b8499422a8a9a2f63e1af9ae8c= 189bafe690514 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -417,6 +417,15 @@ qupv3: geniqup@1ac0000 { #address-cells =3D <2>; #size-cells =3D <2>; =20 + uart0: serial@1a80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x01a80000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_UART0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + status =3D "disabled"; + }; + uart1: serial@1a84000 { compatible =3D "qcom,geni-debug-uart"; reg =3D <0 0x01a84000 0 0x4000>; --- base-commit: 1343433ed38923a21425c602e92120a1f1db5f7a change-id: 20250630-ipq5424_hsuart-0cf24b443abb Best regards, --=20 Kathiravan Thirumoorthy