From nobody Wed Oct 8 11:01:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A88B12857D7; Mon, 30 Jun 2025 12:35:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751286909; cv=none; b=ULs51+2qrY73TXk97ZXMP0QXZzQbfHgdYJCQneCV9sgZApbPk/CJNcklsxZLk7zGcGgbV/3HzlsUVA6Lx2fRrC4tEn2IXxJAbLmc1CbOTsWm7i8EwRFqSGeEDxYuTYSgAmKJomEsx8SbdfjgmcrDeuLkMRIQdruCF6J1JvXPUHU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751286909; c=relaxed/simple; bh=WzM5y2OoQkwywYk7ze1eYenAU+huZ1+9rx3teZ27zKM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Jd6Sz+1GL0nZAcM6+fj9Z9JgkUb4LZf9W/FjC0OA2y2bsl3uRHxkiVVvUqp5dJupvoSdBI4tEbfi2WZpzY+s83thcTqheEZXJNI4Celix8f/9U60LRhKRlus2+oGQxshKpfAsHqcnPqOEyuW3WSij9BsxYleJxlZrUOy2pEXrOI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JGGP0zM1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JGGP0zM1" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3EB46C4CEF1; Mon, 30 Jun 2025 12:35:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751286909; bh=WzM5y2OoQkwywYk7ze1eYenAU+huZ1+9rx3teZ27zKM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=JGGP0zM14oV/gWS7i1uDH+h5xgGgyBsar8b1OQtAMQcla9duII26LNSGIlTrrDLF7 IGyaXQP9SE0Ra9aYanA5/fu/Q4VV0CDnwc7NSe7GawBLZuFdWvTG6U3EGcMK0x8rE4 bvN7K/PK5wtj34SVq0XU1jG5k6PXmtmFVyyDm6cdqA9hms21ckUPLoSc3G9a9WUmjK TM+OgCsHZSBdXyoqNWOKXLIGqeQzESl1ClIXmKX2/BkRVoc91zkRGaqcr6vbn9HRLn gBBmErbgbp0XDD5OrOOY4ijqoTDKG3o9tdGteva1ZbdW2p4fR8mlWYvP23e0XB0yoV We7dHqznfMEkA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EFC0C83030; Mon, 30 Jun 2025 12:35:09 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 30 Jun 2025 16:35:01 +0400 Subject: [PATCH v6 2/3] arm64: dts: qcom: ipq5018: Add MDIO buses Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250630-ipq5018-ge-phy-v6-2-01be06378c15@outlook.com> References: <20250630-ipq5018-ge-phy-v6-0-01be06378c15@outlook.com> In-Reply-To: <20250630-ipq5018-ge-phy-v6-0-01be06378c15@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751286906; l=1519; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=jA4BQsaw0tlEf36IZrwvZtR6C1am2pcwyAdrevsj4Hk=; b=zhpJIuMeUf1JRn427l7eFVhR1EPJ/rB+EyanEchKtvoBAEd02pDGr8SV7up81RN8ZX1b8UOCT M6NL0ziSVpKD8aqeexhAp9s85HOEOYu/sAO7joD8qvnnoS3/CqoFWaI X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem IPQ5018 contains two mdio buses of which one bus is used to control the SoC's internal GE PHY, while the other bus is connected to external PHYs or switches. There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's simply add the mdio nodes for them. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 130360014c5e14c778e348d37e601f60325b0b14..03ebc3e305b267c98a034c41ce4= 7a39269afce75 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -182,6 +182,30 @@ pcie0_phy: phy@86000 { status =3D "disabled"; }; =20 + mdio0: mdio@88000 { + compatible =3D "qcom,ipq5018-mdio"; + reg =3D <0x00088000 0x64>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + clocks =3D <&gcc GCC_MDIO0_AHB_CLK>; + clock-names =3D "gcc_mdio_ahb_clk"; + + status =3D "disabled"; + }; + + mdio1: mdio@90000 { + compatible =3D "qcom,ipq5018-mdio"; + reg =3D <0x00090000 0x64>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + clocks =3D <&gcc GCC_MDIO1_AHB_CLK>; + clock-names =3D "gcc_mdio_ahb_clk"; + + status =3D "disabled"; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5018-tlmm"; reg =3D <0x01000000 0x300000>; --=20 2.49.0