From nobody Wed Oct 8 09:28:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66A3B27055A; Mon, 30 Jun 2025 12:35:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751286909; cv=none; b=MQ5FIshUloX30jEJV9FBRALA4QR3OsUdq4Dqc1QVoZ6Tv5TMxe4PrNJK9bQBerdP+aiq7kijxsdt62AQ5Z1zCM9qknEIhiP0+4z763E7zTOemTRPqtye35UFZ0QorTxLH77d8pJ2QJqr8kCk0PzbPHwObZVoQ2A+d4A8Me5kLC4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751286909; c=relaxed/simple; bh=8Y2htiPy5meWxzHXQzhyzo1AQtbeIgcyev3Yn6FKh6Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KIDGfLini0mZBAJmWFk/1Oy2zbsCpca2d52gGLKcd0VQX5hylZVAbN2zLLo4psqfKim+NGZPgqkrCVeN+Mp6KVNlakakG9QxvDy+Y94YWGrXJb+U8IOGa+Mi4OpHOK1dcSe/ksPNxZ+ZKC+8vm7LvoRJnoSAfEm5GnSghhLnjl4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mPMT8vHr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mPMT8vHr" Received: by smtp.kernel.org (Postfix) with ESMTPS id 34C5BC4CEEF; Mon, 30 Jun 2025 12:35:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751286909; bh=8Y2htiPy5meWxzHXQzhyzo1AQtbeIgcyev3Yn6FKh6Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=mPMT8vHrQ0V8KVI6Il0mkawZgYlIFi9d7naOFlzYL9Mwpr8To2hAhfefixrG7H/yc izB8lNc91m7b0b3hi4bSaxYvEmTZuIKTowvifjxIYFR6Ug7SW7mHUP7SlagELLi0ST +rzwm8ZMnKFspMOchqaD8d81SDxbofmxjbzKyDTi0BgwVHgvjGFSVBWpRu4bnc68o6 jB2kd3ztkdO9DhrnK5KVcDMlL2NkxmomMmGBsnrIYzS9P9cpLQYHguljrFM9LjhoeQ /uEXzZVZqDc90aw/t+dGB7GAJnnOZsWOkHTpNskCgviRYSNd/y5t7GxPHiLt+OPAVG 5dXBoR/Ze0o7w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23671C8302F; Mon, 30 Jun 2025 12:35:09 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 30 Jun 2025 16:35:00 +0400 Subject: [PATCH v6 1/3] clk: qcom: gcc-ipq5018: fix GE PHY reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250630-ipq5018-ge-phy-v6-1-01be06378c15@outlook.com> References: <20250630-ipq5018-ge-phy-v6-0-01be06378c15@outlook.com> In-Reply-To: <20250630-ipq5018-ge-phy-v6-0-01be06378c15@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751286906; l=1220; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=y65n0Od6u+x9wP3HKotpTyPdgu84le/dyFb7G8W0t/E=; b=8GFFdXl2KAWvcdLAfio5sbRql6URuWxu1LrF2UScWzaP2crAPzgbOSYYGfwb2CyAvqVN6HQvG cKUzsL4FKfOCe0qZu/cImN6p6estTR7yvV1/7E6WEQD7X3ZhI9T9Gqf X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The MISC reset is supposed to trigger a resets across the MDC, DSP, and RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask of the reset definition accordingly in the GCC as per the downstream driver. Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit= /00743c3e82fa87cba4460e7a2ba32f473a9ce932 Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- drivers/clk/qcom/gcc-ipq5018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 70f5dcb96700f55da1fb19fc893d22350a7e63bf..6eb86c034fda18c38dcd9726f09= 03841252381da 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -3660,7 +3660,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets= [] =3D { [GCC_WCSS_AXI_S_ARES] =3D { 0x59008, 6 }, [GCC_WCSS_Q6_BCR] =3D { 0x18004, 0 }, [GCC_WCSSAON_RESET] =3D { 0x59010, 0}, - [GCC_GEPHY_MISC_ARES] =3D { 0x56004, 0 }, + [GCC_GEPHY_MISC_ARES] =3D { 0x56004, .bitmask =3D GENMASK(3, 0) }, }; =20 static const struct of_device_id gcc_ipq5018_match_table[] =3D { --=20 2.49.0 From nobody Wed Oct 8 09:28:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A88B12857D7; Mon, 30 Jun 2025 12:35:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751286909; cv=none; b=ULs51+2qrY73TXk97ZXMP0QXZzQbfHgdYJCQneCV9sgZApbPk/CJNcklsxZLk7zGcGgbV/3HzlsUVA6Lx2fRrC4tEn2IXxJAbLmc1CbOTsWm7i8EwRFqSGeEDxYuTYSgAmKJomEsx8SbdfjgmcrDeuLkMRIQdruCF6J1JvXPUHU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751286909; c=relaxed/simple; bh=WzM5y2OoQkwywYk7ze1eYenAU+huZ1+9rx3teZ27zKM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Jd6Sz+1GL0nZAcM6+fj9Z9JgkUb4LZf9W/FjC0OA2y2bsl3uRHxkiVVvUqp5dJupvoSdBI4tEbfi2WZpzY+s83thcTqheEZXJNI4Celix8f/9U60LRhKRlus2+oGQxshKpfAsHqcnPqOEyuW3WSij9BsxYleJxlZrUOy2pEXrOI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JGGP0zM1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JGGP0zM1" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3EB46C4CEF1; Mon, 30 Jun 2025 12:35:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751286909; bh=WzM5y2OoQkwywYk7ze1eYenAU+huZ1+9rx3teZ27zKM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=JGGP0zM14oV/gWS7i1uDH+h5xgGgyBsar8b1OQtAMQcla9duII26LNSGIlTrrDLF7 IGyaXQP9SE0Ra9aYanA5/fu/Q4VV0CDnwc7NSe7GawBLZuFdWvTG6U3EGcMK0x8rE4 bvN7K/PK5wtj34SVq0XU1jG5k6PXmtmFVyyDm6cdqA9hms21ckUPLoSc3G9a9WUmjK TM+OgCsHZSBdXyoqNWOKXLIGqeQzESl1ClIXmKX2/BkRVoc91zkRGaqcr6vbn9HRLn gBBmErbgbp0XDD5OrOOY4ijqoTDKG3o9tdGteva1ZbdW2p4fR8mlWYvP23e0XB0yoV We7dHqznfMEkA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EFC0C83030; Mon, 30 Jun 2025 12:35:09 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 30 Jun 2025 16:35:01 +0400 Subject: [PATCH v6 2/3] arm64: dts: qcom: ipq5018: Add MDIO buses Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250630-ipq5018-ge-phy-v6-2-01be06378c15@outlook.com> References: <20250630-ipq5018-ge-phy-v6-0-01be06378c15@outlook.com> In-Reply-To: <20250630-ipq5018-ge-phy-v6-0-01be06378c15@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751286906; l=1519; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=jA4BQsaw0tlEf36IZrwvZtR6C1am2pcwyAdrevsj4Hk=; b=zhpJIuMeUf1JRn427l7eFVhR1EPJ/rB+EyanEchKtvoBAEd02pDGr8SV7up81RN8ZX1b8UOCT M6NL0ziSVpKD8aqeexhAp9s85HOEOYu/sAO7joD8qvnnoS3/CqoFWaI X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem IPQ5018 contains two mdio buses of which one bus is used to control the SoC's internal GE PHY, while the other bus is connected to external PHYs or switches. There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's simply add the mdio nodes for them. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 130360014c5e14c778e348d37e601f60325b0b14..03ebc3e305b267c98a034c41ce4= 7a39269afce75 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -182,6 +182,30 @@ pcie0_phy: phy@86000 { status =3D "disabled"; }; =20 + mdio0: mdio@88000 { + compatible =3D "qcom,ipq5018-mdio"; + reg =3D <0x00088000 0x64>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + clocks =3D <&gcc GCC_MDIO0_AHB_CLK>; + clock-names =3D "gcc_mdio_ahb_clk"; + + status =3D "disabled"; + }; + + mdio1: mdio@90000 { + compatible =3D "qcom,ipq5018-mdio"; + reg =3D <0x00090000 0x64>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + clocks =3D <&gcc GCC_MDIO1_AHB_CLK>; + clock-names =3D "gcc_mdio_ahb_clk"; + + status =3D "disabled"; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5018-tlmm"; reg =3D <0x01000000 0x300000>; --=20 2.49.0 From nobody Wed Oct 8 09:28:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A883328541A; Mon, 30 Jun 2025 12:35:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751286909; cv=none; b=YfLP0XNjwzgDO7iCg2WaBXp8+Ga1dp8AuPNM3+Pfc6MB81rG3wH9GYi+YCwkNWyTG0S3OHsuSN3mKgrAK7gQcsNpvxUk9X8kcWO4RECIyb8b24wYAj4Nv3wIR+V9E9rTR37KX9lpDJh/sf2i2Dy2+db8ME1lYBeHKbCoce/ZjzY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751286909; c=relaxed/simple; bh=YW0aYGk44OBGXMXwnXBPhhKQgB+lh/nINEBWmVaTupA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tXNCEAt+SZGE7WA/y8VkOS2ruEsEJPmO779x/djqnu/5VOyttotGjosjDxHHVozwigb94UZzb0EUHPun4wRCcKbZy4RWMM/gyp7TfyB0STt0MdfknpwxPCMubKpLhlMc2niASTZOP32wtRl12Q3tEv0DEv0O90MrI2+musIrz7I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hiVxAXGX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hiVxAXGX" Received: by smtp.kernel.org (Postfix) with ESMTPS id 49B71C4CEF0; Mon, 30 Jun 2025 12:35:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751286909; bh=YW0aYGk44OBGXMXwnXBPhhKQgB+lh/nINEBWmVaTupA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=hiVxAXGXQ8H6BdtyN7EFwnMXb/XPGc38WjYW/v2yr3Mg5RweO1YrjAnhtBePaVlia RRD8C1GhKY2gIjKTo225BRlMA3BiErPevvKFHwe/MeQNw0PrdLXr7ulDQ9SZaylhlU B0DfAphss8VK+6PFrDxdGY6+Z74IeQbRoQ10V57sCzaKP5uyQPvIuUCrbp0pN4k8zK SewWjLvTv0219qzLrQ/n6MClsLjxRA8iMMCNc/1iqpeWB/nc0eKvJ34eSUzCfc+mV2 fM2Ah1mhUhkNfTSF3+5rTG/WQc4y1C/cyoT/2A/SyXpJRSnmv97Wi/OoZcC5MXSSg2 /9g0qsKa06fjQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AADEC83035; Mon, 30 Jun 2025 12:35:09 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 30 Jun 2025 16:35:02 +0400 Subject: [PATCH v6 3/3] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250630-ipq5018-ge-phy-v6-3-01be06378c15@outlook.com> References: <20250630-ipq5018-ge-phy-v6-0-01be06378c15@outlook.com> In-Reply-To: <20250630-ipq5018-ge-phy-v6-0-01be06378c15@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751286906; l=2285; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=hFpy0osU/0n+A52muRC0D3Drst6JCZAX5hmtJZDrLks=; b=IbGpuJzXMc5BTx2N1rUvDYbw3TZRyzsQvQdssmrmVKxNooxUSRgWjgh4ug1nAPUDTG89lVvt1 4/MbsLOMbeADHLvXCxRNLeck65T452aoe/sE0r8U3a2ZISQfq7/fig9 X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ5018 SoC contains an internal GE PHY, always at phy address 7. As such, let's add the GE PHY node to the SoC dtsi. The LDO controller found in the SoC must be enabled to provide constant low voltages to the PHY. The mdio-ipq4019 driver already has support for this, so adding the appropriate TCSR register offset. In addition, the GE PHY outputs both the RX and TX clocks to the GCC which gate controls them and routes them back to the PHY itself. So let's create two DT fixed clocks and register them in the GCC node. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 03ebc3e305b267c98a034c41ce47a39269afce75..d47ad62b01991fafa51e7082bd1= fcf6670d9b0bc 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -16,6 +16,18 @@ / { #size-cells =3D <2>; =20 clocks { + gephy_rx_clk: gephy-rx-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + #clock-cells =3D <0>; + }; + + gephy_tx_clk: gephy-tx-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + #clock-cells =3D <0>; + }; + sleep_clk: sleep-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -184,7 +196,8 @@ pcie0_phy: phy@86000 { =20 mdio0: mdio@88000 { compatible =3D "qcom,ipq5018-mdio"; - reg =3D <0x00088000 0x64>; + reg =3D <0x00088000 0x64>, + <0x019475c4 0x4>; #address-cells =3D <1>; #size-cells =3D <0>; =20 @@ -192,6 +205,13 @@ mdio0: mdio@88000 { clock-names =3D "gcc_mdio_ahb_clk"; =20 status =3D "disabled"; + + ge_phy: ethernet-phy@7 { + compatible =3D "ethernet-phy-id004d.d0c0"; + reg =3D <7>; + + resets =3D <&gcc GCC_GEPHY_MISC_ARES>; + }; }; =20 mdio1: mdio@90000 { @@ -232,8 +252,8 @@ gcc: clock-controller@1800000 { <&pcie0_phy>, <&pcie1_phy>, <0>, - <0>, - <0>, + <&gephy_rx_clk>, + <&gephy_tx_clk>, <0>, <0>; #clock-cells =3D <1>; --=20 2.49.0