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charset="utf-8" From: Rob Clark In the next commit, a way for userspace to opt-in to userspace managed VM is added. For this to work, we need to defer creation of the VM until it is needed. Signed-off-by: Rob Clark Signed-off-by: Rob Clark Tested-by: Antonino Maniscalco Reviewed-by: Antonino Maniscalco --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 ++- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 14 +++++++----- drivers/gpu/drm/msm/msm_drv.c | 29 ++++++++++++++++++++----- drivers/gpu/drm/msm/msm_gem_submit.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 9 +++++++- 5 files changed, 43 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 0b78888c58af..7364b7e9c266 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -112,6 +112,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gp= u, { bool sysprof =3D refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; struct msm_context *ctx =3D submit->queue->ctx; + struct drm_gpuvm *vm =3D msm_context_vm(submit->dev, ctx); struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; phys_addr_t ttbr; u32 asid; @@ -120,7 +121,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gp= u, if (ctx->seqno =3D=3D ring->cur_ctx_seqno) return; =20 - if (msm_iommu_pagetable_params(to_msm_vm(ctx->vm)->mmu, &ttbr, &asid)) + if (msm_iommu_pagetable_params(to_msm_vm(vm)->mmu, &ttbr, &asid)) return; =20 if (adreno_gpu->info->family >=3D ADRENO_7XX_GEN1) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index 12bf39c0516c..2baf381ea401 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -369,6 +369,8 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_co= ntext *ctx, { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct drm_device *drm =3D gpu->dev; + /* Note ctx can be NULL when called from rd_open(): */ + struct drm_gpuvm *vm =3D ctx ? msm_context_vm(drm, ctx) : NULL; =20 /* No pointer params yet */ if (*len !=3D 0) @@ -414,8 +416,8 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_co= ntext *ctx, *value =3D 0; return 0; case MSM_PARAM_FAULTS: - if (ctx->vm) - *value =3D gpu->global_faults + to_msm_vm(ctx->vm)->faults; + if (vm) + *value =3D gpu->global_faults + to_msm_vm(vm)->faults; else *value =3D gpu->global_faults; return 0; @@ -423,14 +425,14 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_= context *ctx, *value =3D gpu->suspend_count; return 0; case MSM_PARAM_VA_START: - if (ctx->vm =3D=3D gpu->vm) + if (vm =3D=3D gpu->vm) return UERR(EINVAL, drm, "requires per-process pgtables"); - *value =3D ctx->vm->mm_start; + *value =3D vm->mm_start; return 0; case MSM_PARAM_VA_SIZE: - if (ctx->vm =3D=3D gpu->vm) + if (vm =3D=3D gpu->vm) return UERR(EINVAL, drm, "requires per-process pgtables"); - *value =3D ctx->vm->mm_range; + *value =3D vm->mm_range; return 0; case MSM_PARAM_HIGHEST_BANK_BIT: *value =3D adreno_gpu->ubwc_config.highest_bank_bit; diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index c4b0a38276fa..5cbc2c7b1204 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -218,10 +218,29 @@ static void load_gpu(struct drm_device *dev) mutex_unlock(&init_lock); } =20 +/** + * msm_context_vm - lazily create the context's VM + * + * @dev: the drm device + * @ctx: the context + * + * The VM is lazily created, so that userspace has a chance to opt-in to h= aving + * a userspace managed VM before the VM is created. + * + * Note that this does not return a reference to the VM. Once the VM is c= reated, + * it exists for the lifetime of the context. + */ +struct drm_gpuvm *msm_context_vm(struct drm_device *dev, struct msm_contex= t *ctx) +{ + struct msm_drm_private *priv =3D dev->dev_private; + if (!ctx->vm) + ctx->vm =3D msm_gpu_create_private_vm(priv->gpu, current); + return ctx->vm; +} + static int context_init(struct drm_device *dev, struct drm_file *file) { static atomic_t ident =3D ATOMIC_INIT(0); - struct msm_drm_private *priv =3D dev->dev_private; struct msm_context *ctx; =20 ctx =3D kzalloc(sizeof(*ctx), GFP_KERNEL); @@ -234,7 +253,6 @@ static int context_init(struct drm_device *dev, struct = drm_file *file) kref_init(&ctx->ref); msm_submitqueue_init(dev, ctx); =20 - ctx->vm =3D msm_gpu_create_private_vm(priv->gpu, current); file->driver_priv =3D ctx; =20 ctx->seqno =3D atomic_inc_return(&ident); @@ -413,7 +431,7 @@ static int msm_ioctl_gem_info_iova(struct drm_device *d= ev, * Don't pin the memory here - just get an address so that userspace can * be productive */ - return msm_gem_get_iova(obj, ctx->vm, iova); + return msm_gem_get_iova(obj, msm_context_vm(dev, ctx), iova); } =20 static int msm_ioctl_gem_info_set_iova(struct drm_device *dev, @@ -422,18 +440,19 @@ static int msm_ioctl_gem_info_set_iova(struct drm_dev= ice *dev, { struct msm_drm_private *priv =3D dev->dev_private; struct msm_context *ctx =3D file->driver_priv; + struct drm_gpuvm *vm =3D msm_context_vm(dev, ctx); =20 if (!priv->gpu) return -EINVAL; =20 /* Only supported if per-process address space is supported: */ - if (priv->gpu->vm =3D=3D ctx->vm) + if (priv->gpu->vm =3D=3D vm) return UERR(EOPNOTSUPP, dev, "requires per-process pgtables"); =20 if (should_fail(&fail_gem_iova, obj->size)) return -ENOMEM; =20 - return msm_gem_set_iova(obj, ctx->vm, iova); + return msm_gem_set_iova(obj, vm, iova); } =20 static int msm_ioctl_gem_info_set_metadata(struct drm_gem_object *obj, diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm= _gem_submit.c index d8ff6aeb04ab..068ca618376c 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -63,7 +63,7 @@ static struct msm_gem_submit *submit_create(struct drm_de= vice *dev, =20 kref_init(&submit->ref); submit->dev =3D dev; - submit->vm =3D queue->ctx->vm; + submit->vm =3D msm_context_vm(dev, queue->ctx); submit->gpu =3D gpu; submit->cmd =3D (void *)&submit->bos[nr_bos]; submit->queue =3D queue; diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index a35e1c7bbcdd..29662742a7e1 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -364,7 +364,12 @@ struct msm_context { */ bool closed; =20 - /** @vm: the per-process GPU address-space */ + /** + * @vm: + * + * The per-process GPU address-space. Do not access directly, use + * msm_context_vm(). + */ struct drm_gpuvm *vm; =20 /** @kref: the reference count */ @@ -449,6 +454,8 @@ struct msm_context { atomic64_t ctx_mem; }; =20 +struct drm_gpuvm *msm_context_vm(struct drm_device *dev, struct msm_contex= t *ctx); + /** * msm_gpu_convert_priority - Map userspace priority to ring # and sched p= riority * --=20 2.50.0