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Sun, 29 Jun 2025 07:22:24 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Donald Hunter , Jiri Pirko , Jonathan Corbet , Leon Romanovsky , Chuck Lever , Jeff Layton , NeilBrown , Olga Kornievskaia , Dai Ngo , Tom Talpey , Shuah Khan , , , , , , , Carolina Jubran , Cosmin Ratiu , Mark Bloch Subject: [PATCH net-next v12 4/8] net/mlx5: Add no-op implementation for setting tc-bw on rate objects Date: Sun, 29 Jun 2025 17:21:34 +0300 Message-ID: <20250629142138.361537-5-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250629142138.361537-1-mbloch@nvidia.com> References: <20250629142138.361537-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A104:EE_|BL4PR12MB9483:EE_ X-MS-Office365-Filtering-Correlation-Id: 176a9bb6-de9e-430e-b8ad-08ddb7186a28 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?RRQViPF8Ru4mCWy7xYGuqSh44+NluJQ3AlYiti+vLe5ty0hAKf63nxu2McDD?= =?us-ascii?Q?XjoaX39deWUvO1WIT9NUBnL3Q+i/VUEKazcxnboLq7rS9exjHyTOdTJvuO4x?= =?us-ascii?Q?4T2Hh1mbMMcej8BsDomsQ+ruQPGzBUKnzquwhuIz82QAYYk03bcIVssakCEm?= =?us-ascii?Q?D7YcsK0VMrd9GuHi0yw1Nl3cwtEzCE/bEu2I0o5xdsV/OFxFKAUihivfM2tQ?= =?us-ascii?Q?+fqykj01yMhm3kFp82ikMKvP57yQSnxE3bwnu7KeLqKybaaA1H9edyq5qBxd?= =?us-ascii?Q?xTtVb4mBp6A7ciC0VK4Q8RMff1vHg65faFlfzoVha+n2eZeSuSt9RZg7HpEq?= =?us-ascii?Q?xY70Gu3502h+1RvVtQcKvYCNXJx9IsPlXE0qKz0YvZ8QYmjDGxh9e+GSI/yA?= =?us-ascii?Q?HxpBLoHFZjyrMobOrSuDJIbK0EdtVnLwZ469alKpgFpJerzph6ptDgy9lYox?= =?us-ascii?Q?ACcac85rJyDbljm49bRgLQUbTpMtBewZMFqN5AUf4Hyx4hvRfMIY5JDyKsHV?= =?us-ascii?Q?BdqpTY7QYYSYCz3A4GXOKgyobBrvr+JH4Hde7pX1qyVIgG++zfUk0YCLePbg?= =?us-ascii?Q?BdkauL73rKmLslpnxSYHj6QCdNara+vyVCtJiLXMIrpKSkQjGTh+1iTHw3RO?= =?us-ascii?Q?l1N97ADG3VfDuMYWjo+rj+DOzxD6oVFk2QDqguUsy4IjrAdyopOOBcJUihZq?= =?us-ascii?Q?4d87hqWig6Ni04hj0YulyNBuCB82GS272je1wl5JmMPq9BtdrtBklrFavU6K?= =?us-ascii?Q?Ir12uF8thz91prBm9bpl0Laj7i1kNnRopFOLL/xXwcW6RmAShrJHD+2ouxkH?= =?us-ascii?Q?RK39jChnSaQRDpjqlEYkPBcaNAgkq316Haimb6BwTTevf890/s2SNXIt1MW5?= =?us-ascii?Q?nQNAKuyFPhllSrrahina/s6fNR/QBvamGuGdGeNcJ3IAEcFj3JplfAwCTRqS?= =?us-ascii?Q?DTmQxm9AOpJGdef9wG6IiR01va6rvWxhwcCtYuKEZw5LpKmumkyqfkYj3lMu?= =?us-ascii?Q?+Tu3nvP5fHU1qBvS8VQfCE3p82U2IKWHGSJb6ppJKBGhi7Iadwc+naAyrJUO?= =?us-ascii?Q?5MhVKRCbQJZqNjg6WMwqJlvioVTpisTxWzgF3wlI4l/5FQldhHfUqt2uWX1T?= =?us-ascii?Q?274uBTCJZwmwrNF4+xIUjY3kwhS5oc3y3BOWompnWAtlZBjYV5zeqz8V1/t5?= =?us-ascii?Q?F3oBIwYdaAGYWtjbfdccS9WZ44U5gOCUHyiogDeMVSRgK8CjSS0k3NJmNI6D?= =?us-ascii?Q?f5zznobtnpplI1sf25flBq0FGOB11NfU+hPr2b6bDSiwzWIFuy16aPFk8U6N?= =?us-ascii?Q?m19VYdIdQ8QbGnpFk0zAfveTxCG1a+LEl7SdX1SjJMd+wD6eShxQpJWyYgud?= =?us-ascii?Q?fZfyUM1520C7F2USJIQ9frYg9Fy3OdNrKlXaAU/GGtHDWAJgJPOcCVKP/kzg?= =?us-ascii?Q?ZciPeF4rH+XKrfjTLD2mOrUJnO3puuX94ZcCfM4mVHbdBbyA9vLQz6o0IRMF?= =?us-ascii?Q?gxkAJKj4laH3UULBnZrgibOe1nASEkAC+Fq3?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jun 2025 14:22:44.2822 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 176a9bb6-de9e-430e-b8ad-08ddb7186a28 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9483 Content-Type: text/plain; charset="utf-8" From: Carolina Jubran Introduce `mlx5_esw_devlink_rate_node_tc_bw_set()` and `mlx5_esw_devlink_rate_leaf_tc_bw_set()` with no-op logic. Future patches will add support for setting traffic class bandwidth on rate objects. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Signed-off-by: Mark Bloch --- .../net/ethernet/mellanox/mlx5/core/devlink.c | 2 ++ .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 20 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/esw/qos.h | 8 ++++++++ 3 files changed, 30 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/devlink.c index 42218834183a..3ffa3fbacd16 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c @@ -376,6 +376,8 @@ static const struct devlink_ops mlx5_devlink_ops =3D { .eswitch_encap_mode_get =3D mlx5_devlink_eswitch_encap_mode_get, .rate_leaf_tx_share_set =3D mlx5_esw_devlink_rate_leaf_tx_share_set, .rate_leaf_tx_max_set =3D mlx5_esw_devlink_rate_leaf_tx_max_set, + .rate_leaf_tc_bw_set =3D mlx5_esw_devlink_rate_leaf_tc_bw_set, + .rate_node_tc_bw_set =3D mlx5_esw_devlink_rate_node_tc_bw_set, .rate_node_tx_share_set =3D mlx5_esw_devlink_rate_node_tx_share_set, .rate_node_tx_max_set =3D mlx5_esw_devlink_rate_node_tx_max_set, .rate_node_new =3D mlx5_esw_devlink_rate_node_new, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index b6ae384396b3..ec706e9352e1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -906,6 +906,26 @@ int mlx5_esw_devlink_rate_leaf_tx_max_set(struct devli= nk_rate *rate_leaf, void * return err; } =20 +int mlx5_esw_devlink_rate_leaf_tc_bw_set(struct devlink_rate *rate_leaf, + void *priv, + u32 *tc_bw, + struct netlink_ext_ack *extack) +{ + NL_SET_ERR_MSG_MOD(extack, + "TC bandwidth shares are not supported on leafs"); + return -EOPNOTSUPP; +} + +int mlx5_esw_devlink_rate_node_tc_bw_set(struct devlink_rate *rate_node, + void *priv, + u32 *tc_bw, + struct netlink_ext_ack *extack) +{ + NL_SET_ERR_MSG_MOD(extack, + "TC bandwidth shares are not supported on nodes"); + return -EOPNOTSUPP; +} + int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node= , void *priv, u64 tx_share, struct netlink_ext_ack *extack) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.h index ed40ec8f027e..0a50982b0e27 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h @@ -21,6 +21,14 @@ int mlx5_esw_devlink_rate_leaf_tx_share_set(struct devli= nk_rate *rate_leaf, void u64 tx_share, struct netlink_ext_ack *extack); int mlx5_esw_devlink_rate_leaf_tx_max_set(struct devlink_rate *rate_leaf, = void *priv, u64 tx_max, struct netlink_ext_ack *extack); +int mlx5_esw_devlink_rate_leaf_tc_bw_set(struct devlink_rate *rate_node, + void *priv, + u32 *tc_bw, + struct netlink_ext_ack *extack); +int mlx5_esw_devlink_rate_node_tc_bw_set(struct devlink_rate *rate_node, + void *priv, + u32 *tc_bw, + struct netlink_ext_ack *extack); int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node= , void *priv, u64 tx_share, struct netlink_ext_ack *extack); int mlx5_esw_devlink_rate_node_tx_max_set(struct devlink_rate *rate_node, = void *priv, --=20 2.34.1