From nobody Wed Oct 8 12:40:47 2025 Received: from out-178.mta0.migadu.com (out-178.mta0.migadu.com [91.218.175.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DB6C1FBCA1 for ; Sun, 29 Jun 2025 12:38:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751200736; cv=none; b=icKh8kC/UWo43/vqyCH8UfFW73Usv+mg/OGRrl0QgWKrbSN9rFTIllc9zD0+8eSQ+YhmNNltd2zQjcw72gxVTr3WGsgUgrwLN/co70Mzi+biLzg/xZFwQNtw5FQ53azcZl89zUwVv9QIkbm8pDp5l9yOLEwR2is/DLXiyhfulH4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751200736; c=relaxed/simple; bh=hbCzQra53cQbm9JlGw6eJnRUtAkwWzYlXHL/2fHuU80=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e+jpfBEpUgvvyx8plwnVA5p74+Jm6T5g042HCqhWsDUWbp23De+pbEDCMu0dpu2xy7mjEFFNWCQmfDWuWfcoAAt8bVEWPURznXNN1zgInGgOUO0C2OJY27RH/LxbdC66yrydIYGvRFXHgmb2Bb8wKqwqAGQCyfO/A2z8yYQ31/s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=cknow.org; spf=pass smtp.mailfrom=cknow.org; dkim=pass (2048-bit key) header.d=cknow.org header.i=@cknow.org header.b=XWXOJ4w7; arc=none smtp.client-ip=91.218.175.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=cknow.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cknow.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cknow.org header.i=@cknow.org header.b="XWXOJ4w7" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cknow.org; s=key1; t=1751200732; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nOh9E6KTw/G/RjNvzFhSoJb3dEHhHttr0OlC9cZGWdE=; b=XWXOJ4w7vTU51/rwWezNwWRM5xrPesL/7Q4AjysXh7L9QxsIh2rvyzUrh6LVW6hnpUbBBi yW/CaFNlmWkvetC7TsivrWMGDLdx64jwMoBzyZnu/6DCA+edkbkPG3evgcwqdkO5taFInc PzrdfwJFs28HUBrHw9v+D30Au8ZRU6ELTgg8K6GmQTw1tlnMCHxg5UductyTCiASVoVkV/ 73IeFR0pxVaRMsPPgzxwUYgQfiMolMBugxedkmiTWfMS4CKO9KvFpTu3r2adhXuD11Y0Bl ZcuBQtItYmlhDPbaEnhbUZV7BwpPDqQmHGrHNjgN85NXscIVwtiOvZhbLk1UlA== From: Diederik de Haas To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Dragan Simic , Quentin Schulz , Johan Jonker , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Diederik de Haas Subject: [PATCH v3 02/10] arm64: dts: rockchip: Move dsi address+size-cells from SoC to rk3399 boards Date: Sun, 29 Jun 2025 14:34:43 +0200 Message-ID: <20250629123840.34948-3-didi.debian@cknow.org> In-Reply-To: <20250629123840.34948-1-didi.debian@cknow.org> References: <20250629123840.34948-1-didi.debian@cknow.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The #address-cells and #size-cells properties are not useful on the DSI controller node; they are only useful/required on ports and panel(s). So remove them from the controller node and add them where actually needed on the various rk3399 based boards. This fixes the following DTB validation warnings: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property Signed-off-by: Diederik de Haas --- arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 4 +++- arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 2 ++ arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso | 3 +-- 4 files changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3399-base.dtsi index 9d5f5b083e3c..4dcceb9136b7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi @@ -2071,8 +2071,6 @@ mipi_dsi: dsi@ff960000 { resets =3D <&cru SRST_P_MIPI_DSI0>; reset-names =3D "apb"; rockchip,grf =3D <&grf>; - #address-cells =3D <1>; - #size-cells =3D <0>; status =3D "disabled"; =20 ports { @@ -2112,8 +2110,6 @@ mipi_dsi1: dsi@ff968000 { resets =3D <&cru SRST_P_MIPI_DSI1>; reset-names =3D "apb"; rockchip,grf =3D <&grf>; - #address-cells =3D <1>; - #size-cells =3D <0>; #phy-cells =3D <0>; status =3D "disabled"; =20 diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/ar= m64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index 5e068377a0a2..6aaaf0f7f73f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -627,8 +627,10 @@ &mipi_dphy_rx0 { }; =20 &mipi_dsi { - status =3D "okay"; clock-master; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; =20 ports { mipi_out: port@1 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/a= rm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 909ed14035f7..fe32937a2d16 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -464,6 +464,8 @@ &io_domains { =20 &mipi_dsi { clock-master; + #address-cells =3D <1>; + #size-cells =3D <0>; status =3D "okay"; =20 panel@0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso b/ar= ch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso index b1f4ab22b99c..a26c8e05c13b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-screen.dtso @@ -47,10 +47,9 @@ touch: touchscreen@5d { }; =20 &mipi_dsi { + clock-master; #address-cells =3D <1>; #size-cells =3D <0>; - - clock-master; status =3D "okay"; =20 ports { --=20 2.50.0