From nobody Wed Oct 8 10:56:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8833617A305; Sat, 28 Jun 2025 16:16:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751127372; cv=none; b=TkTwA+Hx+omfHEsvpSQ7c7yTOvOu9/s6UEwvsVTlgbvSfFHNO45Pm4q3KVdMyO0n35LJE6AB1H8yh1EBw7c7+XTDmQK5z4lyBrov9LbV0vXktDRm4gaPeXVw1EmlBM5w6nO/i23GmrMYRPixTg3duoISbrE9dyvvQo8Mx+O7a90= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751127372; c=relaxed/simple; bh=rY5b8vRqdXfrxDOAn0nZ9LkgMlPuDFO9Y76rv/I7xqs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QIy0h4Gz+FKJyguojrfJcbfRPtLSt/SS4M1NjJgUqrxyRWF9VyF2PZyBPSG+ADO3ylwKsc1Ry48yRPBoz2uPU9Xk54hNJF54ZKLcisK4ngV4Liw8hTvITTITw0ZK2Y4MFTRNJyvoxpRsrcU+JfYfOL/A4H+vDKLF9JYiHaiNbz8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sph/C58F; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sph/C58F" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 117DBC4CEF3; Sat, 28 Jun 2025 16:16:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751127372; bh=rY5b8vRqdXfrxDOAn0nZ9LkgMlPuDFO9Y76rv/I7xqs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sph/C58FoShQ8ZeW1fkWGQ3Wd54JKn2/xOnPwbsO1TISvMdye+RGxwAM83zavc558 m4r7MLl038PeGnuaqD4C/bMT96ltpbyOeWijlonfWsb2yFJ1TTYe/plcrnDwcUMLjT V6R+NMidPLidHhTMmfylDp9SjgqcJQjlCYB41IEAl6kli5c7xvbu2a0nz8PpOg4PPV E/sk+Y62g2Ktx8gyC3laCl+htwEPyvLQ1ehkC921PCaxbjlgDYfmmLWr8Zp8SD0lQj OCu1Y8tnKCs4EMdPWJ7iInydjWB/4moQC+4QFyGFN7rSbFVuBnspbDnsRi+UiVh5Pg PXbKb45lcQidg== Received: by wens.tw (Postfix, from userid 1000) id 4A06C5FE36; Sun, 29 Jun 2025 00:16:09 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara , Conor Dooley Subject: [PATCH v3 1/5] dt-bindings: arm: sunxi: Add Xunlong OrangePi 4A board Date: Sun, 29 Jun 2025 00:16:04 +0800 Message-Id: <20250628161608.3072968-2-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250628161608.3072968-1-wens@kernel.org> References: <20250628161608.3072968-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The OrangePi 4A is a typical Raspberry Pi model B sized development board from Xunlong designed around an Allwinner T527 SoC. Add its compatible name to the list of valid ones. Reviewed-by: Andre Przywara Acked-by: Conor Dooley Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentati= on/devicetree/bindings/arm/sunxi.yaml index 7807ea613258..c41d0a0b89e6 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -996,6 +996,11 @@ properties: - const: xunlong,orangepi-3 - const: allwinner,sun50i-h6 =20 + - description: Xunlong OrangePi 4A + items: + - const: xunlong,orangepi-4a + - const: allwinner,sun55i-t527 + - description: Xunlong OrangePi Lite items: - const: xunlong,orangepi-lite --=20 2.39.5 From nobody Wed Oct 8 10:56:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76B563A1B6; Sat, 28 Jun 2025 16:16:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751127372; cv=none; b=uS+zyPa3U1iRo1oTLIlt5knbjttOPsy4JUwQcYYNPAoGPvT/+sOIPbAId/PRMonUP3RcIgZXgPExKu9j9fxW3pm3ChIFQTkdWMpXw0TyVDYHlFlxzKDdO1qqD3tceYafDHA3rQRW5n9S3csZiGtI/9au2aEfrMRw42pNNe0X0/4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751127372; c=relaxed/simple; bh=jrBPbSLIcJ68lougjjnj8b0BgzaQ21Z0SDkMwk7s0Io=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Cd+mnZTkNfAExk21H24ei1JoPv6A2UHXZA+yOsAFNSzP67QJTn3LNySjxniBP7tQXbUnJ/kz5TKYl5jjCKLCpboOiQWW4MrVpNX8N50vOywHNgBg1VCBCuwhicSbCpOITNktK6kWZciRN+kBtCQ1ksQ6okap5nlMlqaM5hAlicE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D8a0Xc1u; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D8a0Xc1u" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EA110C4CEEA; Sat, 28 Jun 2025 16:16:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751127372; bh=jrBPbSLIcJ68lougjjnj8b0BgzaQ21Z0SDkMwk7s0Io=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D8a0Xc1uHZkCDdxI7EOvYTcnUNpVv8fycGtNwRoe07Qh1i64dMZfab1EfBuqHRCeC mOTaGzHJAvXcUObGpl+s2/hOHNwQ65Gbl9fMVV6KDaYo0x1WEU5txYGutUqeVJMchg qSS4SjoDHYgPZFrUC/9BhE69hMX8gbM9Pj04npGYF1fVXGookhllk1ojNOcjc81ldU 4YWK3TWvwGPql8OeCYFUbJUBebPqLkM8uaDD3Jj138n1IKlgj/QNSty7+gxsql7m6X QEIl7Cr0IwwQmF2kC3M8P1YoBKPM2Vo4WEjl08us0yyzPd6fpPQrwVtK2lmfWTCKKC upzGsEFvZq9lw== Received: by wens.tw (Postfix, from userid 1000) id 3BB755FA91; Sun, 29 Jun 2025 00:16:09 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH v3 2/5] arm64: dts: allwinner: a523: Move mmc nodes to correct position Date: Sun, 29 Jun 2025 00:16:05 +0800 Message-Id: <20250628161608.3072968-3-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250628161608.3072968-1-wens@kernel.org> References: <20250628161608.3072968-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai When the mmc nodes were added to the dtsi file, they were inserted in the incorrect position. Move them to the correct place. Reviewed-by: Andre Przywara Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 126 +++++++++--------- 1 file changed, 63 insertions(+), 63 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 51cd148f4227..490f596cad6c 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -181,69 +181,6 @@ ccu: clock-controller@2001000 { #reset-cells =3D <1>; }; =20 - mmc0: mmc@4020000 { - compatible =3D "allwinner,sun55i-a523-mmc", - "allwinner,sun20i-d1-mmc"; - reg =3D <0x04020000 0x1000>; - clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names =3D "ahb", "mmc"; - resets =3D <&ccu RST_BUS_MMC0>; - reset-names =3D "ahb"; - interrupts =3D ; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mmc0_pins>; - status =3D "disabled"; - - max-frequency =3D <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - cap-sdio-irq; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - mmc1: mmc@4021000 { - compatible =3D "allwinner,sun55i-a523-mmc", - "allwinner,sun20i-d1-mmc"; - reg =3D <0x04021000 0x1000>; - clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names =3D "ahb", "mmc"; - resets =3D <&ccu RST_BUS_MMC1>; - reset-names =3D "ahb"; - interrupts =3D ; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mmc1_pins>; - status =3D "disabled"; - - max-frequency =3D <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - cap-sdio-irq; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - mmc2: mmc@4022000 { - compatible =3D "allwinner,sun55i-a523-mmc", - "allwinner,sun20i-d1-mmc"; - reg =3D <0x04022000 0x1000>; - clocks =3D <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names =3D "ahb", "mmc"; - resets =3D <&ccu RST_BUS_MMC2>; - reset-names =3D "ahb"; - interrupts =3D ; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mmc2_pins>; - status =3D "disabled"; - - max-frequency =3D <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - cap-sdio-irq; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - wdt: watchdog@2050000 { compatible =3D "allwinner,sun55i-a523-wdt"; reg =3D <0x2050000 0x20>; @@ -449,6 +386,69 @@ its: msi-controller@3440000 { }; }; =20 + mmc0: mmc@4020000 { + compatible =3D "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg =3D <0x04020000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC0>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc0_pins>; + status =3D "disabled"; + + max-frequency =3D <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc1: mmc@4021000 { + compatible =3D "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg =3D <0x04021000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC1>; + reset-names =3D "ahb"; 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charset="utf-8" From: Chen-Yu Tsai Nodes are supposed to be sorted by address, or if no addresses apply, by node name. The rgmii0 pins are out of order, possibly due to multiple patches adding pin mux settings conflicting. Move the rgmii0 pins to the correct location. Reviewed-by: Andre Przywara Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 490f596cad6c..4839411e51cf 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -126,16 +126,6 @@ pio: pinctrl@2000000 { interrupt-controller; #interrupt-cells =3D <3>; =20 - rgmii0_pins: rgmii0-pins { - pins =3D "PH0", "PH1", "PH2", "PH3", "PH4", - "PH5", "PH6", "PH7", "PH9", "PH10", - "PH14", "PH15", "PH16", "PH17", "PH18"; - allwinner,pinmux =3D <5>; - function =3D "gmac0"; - drive-strength =3D <40>; - bias-disable; - }; - mmc0_pins: mmc0-pins { pins =3D "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; allwinner,pinmux =3D <2>; @@ -163,6 +153,16 @@ mmc2_pins: mmc2-pins { bias-pull-up; }; =20 + rgmii0_pins: rgmii0-pins { + pins =3D "PH0", "PH1", "PH2", "PH3", "PH4", + "PH5", "PH6", "PH7", "PH9", "PH10", + "PH14", "PH15", "PH16", "PH17", "PH18"; + allwinner,pinmux =3D <5>; + function =3D "gmac0"; + drive-strength =3D <40>; + bias-disable; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; allwinner,pinmux =3D <2>; --=20 2.39.5 From nobody Wed Oct 8 10:56:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C6E31DFCB; Sat, 28 Jun 2025 16:16:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751127372; cv=none; b=IRHLH1Fd8mEz3Om2qcxh8OfFvbI/U+BoIhsvEhJSu2SgbqRzlDH76xH4Du+oGT+IEb/i6pVnIcKoghcTjO7wrWIYDlf2U7sfLAon5+LLxgUcLxIVAEffQyVv1Rj1Qr3z9cxMG6rsFQk/SrognXbxryKWe4a+S+gnJTCXLK2bJdQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751127372; c=relaxed/simple; bh=6oH0nwNv26PaXawo3Ih/MoBWIzEnorKGZ6UPBCiGcIc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tq8e8zcPezYVt9SxV6rpJ02Nk3QnB6A0EiGqIbZq/Wv5xDbdunHlbvsur2zM5YwOc3ErcodewiV714iUpIi7kSjDi9bW08CemSIfGGrNkwBEacx+2jRITVGf4SBeNAo8/qgBBGOjinjDlQ3G8Zx1uLgvj8nmIMeQgtMrb9ylsCU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OeW0cAYp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OeW0cAYp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0FAB0C4CEEF; Sat, 28 Jun 2025 16:16:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751127372; bh=6oH0nwNv26PaXawo3Ih/MoBWIzEnorKGZ6UPBCiGcIc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OeW0cAYp2YSdtnU+vLp1dK5SikFM/cCHgwGeOi81Hx6aTejK83MONtlQls0QPiO27 cg52qSiPBRj6dQsB4UqITunAIQo5e6Y5w8pHYmnjAZvX18pRiH/82c2Wwzw6ET8kxZ cV6ON0cWRyNL/XWyRl49TQkhQ88q2oF5uOSGvAC9NpNly+m7F6B5403jDqDPxD0sPn 04CstsYDJ0MG8u2KomTL8kQQC3yY2qsKLS0CvXvzUgkdKx83gCJvbgBXpx0/egAp/M rzqif3hjfcIbSA0yMSEs+XMpVeuWPisvZqTcp4Xat1ZpIJwN1Cjo9VBp/7UMAfvbIJ sft+V+9yw5hUQ== Received: by wens.tw (Postfix, from userid 1000) id 5DA655FE60; Sun, 29 Jun 2025 00:16:09 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH v3 4/5] arm64: dts: allwinner: a523: Add UART1 pins Date: Sun, 29 Jun 2025 00:16:07 +0800 Message-Id: <20250628161608.3072968-5-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250628161608.3072968-1-wens@kernel.org> References: <20250628161608.3072968-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai UART1 is normally used to connect to the Bluetooth side of a Broadcom WiFi+BT combo chip. The connection uses 4 pins. Add pinmux nodes for UART1, one for the RX/TX pins, and one for the RTS/CTS pins. Reviewed-by: Andre Przywara Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 4839411e51cf..cf0bc39aab04 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -168,6 +168,20 @@ uart0_pb_pins: uart0-pb-pins { allwinner,pinmux =3D <2>; function =3D "uart0"; }; + + /omit-if-no-ref/ + uart1_pins: uart1-pins { + pins =3D "PG6", "PG7"; + function =3D "uart1"; + allwinner,pinmux =3D <2>; + }; + + /omit-if-no-ref/ + uart1_rts_cts_pins: uart1-rts-cts-pins { + pins =3D "PG8", "PG9"; + function =3D "uart1"; + allwinner,pinmux =3D <2>; + }; }; =20 ccu: clock-controller@2001000 { --=20 2.39.5 From nobody Wed Oct 8 10:56:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DCD1258CD8; Sat, 28 Jun 2025 16:16:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751127375; cv=none; b=IkYBMkHurX6ei3kw8C7BO7jIXFae07cn+qc7QBmooeurs8olMqbyl/qN2CXOm02q90WS8JuBKw0kvokmiebjkqR87/VQ9QIqTinxXP2bZGh3NpRpP92pFjPzkdAvRC44k9elklbNwa44GQNQDA1o565Sh0TRYU3ii2+mY7GUneI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751127375; c=relaxed/simple; bh=P6QUSH7AUOQT3f+W/JdxQ7eOAig1FZmcEVsaD2TM21w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jazM3/kj/f5fJBwr7jwOvZJqpnkxoinLTaaFPLVJhh+5YYGNQ+AmLD50wNQZWjpQcbjKIKkzpacykmpDmHTPWHzcylZoYrpHgnNAaRLkzDCXNEcSE9EpAoOIrudDDkV0gqQoziDA5lQh1uNqZtIjgKCjO7TRkftaU1WYPXfIDwY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=etsBo4vY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="etsBo4vY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DAD05C4CEEF; Sat, 28 Jun 2025 16:16:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751127375; bh=P6QUSH7AUOQT3f+W/JdxQ7eOAig1FZmcEVsaD2TM21w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=etsBo4vY2Dg16GR8BdSxuqAPzZAsW7F8wNof0LkpPjKbunX/sp8tIaMyTExmBKaaM FjNuULAvPxLC8miVUiVTUbBsP+3P4YQt7qslZ/HAGp42yLz+gQyphMFfyhRETjzgTT AssKrYMH/4H1ssp85h4ot5O7z2huq3f5WkDe2gzWN8tAmpDg0krxx86Xm5zLRRPIWL yeorLr7y02B+VeqnomoH9KgeRsYsDpaYhoEuCCy6coFhKO4zhLyufIlQfmlVKjill0 zVY3XAnnUo+0VhmWOR/AbkzyCGHSIex7qnj7eI/Zd11w6/QGnVM/mrt6GIvChc44mt rzco0vuA1O0RA== Received: by wens.tw (Postfix, from userid 1000) id 61C755FF71; Sun, 29 Jun 2025 00:16:09 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH v3 5/5] arm64: dts: allwinner: t527: Add OrangePi 4A board Date: Sun, 29 Jun 2025 00:16:08 +0800 Message-Id: <20250628161608.3072968-6-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250628161608.3072968-1-wens@kernel.org> References: <20250628161608.3072968-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The OrangePi 4A is a typical Raspberry Pi model B sized development board from Xunlong designed around an Allwinner T527 SoC. The board has the following features: - Allwinner T527 SoC - AXP717B + AXP323 PMICs - Up to 4GB LPDDR4 DRAM - micro SD slot - optional eMMC module - M.2 slot for PCIe 2.0 x1 - 16 MB SPI-NOR flash - 4x USB 2.0 type-A ports (one can be used in gadget mode) - 1x Gigabit ethernet w/ Motorcomm PHY (through yet to be supported GMAC200) - 3.5mm audio jack via internal audio codec - HDMI 2.0 output - eDP, MIPI CSI (2-lane and 4-lane) and MIPI DSI (4-lane) connectors - USB type-C port purely for power - AP6256 (Broadcom BCM4345) WiFi 5.0 + BT 5.0 - unsoldered headers for ADC and an additional USB 2.0 host port - 40-pin GPIO header Add a device tree for it, enabling all peripherals currently supported. Signed-off-by: Chen-Yu Tsai Reviewed-by: Andre Przywara --- Changes since v2: - Actually include cpusldo regulator name change and axp323 aldo1/dldo1 comments - Fix indentation of comment in usb_otg block Changes since v1: - Fixed regulator names for bldo3 and bldo4 - Dropped labels for aldo1, bldo3, and bldo4, which are not really used - Added voltage constraints to aldo2, based on specifications from schematic - Appended "-usb-0v9" to cpusldo's regulator name - Added comments to explain how axp323 aldo1 and dldo1 are tied together --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 385 ++++++++++++++++++ 2 files changed, 386 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.d= ts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/a= llwinner/Makefile index 773cc02a13d0..780aeba0f3a4 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -57,3 +57,4 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx= -sp.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-a527-cubie-a5e.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-h728-x96qpro+.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-t527-avaota-a1.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-t527-orangepi-4a.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts new file mode 100644 index 000000000000..5f97505ec8f9 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -0,0 +1,385 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2025 Chen-Yu Tsai + */ + +/dts-v1/; + +#include "sun55i-a523.dtsi" + +#include +#include + +/ { + model =3D "OrangePi 4A"; + compatible =3D "xunlong,orangepi-4a", "allwinner,sun55i-t527"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + ext_osc32k: ext-osc32k-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <32768>; + clock-output-names =3D "ext_osc32k"; + }; + + leds { + compatible =3D "gpio-leds"; + + /* PWM capable pin, but PWM isn't supported yet. */ + led { + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + }; + }; + + wifi_pwrseq: pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&r_pio 1 1 GPIO_ACTIVE_LOW>; /* PM1 */ + clocks =3D <&rtc CLK_OSC32K_FANOUT>; + clock-names =3D "ext_clock"; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "otg-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_vcc5v>; + gpio =3D <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + enable-active-high; + }; + + reg_pcie_vcc3v3: regulator-pcie-vcc3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-pcie-3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <®_vcc5v>; + gpio =3D <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + enable-active-high; + }; + + reg_usb_vbus: regulator-usb-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_vcc5v>; + gpio =3D <&r_pio 0 12 GPIO_ACTIVE_HIGH>; /* PL12 */ + enable-active-high; + }; + + reg_vcc5v: regulator-vcc5v { + /* board wide 5V supply from USB type-C port */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; +}; + +&ehci0 { + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&mmc0 { + vmmc-supply =3D <®_cldo3>; + cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ + bus-width =3D <4>; + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_dldo1_323>; + vqmmc-supply =3D <®_bldo1>; + status =3D "okay"; + + brcmf: wifi@1 { + compatible =3D "brcm,bcm4329-fmac"; + reg =3D <1>; + interrupt-parent =3D <&r_pio>; + interrupts =3D <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ + interrupt-names =3D "host-wake"; + }; +}; + +&mmc2 { + bus-width =3D <8>; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + vmmc-supply =3D <®_cldo3>; + vqmmc-supply =3D <®_cldo1>; + status =3D "okay"; +}; + +&ohci0 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&pio { + vcc-pb-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pc-supply =3D <®_cldo1>; + vcc-pd-supply =3D <®_cldo3>; + vcc-pe-supply =3D <®_aldo2>; + vcc-pf-supply =3D <®_cldo3>; /* VCC-IO for 3.3v; VCC-MCSI for 1.8v */ + vcc-pg-supply =3D <®_bldo1>; + vcc-ph-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pi-supply =3D <®_cldo3>; + vcc-pj-supply =3D <®_cldo1>; + vcc-pk-supply =3D <®_cldo1>; +}; + +&r_i2c0 { + status =3D "okay"; + + axp717: pmic@35 { + compatible =3D "x-powers,axp717"; + reg =3D <0x35>; + interrupt-controller; + #interrupt-cells =3D <1>; + interrupts-extended =3D <&nmi_intc 0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + vin4-supply =3D <®_vcc5v>; + aldoin-supply =3D <®_vcc5v>; + bldoin-supply =3D <®_vcc5v>; + cldoin-supply =3D <®_vcc5v>; + + regulators { + /* Supplies the "little" cluster (1.4 GHz cores) */ + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vdd-cpul"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt =3D <920000>; + regulator-max-microvolt =3D <920000>; + regulator-name =3D "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <1160000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vcc-dram"; + }; + + reg_dcdc4: dcdc4 { + /* feeds 3.3V pin on GPIO header */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vdd-io"; + }; + + aldo1 { + /* not actually connected */ + regulator-name =3D "avdd-csi"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pe"; + }; + + reg_aldo3: aldo3 { + /* supplies the I2C pins for this PMIC */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-pl-usb"; + }; + + reg_aldo4: aldo4 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pll-dxco-avcc"; + }; + + reg_bldo1: bldo1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pg-wifi"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pm-lpddr"; + }; + + bldo3 { + /* not actually connected */ + regulator-name =3D "afvcc-csi"; + }; + + bldo4 { + /* not actually connected */ + regulator-name =3D "dvdd-csi"; + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-cvp-pc-lvds-mcsi-pk-efuse-pcie-edp-1v8"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3-csi"; + }; + + reg_cldo3: cldo3 { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-io-mmc-nand-pd-pi-usb"; + }; + + reg_cldo4: cldo4 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-3v3-phy1-lcd"; + }; + + reg_cpusldo: cpusldo { + /* supplies the management core */ + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd-cpus-usb-0v9"; + }; + }; + }; + + axp323: pmic@36 { + compatible =3D "x-powers,axp323"; + reg =3D <0x36>; + #interrupt-cells =3D <1>; + interrupt-controller; + status =3D "okay"; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + + regulators { + reg_aldo1_323: aldo1 { + /* less capable and shares load with dldo1 */ + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-wifi"; + }; + + reg_dldo1_323: dldo1 { + /* more capable and shares load with aldo1 */ + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-wifi2"; + }; + + /* Supplies the "big" cluster (1.8 GHz cores) */ + reg_dcdc1_323: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1150000>; + regulator-name =3D "vdd-cpub"; + }; + + /* DCDC2 is polyphased with DCDC1 */ + + /* Some RISC-V management core related voltage */ + reg_dcdc3_323: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd-dnr"; + }; + }; + }; +}; + +&r_pio { +/* + * Specifying the supply would create a circular dependency. + * + * vcc-pl-supply =3D <®_aldo3>; + */ + vcc-pm-supply =3D <®_bldo2>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pb_pins>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "brcm,bcm4345c5"; + clocks =3D <&rtc CLK_OSC32K_FANOUT>; + clock-names =3D "lpo"; + vbat-supply =3D <®_aldo1_323>; + vddio-supply =3D <®_bldo1>; + device-wakeup-gpios =3D <&r_pio 1 3 GPIO_ACTIVE_HIGH>; /* PM3 */ + host-wakeup-gpios =3D <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ + shutdown-gpios =3D <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ + }; +}; + +&usb_otg { + /* + * The OTG controller is connected to one of the type-A ports. + * There is a regulator, controlled by a GPIO, to provide VBUS power + * to the port, and a VBUSDET GPIO, to detect externally provided + * power. But without ID or CC pins there is no real way to do a + * runtime role detection. + */ + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usbphy { + usb0_vbus-supply =3D <®_otg_vbus>; + usb0_vbus_det-gpios =3D <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ + usb1_vbus-supply =3D <®_usb_vbus>; + status =3D "okay"; +}; --=20 2.39.5