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charset="utf-8" From: Thierry Bultel New port types cannot be added in serial_core.h, which is shared with userspace. In order to support new port types, the coming new ones will have BIT(7) set in the id value, and in this case, uartport->type is set to PORT_GENERIC. This commit therefore changes all the places where the port type is read, by not relying on uartport->type but on the private value stored in struct sci_port. Signed-off-by: Thierry Bultel Signed-off-by: Lad Prabhakar Reviewed-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- v12-> v13: - Fixed checkpatch warnings. --- drivers/tty/serial/sh-sci-common.h | 3 + drivers/tty/serial/sh-sci.c | 161 ++++++++++++++++------------- 2 files changed, 93 insertions(+), 71 deletions(-) diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index bd9d9cfac1c8..fcddf66780c9 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -142,6 +142,9 @@ struct sci_port { int rx_fifo_timeout; u16 hscif_tot; =20 + u8 type; + u8 regtype; + const struct sci_port_ops *ops; =20 bool has_rtscts; diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 5c4283ce542d..26536ff2eda1 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -75,6 +75,8 @@ =20 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS =20 +#define SCI_PUBLIC_PORT_ID(port) (((port) & BIT(7)) ? PORT_GENERIC : (port= )) + static struct sci_port sci_ports[SCI_NPORTS]; static unsigned long sci_ports_in_use; static struct uart_driver sci_uart_driver; @@ -580,7 +582,7 @@ static void sci_start_tx(struct uart_port *port) unsigned short ctrl; =20 #ifdef CONFIG_SERIAL_SH_SCI_DMA - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB) { + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB) { u16 new, scr =3D sci_serial_in(port, SCSCR); if (s->chan_tx) new =3D scr | SCSCR_TDRQE; @@ -592,7 +594,7 @@ static void sci_start_tx(struct uart_port *port) =20 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) && dma_submit_error(s->cookie_tx)) { - if (s->cfg->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) + if (s->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) /* Switch irq from SCIF to DMA */ disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); =20 @@ -601,8 +603,8 @@ static void sci_start_tx(struct uart_port *port) } #endif =20 - if (!s->chan_tx || s->cfg->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE || - port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB) { + if (!s->chan_tx || s->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE || + s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB) { /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ ctrl =3D sci_serial_in(port, SCSCR); =20 @@ -611,7 +613,7 @@ static void sci_start_tx(struct uart_port *port) * (transmit interrupt enable) or in the same instruction to start * the transmit process. */ - if (port->type =3D=3D PORT_SCI) + if (s->type =3D=3D PORT_SCI) ctrl |=3D SCSCR_TE; =20 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE); @@ -620,12 +622,13 @@ static void sci_start_tx(struct uart_port *port) =20 static void sci_stop_tx(struct uart_port *port) { + struct sci_port *s =3D to_sci_port(port); unsigned short ctrl; =20 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ ctrl =3D sci_serial_in(port, SCSCR); =20 - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB) + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB) ctrl &=3D ~SCSCR_TDRQE; =20 ctrl &=3D ~SCSCR_TIE; @@ -633,21 +636,22 @@ static void sci_stop_tx(struct uart_port *port) sci_serial_out(port, SCSCR, ctrl); =20 #ifdef CONFIG_SERIAL_SH_SCI_DMA - if (to_sci_port(port)->chan_tx && - !dma_submit_error(to_sci_port(port)->cookie_tx)) { - dmaengine_terminate_async(to_sci_port(port)->chan_tx); - to_sci_port(port)->cookie_tx =3D -EINVAL; + if (s->chan_tx && + !dma_submit_error(s->cookie_tx)) { + dmaengine_terminate_async(s->chan_tx); + s->cookie_tx =3D -EINVAL; } #endif } =20 static void sci_start_rx(struct uart_port *port) { + struct sci_port *s =3D to_sci_port(port); unsigned short ctrl; =20 ctrl =3D sci_serial_in(port, SCSCR) | port_rx_irq_mask(port); =20 - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB) + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB) ctrl &=3D ~SCSCR_RDRQE; =20 sci_serial_out(port, SCSCR, ctrl); @@ -655,11 +659,12 @@ static void sci_start_rx(struct uart_port *port) =20 static void sci_stop_rx(struct uart_port *port) { + struct sci_port *s =3D to_sci_port(port); unsigned short ctrl; =20 ctrl =3D sci_serial_in(port, SCSCR); =20 - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB) + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB) ctrl &=3D ~SCSCR_RDRQE; =20 ctrl &=3D ~port_rx_irq_mask(port); @@ -669,10 +674,12 @@ static void sci_stop_rx(struct uart_port *port) =20 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) { - if (port->type =3D=3D PORT_SCI) { + struct sci_port *s =3D to_sci_port(port); + + if (s->type =3D=3D PORT_SCI) { /* Just store the mask */ sci_serial_out(port, SCxSR, mask); - } else if (to_sci_port(port)->params->overrun_mask =3D=3D SCIFA_ORER) { + } else if (s->params->overrun_mask =3D=3D SCIFA_ORER) { /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ /* Only clear the status bits we want to clear */ sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask); @@ -742,13 +749,13 @@ static void sci_init_pins(struct uart_port *port, uns= igned int cflag) return; } =20 - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB) { + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB) { u16 data =3D sci_serial_in(port, SCPDR); u16 ctrl =3D sci_serial_in(port, SCPCR); =20 /* Enable RXD and TXD pin functions */ ctrl &=3D ~(SCPCR_RXDC | SCPCR_TXDC); - if (to_sci_port(port)->has_rtscts) { + if (s->has_rtscts) { /* RTS# is output, active low, unless autorts */ if (!(port->mctrl & TIOCM_RTS)) { ctrl |=3D SCPCR_RTSC; @@ -765,7 +772,7 @@ static void sci_init_pins(struct uart_port *port, unsig= ned int cflag) } sci_serial_out(port, SCPDR, data); sci_serial_out(port, SCPCR, ctrl); - } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype !=3D SCIx_RZ= V2H_SCIF_REGTYPE) { + } else if (sci_getreg(port, SCSPTR)->size && s->regtype !=3D SCIx_RZV2H_S= CIF_REGTYPE) { u16 status =3D sci_serial_in(port, SCSPTR); =20 /* RTS# is always output; and active low, unless autorts */ @@ -852,8 +859,8 @@ static void sci_transmit_chars(struct uart_port *port) c =3D port->x_char; port->x_char =3D 0; } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { - if (port->type =3D=3D PORT_SCI && - kfifo_is_empty(&tport->xmit_fifo)) { + if (s->type =3D=3D PORT_SCI && + kfifo_is_empty(&tport->xmit_fifo)) { ctrl =3D sci_serial_in(port, SCSCR); ctrl &=3D ~SCSCR_TE; sci_serial_out(port, SCSCR, ctrl); @@ -873,7 +880,7 @@ static void sci_transmit_chars(struct uart_port *port) if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) uart_write_wakeup(port); if (kfifo_is_empty(&tport->xmit_fifo)) { - if (port->type =3D=3D PORT_SCI) { + if (s->type =3D=3D PORT_SCI) { ctrl =3D sci_serial_in(port, SCSCR); ctrl &=3D ~SCSCR_TIE; ctrl |=3D SCSCR_TEIE; @@ -904,7 +911,7 @@ static void sci_receive_chars(struct uart_port *port) if (count =3D=3D 0) break; =20 - if (port->type =3D=3D PORT_SCI) { + if (s->type =3D=3D PORT_SCI) { char c =3D sci_serial_in(port, SCxRDR); if (uart_handle_sysrq_char(port, c)) count =3D 0; @@ -914,8 +921,8 @@ static void sci_receive_chars(struct uart_port *port) for (i =3D 0; i < count; i++) { char c; =20 - if (port->type =3D=3D PORT_SCIF || - port->type =3D=3D PORT_HSCIF) { + if (s->type =3D=3D PORT_SCIF || + s->type =3D=3D PORT_HSCIF) { status =3D sci_serial_in(port, SCxSR); c =3D sci_serial_in(port, SCxRDR); } else { @@ -1052,6 +1059,7 @@ static int sci_handle_breaks(struct uart_port *port) =20 static int scif_set_rtrg(struct uart_port *port, int rx_trig) { + struct sci_port *s =3D to_sci_port(port); unsigned int bits; =20 if (rx_trig >=3D port->fifosize) @@ -1065,7 +1073,7 @@ static int scif_set_rtrg(struct uart_port *port, int = rx_trig) return rx_trig; } =20 - switch (port->type) { + switch (s->type) { case PORT_SCIF: if (rx_trig < 4) { bits =3D 0; @@ -1150,7 +1158,7 @@ static ssize_t rx_fifo_trigger_store(struct device *d= ev, return ret; =20 sci->rx_trigger =3D sci->ops->set_rtrg(port, r); - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB) + if (sci->type =3D=3D PORT_SCIFA || sci->type =3D=3D PORT_SCIFB) sci->ops->set_rtrg(port, 1); =20 return count; @@ -1166,7 +1174,7 @@ static ssize_t rx_fifo_timeout_show(struct device *de= v, struct sci_port *sci =3D to_sci_port(port); int v; =20 - if (port->type =3D=3D PORT_HSCIF) + if (sci->type =3D=3D PORT_HSCIF) v =3D sci->hscif_tot >> HSSCR_TOT_SHIFT; else v =3D sci->rx_fifo_timeout; @@ -1188,7 +1196,7 @@ static ssize_t rx_fifo_timeout_store(struct device *d= ev, if (ret) return ret; =20 - if (port->type =3D=3D PORT_HSCIF) { + if (sci->type =3D=3D PORT_HSCIF) { if (r < 0 || r > 3) return -EINVAL; sci->hscif_tot =3D r << HSSCR_TOT_SHIFT; @@ -1229,11 +1237,11 @@ static void sci_dma_tx_complete(void *arg) schedule_work(&s->work_tx); } else { s->cookie_tx =3D -EINVAL; - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB || - s->cfg->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) { + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB || + s->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) { u16 ctrl =3D sci_serial_in(port, SCSCR); sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE); - if (s->cfg->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) { + if (s->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) { /* Switch irq from DMA to SCIF */ dmaengine_pause(s->chan_tx_saved); enable_irq(s->irqs[SCIx_TXI_IRQ]); @@ -1315,10 +1323,10 @@ static void sci_dma_rx_reenable_irq(struct sci_port= *s) =20 /* Direct new serial port interrupts back to CPU */ scr =3D sci_serial_in(port, SCSCR); - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB || - s->cfg->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) { + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB || + s->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) { enable_irq(s->irqs[SCIx_RXI_IRQ]); - if (s->cfg->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) + if (s->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) s->ops->set_rtrg(port, s->rx_trigger); else scr &=3D ~SCSCR_RDRQE; @@ -1558,8 +1566,8 @@ static enum hrtimer_restart sci_dma_rx_timer_fn(struc= t hrtimer *t) tty_flip_buffer_push(&port->state->port); } =20 - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB || - s->cfg->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB || + s->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) sci_dma_rx_submit(s, true); =20 sci_dma_rx_reenable_irq(s); @@ -1682,8 +1690,8 @@ static void sci_request_dma(struct uart_port *port) =20 s->chan_rx_saved =3D s->chan_rx =3D chan; =20 - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB || - s->cfg->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB || + s->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) sci_dma_rx_submit(s, false); } } @@ -1753,10 +1761,10 @@ static irqreturn_t sci_rx_interrupt(int irq, void *= ptr) u16 ssr =3D sci_serial_in(port, SCxSR); =20 /* Disable future Rx interrupts */ - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB || - s->cfg->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) { + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB || + s->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) { disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); - if (s->cfg->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) { + if (s->regtype =3D=3D SCIx_RZ_SCIFA_REGTYPE) { s->ops->set_rtrg(port, 1); scr |=3D SCSCR_RIE; } else { @@ -1820,7 +1828,7 @@ static irqreturn_t sci_tx_end_interrupt(int irq, void= *ptr) unsigned long flags; u32 ctrl; =20 - if (port->type !=3D PORT_SCI) + if (s->type !=3D PORT_SCI) return sci_tx_interrupt(irq, ptr); =20 uart_port_lock_irqsave(port, &flags); @@ -1867,7 +1875,7 @@ static irqreturn_t sci_er_interrupt(int irq, void *pt= r) } =20 /* Handle errors */ - if (port->type =3D=3D PORT_SCI) { + if (s->type =3D=3D PORT_SCI) { if (sci_handle_errors(port)) { /* discard character in rx buffer */ sci_serial_in(port, SCxSR); @@ -2091,7 +2099,9 @@ static unsigned int sci_tx_empty(struct uart_port *po= rt) =20 static void sci_set_rts(struct uart_port *port, bool state) { - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB) { + struct sci_port *s =3D to_sci_port(port); + + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB) { u16 data =3D sci_serial_in(port, SCPDR); =20 /* Active low */ @@ -2118,7 +2128,9 @@ static void sci_set_rts(struct uart_port *port, bool = state) =20 static bool sci_get_cts(struct uart_port *port) { - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB) { + struct sci_port *s =3D to_sci_port(port); + + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB) { /* Active low */ return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD); } else if (sci_getreg(port, SCSPTR)->size) { @@ -2164,21 +2176,21 @@ static void sci_set_mctrl(struct uart_port *port, u= nsigned int mctrl) =20 if (!(mctrl & TIOCM_RTS)) { /* Disable Auto RTS */ - if (s->cfg->regtype !=3D SCIx_RZV2H_SCIF_REGTYPE) + if (s->regtype !=3D SCIx_RZV2H_SCIF_REGTYPE) sci_serial_out(port, SCFCR, sci_serial_in(port, SCFCR) & ~SCFCR_MCE); =20 /* Clear RTS */ sci_set_rts(port, 0); } else if (s->autorts) { - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB) { + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB) { /* Enable RTS# pin function */ sci_serial_out(port, SCPCR, sci_serial_in(port, SCPCR) & ~SCPCR_RTSC); } =20 /* Enable Auto RTS */ - if (s->cfg->regtype !=3D SCIx_RZV2H_SCIF_REGTYPE) + if (s->regtype !=3D SCIx_RZV2H_SCIF_REGTYPE) sci_serial_out(port, SCFCR, sci_serial_in(port, SCFCR) | SCFCR_MCE); } else { @@ -2315,7 +2327,7 @@ static int sci_sck_calc(struct sci_port *s, unsigned = int bps, int err, min_err =3D INT_MAX; unsigned int sr; =20 - if (s->port.type !=3D PORT_HSCIF) + if (s->type !=3D PORT_HSCIF) freq *=3D 2; =20 for_each_sr(sr, s) { @@ -2342,7 +2354,7 @@ static int sci_brg_calc(struct sci_port *s, unsigned = int bps, int err, min_err =3D INT_MAX; unsigned int sr, dl; =20 - if (s->port.type !=3D PORT_HSCIF) + if (s->type !=3D PORT_HSCIF) freq *=3D 2; =20 for_each_sr(sr, s) { @@ -2375,7 +2387,7 @@ static int sci_scbrr_calc(struct sci_port *s, unsigne= d int bps, unsigned int sr, br, prediv, scrate, c; int err, min_err =3D INT_MAX; =20 - if (s->port.type !=3D PORT_HSCIF) + if (s->type !=3D PORT_HSCIF) freq *=3D 2; =20 /* @@ -2460,8 +2472,8 @@ static void sci_reset(struct uart_port *port) s->ops->set_rtrg(port, 1); timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); } else { - if (port->type =3D=3D PORT_SCIFA || - port->type =3D=3D PORT_SCIFB) + if (s->type =3D=3D PORT_SCIFA || + s->type =3D=3D PORT_SCIFB) s->ops->set_rtrg(port, 1); else s->ops->set_rtrg(port, s->rx_trigger); @@ -2521,8 +2533,8 @@ static void sci_set_termios(struct uart_port *port, s= truct ktermios *termios, */ =20 /* Optional Undivided External Clock */ - if (s->clk_rates[SCI_SCK] && port->type !=3D PORT_SCIFA && - port->type !=3D PORT_SCIFB) { + if (s->clk_rates[SCI_SCK] && s->type !=3D PORT_SCIFA && + s->type !=3D PORT_SCIFB) { err =3D sci_sck_calc(s, baud, &srr1); if (abs(err) < abs(min_err)) { best_clk =3D SCI_SCK; @@ -2607,7 +2619,7 @@ static void sci_set_termios(struct uart_port *port, s= truct ktermios *termios, sci_serial_out(port, SEMR, 0); =20 if (best_clk >=3D 0) { - if (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB) + if (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB) switch (srr + 1) { case 5: smr_val |=3D SCSMR_SRC_5; break; case 7: smr_val |=3D SCSMR_SRC_7; break; @@ -2692,12 +2704,12 @@ static void sci_set_termios(struct uart_port *port,= struct ktermios *termios, * (transmit interrupt enable) or in the same instruction to * start the transmitting process. So skip setting TE here for SCI. */ - if (port->type !=3D PORT_SCI) + if (s->type !=3D PORT_SCI) scr_val |=3D SCSCR_TE; scr_val |=3D SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); if ((srr + 1 =3D=3D 5) && - (port->type =3D=3D PORT_SCIFA || port->type =3D=3D PORT_SCIFB)) { + (s->type =3D=3D PORT_SCIFA || s->type =3D=3D PORT_SCIFB)) { /* * In asynchronous mode, when the sampling rate is 1/5, first * received data may become invalid on some SCIFA and SCIFB. @@ -2741,7 +2753,9 @@ void sci_pm(struct uart_port *port, unsigned int stat= e, =20 static const char *sci_type(struct uart_port *port) { - switch (port->type) { + struct sci_port *s =3D to_sci_port(port); + + switch (s->type) { case PORT_IRDA: return "irda"; case PORT_SCI: @@ -2825,8 +2839,7 @@ void sci_config_port(struct uart_port *port, int flag= s) { if (flags & UART_CONFIG_TYPE) { struct sci_port *sport =3D to_sci_port(port); - - port->type =3D sport->cfg->type; + port->type =3D SCI_PUBLIC_PORT_ID(sport->type); sci_request_port(port); } } @@ -2964,7 +2977,7 @@ static int sci_init_clocks(struct sci_port *sci_port,= struct device *dev) struct clk *clk; unsigned int i; =20 - if (sci_port->cfg->type =3D=3D PORT_HSCIF) + if (sci_port->type =3D=3D PORT_HSCIF) clk_names[SCI_SCK] =3D "hsck"; =20 for (i =3D 0; i < SCI_NUM_CLKS; i++) { @@ -3050,6 +3063,9 @@ static int sci_init_single(struct platform_device *de= v, =20 sci_port->cfg =3D p; =20 + sci_port->type =3D p->type; + sci_port->regtype =3D p->regtype; + port->iotype =3D UPIO_MEM; port->line =3D index; port->has_sysrq =3D IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); @@ -3128,11 +3144,11 @@ static int sci_init_single(struct platform_device *= dev, return ret; } =20 - port->type =3D p->type; + port->type =3D SCI_PUBLIC_PORT_ID(p->type); port->flags =3D UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; port->fifosize =3D sci_port->params->fifosize; =20 - if (port->type =3D=3D PORT_SCI && !dev->dev.of_node) { + if (p->type =3D=3D PORT_SCI && !dev->dev.of_node) { if (sci_port->reg_size >=3D 0x20) port->regshift =3D 2; else @@ -3322,13 +3338,13 @@ static struct uart_driver sci_uart_driver =3D { =20 static void sci_remove(struct platform_device *dev) { - struct sci_port *port =3D platform_get_drvdata(dev); - unsigned int type =3D port->port.type; /* uart_remove_... clears it */ + struct sci_port *s =3D platform_get_drvdata(dev); + unsigned int type =3D s->type; /* uart_remove_... clears it */ =20 - sci_ports_in_use &=3D ~BIT(port->port.line); - uart_remove_one_port(&sci_uart_driver, &port->port); + sci_ports_in_use &=3D ~BIT(s->port.line); + uart_remove_one_port(&sci_uart_driver, &s->port); =20 - if (port->port.fifosize > 1) + if (s->port.fifosize > 1) device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); if (type =3D=3D PORT_SCIFA || type =3D=3D PORT_SCIFB || type =3D=3D PORT_= HSCIF) device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); @@ -3682,8 +3698,8 @@ static int sci_probe(struct platform_device *dev) if (ret) return ret; } - if (sp->port.type =3D=3D PORT_SCIFA || sp->port.type =3D=3D PORT_SCIFB || - sp->port.type =3D=3D PORT_HSCIF) { + if (sp->type =3D=3D PORT_SCIFA || sp->type =3D=3D PORT_SCIFB || + sp->type =3D=3D PORT_HSCIF) { ret =3D device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); if (ret) { if (sp->port.fifosize > 1) { @@ -3799,8 +3815,11 @@ int __init scix_early_console_setup(struct earlycon_= device *device, if (!device->port.membase) return -ENODEV; =20 - device->port.type =3D data->type; + device->port.type =3D SCI_PUBLIC_PORT_ID(data->type); + sci_ports[0].port =3D device->port; + sci_ports[0].type =3D data->type; + sci_ports[0].regtype =3D data->regtype; =20 port_cfg.type =3D data->type; port_cfg.regtype =3D data->regtype; --=20 2.49.0