From nobody Wed Oct 8 13:21:51 2025 Received: from mxout2.routing.net (mxout2.routing.net [134.0.28.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 260B122D781; Sat, 28 Jun 2025 09:18:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.0.28.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751102297; cv=none; b=FsZFmE87yJhTlNHQf6X+WleutrdOM97YakKlgDQUhDOSwFqe07rxwYqyW5J2xEJQc5d5OLwBvae3gOoraFDdPTH8jBa0PHGAs76hlwaFDxAkKC4rDqdEPbX2QTlFwAkZnW4WkRe6cmHBr85FAdmZ+hE+ZG8Bc6vYhiAbagGfR7U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751102297; c=relaxed/simple; bh=CXJdMVM7yfnfOWdD19oSNPqLnLxqQfuOKdmhOWln+X4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YGPgGOvKgX9bvq83yR1KxZML59xwakRQ9KzqE+yCKveFo4pHU9khoEvBkibQZCaZiyRbK9l6elliXTrcd4k/dvTpxhD9dAFhTJPr6kz8yD+3AJjaiKCBmyeBN+Y/Si0oiHaUMAu85JI+sK8ioUHy8zd7/xSUGZH2fGy5/5iSs4c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de; spf=pass smtp.mailfrom=fw-web.de; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b=OJl61i4w; arc=none smtp.client-ip=134.0.28.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fw-web.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b="OJl61i4w" Received: from mxbulk.masterlogin.de (unknown [192.168.10.85]) by mxout2.routing.net (Postfix) with ESMTP id 26A2B601EA; Sat, 28 Jun 2025 09:10:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1751101853; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SHQ5vPeo13GqSQMpnsgrtHpzp9AC7Cqs5ZLxrZU37Ag=; b=OJl61i4w2r/wDPM1tGfm8/8OPZ+kfX6xnX4H5olTFdvH1P56Bi3tvDF4wJXup6QWaBWYoJ my4TlWMxW50bd1r4gfm7i06RMWk/hdCSUOPRrKziQw4NEfBWFeP1KnU/KK5E3oqgn6GxGU kYylN55GWY0gOSJd++IxB3xapRESAhg= Received: from frank-u24.. (fttx-pool-217.61.150.139.bambit.de [217.61.150.139]) by mxbulk.masterlogin.de (Postfix) with ESMTPSA id BFFF512272D; Sat, 28 Jun 2025 09:10:52 +0000 (UTC) From: Frank Wunderlich To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , Johnson Wang , =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Landen Chao , DENG Qingfang , Sean Wang , Daniel Golle , Lorenzo Bianconi , Felix Fietkau , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v6 07/15] arm64: dts: mediatek: mt7988: add cci node Date: Sat, 28 Jun 2025 11:10:31 +0200 Message-ID: <20250628091043.57645-8-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250628091043.57645-1-linux@fw-web.de> References: <20250628091043.57645-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add cci devicetree node for cpu frequency scaling. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno --- v3: - add mt7988-cci compatible as suggested by angelo --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7988a.dtsi index c46b31f8d653..560ec86dbec0 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -12,6 +12,35 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 + cci: cci { + compatible =3D "mediatek,mt7988-cci", "mediatek,mt8183-cci"; + clocks =3D <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names =3D "cci", "intermediate"; + operating-points-v2 =3D <&cci_opp>; + }; + + cci_opp: opp-table-cci { + compatible =3D "operating-points-v2"; + opp-shared; + opp-480000000 { + opp-hz =3D /bits/ 64 <480000000>; + opp-microvolt =3D <850000>; + }; + opp-660000000 { + opp-hz =3D /bits/ 64 <660000000>; + opp-microvolt =3D <850000>; + }; + opp-900000000 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <850000>; + }; + opp-1080000000 { + opp-hz =3D /bits/ 64 <1080000000>; + opp-microvolt =3D <900000>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -25,6 +54,7 @@ cpu0: cpu@0 { <&topckgen CLK_TOP_XTAL>; clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster0_opp>; + mediatek,cci =3D <&cci>; }; =20 cpu1: cpu@1 { @@ -36,6 +66,7 @@ cpu1: cpu@1 { <&topckgen CLK_TOP_XTAL>; clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster0_opp>; + mediatek,cci =3D <&cci>; }; =20 cpu2: cpu@2 { @@ -47,6 +78,7 @@ cpu2: cpu@2 { <&topckgen CLK_TOP_XTAL>; clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster0_opp>; + mediatek,cci =3D <&cci>; }; =20 cpu3: cpu@3 { @@ -58,6 +90,7 @@ cpu3: cpu@3 { <&topckgen CLK_TOP_XTAL>; clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster0_opp>; + mediatek,cci =3D <&cci>; }; =20 cluster0_opp: opp-table-0 { --=20 2.43.0