From nobody Wed Oct 8 13:21:51 2025 Received: from mxout4.routing.net (mxout4.routing.net [134.0.28.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FBEE224B14; Sat, 28 Jun 2025 09:11:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.0.28.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751101864; cv=none; b=ggQN/vlEsiXO77JiAoFBaskxpKZDImZtwMe9MIm5W9j24lgnJGBUydbNqZvtbz/5H4eOfzZLSTpT2xPiwiGCJAEuo5MgqgiE1lguvjcjj0biNX4m14OY65D+fQyk/t1hzMuwsMXjiKyaPkeEo261mR/HB0VWtLZRsAGLOLc8+QU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751101864; c=relaxed/simple; bh=gPrGHtbLr6wNB43kPK+9dUxlp1aSRU8byJ8ozBbRMGw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DLYEuilinzg/9ZdGVyuGg0I/k3tZtn6ezhLZQAEQ18VdhoIM9ZmkBZ6mA/Szcs+V5qDedaGP9y/M05jjzDfU8Y2fUFOIahQnr11pLP0XSFbZTP3nMyT7/zEjsKbxtmbj1hTljjJ8kv0fzfALBVe4sdp5K71EtM5x7p9FPA/CAgA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de; spf=pass smtp.mailfrom=fw-web.de; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b=mWudAFyR; arc=none smtp.client-ip=134.0.28.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fw-web.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b="mWudAFyR" Received: from mxbulk.masterlogin.de (unknown [192.168.10.85]) by mxout4.routing.net (Postfix) with ESMTP id E29AF1012C7; Sat, 28 Jun 2025 09:10:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1751101853; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2Up+TpRAQJFsd3iE9H547AQliakgI9CQqLhSEL2RQMo=; b=mWudAFyRKc5vJ1Nv/ipL2L9dbatHBVzl4YvJ7/OQRGZbgeU+nySu0LqK4KBJ9QCwuDNAAY cP87iWrYCDYEOHbV9Py21Xbi1sgl3aITzL0Y1H52HLb3YHM9barH44QtF5NkA4nQCyXM8S nbcWU+g3uT8pi6KneZCSovBYWnwV+uY= Received: from frank-u24.. (fttx-pool-217.61.150.139.bambit.de [217.61.150.139]) by mxbulk.masterlogin.de (Postfix) with ESMTPSA id 88BB812272D; Sat, 28 Jun 2025 09:10:53 +0000 (UTC) From: Frank Wunderlich To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , Johnson Wang , =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Landen Chao , DENG Qingfang , Sean Wang , Daniel Golle , Lorenzo Bianconi , Felix Fietkau , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v6 09/15] arm64: dts: mediatek: mt7988: add switch node Date: Sat, 28 Jun 2025 11:10:33 +0200 Message-ID: <20250628091043.57645-10-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250628091043.57645-1-linux@fw-web.de> References: <20250628091043.57645-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add mt7988 builtin mt753x switch nodes. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno --- v4: - drop phy-mode for gsw-phy - reorder phy-mode after phy-handle - drop interrupt parent from switch v2: - drop labels and led-function too (have to be in board) --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 148 ++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7988a.dtsi index cf765a6b1fa8..767782a207a4 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -742,6 +742,154 @@ ethsys: clock-controller@15000000 { #reset-cells =3D <1>; }; =20 + switch: switch@15020000 { + compatible =3D "mediatek,mt7988-switch"; + reg =3D <0 0x15020000 0 0x8000>; + interrupt-controller; + #interrupt-cells =3D <1>; + interrupts =3D ; + resets =3D <ðwarp MT7988_ETHWARP_RST_SWITCH>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_port0: port@0 { + reg =3D <0>; + phy-handle =3D <&gsw_phy0>; + phy-mode =3D "internal"; + }; + + gsw_port1: port@1 { + reg =3D <1>; + phy-handle =3D <&gsw_phy1>; + phy-mode =3D "internal"; + }; + + gsw_port2: port@2 { + reg =3D <2>; + phy-handle =3D <&gsw_phy2>; + phy-mode =3D "internal"; + }; + + gsw_port3: port@3 { + reg =3D <3>; + phy-handle =3D <&gsw_phy3>; + phy-mode =3D "internal"; + }; + + port@6 { + reg =3D <6>; + ethernet =3D <&gmac0>; + phy-mode =3D "internal"; + + fixed-link { + speed =3D <10000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + mediatek,pio =3D <&pio>; + + gsw_phy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + interrupts =3D <0>; + nvmem-cells =3D <&phy_calibration_p0>; + nvmem-cell-names =3D "phy-cal-data"; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_phy0_led0: led@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + gsw_phy0_led1: led@1 { + reg =3D <1>; + status =3D "disabled"; + }; + }; + }; + + gsw_phy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + interrupts =3D <1>; + nvmem-cells =3D <&phy_calibration_p1>; + nvmem-cell-names =3D "phy-cal-data"; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_phy1_led0: led@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + gsw_phy1_led1: led@1 { + reg =3D <1>; + status =3D "disabled"; + }; + }; + }; + + gsw_phy2: ethernet-phy@2 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <2>; + interrupts =3D <2>; + nvmem-cells =3D <&phy_calibration_p2>; + nvmem-cell-names =3D "phy-cal-data"; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_phy2_led0: led@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + gsw_phy2_led1: led@1 { + reg =3D <1>; + status =3D "disabled"; + }; + }; + }; + + gsw_phy3: ethernet-phy@3 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <3>; + interrupts =3D <3>; + nvmem-cells =3D <&phy_calibration_p3>; + nvmem-cell-names =3D "phy-cal-data"; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_phy3_led0: led@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + gsw_phy3_led1: led@1 { + reg =3D <1>; + status =3D "disabled"; + }; + }; + }; + }; + }; + ethwarp: clock-controller@15031000 { compatible =3D "mediatek,mt7988-ethwarp"; reg =3D <0 0x15031000 0 0x1000>; --=20 2.43.0