From nobody Wed Oct 8 15:15:35 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98BC321770A; Fri, 27 Jun 2025 11:58:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751025500; cv=none; b=jJVQ3NT5lB6KBYkfUpfPhTuMcF6E7cPKiq8hdb0p80Kpp6tgf1nU6vaJz2WI+z/z/0nBvp+M+AIKBIPXzz33T/tBEUSaOB3W0+K0162/kCNxqF2JLP0Sg2eZ10KPE/8cA//q9tTV1G2tmL6mNOD5rhFyVS+49WaQcB3bbWWttrI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751025500; c=relaxed/simple; bh=1A9CY0H/kYTojtxll//4SQPbJ+jWznvduyifJPT4qpI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nzPA1THnXeLwZnfLLTd0IUDOo5n/N088bM8SkfLfgYHSz82JyeXh1bFGNvy3gUldz6SS7m3TsfeaXSt4uZG4ziSGPHbvhlIWQNi+a+TvPGJ/1L4XlFumvTMoA5WOdiRxEN0FHYTGOcSPHJdjeffbUvPYp7L4zarE5Y7//7JA+TI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=wysEWNWe; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="wysEWNWe" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55RBw6at2404196; Fri, 27 Jun 2025 06:58:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1751025486; bh=2nB2XrYs3/yr4cfRNXfAXTu6rjkWvNQLgoMjODS48vE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wysEWNWeeD7frHfjNt+bWNcEygYUShvB6UgH5G1zcwZg3HwUov5UJwWEdW0smCv3z 1ebNPpdLOLwXatFandWAz1MhomSrKlTHe+WMZf4OU8gOKqnqPj6q17SgbK0qq3/l6e iS1s5gz9f43WqtFFGhVX6K1ScCRpyKrezAqwGfcE= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55RBw6Tq407111 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 27 Jun 2025 06:58:06 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 27 Jun 2025 06:58:06 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 27 Jun 2025 06:58:06 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55RBw5w12755169; Fri, 27 Jun 2025 06:58:06 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , , , Subject: [PATCH v5 3/4] arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCs Date: Fri, 27 Jun 2025 17:27:52 +0530 Message-ID: <20250627115753.2246881-4-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250627115753.2246881-1-p-bhagat@ti.com> References: <20250627115753.2246881-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Update k3-pinctrl file to include pin definitions for AM62D2 family of SoCs. Signed-off-by: Paresh Bhagat --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index cac7cccc1112..0cf57179c974 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -63,6 +63,9 @@ #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 +#define AM62DX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) +#define AM62DX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) + #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 --=20 2.34.1