From nobody Wed Oct 8 12:33:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 996D41DC9A3; Sat, 28 Jun 2025 03:35:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081722; cv=none; b=HsUgi7WpbMZc0NNnPiKflMB/D1JXqwSwxtmCtoUPFyhD+AVU278QSdZW+oMWIYSmGxbEcH6b6+5P9I2xNL0z0gbjUD5YXXYKyBG2vHQNK59WsvbRXndxmo139stkTiQUMr9cWOPKvYsb/wf0nEoywRGrr5kjU+P9jGMzOXfkTeM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081722; c=relaxed/simple; bh=s9EY1xoCTSXe3LXRtsiD6ykIH2wv0AgLTU6Q6NZ6HRY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OU4ujcws8p245D4c5PnmtohCwSBg+y7bOD2pMCqPpPqLROcgA5yuzlbQNVMfoEQsw8QrqOrhvQ3JWpeZh/lkMAyKpaGtOY/mDXEwY3jgaAAlbaszieoKbgAXiobEDsUiYd7Qzhz+F6CBhMVFxIL1GTSY282zECqBYZH3ty0dvPc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=eV2Q6Zyu; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="eV2Q6Zyu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751081721; x=1782617721; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=s9EY1xoCTSXe3LXRtsiD6ykIH2wv0AgLTU6Q6NZ6HRY=; b=eV2Q6ZyuRfvmhlbRFS4dpMjuvPP+KLaJPcD12DhX9ZoVIBfJzb1w7pFO uKPUL67mORSvQL7R0yrhnwsKwUJQ+iNe9FCY6+JBxaHbQArclooM3efv0 Ik3t+3H6QGp1w5wB2ogMVdOfvAXCgjr4vaY7muvYBxFeekGkxMo7T1jRL uUPY2Cm8DwSae0CNywWH/GhDfTYFMMPbXBqEbAu4+Jk5ID5HDjpq0WkS2 bEM9r7s6ld7VL8J7s5oVfx3AQQpVKhgpNwO+EVbNu3GnZEaoPP5zpoKwd pL+JKxw69HunsnGMOdWgxMVEDgeW+wFj33CIOi3zNUqO2HNDMoBboUwIw A==; X-CSE-ConnectionGUID: GVmPJyG3SqKI04JSsCBujA== X-CSE-MsgGUID: t2yAe5quQli8Gm+zypvv4A== X-IronPort-AV: E=McAfee;i="6800,10657,11477"; a="53335315" X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="53335315" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:19 -0700 X-CSE-ConnectionGUID: 4FEp2KyLTSyYRB/3M03tZg== X-CSE-MsgGUID: OTd2bSHFSnSS8+Bso9AhrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="153141917" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by orviesa007.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:18 -0700 From: Ricardo Neri Date: Fri, 27 Jun 2025 20:35:07 -0700 Subject: [PATCH v5 01/10] x86/acpi: Add a helper functions to setup and access the wakeup mailbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rneri-wakeup-mailbox-v5-1-df547b1d196e@linux.intel.com> References: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> In-Reply-To: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751081737; l=3970; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=s9EY1xoCTSXe3LXRtsiD6ykIH2wv0AgLTU6Q6NZ6HRY=; b=xBFp2wyk51bdqt8PiSY1kNZPqGW5l1kIw8zXSsz1Fx/zgAMPjdi7xoBNzrpqijHvtg3cExfji 2jQy0w+H/evBZ51dzpWRdRHmURWYGeqph6Vjfpe026PrWXNFuxD+Tfg X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= In preparation to move the functionality to wake secondary CPUs up out of the ACPI code, add two helper functions. The function acpi_setup_mp_wakeup_mailbox() stores the physical address of the mailbox and updates the wakeup_secondary_cpu_64() APIC callback. There is a slight change in behavior: now the APIC callback is updated before configuring CPU hotplug offline behavior. This is fine as the APIC callback continues to be updated unconditionally, regardless of the restriction on CPU offlining. The function acpi_madt_multiproc_wakeup_mailbox() returns a pointer to the mailbox. Use this helper function only in the portions of the code for which the variable acpi_mp_wake_mailbox will be out of scope once it is relocated out of the ACPI directory. The wakeup mailbox is only supported for CONFIG_X86_64 and needed only with CONFIG_SMP=3Dy. Signed-off-by: Ricardo Neri Acked-by: Rafael J. Wysocki --- Changes since v4: - None Changes since v3: - Squashed the two first patches of the series into one, both introduce helper functions. (Rafael) - Renamed setup_mp_wakeup_mailbox() as acpi_setup_mp_wakeup_mailbox(). (Rafael) - Dropped the function prototype for !CONFIG_X86_64. (Rafael) Changes since v2: - Introduced this patch. Changes since v1: - N/A --- arch/x86/include/asm/smp.h | 3 +++ arch/x86/kernel/acpi/madt_wakeup.c | 20 +++++++++++++++----- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index 0c1c68039d6f..77dce560a70a 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -146,6 +146,9 @@ static inline struct cpumask *cpu_l2c_shared_mask(int c= pu) return per_cpu(cpu_l2c_shared_map, cpu); } =20 +void acpi_setup_mp_wakeup_mailbox(u64 addr); +struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void= ); + #else /* !CONFIG_SMP */ #define wbinvd_on_cpu(cpu) wbinvd() static inline int wbinvd_on_all_cpus(void) diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index 6d7603511f52..c3ac5ecf3e7d 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -37,6 +37,7 @@ static void acpi_mp_play_dead(void) =20 static void acpi_mp_cpu_die(unsigned int cpu) { + struct acpi_madt_multiproc_wakeup_mailbox *mailbox =3D acpi_get_mp_wakeup= _mailbox(); u32 apicid =3D per_cpu(x86_cpu_to_apicid, cpu); unsigned long timeout; =20 @@ -46,13 +47,13 @@ static void acpi_mp_cpu_die(unsigned int cpu) * * BIOS has to clear 'command' field of the mailbox. */ - acpi_mp_wake_mailbox->apic_id =3D apicid; - smp_store_release(&acpi_mp_wake_mailbox->command, + mailbox->apic_id =3D apicid; + smp_store_release(&mailbox->command, ACPI_MP_WAKE_COMMAND_TEST); =20 /* Don't wait longer than a second. */ timeout =3D USEC_PER_SEC; - while (READ_ONCE(acpi_mp_wake_mailbox->command) && --timeout) + while (READ_ONCE(mailbox->command) && --timeout) udelay(1); =20 if (!timeout) @@ -227,7 +228,7 @@ int __init acpi_parse_mp_wake(union acpi_subtable_heade= rs *header, =20 acpi_table_print_madt_entry(&header->common); =20 - acpi_mp_wake_mailbox_paddr =3D mp_wake->mailbox_address; + acpi_setup_mp_wakeup_mailbox(mp_wake->mailbox_address); =20 if (mp_wake->version >=3D ACPI_MADT_MP_WAKEUP_VERSION_V1 && mp_wake->header.length >=3D ACPI_MADT_MP_WAKEUP_SIZE_V1) { @@ -243,7 +244,16 @@ int __init acpi_parse_mp_wake(union acpi_subtable_head= ers *header, acpi_mp_disable_offlining(mp_wake); } =20 + return 0; +} + +void __init acpi_setup_mp_wakeup_mailbox(u64 mailbox_paddr) +{ + acpi_mp_wake_mailbox_paddr =3D mailbox_paddr; apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); +} =20 - return 0; +struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void) +{ + return acpi_mp_wake_mailbox; } --=20 2.43.0 From nobody Wed Oct 8 12:33:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 767BC21B191; Sat, 28 Jun 2025 03:35:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081723; cv=none; b=ZOOMGUlat1k6HtUz1XFOWFe1R2G+cC/4sGJ5S19NTEeNawJk+wngvylziccSYAPqWzt04bo1+BklDf2bGZUvIQSq/IENlqhQubwwz7nBd/f29jQVTHN3lXC5P5vLTEqxDghuvF2JiFO7URfhsDWRml+KdryH9m0MWGK+RjtR+VQ= ARC-Message-Signature: i=1; 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d="scan'208";a="153141921" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by orviesa007.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:19 -0700 From: Ricardo Neri Date: Fri, 27 Jun 2025 20:35:08 -0700 Subject: [PATCH v5 02/10] x86/acpi: Move acpi_wakeup_cpu() and helpers to smpwakeup.c Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rneri-wakeup-mailbox-v5-2-df547b1d196e@linux.intel.com> References: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> In-Reply-To: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751081737; l=9612; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=j8bwDO3WHMvsfI9FYwYOft+Xg9EMM6fDrrMDsmZxkIM=; b=iOLUJv03U65R+nis5QaxTTGaya9G/6TWV3DzM2ESFPNOSRyjUxFgflzE18qBEyhRjI5wnYLoo zXwR7rG40rNBLk7IXm6RxlJGTTHxiat92JldiVjUoj0D2xdlAQWBtS0 X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= The bootstrap processor uses acpi_wakeup_cpu() to indicate to firmware that it wants to boot a secondary CPU using a mailbox as described in the Multiprocessor Wakeup Structure of the ACPI specification. The platform firmware may implement the mailbox as described in the ACPI specification but enumerate it using a DeviceTree graph. An example of this is OpenHCL paravisor. Move the code used to setup and use the mailbox for CPU wakeup out of the ACPI directory into a new smpwakeup.c file that both ACPI and DeviceTree can use. No functional changes are intended. Co-developed-by: Yunhong Jiang Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri Acked-by: Rafael J. Wysocki --- Changes since v4: - Removed dependency on CONFIG_OF. It will be added in a later patch. (Rafael) - Rebased on v6.16-rc3. Changes since v3: - Create a new file smpwakeup.c instead of relocating it to smpboot.c. (Rafael) Changes since v2: - Only move to smpboot.c the portions of the code that configure and use the mailbox. This also resolved the compile warnings about unused functions that Michael Kelley reported. - Edited the commit message for clarity. Changes since v1: - None. --- arch/x86/Kconfig | 7 ++++ arch/x86/kernel/Makefile | 1 + arch/x86/kernel/acpi/madt_wakeup.c | 76 ---------------------------------- arch/x86/kernel/smpwakeup.c | 83 ++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 91 insertions(+), 76 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 71019b3b54ea..e3009cb59928 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1114,6 +1114,13 @@ config X86_LOCAL_APIC depends on X86_64 || SMP || X86_UP_APIC || PCI_MSI select IRQ_DOMAIN_HIERARCHY =20 +config X86_MAILBOX_WAKEUP + def_bool y + depends on ACPI_MADT_WAKEUP + depends on X86_64 + depends on SMP + depends on X86_LOCAL_APIC + config ACPI_MADT_WAKEUP def_bool y depends on X86_64 diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 0d2a6d953be9..1fce3d20cf2d 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -94,6 +94,7 @@ apm-y :=3D apm_32.o obj-$(CONFIG_APM) +=3D apm.o obj-$(CONFIG_SMP) +=3D smp.o obj-$(CONFIG_SMP) +=3D smpboot.o +obj-$(CONFIG_X86_MAILBOX_WAKEUP) +=3D smpwakeup.o obj-$(CONFIG_X86_TSC) +=3D tsc_sync.o obj-$(CONFIG_SMP) +=3D setup_percpu.o obj-$(CONFIG_X86_MPPARSE) +=3D mpparse.o diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index c3ac5ecf3e7d..a7e0158269b0 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -2,12 +2,10 @@ #include #include #include -#include #include #include #include #include -#include #include #include #include @@ -15,12 +13,6 @@ #include #include =20 -/* Physical address of the Multiprocessor Wakeup Structure mailbox */ -static u64 acpi_mp_wake_mailbox_paddr __ro_after_init; - -/* Virtual address of the Multiprocessor Wakeup Structure mailbox */ -static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox; - static u64 acpi_mp_pgd __ro_after_init; static u64 acpi_mp_reset_vector_paddr __ro_after_init; =20 @@ -127,63 +119,6 @@ static int __init acpi_mp_setup_reset(u64 reset_vector) return 0; } =20 -static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip, unsigned in= t cpu) -{ - if (!acpi_mp_wake_mailbox_paddr) { - pr_warn_once("No MADT mailbox: cannot bringup secondary CPUs. Booting wi= th kexec?\n"); - return -EOPNOTSUPP; - } - - /* - * Remap mailbox memory only for the first call to acpi_wakeup_cpu(). - * - * Wakeup of secondary CPUs is fully serialized in the core code. - * No need to protect acpi_mp_wake_mailbox from concurrent accesses. - */ - if (!acpi_mp_wake_mailbox) { - acpi_mp_wake_mailbox =3D memremap(acpi_mp_wake_mailbox_paddr, - sizeof(*acpi_mp_wake_mailbox), - MEMREMAP_WB); - } - - /* - * Mailbox memory is shared between the firmware and OS. Firmware will - * listen on mailbox command address, and once it receives the wakeup - * command, the CPU associated with the given apicid will be booted. - * - * The value of 'apic_id' and 'wakeup_vector' must be visible to the - * firmware before the wakeup command is visible. smp_store_release() - * ensures ordering and visibility. - */ - acpi_mp_wake_mailbox->apic_id =3D apicid; - acpi_mp_wake_mailbox->wakeup_vector =3D start_ip; - smp_store_release(&acpi_mp_wake_mailbox->command, - ACPI_MP_WAKE_COMMAND_WAKEUP); - - /* - * Wait for the CPU to wake up. - * - * The CPU being woken up is essentially in a spin loop waiting to be - * woken up. It should not take long for it wake up and acknowledge by - * zeroing out ->command. - * - * ACPI specification doesn't provide any guidance on how long kernel - * has to wait for a wake up acknowledgment. It also doesn't provide - * a way to cancel a wake up request if it takes too long. - * - * In TDX environment, the VMM has control over how long it takes to - * wake up secondary. It can postpone scheduling secondary vCPU - * indefinitely. Giving up on wake up request and reporting error opens - * possible attack vector for VMM: it can wake up a secondary CPU when - * kernel doesn't expect it. Wait until positive result of the wake up - * request. - */ - while (READ_ONCE(acpi_mp_wake_mailbox->command)) - cpu_relax(); - - return 0; -} - static void acpi_mp_disable_offlining(struct acpi_madt_multiproc_wakeup *m= p_wake) { cpu_hotplug_disable_offlining(); @@ -246,14 +181,3 @@ int __init acpi_parse_mp_wake(union acpi_subtable_head= ers *header, =20 return 0; } - -void __init acpi_setup_mp_wakeup_mailbox(u64 mailbox_paddr) -{ - acpi_mp_wake_mailbox_paddr =3D mailbox_paddr; - apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); -} - -struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void) -{ - return acpi_mp_wake_mailbox; -} diff --git a/arch/x86/kernel/smpwakeup.c b/arch/x86/kernel/smpwakeup.c new file mode 100644 index 000000000000..5089bcda615d --- /dev/null +++ b/arch/x86/kernel/smpwakeup.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include +#include +#include +#include +#include +#include + +/* Physical address of the Multiprocessor Wakeup Structure mailbox */ +static u64 acpi_mp_wake_mailbox_paddr __ro_after_init; + +/* Virtual address of the Multiprocessor Wakeup Structure mailbox */ +static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox; + +static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip, unsigned in= t cpu) +{ + if (!acpi_mp_wake_mailbox_paddr) { + pr_warn_once("No MADT mailbox: cannot bringup secondary CPUs. Booting wi= th kexec?\n"); + return -EOPNOTSUPP; + } + + /* + * Remap mailbox memory only for the first call to acpi_wakeup_cpu(). + * + * Wakeup of secondary CPUs is fully serialized in the core code. + * No need to protect acpi_mp_wake_mailbox from concurrent accesses. + */ + if (!acpi_mp_wake_mailbox) { + acpi_mp_wake_mailbox =3D memremap(acpi_mp_wake_mailbox_paddr, + sizeof(*acpi_mp_wake_mailbox), + MEMREMAP_WB); + } + + /* + * Mailbox memory is shared between the firmware and OS. Firmware will + * listen on mailbox command address, and once it receives the wakeup + * command, the CPU associated with the given apicid will be booted. + * + * The value of 'apic_id' and 'wakeup_vector' must be visible to the + * firmware before the wakeup command is visible. smp_store_release() + * ensures ordering and visibility. + */ + acpi_mp_wake_mailbox->apic_id =3D apicid; + acpi_mp_wake_mailbox->wakeup_vector =3D start_ip; + smp_store_release(&acpi_mp_wake_mailbox->command, + ACPI_MP_WAKE_COMMAND_WAKEUP); + + /* + * Wait for the CPU to wake up. + * + * The CPU being woken up is essentially in a spin loop waiting to be + * woken up. It should not take long for it wake up and acknowledge by + * zeroing out ->command. + * + * ACPI specification doesn't provide any guidance on how long kernel + * has to wait for a wake up acknowledgment. It also doesn't provide + * a way to cancel a wake up request if it takes too long. + * + * In TDX environment, the VMM has control over how long it takes to + * wake up secondary. It can postpone scheduling secondary vCPU + * indefinitely. Giving up on wake up request and reporting error opens + * possible attack vector for VMM: it can wake up a secondary CPU when + * kernel doesn't expect it. Wait until positive result of the wake up + * request. + */ + while (READ_ONCE(acpi_mp_wake_mailbox->command)) + cpu_relax(); + + return 0; +} + +void __init acpi_setup_mp_wakeup_mailbox(u64 mailbox_paddr) +{ + acpi_mp_wake_mailbox_paddr =3D mailbox_paddr; + apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); +} + +struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void) +{ + return acpi_mp_wake_mailbox; +} --=20 2.43.0 From nobody Wed Oct 8 12:33:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2219821B9CE; Sat, 28 Jun 2025 03:35:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081723; cv=none; b=F/6jbfHLIZ8ohS02E8Y2yOzP2nodmczjLzUeQXyyzM+yoO4UIwAw8O280kqY5cQ/i4xaEa+fHuKzTon4vSUwDuRq1IJxAxNZHJZSgAgwUaiVSkoRG4FhWKMZham/vZkYwcDx/Dj7TVuKG6eb8iWnAqoOM1nDdICvrd4GUtN/kbs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081723; c=relaxed/simple; bh=HLSJ1P1a0+J8j3M3+k+W/9+PRSEANrkFCHDDgD2xw+k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YImt1WJew2Ggl7jPhViCYoBOI6yId6wEwbvorxnpcz4kKKVRizOoZOYMgDEGHu7HmERFOmDOSG7LPZPaMg8T8AytYwepPD3qTcNndArTxdclJYTKs+aSo6nMzMsU/VrFddQ5PnEVROHM0yUIeeI0YnJx4WJNJqH6YPXpfVFBIys= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dp9R4M1m; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dp9R4M1m" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751081722; x=1782617722; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=HLSJ1P1a0+J8j3M3+k+W/9+PRSEANrkFCHDDgD2xw+k=; b=dp9R4M1meDcFBaljuoIinoDlX74qC+PFhMpZkaoygROpbZoLh0pdhozK 45E8JVSGjVjnBjklmhiVmJeP7JCPgWTCfa3TmN9nvniU8IE+4e/Sz7Nd5 IX3kOmK/FAWirrRy8FtpgHutglC5xG8SSZ9lS25Lv6CMGxFYuDxwUtfwx 9vPpHUGjFtrazPZ4a5P4xCbeP7harWzsquLytIKngJ64bndra5pA4C2KC 9GdXaTsuep95s2fBwRuftuzPxil/pX6ieXbHRI4CRylylILMSKT7VH1Yd L3u5bG1Dg0REC+ohuyoqD+PNEsoEQpMemP3uw7zMc/aqwaltz3eAEIJg4 g==; X-CSE-ConnectionGUID: ubHgi4oURBObOTir33KIGQ== X-CSE-MsgGUID: Q4pAb1PWSNGEPYzi/sLVmg== X-IronPort-AV: E=McAfee;i="6800,10657,11477"; a="53335325" X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="53335325" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:20 -0700 X-CSE-ConnectionGUID: i1760zz6TF6Pwtpt1rMuLg== X-CSE-MsgGUID: 3RVbVeNJShGwbqp4sFmLTA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="153141926" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by orviesa007.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:19 -0700 From: Ricardo Neri Date: Fri, 27 Jun 2025 20:35:09 -0700 Subject: [PATCH v5 03/10] dt-bindings: reserved-memory: Wakeup Mailbox for Intel processors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rneri-wakeup-mailbox-v5-3-df547b1d196e@linux.intel.com> References: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> In-Reply-To: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751081737; l=4718; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=HLSJ1P1a0+J8j3M3+k+W/9+PRSEANrkFCHDDgD2xw+k=; b=ROTSW5k/L6MozCceFHd2ghE07viBG/E/oCWuJB5/1tx4K1HpwLgO5jBWY0P6BwqaM68gA2vUY IEt7NUbCyoYBTf4/Rx1v8lL9ePFDUN3YYhk+zbKQo/pJ2L+X5sgkU7Y X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= Add DeviceTree bindings to enumerate the wakeup mailbox used in platform firmware for Intel processors. x86 platforms commonly boot secondary CPUs using an INIT assert, de-assert followed by Start-Up IPI messages. The wakeup mailbox can be used when this mechanism is unavailable. The wakeup mailbox offers more control to the operating system to boot secondary CPUs than a spin-table. It allows the reuse of same wakeup vector for all CPUs while maintaining control over which CPUs to boot and when. While it is possible to achieve the same level of control using a spin- table, it would require to specify a separate `cpu-release-addr` for each secondary CPU. The operation and structure of the mailbox is described in the Multiprocessor Wakeup Structure defined in the ACPI specification. Note that this structure does not specify how to publish the mailbox to the operating system (ACPI-based platform firmware uses a separate table). No ACPI table is needed in DeviceTree-based firmware to enumerate the mailbox. Add a `compatible` property that the operating system can use to discover the mailbox. Nodes wanting to refer to the reserved memory usually define a `memory-region` property. /cpus/cpu* nodes would want to refer to the mailbox, but they do not have such property defined in the DeviceTree specification. Moreover, it would imply that there is a memory region per CPU. Co-developed-by: Yunhong Jiang Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri Acked-by: Rafael J. Wysocki Reviewed-by: Rob Herring (Arm) --- Changes since v4: - Specified the version and section of the ACPI spec in which the wakeup mailbox is defined. (Rafael) - Fixed a warning from yamllint about line lengths of URLs. Changes since v3: - Removed redefinitions of the mailbox and instead referred to ACPI specification as per discussion on LKML. - Clarified that DeviceTree-based firmware do not require the use of ACPI tables to enumerate the mailbox. (Rob) - Described the need of using a `compatible` property. - Dropped the `alignment` property. (Krzysztof, Rafael) - Used a real address for the mailbox node. (Krzysztof) Changes since v2: - Implemented the mailbox as a reserved-memory node. Add to it a `compatible` property. (Krzysztof) - Explained the relationship between the mailbox and the `enable-mehod` property of the CPU nodes. - Expanded the documentation of the binding. Changes since v1: - Added more details to the description of the binding. - Added requirement a new requirement for cpu@N nodes to add an `enable-method`. --- .../reserved-memory/intel,wakeup-mailbox.yaml | 50 ++++++++++++++++++= ++++ 1 file changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/reserved-memory/intel,wakeup= -mailbox.yaml b/Documentation/devicetree/bindings/reserved-memory/intel,wak= eup-mailbox.yaml new file mode 100644 index 000000000000..a80d3bac44c2 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbo= x.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/intel,wakeup-mailbox.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wakeup Mailbox for Intel processors + +description: | + The Wakeup Mailbox provides a mechanism for the operating system to wake= up + secondary CPUs on Intel processors. It is an alternative to the INIT-!IN= IT- + SIPI sequence used on most x86 systems. + + The structure and operation of the mailbox is described in the Multiproc= essor + Wakeup Structure of the ACPI specification version 6.6 section 5.2.12.19= [1]. + + The implementation of the mailbox in platform firmware is described in t= he + Intel TDX Virtual Firmware Design Guide section 4.3.5 [2]. + + 1: https://uefi.org/specs/ACPI/6.6/05_ACPI_Software_Programming_Model.ht= ml#multiprocessor-wakeup-structure + 2: https://www.intel.com/content/www/us/en/content-details/733585/intel-= tdx-virtual-firmware-design-guide.html + + +maintainers: + - Ricardo Neri + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: intel,wakeup-mailbox + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <1>; + + wakeup-mailbox@ffff0000 { + compatible =3D "intel,wakeup-mailbox"; + reg =3D <0x0 0xffff0000 0x1000>; + }; + }; --=20 2.43.0 From nobody Wed Oct 8 12:33:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E86B21C186; Sat, 28 Jun 2025 03:35:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081724; cv=none; b=tuv/c/B9FBlFqiSuvVP7QNqyetPyul2QxWFlMqRcOMT7iwn7BigNm4qdKY+VzB6g+2CxcuVLWaTtbedO7mwgRToPc1pjWO/jgLP9tUQszVNoaZAXKQGG6DqWJMEaYh3VDZL0TM/lppNjR961Je0I7Qj8+oi6W3VOFQ1JxUOPM3I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081724; c=relaxed/simple; bh=KGJP3nxc6fAkIgk3la9kd24UeoXHH3LZl3OFegytHj8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=vAWnXE9LEqm3yRz+XJWe7WGAOpJyg8STkrGcwEuTxPP2yVGU2PUT/bGCnAVBFEncEA3dFCCyECsz/blDxlnC87a15V1O93/DmPXW51yvUUW7OxR8P1pmTY1rlii47HRB47VqILlI6wf3VzDJ21kCDqPgUS5U7wX3NwpAu9vpHX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FL62iX2K; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FL62iX2K" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751081723; x=1782617723; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=KGJP3nxc6fAkIgk3la9kd24UeoXHH3LZl3OFegytHj8=; b=FL62iX2KPjsRU13o5EhzltySvZEZGxsfqdT7CwIKp+pXB6cmrifn4jkl wYImZXW7kDVcUK4dCb6kPkfkWRQf6XCRBjfpvOOYhZEC28ZGReBYxVnvX q9HZqWwKrZDnMM6EcxLFoIbRlMevUSS3aZxIOSB8cShUAGERMaFHPSf30 apsDPRCRtMwyyUmSjYvhu7UQ1ppirqCeuYmdDQuC9WDPUbZ0+mSIh/1WD FktpISQ9KdHxTfhHQj9qQc2mICiKoorm6I1adnbulcyF+ybG9NjfOA3Bi X93sXs+VKBTA83RSBRxYohz2vPfbj79gfUWXvaECs0dpX3qVJs2/UqkRV w==; X-CSE-ConnectionGUID: /5rsuMbrRbe+OfPzuW87Cw== X-CSE-MsgGUID: tJtSgauVSSyXpW+V+oezyQ== X-IronPort-AV: E=McAfee;i="6800,10657,11477"; a="53335330" X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="53335330" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:20 -0700 X-CSE-ConnectionGUID: 7+qyvk0GTH27qfYtN/MIcQ== X-CSE-MsgGUID: yY0nxV/lTAqxG6MhpvdI4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="153141931" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by orviesa007.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:19 -0700 From: Ricardo Neri Date: Fri, 27 Jun 2025 20:35:10 -0700 Subject: [PATCH v5 04/10] x86/dt: Parse the Wakeup Mailbox for Intel processors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rneri-wakeup-mailbox-v5-4-df547b1d196e@linux.intel.com> References: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> In-Reply-To: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751081737; l=4671; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=KGJP3nxc6fAkIgk3la9kd24UeoXHH3LZl3OFegytHj8=; b=MhuKuyKFBN/ZcWk1phHIjifrsUw360CkK408sE3DgyKH8M4GettG4XfQwaBAkTvNV8RPitnhT uWEbpIzfUEQAvyQnfEWq1gMwpgHx0Nd/gHuI6mTb8zYeXUIPcScKDJy X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= The Wakeup Mailbox is a mechanism to boot secondary CPUs used on systems that do not want or cannot use the INIT + StartUp IPI messages. The platform firmware is expected to implement the mailbox as described in the Multiprocessor Wakeup Structure of the ACPI specification. It is also expected to publish the mailbox to the operating system as described in the corresponding DeviceTree schema that accompanies the documentation of the Linux kernel. Reuse the existing functionality to set the memory location of the mailbox and update the wakeup_secondary_cpu_64() APIC callback. Make this functionality available to DeviceTree-based systems by making CONFIG_X86_ MAILBOX_WAKEUP depend on either CONFIG_OF or CONFIG_ACPI_MADT_WAKEUP. do_boot_cpu() uses wakeup_secondary_cpu_64() when set. If a wakeup mailbox is found (enumerated via an ACPI table or a DeviceTree node) it will be used unconditionally. For cases in which this behavior is not desired, this APIC callback can be updated later during boot using platform-specific hooks. Co-developed-by: Yunhong Jiang Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v4: - Made CONFIG_X86_MAILBOX_WAKEUP depend on CONFIG_OF or CONFIG_ACPI_ MADT_WAKEUP. Changes since v3: - Look for the wakeup mailbox unconditionally, regardless of whether cpu@N nodes have an `enable-method` property. - Add a reference to the ACPI specification. (Rafael) Changes since v2: - Added extra sanity checks when parsing the mailbox node. - Probe the mailbox using its `compatible` property - Setup the Wakeup Mailbox if the `enable-method` is found in the CPU nodes. - Cleaned up unneeded ifdeffery. - Clarified the mechanisms used to override the wakeup_secondary_64() callback to not use the mailbox when not desired. (Michael) - Edited the commit message for clarity. Changes since v1: - Disabled CPU offlining. - Modified dtb_parse_mp_wake() to return the address of the mailbox. --- arch/x86/Kconfig | 2 +- arch/x86/kernel/devicetree.c | 47 ++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e3009cb59928..027f8ae878ec 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1116,7 +1116,7 @@ config X86_LOCAL_APIC =20 config X86_MAILBOX_WAKEUP def_bool y - depends on ACPI_MADT_WAKEUP + depends on OF || ACPI_MADT_WAKEUP depends on X86_64 depends on SMP depends on X86_LOCAL_APIC diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index dd8748c45529..494a560614a8 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 #include #include @@ -125,6 +126,51 @@ static void __init dtb_setup_hpet(void) #endif } =20 +#if defined(CONFIG_X86_64) && defined(CONFIG_SMP) + +#define WAKEUP_MAILBOX_SIZE 0x1000 +#define WAKEUP_MAILBOX_ALIGN 0x1000 + +/** dtb_wakeup_mailbox_setup() - Parse the wakeup mailbox from the device = tree + * + * Look for the presence of a wakeup mailbox in the DeviceTree. The mailbo= x is + * expected to follow the structure and operation described in the Multipr= ocessor + * Wakeup Structure of the ACPI specification. + */ +static void __init dtb_wakeup_mailbox_setup(void) +{ + struct device_node *node; + struct resource res; + + node =3D of_find_compatible_node(NULL, NULL, "intel,wakeup-mailbox"); + if (!node) + return; + + if (of_address_to_resource(node, 0, &res)) + goto done; + + /* The mailbox is a 4KB-aligned region.*/ + if (res.start & (WAKEUP_MAILBOX_ALIGN - 1)) + goto done; + + /* The mailbox has a size of 4KB. */ + if (res.end - res.start + 1 !=3D WAKEUP_MAILBOX_SIZE) + goto done; + + /* Not supported when the mailbox is used. */ + cpu_hotplug_disable_offlining(); + + acpi_setup_mp_wakeup_mailbox(res.start); +done: + of_node_put(node); +} +#else /* !CONFIG_X86_64 || !CONFIG_SMP */ +static inline int dtb_wakeup_mailbox_setup(void) +{ + return -EOPNOTSUPP; +} +#endif /* CONFIG_X86_64 && CONFIG_SMP */ + #ifdef CONFIG_X86_LOCAL_APIC =20 static void __init dtb_cpu_setup(void) @@ -287,6 +333,7 @@ static void __init x86_dtb_parse_smp_config(void) =20 dtb_setup_hpet(); dtb_apic_setup(); + dtb_wakeup_mailbox_setup(); } =20 void __init x86_flattree_get_config(void) --=20 2.43.0 From nobody Wed Oct 8 12:33:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C1E821CA0D; Sat, 28 Jun 2025 03:35:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081725; cv=none; b=sKCkqwwXyd4OoCk1+wlJGbeDBcrrApt1jOxXlfkBO6AgO8Rnew+MtfNJf/wbnBHfq0qdbo93yEJlnSBp9e5DuKV+RpS81LhIVtatv9wCe55xUl7uwoO8puc7HyJV8xQRPvo6x6sbJHeWW52fpTAmeP+5eFQFHjgUn7QeFISPnwU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081725; c=relaxed/simple; bh=/INFvW4Qi6kj0Usw93W5OwBiOHfJrQKbA2C20+QLwds=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZXp8ATCHGW7J25TTA/6eVJee0V41AMfP7QLkn2d7u5R3epaZW7NXg6ry+NuuXbp1vDepjgEmL7y59ga37mDlUNNTbP3RRkDrZIWIUrK/UrpziXTKw0g+Y8oohFeStxsJCpWNUPTn9lwU+drdy6QN0DsiIiPIZBk4dGKtqSXiqI8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Lg6BSzgC; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Lg6BSzgC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751081724; x=1782617724; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=/INFvW4Qi6kj0Usw93W5OwBiOHfJrQKbA2C20+QLwds=; b=Lg6BSzgCQPRPJwuNbGb8VQu5nliojT6j7PzjPjkFuotrzNjfn/tsqe9x lykbTHh5LhSVgbOvD/5Ef8xBX+A/yX4FMUyDVv6MGMatKt5iQGsF0QvpI HoJRC+OAobpmhg3dTRK036CLQwfJXwla2236aw8ccuJGgZKEN4NYwtgoS UrsjEgbRDALcqiRj+aJcfqe2q0ct4moCSZtefzVZ9N1RUJvUG98mVCtxY IQL1FaYyXY7srmQ2xNUJfnDKJuTSun8r6jlXYm8n9nIpVIKBPJfVBs/3K lr/VGf4PpLtRLm/MQuHwNc/eYUAldpd8XJoNorLaJra92gpxv6uYzDyvE g==; X-CSE-ConnectionGUID: TttKtrDVTue9U94KJGgE2Q== X-CSE-MsgGUID: OcD7/SchRz+/AC3jCQWnEw== X-IronPort-AV: E=McAfee;i="6800,10657,11477"; a="53335335" X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="53335335" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:21 -0700 X-CSE-ConnectionGUID: 7QUh+mIGRPyi7zf2WSQ4LQ== X-CSE-MsgGUID: Pu09oazjTrSJam+6hyybFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="153141938" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by orviesa007.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:20 -0700 From: Ricardo Neri Date: Fri, 27 Jun 2025 20:35:11 -0700 Subject: [PATCH v5 05/10] x86/hyperv/vtl: Set real_mode_header in hv_vtl_init_platform() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rneri-wakeup-mailbox-v5-5-df547b1d196e@linux.intel.com> References: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> In-Reply-To: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Thomas Gleixner , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751081737; l=2018; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=s/4d/L3MtI822NkMfDzjH/6F6iBEhiXrR7cqJZV+mls=; b=C7u4HhtenpEjBNMxz4L9ZCpzbnjUEXumSps9XJKGY6Cpe0b6CnNydI0qDTrcLz9t5bP4ZCUil fG1u5eYKJKdBxXWlgY+F2mbgftJVnmF5fQprHn353OP7y1aL818mnK6 X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang Hyper-V VTL clears x86_platform.realmode_{init(), reserve()} in hv_vtl_platform_init() whereas it sets real_mode_header later in hv_vtl_early_init(). There is no need to deal with the real mode memory in two places: x86_platform.realmode_init() is invoked much later via an early_initcall. Set real_mode_header in hv_vtl_init_platform() to keep all code dealing with memory for the real mode trampoline in one place. Besides making the code more readable, it prepares it for a subsequent changeset in which the behavior needs to change to support Hyper-V VTL guests in TDX environment. Reviewed-by: Michael Kelley Suggested-by: Thomas Gleixner Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v4: - None Changes since v3: - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Edited the commit message for clarity. Changes since v1: - Introduced this patch. --- arch/x86/hyperv/hv_vtl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 042e8712d8de..e10b63b7a49f 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -65,6 +65,7 @@ void __init hv_vtl_init_platform(void) =20 x86_platform.realmode_reserve =3D x86_init_noop; x86_platform.realmode_init =3D x86_init_noop; + real_mode_header =3D &hv_vtl_real_mode_header; x86_init.irqs.pre_vector_init =3D x86_init_noop; x86_init.timers.timer_init =3D x86_init_noop; x86_init.resources.probe_roms =3D x86_init_noop; @@ -244,7 +245,6 @@ int __init hv_vtl_early_init(void) panic("XSAVE has to be disabled as it is not supported by this module.\n" "Please add 'noxsave' to the kernel command line.\n"); =20 - real_mode_header =3D &hv_vtl_real_mode_header; apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu= ); =20 return 0; --=20 2.43.0 From nobody Wed Oct 8 12:33:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 130BC21D3DF; Sat, 28 Jun 2025 03:35:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081726; cv=none; b=NwJQtTao4GTEYH564h0j47PW/O/ExYbMrzpOjpMuR2Q2Bc13iVnbD26JC/Xf6HTxUoc6WPDeiMmT5lI79ot6Fdz/eaZ7QRuNWdg8JU+DYkcaGUQyaAo5vyXTVIGrzoRXsm2Vywzjp/+RuvSmo5z52YVzJlU1WOxnaULYyjg3tmA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081726; c=relaxed/simple; bh=Kts6osMw25DFJPrmkqjwGgkGlhZj4Myjy58szbwE5mI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Q0+WmGpvVsZ89yKTcF2BnKj12UlyXa2SoAxEInyTnJEPBM+6kBjEIVpYxrUy3WZTvRT4I0iN1080jZEQnhCPoIRdMlJU3UplvwsWA4XnHzmf5TZS1NbMDdeCoX4rfK7iUPKhXzllHRu+qv9nqG+DFwe9DhJgg6N1zWfS/ondl5o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GLYPp4M9; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GLYPp4M9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751081724; x=1782617724; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=Kts6osMw25DFJPrmkqjwGgkGlhZj4Myjy58szbwE5mI=; b=GLYPp4M9+8e0fSc5bHqNrErRHTSgB20Yo+GVrYTSW/Vywyfq8G2bhRGI i3euI28Vg28SjpjUtpgJG8xYrD1zwUsWVbhteCUJidU0+ETrGFcnHnSbb 3U/EPDM0mIrEc6i972Won3voLtf4UTP0f/BwjHg0pLTzZXMEBp0Pvz3Y7 +FDngSKKHh13k1RI54kub6j3R2g2tXYgdUGrXs6f8i9HsF4fwUOvCKT6Z YO5iLzduPFMMIgu9csks8KlkY7QEHPg9oLHOCLeCi1qCl/K8wvPTPWt6P 9YoWj7c4txFg8upcltK5bPexAOWyOm7BhnDGjo8iLF79ToFGL1jjbpLic Q==; X-CSE-ConnectionGUID: M4wEEV9QSuS6SPNwKugqdg== X-CSE-MsgGUID: mqKbW3Y4R6qlc4Cei00+MA== X-IronPort-AV: E=McAfee;i="6800,10657,11477"; a="53335342" X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="53335342" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:21 -0700 X-CSE-ConnectionGUID: 6cjRth4PQ1W+yY8rugUgrg== X-CSE-MsgGUID: UbsGVhuVSgOEzqJzdHCZsg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="153141943" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by orviesa007.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:20 -0700 From: Ricardo Neri Date: Fri, 27 Jun 2025 20:35:12 -0700 Subject: [PATCH v5 06/10] x86/realmode: Make the location of the trampoline configurable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rneri-wakeup-mailbox-v5-6-df547b1d196e@linux.intel.com> References: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> In-Reply-To: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Thomas Gleixner , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751081737; l=3901; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=3Y2yQTIkiUMza6WQc6fzVojZ2dudUc37najPGFxbD1U=; b=Gc08BMYpD5yUks4YcmUApezjyQIp4cgUYBoY20Zw9gn8hkGm7vEAG1Hc/IlOEHvHo1gWZ7uT0 aLbJ/v8atJwCoEjrIQzZoJNofSx1O4zeDcyZzkPYpVxg02ofUgYi5gY X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang x86 CPUs boot in real mode. This mode uses 20-bit memory addresses (16-bit registers plus 4-bit segment selectors). This implies that the trampoline must reside under the 1MB memory boundary. There are platforms in which the firmware boots the secondary CPUs, switches them to long mode and transfers control to the kernel. An example of such mechanism is the ACPI Multiprocessor Wakeup Structure. In this scenario there is no restriction to locate the trampoline under 1MB memory. Moreover, certain platforms (for example, Hyper-V VTL guests) may not have memory available for allocation under 1MB. Add a new member to struct x86_init_resources to specify the upper bound for the location of the trampoline memory. Keep the default upper bound of 1MB to conserve the current behavior. Reviewed-by: Michael Kelley Originally-by: Thomas Gleixner Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v4: - None Changes since v3: - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Edited the commit message for clarity. - Minor tweaks to comments. - Removed the option to not reserve the first 1MB of memory as it is not needed. Changes since v1: - Added this patch using code that Thomas suggested: https://lore.kernel.org/lkml/87a5ho2q6x.ffs@tglx/ --- arch/x86/include/asm/x86_init.h | 3 +++ arch/x86/kernel/x86_init.c | 3 +++ arch/x86/realmode/init.c | 7 +++---- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_ini= t.h index 36698cc9fb44..e770ce507a87 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -31,12 +31,15 @@ struct x86_init_mpparse { * platform * @memory_setup: platform specific memory setup * @dmi_setup: platform specific DMI setup + * @realmode_limit: platform specific address limit for the real mode tra= mpoline + * (default 1M) */ struct x86_init_resources { void (*probe_roms)(void); void (*reserve_resources)(void); char *(*memory_setup)(void); void (*dmi_setup)(void); + unsigned long realmode_limit; }; =20 /** diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index 0a2bbd674a6d..a25fd7282811 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -9,6 +9,7 @@ #include #include #include +#include =20 #include #include @@ -69,6 +70,8 @@ struct x86_init_ops x86_init __initdata =3D { .reserve_resources =3D reserve_standard_io_resources, .memory_setup =3D e820__memory_setup_default, .dmi_setup =3D dmi_setup, + /* Has to be under 1M so we can execute real-mode AP code. */ + .realmode_limit =3D SZ_1M, }, =20 .mpparse =3D { diff --git a/arch/x86/realmode/init.c b/arch/x86/realmode/init.c index 88be32026768..694d80a5c68e 100644 --- a/arch/x86/realmode/init.c +++ b/arch/x86/realmode/init.c @@ -46,7 +46,7 @@ void load_trampoline_pgtable(void) =20 void __init reserve_real_mode(void) { - phys_addr_t mem; + phys_addr_t mem, limit =3D x86_init.resources.realmode_limit; size_t size =3D real_mode_size_needed(); =20 if (!size) @@ -54,10 +54,9 @@ void __init reserve_real_mode(void) =20 WARN_ON(slab_is_available()); =20 - /* Has to be under 1M so we can execute real-mode AP code. */ - mem =3D memblock_phys_alloc_range(size, PAGE_SIZE, 0, 1<<20); + mem =3D memblock_phys_alloc_range(size, PAGE_SIZE, 0, limit); if (!mem) - pr_info("No sub-1M memory is available for the trampoline\n"); + pr_info("No memory below %pa for the real-mode trampoline\n", &limit); else set_real_mode_mem(mem); =20 --=20 2.43.0 From nobody Wed Oct 8 12:33:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0F6621E087; Sat, 28 Jun 2025 03:35:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; 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a="53335348" X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="53335348" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:21 -0700 X-CSE-ConnectionGUID: Jyf+GzUgSm2Ojz2uycDGuw== X-CSE-MsgGUID: Wa+jJ2d7TPqOAff3hoVhKQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="153141947" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by orviesa007.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:21 -0700 From: Ricardo Neri Date: Fri, 27 Jun 2025 20:35:13 -0700 Subject: [PATCH v5 07/10] x86/hyperv/vtl: Setup the 64-bit trampoline for TDX guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rneri-wakeup-mailbox-v5-7-df547b1d196e@linux.intel.com> References: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> In-Reply-To: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751081737; l=2563; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=v53YIEDb5wEecGCYiRI9pSAZEMooPBl6C6+NHy1rJw4=; b=dsGZ9Lm5tU4WnkSGeayXzXSkr5L4Gn5pyBmPg9HRIhUWFgMBBDqh/CSXzfIxAI/PALl+wN/Cq tlxEXHw+QLaCwEtJZyKnFqkqmaX0MDWwXcmJUN4WOQXZgJLOwRwxw6W X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang The hypervisor is an untrusted entity for TDX guests. It cannot be used to boot secondary CPUs - neither via hypercalls not the INIT assert, de-assert plus Start-Up IPI messages. Instead, the platform virtual firmware boots the secondary CPUs and puts them in a state to transfer control to the kernel. This mechanism uses the wakeup mailbox described in the Multiprocessor Wakeup Structure of the ACPI specification. The entry point to the kernel is trampoline_start64. Allocate and setup the trampoline using the default x86_platform callbacks. The platform firmware configures the secondary CPUs in long mode. It is no longer necessary to locate the trampoline under 1MB memory. After handoff from firmware, the trampoline code switches briefly to 32-bit addressing mode, which has an addressing limit of 4GB. Set the upper bound of the trampoline memory accordingly. Reviewed-by: Michael Kelley Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v4: - None Changes since v3: - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Added a note regarding there is no need to check for a present paravisor. - Edited commit message for clarity. Changes since v1: - Dropped the function hv_reserve_real_mode(). Instead, used the new members realmode_limit and reserve_bios members of x86_init to set the upper bound of the trampoline memory. (Thomas) --- arch/x86/hyperv/hv_vtl.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index e10b63b7a49f..ca0d23206e67 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -63,9 +63,14 @@ void __init hv_vtl_init_platform(void) */ pr_info("Linux runs in Hyper-V Virtual Trust Level %d\n", ms_hyperv.vtl); =20 - x86_platform.realmode_reserve =3D x86_init_noop; - x86_platform.realmode_init =3D x86_init_noop; - real_mode_header =3D &hv_vtl_real_mode_header; + /* There is no paravisor present if we are here. */ + if (hv_isolation_type_tdx()) { + x86_init.resources.realmode_limit =3D SZ_4G; + } else { + x86_platform.realmode_reserve =3D x86_init_noop; + x86_platform.realmode_init =3D x86_init_noop; + real_mode_header =3D &hv_vtl_real_mode_header; + } x86_init.irqs.pre_vector_init =3D x86_init_noop; x86_init.timers.timer_init =3D x86_init_noop; x86_init.resources.probe_roms =3D x86_init_noop; --=20 2.43.0 From nobody Wed Oct 8 12:33:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B45221FF42; Sat, 28 Jun 2025 03:35:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081727; cv=none; b=oi3TE6zsmKB3qzuJk/99lASlWdMYQbhJVStKflS38PxXLpVTDNhCqhp3jX6/Nqv0WHyXzGrtimUHW/IkjlgD1FEFFarbwPJ9XEJXKVD6V08+YhnXqLjR0eNR+Ksjl14Z2h3pb6znWuR1kaGXcxUZIjrMmXspNDh95m0kQAvjYKA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081727; c=relaxed/simple; bh=N2fJS0od4PztBQXpKokHlCgKokIm3lqpe/O3tOSfUV4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Y3zB4bytZhYFfu6vT96xNblXKvTeKcYiWsojb87U8XHyC2kHdgmo/CACeoUG+JeJOlxHmxXwRALo41gAMcB1sAQcSTUG1sUFaraCNn9kh55BctMVV65ejrlf9Q1HTUNoxHFDWCkVZ6hGkHlDiCM1uDPt+r9QG8UKtFEN+Xu3DFs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lkgCWFAC; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lkgCWFAC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751081726; x=1782617726; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=N2fJS0od4PztBQXpKokHlCgKokIm3lqpe/O3tOSfUV4=; b=lkgCWFACbjGSxamGhQRx8JGJaPAGPQtezfAM6Jk4uUQVo6j27qbvOYJK +tH7QljxpUVmclIBQIVelsESplXWBkaS+1xL2Pyf94dHcPo1bgjFqE+MH odNHBPe9H8KSXx8Eh+Lb++qTZSUqkbnaCtpUEuI1fX/Vskmao0PP+8Xi/ 1JbYRMiU/ReRn0FLLeeZMYCPo4VuByGMfdcxU9zo1xXsq1JWkMxl1cluh RXIP5VCm81uuvb8PbXGXKrDsCvSQcu1zaGqxI0ntnKDsDwhJrXfMcl7NA AQtpHjdGZserB2DcvUJuIe+DiY35X3JROxJJmJILhscQf3QIZfag9D5GB Q==; X-CSE-ConnectionGUID: HgrSb0tZTCS3ElW+ZJnFXA== X-CSE-MsgGUID: G9qbBnFUQ5eJweLdaFgUjg== X-IronPort-AV: E=McAfee;i="6800,10657,11477"; a="53335355" X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="53335355" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:22 -0700 X-CSE-ConnectionGUID: kfyg3/E6SeqynujUeDj2WQ== X-CSE-MsgGUID: wbA/7BLHQu2SYB/oZkgZ3Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="153141952" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by orviesa007.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:21 -0700 From: Ricardo Neri Date: Fri, 27 Jun 2025 20:35:14 -0700 Subject: [PATCH v5 08/10] x86/smpwakeup: Add a helper get the address of the wakeup mailbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rneri-wakeup-mailbox-v5-8-df547b1d196e@linux.intel.com> References: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> In-Reply-To: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751081737; l=1696; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=N2fJS0od4PztBQXpKokHlCgKokIm3lqpe/O3tOSfUV4=; b=e6+Ki4qiU6OhUu5Q188/7DKWvc0LchICJK/SMkRzZEEvu594NtkYFUduWsG7XSzROV7T1F9as uuS03V24zd4A4A54Li7xDbxKVFrS/zwy5PnKAkqGF9obemIJcRY/p6i X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= A Hyper-V VTL level 2 guest on a TDX environment needs to map the physical page of the ACPI Multiprocessor Wakeup Structure as private (encrypted). It needs to know the physical address of this structure. Add a helper function. Reviewed-by: Michael Kelley Suggested-by: Michael Kelley Signed-off-by: Ricardo Neri --- Changes since v4: - None Changes since v3: - Renamed function to acpi_get_mp_wakeup_mailbox_paddr(). - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Introduced this patch Changes since v1: - N/A --- arch/x86/include/asm/smp.h | 1 + arch/x86/kernel/smpwakeup.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index 77dce560a70a..158e8979342e 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -148,6 +148,7 @@ static inline struct cpumask *cpu_l2c_shared_mask(int c= pu) =20 void acpi_setup_mp_wakeup_mailbox(u64 addr); struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void= ); +u64 acpi_get_mp_wakeup_mailbox_paddr(void); =20 #else /* !CONFIG_SMP */ #define wbinvd_on_cpu(cpu) wbinvd() diff --git a/arch/x86/kernel/smpwakeup.c b/arch/x86/kernel/smpwakeup.c index 5089bcda615d..f730a66b6fc8 100644 --- a/arch/x86/kernel/smpwakeup.c +++ b/arch/x86/kernel/smpwakeup.c @@ -81,3 +81,8 @@ struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wa= keup_mailbox(void) { return acpi_mp_wake_mailbox; } + +u64 acpi_get_mp_wakeup_mailbox_paddr(void) +{ + return acpi_mp_wake_mailbox_paddr; +} --=20 2.43.0 From nobody Wed Oct 8 12:33:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 615FF220F5A; Sat, 28 Jun 2025 03:35:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081728; cv=none; b=Phj3Ba6PO/CG4jfxOxCfIQJHeH4YOCJ1jERimC/HkTVjRuWh91jLGSijmJIrHkBnhoFx85oD/FcWJ6PaK3Z1ZarPQ4E5P3I1LoWXRItzmBj+2/+tozUeaaBQFsWMIJgfaLx+pDqZ94A27/TEXResd1zzdhpMfg/DhO2wpUQl9zk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081728; c=relaxed/simple; bh=bA+cp60Wn+c2Q2SZQk3sBkJyRd3e890T+LyFFWB2XgE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rU9xgQR3Z0bU2lww8Oxz9uKk+B8Mg+WXD3SKFrXdnpA1PEy5EQmgLBY/rLtDqlxAQp9z3NIhbV5JnWWXftLa+eJnHF2Mva+HqZFC37uH5N4UIEIQzX28PBkeD/lt4KtY2cUwMF2MSX5OPr0jTm3mXZxcFtr3NpDX9cNj3tsXsRs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HhNXkMD8; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HhNXkMD8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751081727; x=1782617727; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=bA+cp60Wn+c2Q2SZQk3sBkJyRd3e890T+LyFFWB2XgE=; b=HhNXkMD8TrSO6aFHeyjC7EUD+wsGpp36Ia6ZKeiIdBRMzfEC0J1ziQRJ NQnJZNEjxc7dy5sENA7r0Op4++Ex09i1SFRJNOan6BYtq/ZyQCXeDFAIR h8RwGganbyTO0MRd+oDMLtGhCv6j3BV18o1Z9di30pCAEqKu08riHvShp njx3uwno+MrGOQIxn080GlKMf4k2tD35TNc5DqA4OpaAHqhv98CiKz6yq CindFnstOy0pMZBisi5EwF86DNXQDFgHwKd+KIlNot9ij33n7P4HenLtX ZYMhcpbLFqG4Z7ckYXQn/weDStitUGEm0F44OvXGVtoZ/yNvCjKa0kxSG Q==; X-CSE-ConnectionGUID: X4bHyIXERzClQSCml01ZRw== X-CSE-MsgGUID: fbxARklrQ4y7wISliXaDaQ== X-IronPort-AV: E=McAfee;i="6800,10657,11477"; a="53335362" X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="53335362" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:22 -0700 X-CSE-ConnectionGUID: QFza1kH1R8OmyHa67d5u8A== X-CSE-MsgGUID: her6WysNTaWVZqgZ+5Pkqg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="153141956" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by orviesa007.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:21 -0700 From: Ricardo Neri Date: Fri, 27 Jun 2025 20:35:15 -0700 Subject: [PATCH v5 09/10] x86/hyperv/vtl: Mark the wakeup mailbox page as private Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rneri-wakeup-mailbox-v5-9-df547b1d196e@linux.intel.com> References: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> In-Reply-To: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751081737; l=2277; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=9g1YRz6FR6zJlHZ79s4vEPUPGZUICsglX98SibsY/ZY=; b=PptK7p3kg/euz4gfz+AKQVUtImSQRNvFKTF7PbB15t8dTYJ/c7/2oc4wYqFkFnel9sDPr/38g j2ZaeSskVxoCWf/4SMBQEBHmZEY9PJ4R/DPPDY87yjHSHj7Xaw99pZd X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang The current code maps MMIO devices as shared (decrypted) by default in a confidential computing VM. In a TDX environment, secondary CPUs are booted using the Multiprocessor Wakeup Structure defined in the ACPI specification. The virtual firmware and the operating system function in the guest context, without intervention from the VMM. Map the physical memory of the mailbox as private. Use the is_private_mmio() callback. Reviewed-by: Michael Kelley Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v4: - None Changes since v3: - Updated to use the renamed function acpi_get_mp_wakeup_mailbox_paddr(). - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Use the new helper function get_mp_wakeup_mailbox_paddr(). - Edited the commit message for clarity. Changes since v1: - Added the helper function within_page() to improve readability - Override the is_private_mmio() callback when detecting a TDX environment. The address of the mailbox is checked in hv_is_private_mmio_tdx(). --- arch/x86/hyperv/hv_vtl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index ca0d23206e67..ed633a7e05b4 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -54,6 +54,18 @@ static void __noreturn hv_vtl_restart(char __maybe_unus= ed *cmd) hv_vtl_emergency_restart(); } =20 +static inline bool within_page(u64 addr, u64 start) +{ + return addr >=3D start && addr < (start + PAGE_SIZE); +} + +static bool hv_vtl_is_private_mmio_tdx(u64 addr) +{ + u64 mb_addr =3D acpi_get_mp_wakeup_mailbox_paddr(); + + return mb_addr && within_page(addr, mb_addr); +} + void __init hv_vtl_init_platform(void) { /* @@ -66,6 +78,8 @@ void __init hv_vtl_init_platform(void) /* There is no paravisor present if we are here. */ if (hv_isolation_type_tdx()) { x86_init.resources.realmode_limit =3D SZ_4G; + x86_platform.hyper.is_private_mmio =3D hv_vtl_is_private_mmio_tdx; + } else { x86_platform.realmode_reserve =3D x86_init_noop; x86_platform.realmode_init =3D x86_init_noop; --=20 2.43.0 From nobody Wed Oct 8 12:33:57 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBEE7221286; Sat, 28 Jun 2025 03:35:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081728; cv=none; b=KxFhxDF9ymrJjfW9l6KerbSMQ9pZafCBTszkTpugHh8YBeneMwwO+M3WwKjkTeqypPXlIGqnXroGCXQEMn3yMuVrVRqfF1+bRz/vo71EblOgcXJBqXm5EfL3Q0/bRRfNh4igD4tRPl9BuAsGs2RKkKbBIUpM7gyxCvFzVgV7dCo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751081728; c=relaxed/simple; bh=T9YueJiAj+n6P/e5GV63Kzix4CrmOOaujBI5JnNGJTE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=usYf28VQ9fkkwqh4y6J/vnGtvegvV5NVYo12DjAHVIIq/u70EraERwEEYnxccTa0id/wTjE8zqLseWwelJMnPCRiVpG3P/aQyDgO++G0jTeSzOXjXpPl15cn3UFDJ24ni8nAYRr6AS03YaQR+vJYvNLCZgG1qMyStvyXP1J031A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=AnE3GvH7; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="AnE3GvH7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751081727; x=1782617727; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=T9YueJiAj+n6P/e5GV63Kzix4CrmOOaujBI5JnNGJTE=; b=AnE3GvH7ccKSJm2EzdnNy2g+yJK/+INoY3Z7WcaLhKHt6TAMi9PPYA2N meQNzdrlUCKtzWvYWciyhxUxk3+Q8swPH7vN1zlznOUPusoFyoFAe2ZOY 2RyiNZrtxPfpL+cczSQIJLnmTiQIrhLXKaJ1qTzhWqVztulrdbDEAJpk/ 3fA3BYlmGyxyTQJLj5prH5ZotW58ekTVMtQkDkmJL7hTTHjngEhnT6F/W XEY7LOURfIl8g6+S9/T0I15e5DsJqtviiss8IhjrQsB00C94DZkEbj2o/ 9mnEedDHMHBf/nOv7w0VjHEAML/gT1RrolwvgIYcb15OAhtbMbzDgJh6u w==; X-CSE-ConnectionGUID: B5MojksGT+WaUwvVrD5EaQ== X-CSE-MsgGUID: Ns8rktOYReKuyNLBhoksyg== X-IronPort-AV: E=McAfee;i="6800,10657,11477"; a="53335367" X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="53335367" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:23 -0700 X-CSE-ConnectionGUID: WWKhVj/bQHuwpsuztdkwSg== X-CSE-MsgGUID: uwDk4xcSTDKSAvIAx5g4Ow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,272,1744095600"; d="scan'208";a="153141960" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by orviesa007.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2025 20:35:22 -0700 From: Ricardo Neri Date: Fri, 27 Jun 2025 20:35:16 -0700 Subject: [PATCH v5 10/10] x86/hyperv/vtl: Use the wakeup mailbox to boot secondary CPUs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rneri-wakeup-mailbox-v5-10-df547b1d196e@linux.intel.com> References: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> In-Reply-To: <20250627-rneri-wakeup-mailbox-v5-0-df547b1d196e@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751081737; l=1858; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=T9YueJiAj+n6P/e5GV63Kzix4CrmOOaujBI5JnNGJTE=; b=o+h3qNZaK9P6IrPcq4aIXzZ9PfkETm0kElx9WkN8z3CpUP1kRiZ5h2gAds/e7BEHwhMHHQ6l7 Jj1F9ZMKI8wBRh50Iq+y0zkbQeXAhu1jAWQ8fbvjxpehhno3Ct/4q+o X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= The hypervisor is an untrusted entity for TDX guests. It cannot be used to boot secondary CPUs. The function hv_vtl_wakeup_secondary_cpu() cannot be used. Instead, the virtual firmware boots the secondary CPUs and places them in a state to transfer control to the kernel using the wakeup mailbox. The kernel updates the APIC callback wakeup_secondary_cpu_64() to use the mailbox if detected early during boot (enumerated via either an ACPI table or a DeviceTree node). Reviewed-by: Michael Kelley Signed-off-by: Ricardo Neri --- Changes since v4: - None Changes since v3: - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Unconditionally use the wakeup mailbox in a TDX confidential VM. (Michael). - Edited the commit message for clarity. Changes since v1: - None --- arch/x86/hyperv/hv_vtl.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index ed633a7e05b4..d82e040d9d9a 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -264,7 +264,15 @@ int __init hv_vtl_early_init(void) panic("XSAVE has to be disabled as it is not supported by this module.\n" "Please add 'noxsave' to the kernel command line.\n"); =20 - apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu= ); + /* + * TDX confidential VMs do not trust the hypervisor and cannot use it to + * boot secondary CPUs. Instead, they will be booted using the wakeup + * mailbox if detected during boot. See setup_arch(). + * + * There is no paravisor present if we are here. + */ + if (!hv_isolation_type_tdx()) + apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cp= u); =20 return 0; } --=20 2.43.0