From nobody Wed Oct 8 13:28:16 2025 Received: from smtp-1909.mail.infomaniak.ch (smtp-1909.mail.infomaniak.ch [185.125.25.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFF69339A8 for ; Fri, 27 Jun 2025 10:54:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.125.25.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751021663; cv=none; b=QA5XPls5os6BWPWvzjhSkgJWfBJdSprFwJOVOzFdU+acdySHL9as0Wz6gYaLLmmfWI7jIQQVlVMLgQvB44zlErAOY3ncVYgPZT9d2NsgNLfZ2dyJ2+U5+CDSsgTNcOViVqMFJ7lbfl2dWW5kTGZz8ydf6MbuGIuDVsTb/z/bIdU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751021663; c=relaxed/simple; bh=ps8TnDc3mwOIZCMqh0n9tjAgd+5Ba8NAdAEEqvpYOjA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ee4eVq/jT2HSQSG7xDlSvH6arFJQKVn2IcqNS9mDqoPULB5Z0l1GtU7MfGk+i4Nynr4YbcVW+yY1tZM5dhLr33nqtJPEx3e4QtH9L69ntP+X5Z7VHXp3h/jILis/oOHmCX6tVBVashIfCNL9tUJzWNmmEmeofdUb753cUhN3/Q8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=185.125.25.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0001.mail.infomaniak.ch (smtp-4-0001.mail.infomaniak.ch [10.7.10.108]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4bTC9K2yQlzYWw; Fri, 27 Jun 2025 12:54:13 +0200 (CEST) Received: from unknown by smtp-4-0001.mail.infomaniak.ch (Postfix) with ESMTPA id 4bTC9J29nszy7b; Fri, 27 Jun 2025 12:54:12 +0200 (CEST) From: Quentin Schulz Date: Fri, 27 Jun 2025 12:53:53 +0200 Subject: [PATCH v4 1/5] dt-bindings: mfd: rk806: allow to customize PMIC reset mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rk8xx-rst-fun-v4-1-ce05d041b45f@cherry.de> References: <20250627-rk8xx-rst-fun-v4-0-ce05d041b45f@cherry.de> In-Reply-To: <20250627-rk8xx-rst-fun-v4-0-ce05d041b45f@cherry.de> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel Cc: Lukasz Czechowski , Daniel Semkowicz , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz The RK806 PMIC allows to configure its reset/restart behavior whenever the PMIC is reset either programmatically or via some external pins (e.g. PWRCTRL or RESETB). The following modes exist: - 0; restart PMU, - 1; reset all power off reset registers and force state to switch to ACTIVE mode, - 2; same as mode 1 and also pull RESETB pin down for 5ms, For example, some hardware may require a full restart (mode 0) in order to function properly as regulators are shortly interrupted in this mode. This is the case for RK3588 Jaguar and RK3588 Tiger which have a companion microcontroller running on an independent power supply and monitoring the PMIC power rail to know the state of the main system. When it detects a restart, it resets its own IPs exposed to the main system as if to simulate its own reset. Failing to perform this fake reset of the microcontroller may break things (e.g. watchdog not automatically disabled, buzzer still running until manually disabled, leftover configuration from previous main system state, etc...). Some other systems may be depending on the power rails to not be interrupted even for a small amount of time[1]. This allows to specify how the PMIC should perform on the hardware level and may differ between harwdare designs, so a DT property seems warranted. I unfortunately do not see how this could be made generic enough to make it a non-vendor property. [1] https://lore.kernel.org/linux-rockchip/2577051.irdbgypaU6@workhorse/ Reviewed-by: Krzysztof Kozlowski Signed-off-by: Quentin Schulz Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/mfd/rockchip,rk806.yaml | 21 +++++++++++++++++= ++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml b/Do= cumentation/devicetree/bindings/mfd/rockchip,rk806.yaml index 3c2b06629b75ea94f90712470bf14ed7fc16d68d..eb5bca31948ef0d39c46025d0cc= a65b8b4105a50 100644 --- a/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml +++ b/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml @@ -31,6 +31,27 @@ properties: =20 system-power-controller: true =20 + rockchip,reset-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + Mode to use when a reset of the PMIC is triggered. + + The reset can be triggered either programmatically, via one of + the PWRCTRL pins (provided additional configuration) or + asserting RESETB pin low. + + The following modes are supported + + - 0; restart PMU, + - 1; reset all power off reset registers and force state to + switch to ACTIVE mode, + - 2; same as mode 1 and also pull RESETB pin down for 5ms, + + For example, some hardware may require a full restart (mode 0) + in order to function properly as regulators are shortly + interrupted in this mode. + vcc1-supply: description: The input supply for dcdc-reg1. --=20 2.50.0 From nobody Wed Oct 8 13:28:16 2025 Received: from smtp-8fa9.mail.infomaniak.ch (smtp-8fa9.mail.infomaniak.ch [83.166.143.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEE8B1917FB for ; Fri, 27 Jun 2025 11:00:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=83.166.143.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751022034; cv=none; b=P/f32azkM2Zy/K0qF5maiCbxuelSIEzw2kdZWCdwugG69tJDg9HmNvlYAaP8r6f9XBotWNbRE1dYu9s5H1bm/dkiXELaCnO+bXmx762gJS803i54R9CvY+JsDvI3BN6x3Wpug3C6CUYXnqLSCQLvscFKJeCF3AbSgqQnOC4B5NU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751022034; c=relaxed/simple; bh=6IQyvKuNPWfXTg0M6rLgs9YlTBI3PR96YEbujeEt3os=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eSMEo3TqMPjampu849P7ekVJgPPkfJlNUAV9DGwjG7StTMZmef8j12C+hxSEEOrHMxP0NgurZWVx2y3+1aYpL8RXRyhP6cs8AOGmbgujiJeT2fWOl732nirZoaRBdWgzN0XC85TFe7Kv81gTrwFmCP2lB356JnSgQxLtxsAaWKg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=83.166.143.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0001.mail.infomaniak.ch (unknown [IPv6:2001:1600:7:10::a6c]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4bTC9L4pN1zW0Y; Fri, 27 Jun 2025 12:54:14 +0200 (CEST) Received: from unknown by smtp-4-0001.mail.infomaniak.ch (Postfix) with ESMTPA id 4bTC9K3SKyzx9C; Fri, 27 Jun 2025 12:54:13 +0200 (CEST) From: Quentin Schulz Date: Fri, 27 Jun 2025 12:53:54 +0200 Subject: [PATCH v4 2/5] mfd: rk8xx-core: allow to customize RK806 reset mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rk8xx-rst-fun-v4-2-ce05d041b45f@cherry.de> References: <20250627-rk8xx-rst-fun-v4-0-ce05d041b45f@cherry.de> In-Reply-To: <20250627-rk8xx-rst-fun-v4-0-ce05d041b45f@cherry.de> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel Cc: Lukasz Czechowski , Daniel Semkowicz , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz The RK806 PMIC has a bitfield for configuring the restart/reset behavior (which I assume Rockchip calls "function") whenever the PMIC is reset either programmatically (c.f. DEV_RST in the datasheet) or via PWRCTRL or RESETB pins. For RK806, the following values are possible for RST_FUN: 0b00 means "Restart PMU" 0b01 means "Reset all the power off reset registers, forcing the state to switch to ACTIVE mode" 0b10 means "Reset all the power off reset registers, forcing the state to switch to ACTIVE mode, and simultaneously pull down the RESETB PIN for 5mS before releasing" 0b11 means the same as for 0b10 just above. This adds the appropriate logic in the driver to parse the new rockchip,reset-mode DT property to pass this information. It just happens that the values in the binding match the values to write in the bitfield so no mapping is necessary. If it is missing, the register is left untouched and relies either on the silicon default or on whatever was set earlier in the boot stages (e.g. the bootloader). Signed-off-by: Quentin Schulz --- drivers/mfd/rk8xx-core.c | 12 ++++++++++++ include/linux/mfd/rk808.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/mfd/rk8xx-core.c b/drivers/mfd/rk8xx-core.c index 71c2b80a4678d627e86cfbec8135f08e262559d3..def4587fdfb8b82e5548e70310d= 3e16e6d07d7af 100644 --- a/drivers/mfd/rk8xx-core.c +++ b/drivers/mfd/rk8xx-core.c @@ -10,6 +10,7 @@ * Author: Wadim Egorov */ =20 +#include #include #include #include @@ -699,6 +700,7 @@ int rk8xx_probe(struct device *dev, int variant, unsign= ed int irq, struct regmap const struct mfd_cell *cells; int dual_support =3D 0; int nr_pre_init_regs; + u32 rst_fun =3D 0; int nr_cells; int ret; int i; @@ -726,6 +728,16 @@ int rk8xx_probe(struct device *dev, int variant, unsig= ned int irq, struct regmap cells =3D rk806s; nr_cells =3D ARRAY_SIZE(rk806s); dual_support =3D IRQF_SHARED; + + ret =3D device_property_read_u32(dev, "rockchip,reset-mode", &rst_fun); + if (ret) + break; + + ret =3D regmap_update_bits(rk808->regmap, RK806_SYS_CFG3, RK806_RST_FUN_= MSK, + FIELD_PREP(RK806_RST_FUN_MSK, rst_fun)); + if (ret) + return dev_err_probe(dev, ret, + "Failed to configure requested restart/reset behavior\n"); break; case RK808_ID: rk808->regmap_irq_chip =3D &rk808_irq_chip; diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h index 69cbea78b430b562a23d995263369d475daa6287..28170ee08898ca59c76a741a1d4= 2763a42b72380 100644 --- a/include/linux/mfd/rk808.h +++ b/include/linux/mfd/rk808.h @@ -812,6 +812,8 @@ enum rk806_pin_dr_sel { #define RK806_INT_POL_H BIT(1) #define RK806_INT_POL_L 0 =20 +/* SYS_CFG3 */ +#define RK806_RST_FUN_MSK GENMASK(7, 6) #define RK806_SLAVE_RESTART_FUN_MSK BIT(1) #define RK806_SLAVE_RESTART_FUN_EN BIT(1) #define RK806_SLAVE_RESTART_FUN_OFF 0 --=20 2.50.0 From nobody Wed Oct 8 13:28:16 2025 Received: from smtp-190d.mail.infomaniak.ch (smtp-190d.mail.infomaniak.ch [185.125.25.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B091E225795 for ; Fri, 27 Jun 2025 11:00:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.125.25.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751022034; cv=none; b=CtnJHUNEG6sTlgf5lWB2E5R+NElsMzPqspa+y8w34pjbRiNclVnAAG9Hh9gnOg9vUgYjThv8BA5ONiq885oyktgod2nB69fN0lMal5PRHjnGME8NQ7Xm5hGXjG1jVXSzxcdr+Lz/CTpcS9QVFgWTQpZGNELh3FTia4H08EYZBL4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751022034; c=relaxed/simple; bh=LsaoDkpHaIvDprZXOBsbjGmnELRN0iRLh8XBRohcrgk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lxHAAP7rg/QjHRgArAOBHJpCbtrFFENOfz2OzM5TM0vm2Kw+ikWMyqp2E7reJUwZ+f6w5wjc1NjIaCPSCSLwzkCFc7soyeJo4rK+SRuOGvVshQtEdcFhFEC20NKJ5gyJlQt/MhmZs1jUNmXW89NQvr6aC5Z41Wz1HgkQ9R8KwyQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=185.125.25.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0001.mail.infomaniak.ch (smtp-4-0001.mail.infomaniak.ch [10.7.10.108]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4bTC9N0HHJzZJB; Fri, 27 Jun 2025 12:54:16 +0200 (CEST) Received: from unknown by smtp-4-0001.mail.infomaniak.ch (Postfix) with ESMTPA id 4bTC9L6XsKzvrY; Fri, 27 Jun 2025 12:54:14 +0200 (CEST) From: Quentin Schulz Date: Fri, 27 Jun 2025 12:53:55 +0200 Subject: [PATCH v4 3/5] arm64: dts: rockchip: add header for RK8XX PMIC constants Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rk8xx-rst-fun-v4-3-ce05d041b45f@cherry.de> References: <20250627-rk8xx-rst-fun-v4-0-ce05d041b45f@cherry.de> In-Reply-To: <20250627-rk8xx-rst-fun-v4-0-ce05d041b45f@cherry.de> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel Cc: Lukasz Czechowski , Daniel Semkowicz , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz To make it easier to read the device tree, let's add constants for the rockchip,reset-mode property values that are currently only applicable to RK806 PMIC. Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/rk8xx.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk8xx.h b/arch/arm64/boot/dts/roc= kchip/rk8xx.h new file mode 100644 index 0000000000000000000000000000000000000000..a6fbef71c06493c35b0f3697476= 167aaafa24f30 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk8xx.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ +/* + * Device Tree defines for Rockchip RK8xx PMICs + * + * Copyright 2025 Cherry Embedded Solutions GmbH + * + * Author: Quentin Schulz + */ + +#ifndef _DT_MFD_ROCKCHIP_RK8XX_H +#define _DT_MFD_ROCKCHIP_RK8XX_H + +/* For use with rockchip,reset-mode property */ +#define RK806_RESTART 0 +#define RK806_RESET 1 +#define RK806_RESET_NOTIFY 2 + +#endif --=20 2.50.0 From nobody Wed Oct 8 13:28:16 2025 Received: from smtp-190f.mail.infomaniak.ch (smtp-190f.mail.infomaniak.ch [185.125.25.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B1A729B773; Fri, 27 Jun 2025 11:00:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.125.25.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751022041; cv=none; b=L8m+TzKiD8QProopxWPJzHBVhpBFejncrQC8Umnt/EVr/s3Rs86rlP8o1QZHN0kDLzb6N5aFua9UiHLBkmTha2ZjcMYZVrL8ceH6mtO4YJge6PQYd1Tl5pFeBn3wLcUayA0er8lYbMIxSmdQd7aaZ/7n+EEsk/3rkPFphRAA6LI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751022041; c=relaxed/simple; bh=30Dnyv1dF4DnBpa2oEEXfw7yRvrgEeQITsAYxnpbgS8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qSEEhorgY65veJR5H7dgDriwtypl4DR+/XvTcCMwazGanhvUdhCP8OE0K2PYXceEGef6mN7+tx7z9qsZ1vPybw40So+6YBuylvV4qcXeWcnkxmEM2oHoBdUuqUY9JhrtJ5/G12CfSNs8KVUaFU9KdVB/o8bW++H24hZFw7Gv6qY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=185.125.25.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0001.mail.infomaniak.ch (smtp-4-0001.mail.infomaniak.ch [10.7.10.108]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4bTC9P1q2ZzZJF; Fri, 27 Jun 2025 12:54:17 +0200 (CEST) Received: from unknown by smtp-4-0001.mail.infomaniak.ch (Postfix) with ESMTPA id 4bTC9N13KQzw8D; Fri, 27 Jun 2025 12:54:16 +0200 (CEST) From: Quentin Schulz Date: Fri, 27 Jun 2025 12:53:56 +0200 Subject: [PATCH v4 4/5] arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Jaguar Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rk8xx-rst-fun-v4-4-ce05d041b45f@cherry.de> References: <20250627-rk8xx-rst-fun-v4-0-ce05d041b45f@cherry.de> In-Reply-To: <20250627-rk8xx-rst-fun-v4-0-ce05d041b45f@cherry.de> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel Cc: Lukasz Czechowski , Daniel Semkowicz , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz The bootloader for RK3588 Jaguar currently forces the PMIC reset behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X which is incorrect for our devices. It is required to restart the PMU as otherwise the companion microcontroller cannot detect the PMIC (and by extension the full product and main SoC) being rebooted which is an issue as that is used to reset a few things like the PWM beeper and watchdogs. Let's add the new rockchip,reset-mode property to make sure the PMIC reset behavior is the expected one. Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/bo= ot/dts/rockchip/rk3588-jaguar.dts index ebe77cdd24e803b00fb848dc81258909472290f1..176925d0a1a809d1e2500f5e5ef= bbfa6a6d0bd42 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -10,6 +10,7 @@ #include #include #include +#include "rk8xx.h" #include "rk3588.dtsi" =20 / { @@ -693,6 +694,7 @@ pmic@0 { vcc13-supply =3D <&vcc_1v1_nldo_s3>; vcc14-supply =3D <&vcc_1v1_nldo_s3>; vcca-supply =3D <&vcc5v0_sys>; + rockchip,reset-mode =3D ; =20 rk806_dvs1_null: dvs1-null-pins { pins =3D "gpio_pwrctrl1"; --=20 2.50.0 From nobody Wed Oct 8 13:28:16 2025 Received: from smtp-8fab.mail.infomaniak.ch (smtp-8fab.mail.infomaniak.ch [83.166.143.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 359E029AB11 for ; Fri, 27 Jun 2025 11:10:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=83.166.143.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751022635; cv=none; b=NiB/5DnZaYverh3zXWlZqCQzL2sR34MEMk+9Dulzc8MRJEgYi2GViGVWNQgTw/8OjTl1S5GDoOONs2EhdSRjMtjc/nEEMnfJHBHDvxPwmh8BaSDgFfVdcUIb5adw95MmtLK70x1G+BL3Fo2TcrhLagpFP6XludmOtlMq6KoQJOo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751022635; c=relaxed/simple; bh=QVNN6PEuKtjv/LwBBEU6+ak92MwPeasvGzcyPAw29aY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eKyKA5lb7Av+zC1G/CIrFTZQmK++eN87qr/1X9rsUS92UBfMa9nnY8hB7DWrIuIjD2Gz4Kp3iBF9RAJgfHOkPDwIQuHRvvw4t9Kvw+McryL/Xw1NFppZt20KLeIA93V3r2ONHTKTU1IU0Ih+m9526OZRCsiAS/rjAqlyrKOUwOA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=83.166.143.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0001.mail.infomaniak.ch (unknown [IPv6:2001:1600:7:10::a6c]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4bTC9Q2slpzVtZ; Fri, 27 Jun 2025 12:54:18 +0200 (CEST) Received: from unknown by smtp-4-0001.mail.infomaniak.ch (Postfix) with ESMTPA id 4bTC9P25PgzxLs; Fri, 27 Jun 2025 12:54:17 +0200 (CEST) From: Quentin Schulz Date: Fri, 27 Jun 2025 12:53:57 +0200 Subject: [PATCH v4 5/5] arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Tiger Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-rk8xx-rst-fun-v4-5-ce05d041b45f@cherry.de> References: <20250627-rk8xx-rst-fun-v4-0-ce05d041b45f@cherry.de> In-Reply-To: <20250627-rk8xx-rst-fun-v4-0-ce05d041b45f@cherry.de> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel Cc: Lukasz Czechowski , Daniel Semkowicz , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz The bootloader for RK3588 Tiger currently forces the PMIC reset behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X which is incorrect for our devices. It is required to restart the PMU as otherwise the companion microcontroller cannot detect the PMIC (and by extension the full product and main SoC) being rebooted which is an issue as that is used to reset a few things like the PWM beeper and watchdogs. Let's add the new rockchip,reset-mode property to make sure the PMIC reset behavior is the expected one. Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/bo= ot/dts/rockchip/rk3588-tiger.dtsi index c4933a08dd1e3c92f3e0747135faf97c5eeca906..b44e89e1bb1599ee70b921598c2= eb6fd54614f55 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include "rk8xx.h" #include "rk3588.dtsi" =20 / { @@ -440,6 +441,7 @@ pmic@0 { vcc13-supply =3D <&vcc_1v1_nldo_s3>; vcc14-supply =3D <&vcc_1v1_nldo_s3>; vcca-supply =3D <&vcc5v0_sys>; + rockchip,reset-mode =3D ; =20 rk806_dvs1_null: dvs1-null-pins { pins =3D "gpio_pwrctrl1"; --=20 2.50.0