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Fri, 27 Jun 2025 03:22:14 -0700 (PDT) From: James Clark Date: Fri, 27 Jun 2025 11:21:42 +0100 Subject: [PATCH v4 6/6] spi: spi-fsl-dspi: Report FIFO overflows as errors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-james-nxp-spi-dma-v4-6-178dba20c120@linaro.org> References: <20250627-james-nxp-spi-dma-v4-0-178dba20c120@linaro.org> In-Reply-To: <20250627-james-nxp-spi-dma-v4-0-178dba20c120@linaro.org> To: Vladimir Oltean , Mark Brown , Vladimir Oltean , Arnd Bergmann , Larisa Grigore , Frank Li , Christoph Hellwig Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 In target mode, the host sending more data than can be consumed would be a common problem for any message exceeding the FIFO or DMA buffer size. Cancel the whole message as soon as this condition is hit as the message will be corrupted. Only do this for target mode in a DMA transfer, it's not likely these flags will be set in host mode so it's not worth adding extra checks. In IRQ and polling modes we use the same transfer functions for hosts and targets so the error flags always get checked. This is slightly inconsistent but it's not worth doing the check conditionally because it may catch some host programming errors in the future. Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 46d3cae9efed..2c2a263c5276 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -478,6 +478,17 @@ static void dspi_push_rx(struct fsl_dspi *dspi, u32 rx= data) dspi->dev_to_host(dspi, rxdata); } =20 +static int dspi_fifo_error(struct fsl_dspi *dspi, u32 spi_sr) +{ + if (spi_sr & (SPI_SR_TFUF | SPI_SR_RFOF)) { + dev_err_ratelimited(&dspi->pdev->dev, "FIFO errors:%s%s\n", + spi_sr & SPI_SR_TFUF ? " TX underflow," : "", + spi_sr & SPI_SR_RFOF ? " RX overflow," : ""); + return -EIO; + } + return 0; +} + #if IS_ENABLED(CONFIG_DMA_ENGINE) =20 /* Prepare one TX FIFO entry (txdata plus cmd) */ @@ -566,6 +577,7 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *d= spi) struct device *dev =3D &dspi->pdev->dev; struct fsl_dspi_dma *dma =3D dspi->dma; int time_left; + u32 spi_sr; int i; =20 for (i =3D 0; i < dspi->words_in_flight; i++) @@ -614,7 +626,8 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *d= spi) =20 if (spi_controller_is_target(dspi->ctlr)) { wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete); - return 0; + regmap_read(dspi->regmap, SPI_SR, &spi_sr); + return dspi_fifo_error(dspi, spi_sr); } =20 time_left =3D wait_for_completion_timeout(&dspi->dma->cmd_tx_complete, @@ -1067,6 +1080,9 @@ static void dspi_poll(struct fsl_dspi *dspi) regmap_read(dspi->regmap, SPI_SR, &spi_sr); regmap_write(dspi->regmap, SPI_SR, spi_sr); =20 + dspi->cur_msg->status =3D dspi_fifo_error(dspi, spi_sr); + if (dspi->cur_msg->status) + return; if (spi_sr & SPI_SR_CMDTCF) break; } @@ -1085,6 +1101,7 @@ static void dspi_poll(struct fsl_dspi *dspi) static irqreturn_t dspi_interrupt(int irq, void *dev_id) { struct fsl_dspi *dspi =3D (struct fsl_dspi *)dev_id; + int status; u32 spi_sr; =20 regmap_read(dspi->regmap, SPI_SR, &spi_sr); @@ -1093,6 +1110,14 @@ static irqreturn_t dspi_interrupt(int irq, void *dev= _id) if (!(spi_sr & SPI_SR_CMDTCF)) return IRQ_NONE; =20 + status =3D dspi_fifo_error(dspi, spi_sr); + if (status) { + if (dspi->cur_msg) + WRITE_ONCE(dspi->cur_msg->status, status); + complete(&dspi->xfer_done); + return IRQ_HANDLED; + } + dspi_rxtx(dspi); =20 if (!dspi->len) { --=20 2.34.1